Heat dissipation ground hole structure, semiconductor device and preparation method of heat dissipation ground hole structure

Abstract

The invention relates to a heat dissipation ground hole structure, a semiconductor device and a preparation method of the heat dissipation ground hole structure, the heat dissipation ground hole structure comprises a device substrate, an N-type semiconductor layer and a P-type semiconductor layer, and the device substrate is provided with a first grounding hole and a second grounding hole in a penetrating manner; the N-type semiconductor layer is arranged in the first grounding hole; the P-type semiconductor layer is arranged in the second grounding hole; the N-type semiconductor layer and the P-type semiconductor layer are connected in series, and both the N-type semiconductor layer and the P-type semiconductor layer are configured to transfer heat of the front surface of the device substrate to the back surface of the device substrate in a conducting state. Compared with the prior art, the HEMT device has the advantages that heat transfer is achieved by combining the Peltier effect and the Thomson effect with the ground hole structure, the heat dissipation capacity of the first ground hole and the second ground hole is greatly improved, the good heat dissipation effect can be achieved, active heat dissipation is achieved, and therefore the performance such as the power and the maximum working temperature of the HEMT device can be improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a heat dissipation ground hole structure, a semiconductor device, and a method for preparing the heat dissipation ground hole structure. Background Art

[0002] At present, the traditional power amplifier structure is mainly a transistor, and the source of the transistor is grounded through a ground hole. The power amplifier generates a lot of heat when working, which can easily cause the device to produce current collapse, resulting in its power and power added efficiency not being maximized, and even worse, the device is burned.

[0003] Traditional heat dissipation technologies include metal heat sinks and front air cooling, which act on the entire circuit board and cannot dissipate heat for the hottest device parts. In addition, traditional heat dissipation technologies are large in size and cannot be used in application scenarios such as confined spaces and closed spaces. Summary of the invention

[0004] The purpose of the present application is to provide a heat dissipation ground hole structure, a semiconductor device and a method for preparing the heat dissipation ground hole structure, which can achieve good heat dissipation effect and active heat dissipation, thereby improving the power and maximum operating temperature of the HEMT device.

[0005] In order to achieve the above object, the present invention is implemented by the following scheme:

[0006] In a first aspect, the present invention provides a heat dissipation hole structure, comprising:

[0007] A device substrate, wherein a first grounding hole and a second grounding hole are formed through the device substrate;

[0008] An N-type semiconductor layer, the N-type semiconductor layer is disposed in the first grounding hole and extends to two end openings of the first grounding hole;

[0009] A P-type semiconductor layer, wherein the P-type semiconductor layer is disposed in the second grounding hole and extends to two end openings of the second grounding hole;

[0010] The N-type semiconductor layer and the P-type semiconductor layer are connected in series, and both the N-type semiconductor layer and the P-type semiconductor layer are configured to transfer heat from the front side of the device substrate to the back side of the device substrate in a conducting state.

[0011] In an optional embodiment, the heat dissipation ground hole structure further includes a first front conductive layer and a second front conductive layer, the first front conductive layer is arranged on the front side of the device substrate and covers the first ground hole; the N-type semiconductor layer is at least arranged on the side wall of the first ground hole and is in electrical contact with the first front conductive layer;

[0012] The second front conductive layer is disposed on the front side of the device substrate and covers the second grounding hole; the P-type semiconductor layer is at least disposed on the side wall of the second grounding hole and is in electrical contact with the second front conductive layer;

[0013] The first front conductive layer and the second front conductive layer are electrically connected, the N-type semiconductor layer is configured to transfer the heat of the first front conductive layer to the back side of the device substrate in an on state, and the P-type semiconductor layer is configured to transfer the heat of the second front conductive layer to the back side of the device substrate in an on state.

[0014] In an optional embodiment, the heat dissipation ground hole structure further includes a first back side conductive layer and a second back side conductive layer, the first back side conductive layer is arranged on the back side of the device substrate and extends to the first ground hole, and the N-type semiconductor layer is in electrical contact with the first back side conductive layer;

[0015] The second back side conductive layer is disposed on the back side of the device substrate and extends to the second grounding hole, and the P-type semiconductor layer is in electrical contact with the second back side conductive layer.

[0016] In an optional embodiment, the first back side conductive layer and the second back side conductive layer in the same heat dissipation ground hole structure are spaced apart, and the first back side conductive layer is configured to be in electrical contact with the second back side conductive layer in an adjacent heat dissipation ground hole structure, and the second back side conductive layer is configured to be in electrical contact with the first back side conductive layer in an adjacent heat dissipation ground hole structure.

[0017] In an optional embodiment, a gold wire is disposed between the first front-side conductive layer and the second front-side conductive layer, and the first front-side conductive layer and the second front-side conductive layer are electrically connected via the gold wire.

[0018] In an optional embodiment, the first front conductive layer includes a first etch barrier layer and a first front metal layer, the first etch barrier layer is arranged on the front side of the device substrate and covers the first grounding hole, and the first front metal layer is arranged on the front side of the device substrate and covers the first etch barrier layer.

[0019] The second front conductive layer includes a second etch barrier layer and a second front metal layer, the second etch barrier layer is arranged on the front side of the device substrate and covers the second grounding hole, and the second front metal layer is arranged on the front side of the device substrate and covers the second etch barrier layer.

[0020] In an optional embodiment, the first etch stop layer is configured as the bottom wall of the first grounding hole, and the N-type semiconductor layer is arranged on the side walls and bottom walls of the first grounding hole; the second etch stop layer is configured as the bottom wall of the second grounding hole, and the P-type semiconductor layer is arranged on the side walls and bottom walls of the second grounding hole.

[0021] In an optional embodiment, the side of the N-type semiconductor layer away from the first etch stop layer extends to the opening periphery of the first grounding hole, and the first back conductive layer partially covers the N-type semiconductor layer;

[0022] A side of the P-type semiconductor layer away from the first etch stop layer extends to an opening periphery of the second grounding hole, and the second back conductive layer partially covers the P-type semiconductor layer.

[0023] In an optional embodiment, the N-type semiconductor layer and the P-type semiconductor layer both include Bi2Te3-Sb2Te3 solid solution, Bi2Te3-Bi2Se3 solid solution, ternary Bi2Te3-S b2 At least one of Te3-Sb2Se3 solid solutions.

[0024] In a second aspect, the present invention provides a semiconductor device, comprising a source electrode, a drain electrode, a gate electrode and a heat dissipation ground hole structure as described in any of the aforementioned embodiments, wherein the source electrode, the drain electrode and the gate electrode are all arranged on the device substrate and are spaced apart from the first ground hole and the second ground hole.

[0025] In an optional embodiment, a source grounding hole is further provided through the device substrate, a source conductive layer is further provided on the front side of the device substrate, the source conductive layer covers the source grounding hole and is connected to the source electrode, a first back metal layer is provided in the source grounding hole, a second back metal layer is further provided on the back side of the device substrate, the second back metal layer extends to the source grounding hole, and the first back metal layer is electrically contacted with the source conductive layer and the second back metal layer at the same time.

[0026] In a third aspect, the present invention provides a method for preparing a heat dissipation ground hole structure, which is used to prepare the heat dissipation ground hole structure as described in the above embodiment, and the preparation method comprises:

[0027] providing a device substrate;

[0028] forming a first grounding hole and a second grounding hole on the device substrate;

[0029] Disposing an N-type semiconductor layer in the first grounding hole;

[0030] Disposing a P-type semiconductor layer in the second grounding hole;

[0031] The N-type semiconductor layer and the P-type semiconductor layer are connected in series, and both the N-type semiconductor layer and the P-type semiconductor layer are configured to transfer heat from the front side of the device substrate to the back side of the device substrate in a conducting state.

[0032] Through the above technical solution, the embodiment of the present invention opens the first grounding hole and the second grounding hole on the device substrate, and fills the first grounding hole and the second grounding hole with N-type semiconductor and P-type semiconductor. In the on state, a positive voltage can be applied to the N-type heat dissipation hole, and a negative voltage can be applied to the P-type heat dissipation hole. The electron flow in the N-type semiconductor is from the front side to the back side of the device substrate, and the hole flow in the P-type semiconductor is also from the front side to the back side of the device substrate. Due to the Peltier effect and the Thomson effect, the end of the N-type semiconductor layer and the P-type semiconductor layer close to the front side of the device substrate will form a heat absorption end, thereby absorbing additional heat, and the end close to the back side will form a heat release section, thereby releasing additional heat, so as to achieve the effect of actively transporting heat from the front side to the back side. Compared with the prior art, the embodiment of the present invention uses the Peltier effect and the Thomson effect combined with the ground hole structure to realize heat transfer, greatly improves the heat dissipation capacity of the first grounding hole and the second grounding hole, can achieve good heat dissipation effect, realize active heat dissipation, and thus can improve the power and maximum operating temperature of the HEMT device.

[0033] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0035] Figure 1 This is a schematic diagram of the cross-sectional structure of the heat dissipation hole structure in the embodiment of the present application;

[0036] Figure 2 This is a schematic diagram of the working state of the heat dissipation hole structure in the embodiment of the present application;

[0037] Figure 3 This is a schematic diagram of the cross-sectional structure of adjacent heat dissipation hole structures in an embodiment of the present application;

[0038] Figure 4 A top view of adjacent heat dissipation hole structures in an embodiment of the present application;

[0039] Figure 5A top view of a semiconductor device in an embodiment of the present application;

[0040] Figure 6 for Figure 5 Schematic diagram of the cross-sectional structure at AA in the middle;

[0041] Figure 7 for Figure 5 Schematic diagram of the cross-sectional structure at BB in the middle;

[0042] Figures 8 to 13 1 is a process flow chart of a method for preparing a heat dissipation hole structure in an embodiment of the present application.

[0043] Icon: 100-heat dissipation ground hole structure; 110-device substrate; 111-first grounding hole; 113-second grounding hole; 120-N-type semiconductor layer; 130-P-type semiconductor layer; 140-first front conductive layer; 141-first etching barrier layer; 143-first front metal layer; 150-second front conductive layer; 151-second etching barrier layer; 153-second front metal layer; 160-first back conductive layer; 170-second back conductive layer; 180-gold wire; 200-semiconductor device; 210-source electrode; 220-drain electrode; 230-gate electrode; 240-source conductive layer; 250-source grounding hole; 260-first back metal layer; 270-second back metal layer. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0045] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0046] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0047] As disclosed in the background art, the heat dissipation method of existing HEMT devices is usually a metal heat sink or front air cooling, which can only dissipate heat for the entire circuit chip or packaging structure, but cannot specifically dissipate heat for the hottest device part of the device.

[0048] Furthermore, in a conventional source grounding hole structure, a conductive metal is provided therein. Although this conductive metal and the grounding hole can achieve a certain heat dissipation function, the main purpose of this layer of metal is to achieve electrical connection and can only achieve passive heat dissipation, that is, heat dissipation is only achieved through heat conduction. This heat dissipation method is inefficient and difficult to meet heat dissipation requirements.

[0049] In view of the above problems, the present invention provides a heat dissipation ground hole structure that can be integrated on a device, a preparation method thereof, and a semiconductor device. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0050] See also Figure 1 and Figure 2 (The arrows in the figure indicate the direction of heat transfer). The embodiment of the present invention provides a heat dissipation ground hole structure 100, which can achieve good heat dissipation effect and realize active heat dissipation, thereby improving the power and maximum operating temperature of the HEMT device.

[0051] The heat dissipation ground hole structure 100 provided in the embodiment of the present invention includes a device substrate 110, an N-type semiconductor layer 120 and a P-type semiconductor layer 130. The device substrate 110 is penetrated with a first grounding hole 111 and a second grounding hole 113; the N-type semiconductor layer 120 is arranged in the first grounding hole 111 and extends to the two end openings of the first grounding hole 111; the P-type semiconductor layer 130 is arranged in the second grounding hole 113 and extends to the two end openings of the second grounding hole 113; wherein the N-type semiconductor layer 120 and the P-type semiconductor layer 130 are connected in series, and both the N-type semiconductor layer 120 and the P-type semiconductor layer 130 are configured to transfer the heat on the front side of the device substrate 110 to the back side of the device substrate 110 in a conductive state.

[0052] It should be noted that the device substrate 110 here is the substrate structure of the semiconductor device 200, that is, the heat dissipation ground hole structure 100 is integrated in the semiconductor device 200, and can directly dissipate heat from the device structure. In the on state, the first ground hole 111 can apply a positive voltage, and the second ground hole 113 can apply a negative voltage, so that the side of the N-type semiconductor layer 120 close to the back of the substrate is connected to the positive electrode, and the side of the P-type semiconductor layer 130 close to the back of the substrate is connected to the negative electrode, and they can be connected in series on the front. Therefore, in the on state, the electron flow in the N-type semiconductor is from the front to the back of the device substrate 110, and the hole flow in the P-type semiconductor is also from the front to the back of the device substrate 110. Due to the Peltier effect and the Thomson effect, the end of the N-type semiconductor layer 120 and the P-type semiconductor layer 130 close to the front of the device substrate 110 will form a heat absorption end, thereby absorbing additional heat, and the end close to the back will form a heat release section, thereby releasing additional heat, so as to achieve the effect of actively transporting heat from the front to the back, thereby achieving active heat dissipation.

[0053] It is worth noting that the Peltier Effect refers to the phenomenon that when an electric current passes through a junction composed of two different materials, heat is absorbed or released at the junction. When an electric current passes through a junction composed of two different materials (such as n-type and p-type semiconductors), electrons carry energy in the process of transferring from one material to another. If electrons transfer from a high energy level to a low energy level, heat is released at the junction; if electrons transfer from a low energy level to a high energy level, heat is absorbed at the junction. The Thomson Effect refers to the phenomenon that when an electric current passes through different temperature regions of the same material, heat is generated or absorbed inside the material. When an electric current passes through different temperature regions of the same material, the energy distribution of electrons at different temperatures is different. If electrons flow from a high temperature region to a low temperature region, energy is released; if electrons flow from a low temperature region to a high temperature region, energy is absorbed.

[0054] Furthermore, the heat dissipation ground hole structure 100 further includes a first front conductive layer 140 and a second front conductive layer 150, wherein the first front conductive layer 140 is disposed on the front of the device substrate 110 and covers the first ground hole 111. The N-type semiconductor layer 120 is at least disposed on the side wall of the first ground hole 111 and is in electrical contact with the first front conductive layer 140; the second front conductive layer 150 is disposed on the front of the device substrate 110 and covers the second ground hole 113. The P-type semiconductor layer 130 is at least disposed on the side wall of the second ground hole 113 and is in electrical contact with the second front conductive layer 150. The first front conductive layer 140 and the second front conductive layer 150 are electrically connected, and the N-type semiconductor layer 120 is configured to transfer the heat of the first front conductive layer 140 to the back of the device substrate 110 in the on state, and the P-type semiconductor layer 130 is configured to transfer the heat of the second front conductive layer 150 to the back of the device substrate 110 in the on state.

[0055] It should be noted that the preparation process of the first front conductive layer 140 and the second front conductive layer 150 can be consistent with the front process of the semiconductor device 200, and the first front conductive layer 140 can completely cover the first grounding hole 111, and the second front conductive layer 150 can completely cover the second grounding hole 113. The arrangement of the first front conductive layer 140 and the second front conductive layer 150 can enable the N-type semiconductor layer 120 and the P-type semiconductor layer 130 to be electrically connected on the front side, and the arrangement of the first front conductive layer 140 and the second front conductive layer 150 is also conducive to forming the first grounding hole 111 and the second grounding hole 113.

[0056] Further, the heat dissipation ground hole structure 100 also includes a first back conductive layer 160 and a second back conductive layer 170, the first back conductive layer 160 is arranged on the back of the device substrate 110 and extends to the first grounding hole 111, and the N-type semiconductor layer 120 is in electrical contact with the first back conductive layer 160. The second back conductive layer 170 is arranged on the back of the device substrate 110 and extends to the second grounding hole 113, and the P-type semiconductor layer 130 is in electrical contact with the second back conductive layer 170. Specifically, the first back conductive layer 160 and the second back conductive layer 170 are both metal layers, and the first back conductive layer 160 can be in direct contact with the N-type semiconductor layer 120 to achieve electrical connection, and the second back conductive layer 170 can be in direct contact with the P-type semiconductor layer 130 to achieve electrical connection. By providing the first back conductive layer 160 and the second back conductive layer 170, the first back conductive layer 160 and the second back conductive layer 170 are connected to an external circuit, so that it is convenient to apply a positive voltage to the N-type semiconductor layer 120 and a negative voltage to the P-type semiconductor layer 130.

[0057] See also Figures 3 to 7In some embodiments, the first back conductive layer 160 and the second back conductive layer 170 in the same heat dissipation ground hole structure 100 are arranged at intervals, and the first back conductive layer 160 is configured to be in electrical contact with the second back conductive layer 170 in the adjacent heat dissipation ground hole structure 100, and the second back conductive layer 170 is configured to be in electrical contact with the first back conductive layer 160 in the adjacent heat dissipation ground hole structure 100. Specifically, the first back conductive layer 160 and the second back conductive layer 170 are arranged at intervals, which can avoid short circuits and ensure that the N-type semiconductor layer 120 and the P-type semiconductor layer 130 are connected in series. In addition, a plurality of heat dissipation ground hole structures 100 can be arranged on a semiconductor device 200, and the device substrates 110 of the plurality of heat dissipation ground hole structures 100 are integrated into one body and constitute the substrate of the semiconductor device 200, so that the plurality of heat dissipation ground hole structures 100 can form an array heat dissipation structure and can achieve fixed-point heat dissipation.

[0058] Please continue to see Figure 1 and Figure 2 In some embodiments, a gold wire 180 is disposed between the first front conductive layer 140 and the second front conductive layer 150, and the first front conductive layer 140 and the second front conductive layer 150 are electrically connected through the gold wire 180. Specifically, the gold wire 180 can be formed between the first front conductive layer 140 and the second front conductive layer 150 by a wire bonding process, so that the first front conductive layer 140 and the second front conductive layer 150 can be prevented from occupying too much space while ensuring that the N-type semiconductor layer 120 and the P-type semiconductor layer 130 are connected in series.

[0059] In some embodiments, the first front conductive layer 140 includes a first etch barrier layer 141 and a first front metal layer 143. The first etch barrier layer 141 is disposed on the front of the device substrate 110 and covers the first grounding hole 111. The first front metal layer 143 is disposed on the front of the device substrate 110 and covers the first etch barrier layer 141. Specifically, the first etch barrier layer 141 can completely cover the first grounding hole 111. When preparing the first grounding hole 111, the first etch barrier layer 141 can be used as an etching stop layer, so that the first grounding hole 111 can be etched to form the first grounding hole 111. The first front metal layer 143 can be coated outside the first etch barrier layer 141, thereby expanding the extension range, and the first front metal layer 143 can also be used as a heat dissipation layer to increase the effective heat dissipation range and further improve the heat dissipation effect.

[0060] The second front conductive layer 150 includes a second etch stop layer 151 and a second front metal layer 153. The second etch stop layer 151 is disposed on the front of the device substrate 110 and covers the second grounding hole 113. The second front metal layer 153 is disposed on the front of the device substrate 110 and covers the second etch stop layer 151. Specifically, the second etch stop layer 151 can completely cover the second grounding hole 113. When preparing the second grounding hole 113, the second etch stop layer 151 can be used as an etching stop layer, so that the second grounding hole 113 can be etched to form the second grounding hole 113. The second front metal layer 153 can be coated outside the second etch stop layer 151, thereby expanding the extension range, and the second front metal layer 153 can also be used as a heat dissipation layer to increase the effective heat dissipation range and further improve the heat dissipation effect.

[0061] In some embodiments, the first etch stop layer 141 is configured as the bottom wall of the first ground hole 111, and the N-type semiconductor layer 120 is disposed on the sidewall and bottom wall of the first ground hole 111; the second etch stop layer 151 is configured as the bottom wall of the second ground hole 113, and the P-type semiconductor layer 130 is disposed on the sidewall and bottom wall of the second ground hole 113. Specifically, when the N-type semiconductor layer 120 is actually prepared, the N-type semiconductor material can be directly deposited on the sidewall and bottom wall of the first ground hole 111 through a deposition process to form the N-type semiconductor layer 120, and then the P-type semiconductor material can be deposited on the sidewall and bottom wall of the second ground hole 113 through a deposition process again to form the P-type semiconductor layer 130. The N-type semiconductor layer 120 covers the sidewall and bottom wall of the first ground hole 111 at the same time, and the P-type semiconductor layer 130 covers the sidewall and bottom wall of the second ground hole 113 at the same time, which can expand their contact area, thereby increasing the heat absorption area, and further improving the heat dissipation effect.

[0062] In some embodiments, the side of the N-type semiconductor layer 120 away from the first etch stop layer 141 extends to the opening periphery of the first grounding hole 111, and the first back conductive layer 160 partially covers the N-type semiconductor layer 120; the side of the P-type semiconductor layer 130 away from the first etch stop layer 141 extends to the opening periphery of the second grounding hole 113, and the second back conductive layer 170 partially covers the P-type semiconductor layer 130. Specifically, the N-type semiconductor layer 120 can extend to the opening periphery of the first grounding hole 111, and the P-type semiconductor layer 130 can extend to the opening periphery of the second grounding hole 113. On the one hand, the opening range of the N-type semiconductor layer 120 and the P-type semiconductor layer 130 can be expanded, the heat release area can be increased, and the heat dissipation effect can be improved. On the other hand, the N-type semiconductor layer 120 and the first back conductive layer 160, and the P-type semiconductor layer 130 and the second back conductive layer 170 can be fully contacted to ensure the electrical connection effect.

[0063] In some embodiments, the N-type semiconductor layer 120 and the P-type semiconductor layer 130 both include Bi2Te3-Sb2Te3 solid solution, Bi2Te3-Bi2Se3 solid solution, ternary Bi2Te3-S b2 At least one of Te3-Sb2Se3 solid solutions. By using semiconductor materials with Pateer effect and Thomson effect, a ground hole with active heat dissipation function is realized.

[0064] The embodiment of the present invention further provides a method for preparing a heat dissipation ground hole structure 100, which is used to prepare the heat dissipation ground hole structure 100 as described in the above embodiment. The preparation method comprises the following steps:

[0065] S1: providing a device substrate 110.

[0066] See also Figure 8 Specifically, the device substrate 110 may be a substrate of the semiconductor device 200 , so that the device structure and the heat dissipation hole structure can be formed simultaneously.

[0067] S2 : forming a first front conductive layer 140 and a second front conductive layer 150 on the front surface of the device substrate 110 .

[0068] See also Fig. 9 Specifically, first, the preparation of the first front conductive layer 140 and the second front conductive layer 150 is completed on the front side of the substrate. The preparation process of the first front conductive layer 140 and the second front conductive layer 150 can be carried out together with the front process of the semiconductor device 200.

[0069] S3 : forming a first grounding hole 111 and a second grounding hole 113 on the back surface of the device substrate 110 .

[0070] See also Fig.10 Specifically, the first grounding hole 111 and the second grounding hole 113 can be formed by etching at the corresponding positions of the back side of the substrate and the first front conductive layer 140 and the second front conductive layer 150, and at the same time, the source grounding hole 250 of the semiconductor device 200 can be formed by etching. The first front conductive layer 140 and the second front conductive layer 150 can serve as etching stop layers for the first grounding hole 111 and the second grounding hole 113.

[0071] S4 : Disposing an N-type semiconductor layer 120 in the first ground hole 111 .

[0072] See also Fig.11 Specifically, the N-type semiconductor layer 120 may be deposited in the first ground hole 111 by a chemical vapor deposition process or a physical vapor deposition process.

[0073] S5 : a P-type semiconductor layer 130 is disposed in the second ground hole 113 .

[0074] See also Fig.12 Specifically, the P-type semiconductor layer 130 may be deposited in the second ground hole 113 by a chemical vapor deposition process or a physical vapor deposition process.

[0075] S6 : forming a first back side conductive layer 160 and a second back side conductive layer 170 on the back side of the device substrate 110 .

[0076] See also Fig.13 After the preparation of the P-type semiconductor layer 130 is completed, the preparation of the first back metal layer 260 in the source grounding hole 250 of the semiconductor device 200 can be completed, so that the filling step is completed in all grounding holes. Figure 7 , and then a first back conductive layer 160 , a second back conductive layer 170 and a second back metal layer 270 are formed on the back side of the substrate by a partitioned sputtering or deposition process, thereby completing the heat dissipation ground hole structure 100 and the semiconductor device 200 process at the same time.

[0077] Finally, the wire bonding process is completed, so that the gold wire 180 connects the first front conductive layer 140 and the second front conductive layer 150. The N-type semiconductor layer 120 and the P-type semiconductor layer 130 are connected in series, and both the N-type semiconductor layer 120 and the P-type semiconductor layer 130 are configured to transfer the heat on the front side of the device substrate 110 to the back side of the device substrate 110 in the on state.

[0078] It should be noted that the preparation process of the heat dissipation ground hole structure 100 is carried out together with the preparation process of the semiconductor device 200, and the front process, ground hole process and back process can all be universal, so it is fully compatible with existing processes, reducing process costs.

[0079] See also Figures 5 to 7The embodiment of the present invention further provides a semiconductor device 200, comprising a source electrode 210, a drain electrode 220, a gate electrode 230 and the aforementioned heat dissipation ground hole structure 100, the heat dissipation ground hole structure 100, comprising a device substrate 110, an N-type semiconductor layer 120 and a P-type semiconductor layer 130, wherein a first grounding hole 111 and a second grounding hole 113 are provided through the device substrate 110; the N-type semiconductor layer 120 is provided in the first grounding hole 111 and extends to the openings at both ends of the first grounding hole 111; the P-type semiconductor layer 130 is provided in the second grounding hole 113 and extends to the openings at both ends of the second grounding hole 113; wherein the N-type semiconductor layer 120 and the P-type semiconductor layer 130 are connected in series, and both the N-type semiconductor layer 120 and the P-type semiconductor layer 130 are configured to transfer heat from the front side of the device substrate 110 to the back side of the device substrate 110 in a conducting state. The source electrode 210 , the drain electrode 220 , and the gate electrode 230 are all disposed on the device substrate 110 , and are spaced apart from the first ground hole 111 and the second ground hole 113 .

[0080] It should be noted that the semiconductor device 200 here can be a power amplifier, such as a HEMT device, and the arrangement and position of the source electrode 210, the drain electrode 220 and the gate electrode 230 are consistent with those of a conventional HEMT device. In addition, the resistor attached to the heat dissipation ground hole structure 100 can be used in a gate stabilization circuit without increasing the additional chip area.

[0081] In some embodiments, the device substrate 110 is further provided with a source grounding hole 250, a source conductive layer 240 is further provided on the front side of the device substrate 110, the source conductive layer 240 covers the source grounding hole 250 and is connected to the source electrode 210, a first back metal layer 260 is provided in the source grounding hole 250, a second back metal layer 270 is further provided on the back side of the device substrate 110, the second back metal layer 270 extends to the source grounding hole 250, and the first back metal layer 260 is in electrical contact with the source conductive layer 240 and the second back metal layer 270 at the same time.

[0082] It should be noted that, in this embodiment, the first front conductive layer 140 and the second front conductive layer 150 may preferably be close to the gate electrode 230, so as to achieve fixed-point heat dissipation, effectively reduce the junction temperature of the HEMT device (ranging from 10 degrees to 40 degrees), increase the output power of the device, improve the power added efficiency, increase the maximum operating temperature, and increase the device life.

[0083] The embodiment of the present invention further provides a method for preparing a semiconductor device 200, which is used to prepare the aforementioned semiconductor device 200. The method comprises the following steps:

[0084] Step 1: Complete the front side process of the semiconductor device 200 .

[0085] See also Fig. 9 Specifically, the gate electrode 230, the source electrode 210, and the drain electrode 220 can be prepared on the front side of the substrate, and the first front side conductive layer 140, the second front side conductive layer 150 and the source conductive layer 240 can be formed. The front side process can refer to the existing HEMT device.

[0086] Step 2: A first grounding hole 111 , a second grounding hole 113 and a source grounding hole 250 are formed by etching on the back side of the substrate.

[0087] See also Fig.10 Specifically, the first grounding hole 111, the second grounding hole 113 and the source grounding hole 250 can be etched together, the first grounding hole 111 is etched at a corresponding position of the first front conductive layer 140, the second grounding hole 113 is etched at a corresponding position of the second front conductive layer 150, and the source grounding hole 250 is formed at a corresponding position of the source conductive layer 240.

[0088] Step 3: forming an N-type semiconductor layer 120 in the first ground hole 111 .

[0089] See also Fig.11 Specifically, a photoresist may be disposed on the back side of the substrate, and the first grounding hole 111 may be exposed by a photolithography and development process, and the photoresist may be removed after the N-type semiconductor layer 120 is deposited, so that the N-type semiconductor layer 120 is deposited and formed in the first grounding hole 111 .

[0090] Step 4: forming a P-type semiconductor layer 130 in the second ground hole 113 .

[0091] See also Fig.12 Specifically, a photoresist may be disposed on the back side of the substrate, and the second grounding hole 113 may be exposed by a photolithography and development process, and the photoresist may be removed after the P-type semiconductor layer 130 is deposited, so that the P-type semiconductor layer 130 is deposited and formed in the second grounding hole 113 .

[0092] Step 5: forming a first back metal layer 260 in the source grounding hole 250 .

[0093] See also Fig.13 Specifically, a photoresist may be disposed on the back side of the substrate, and the source grounding hole 250 may be exposed by a photolithography development process, and the first back metal layer 260 may be deposited or sputtered and then the photoresist may be removed, so that the first back metal layer 260 is formed in the source grounding hole 250 .

[0094] Step 6: Complete the preparation of the back metal.

[0095] Please continue to see Figure 7Specifically, the first back conductive layer 160, the second back conductive layer 170 and the second back metal layer 270 can all be made of the same metal, such as copper, so the first back conductive layer 160, the second back conductive layer 170 and the second back metal layer 270 can be formed by simultaneous deposition or sputtering. The first back conductive layer 160 and the second back conductive layer 170 in the same heat dissipation ground hole structure 100 are spaced apart, and the first back conductive layer 160 and the second back conductive layer 170 in adjacent heat dissipation ground hole structures 100 are connected. At the same time, the second back metal layer 270 can be spaced apart from the first back conductive layer 160 and the second back conductive layer 170 at the same time.

[0096] Through the above technical solution, the embodiment of the present invention opens the first grounding hole 111 and the second grounding hole 113 on the device substrate 110, and fills the first grounding hole 111 and the second grounding hole 113 with N-type semiconductor and P-type semiconductor. In the on state, a positive voltage can be applied to the N-type heat dissipation hole, and a negative voltage can be applied to the P-type heat dissipation hole. The electron flow in the N-type semiconductor is from the front side to the back side of the device substrate 110, and the hole flow in the P-type semiconductor is also from the front side to the back side of the device substrate 110. Due to the Peltier effect and the Thomson effect, the end of the N-type semiconductor layer 120 and the P-type semiconductor layer 130 close to the front side of the device substrate 110 will form a heat absorption end, thereby absorbing additional heat, and the end close to the back side will form a heat release section, thereby releasing additional heat, so as to achieve the effect of actively transporting heat from the front side to the back side. Compared with the prior art, the embodiment of the present invention utilizes the Peltier effect and the Thomson effect in combination with the ground hole structure to realize heat transfer, which greatly improves the heat dissipation capacity of the first ground hole 111 and the second ground hole 113, can achieve good heat dissipation effect, realize active heat dissipation, and thus can improve the power and maximum operating temperature of the HEMT device.

[0097] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A heat dissipation hole structure, characterized in that: include: A device substrate (110), wherein a first grounding hole (111) and a second grounding hole (113) are provided through the device substrate (110); An N-type semiconductor layer (120), the N-type semiconductor layer (120) being arranged in the first grounding hole (111) and extending to openings at both ends of the first grounding hole (111); A P-type semiconductor layer (130), the P-type semiconductor layer (130) being arranged in the second grounding hole (113) and extending to openings at both ends of the second grounding hole (113); The N-type semiconductor layer (120) and the P-type semiconductor layer (130) are connected in series, and both the N-type semiconductor layer (120) and the P-type semiconductor layer (130) are configured to transfer heat from the front side of the device substrate (110) to the back side of the device substrate (110) in a conducting state.

2. The heat dissipation ground hole structure according to claim 1, characterized in that: The heat dissipation ground hole structure further comprises a first front conductive layer (140) and a second front conductive layer (150), wherein the first front conductive layer (140) is arranged on the front side of the device substrate (110) and covers the first ground hole (111); the N-type semiconductor layer (120) is at least arranged on the side wall of the first ground hole (111) and is in electrical contact with the first front conductive layer (140); The second front conductive layer (150) is arranged on the front side of the device substrate (110) and covers the second grounding hole (113); the P-type semiconductor layer (130) is at least arranged on the side wall of the second grounding hole (113) and is in electrical contact with the second front conductive layer (150); The first front conductive layer (140) and the second front conductive layer (150) are electrically connected, the N-type semiconductor layer (120) is configured to transfer heat from the first front conductive layer (140) to the back side of the device substrate (110) in an on state, and the P-type semiconductor layer (130) is configured to transfer heat from the second front conductive layer (150) to the back side of the device substrate (110) in an on state.

3. The heat dissipation ground hole structure according to claim 2, characterized in that: The heat dissipation ground hole structure further comprises a first back side conductive layer (160) and a second back side conductive layer (170), wherein the first back side conductive layer (160) is arranged on the back side of the device substrate (110) and extends to the first ground hole (111), and the N-type semiconductor layer (120) is in electrical contact with the first back side conductive layer (160); The second back side conductive layer (170) is arranged on the back side of the device substrate (110) and extends to the second grounding hole (113); the P-type semiconductor layer (130) is in electrical contact with the second back side conductive layer (170).

4. The heat dissipation ground hole structure according to claim 3, characterized in that: The first back side conductive layer (160) and the second back side conductive layer (170) in the same heat dissipation ground hole structure are arranged at intervals, and the first back side conductive layer (160) is configured to be in electrical contact with the second back side conductive layer (170) in an adjacent heat dissipation ground hole structure, and the second back side conductive layer (170) is configured to be in electrical contact with the first back side conductive layer (160) in an adjacent heat dissipation ground hole structure.

5. The heat dissipation ground hole structure according to claim 3, characterized in that: A gold wire (180) is provided between the first front conductive layer (140) and the second front conductive layer (150), and the first front conductive layer (140) and the second front conductive layer (150) are electrically connected via the gold wire (180).

6. The heat dissipation ground hole structure according to claim 3, characterized in that: The first front conductive layer (140) comprises a first etch barrier layer (141) and a first front metal layer (143), the first etch barrier layer (141) being arranged on the front side of the device substrate (110) and covering the first grounding hole (111), and the first front metal layer (143) being arranged on the front side of the device substrate (110) and covering the first etch barrier layer (141); The second front conductive layer (150) comprises a second etch barrier layer (151) and a second front metal layer (153); the second etch barrier layer (151) is arranged on the front side of the device substrate (110) and covers the second grounding hole (113); the second front metal layer (153) is arranged on the front side of the device substrate (110) and covers the second etch barrier layer (151).

7. The heat dissipation ground hole structure according to claim 6, characterized in that: The first etch stop layer (141) is configured as the bottom wall of the first ground hole (111), and the N-type semiconductor layer (120) is arranged on the side walls and the bottom wall of the first ground hole (111); the second etch stop layer (151) is configured as the bottom wall of the second ground hole (113), and the P-type semiconductor layer (130) is arranged on the side walls and the bottom wall of the second ground hole (113).

8. The heat dissipation ground hole structure according to claim 6, characterized in that: A side of the N-type semiconductor layer (120) away from the first etching stop layer (141) extends to the opening periphery of the first grounding hole (111), and the first back conductive layer (160) partially covers the N-type semiconductor layer (120); A side of the P-type semiconductor layer (130) away from the first etching stop layer (141) extends to the opening periphery of the second grounding hole (113), and the second back conductive layer (170) partially covers the P-type semiconductor layer (130).

9. The heat dissipation ground hole structure according to any one of claims 1 to 8, characterized in that: The N-type semiconductor layer (120) and the P-type semiconductor layer (130) both include Bi2Te3-Sb2Te3 solid solution, Bi2Te3-Bi2Se3 solid solution, ternary Bi2Te3-S b2 At least one of Te3-Sb2Se3 solid solutions.

10. A semiconductor device, characterized in that: comprising a source electrode (210), a drain electrode (220), a gate electrode (230) and a heat dissipation ground hole structure according to any one of claims 1 to 9, wherein the source electrode (210), the drain electrode (220) and the gate electrode (230) are all arranged on the device substrate (110) and are spaced apart from the first ground hole (111) and the second ground hole (113); The device substrate (110) is also provided with a source grounding hole (250) penetrating therethrough; a source conductive layer (240) is also provided on the front side of the device substrate (110); the source conductive layer (240) covers the source grounding hole (250) and is connected to the source electrode (210); a first back metal layer (260) is provided in the source grounding hole (250); a second back metal layer (270) is also provided on the back side of the device substrate (110); the second back metal layer (270) extends to the source grounding hole (250); and the first back metal layer (260) is in electrical contact with both the source conductive layer (240) and the second back metal layer (270).

11. A method for preparing a heat dissipation hole structure, characterized in that: Used to prepare the heat dissipation ground hole structure according to claim 1, the preparation method comprising: Providing a device substrate (110); forming a first grounding hole (111) and a second grounding hole (113) on the device substrate (110); An N-type semiconductor layer (120) is arranged in the first grounding hole (111); A P-type semiconductor layer (130) is provided in the second grounding hole (113); The N-type semiconductor layer (120) and the P-type semiconductor layer (130) are connected in series, and both the N-type semiconductor layer (120) and the P-type semiconductor layer (130) are configured to transfer heat from the front side of the device substrate (110) to the back side of the device substrate (110) in a conducting state.

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