Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a semiconductor device manufacturing method. The purpose of the present invention is to improve the heat dissipation performance of a semiconductor device without increasing the size. A semiconductor device (101) is provided with: a base material; a semiconductor chip (3) mounted on the upper surface of the substrate; a main electrode and a signal electrode (31) respectively formed in different regions on the semiconductor chip (3); a main terminal (5) joined to the main electrode; and a signal terminal (6) connected to the signal electrode (31) via a metal wire (7), the signal terminal (6) having a region where the metal wire (7) is bonded suspended above the base material in a state separated from the base material.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Art

[0002] Generally, wire bonding is used when forming internal wiring of a semiconductor device, and the wire bonding uses metal wires. However, in semiconductor devices that seek high reliability for automotive applications, the main terminals are often directly bonded to the semiconductor chip by solder (for example, see Patent Document 1). The semiconductor module of Patent Document 1 describes a semiconductor module that improves heat dissipation and reliability by improving the adhesion between the semiconductor device and the heat sink fins.

[0003] Patent Document 1: International Publication No. 2020 / 245996

[0004] In the prior art, the heat generated by the power supply of the semiconductor chip is mainly diffused laterally through the heat sink, and then dissipated to the heat sink fins. The larger the area of ​​the heat sink, the more heat can be diffused laterally, and the heat can be dissipated to the heat sink fins over a wider area, but there is a problem of large-scale semiconductor devices. Summary of the invention

[0005] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to improve the heat dissipation of a semiconductor device without increasing its size.

[0006] The semiconductor device of the present invention comprises: a substrate; a semiconductor chip mounted on the upper surface of the substrate; a main electrode and a signal electrode, which are respectively formed in different areas on the semiconductor chip; a main terminal joined to the main electrode; and a signal terminal connected to the signal electrode via a metal wire, wherein the area of ​​the signal terminal joined to the metal wire is suspended above the substrate in a state separated from the substrate.

[0007] Effects of the Invention

[0008] According to the semiconductor device of the present invention, even if the substrate is expanded in the lateral direction, there is no interference with the signal terminals, and thus the heat dissipation performance can be improved without increasing the size. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0010] Figure 2 It is a top view of the semiconductor device according to the first embodiment.

[0011] Figure 3 It is a cross-sectional view of a semiconductor device according to a comparative example.

[0012] Figure 4 It is a top view of a semiconductor device according to a comparative example.

[0013] Figure 5 It is a cross-sectional view showing the process of bonding a metal wire to the front end of a signal terminal in the semiconductor device involved in the comparative example.

[0014] Figure 6 It is a cross-sectional view showing the process of bonding a metal wire to the front end of a signal terminal in the semiconductor device according to Embodiment 1.

[0015] Figure 7 It is a cross-sectional view showing the process of bonding a metal wire to the front end of a signal terminal in the semiconductor device according to Embodiment 1.

[0016] Figure 8 It is a top view showing the process of bonding a metal wire to the front end of a signal terminal in the semiconductor device according to Embodiment 1.

[0017] Fig. 9 It is a cross-sectional view of the semiconductor device according to the first modification of Embodiment 1.

[0018] Fig.10 It is a cross-sectional view of the semiconductor device according to the second modification of Embodiment 1.

[0019] Fig.11 It is a cross-sectional view of the semiconductor device according to Embodiment 2.

[0020] Fig.12 It is a top view of the semiconductor device according to Embodiment 2.

[0021] Fig.13 It is a top view showing the signal terminal traces on the heat sink of the semiconductor device according to Embodiment 2. Detailed Embodiments

[0022] <A. Embodiment 1>

[0023] <A-1. Structure>

[0024] Figure 1 It is a cross-sectional view showing the structure of the semiconductor device 101 according to Embodiment 1. Figure 2 It is a top view showing the structure of the semiconductor device 101. Hereinafter, Figure 1 and Figure 2 are used to explain the structure of the semiconductor device 101.

[0025] The semiconductor device 101 is configured to include a heat sink 1, a chip bonding material 2, a semiconductor chip 3, a main terminal bonding material 4, a main terminal 5, a signal terminal 6, a metal wire 7, a packaging material 8, an insulating sheet 9, and a metal foil 10.

[0026] The heat sink 1 is a plate-shaped component with a thickness of 3 mm and mainly made of Cu. The heat sink 1 is an example of a substrate bonded to a semiconductor chip 3. Two semiconductor chips 3 are bonded to the upper surface of the heat sink 1 via a die bonding material 2. The die bonding material 2 is, for example, solder. The semiconductor chip 3 is, for example, an IGBT (Insulated Gate Bipolar Transistor) and a FWD (Free Wheel Diode).

[0027] An insulating sheet 9 is attached to the lower surface of the heat sink 1 . A metal foil 10 is attached to the surface of the insulating sheet 9 on the opposite side to the heat sink 1 .

[0028] On the surface of the semiconductor chip 3 opposite to the heat sink 1, i.e., the upper surface, the main electrode (not shown) and the signal electrode 31 are formed in separate areas from each other. The main electrode is an electrode for inputting and outputting the main current. The end of the main terminal 5 is bonded to the main electrode by the main terminal bonding material 4. The main terminal 5 is a terminal through which the main current flows. The main terminal bonding material 4 is, for example, solder. The signal electrode 31 is an electrode for inputting and outputting a control signal or a sensing signal. The end of the signal terminal 6 is connected to the signal electrode 31 by a metal wire 7. That is, the signal electrode 31 and the signal terminal 6 are connected by a wire bonding method. The signal terminal 6 is a terminal through which a control signal or a sensing signal flows. The metal wire 7 is a wire with a diameter of 200μm with Al as the main material.

[0029] At least a part of the heat sink 1 , the die bonding material 2 , the semiconductor chip 3 , the main terminal bonding material 4 , the main terminal 5 , the signal terminal 6 , the metal wire 7 , the insulating sheet 9 , and the metal foil 10 is encapsulated by an encapsulating material 8 made of an insulating resin.

[0030] The ends of the main terminals 5 and the signal terminals 6 that are not connected to the semiconductor chip 3 are exposed from the packaging material 8 and function as external terminals. At least a portion of the lower surface of the metal foil 10 on the opposite side of the heat sink 1 is exposed from the packaging material 8 and is connected to the heat sink fins when the semiconductor device 101 is installed in a power conversion device or the like.

[0031] The signal terminal 6 is separated from the heat sink 1 by 1.5 mm in the thickness direction of the semiconductor device 101. In addition, the end of the signal terminal 6 connected to the metal wire 7 is suspended above the heat sink 1 with a gap of 5 mm. In other words, the end of the signal terminal 6 connected to the metal wire 7 overlaps with the heat sink 1 when viewed from above. The main terminal 5 is also suspended above the heat sink 1 in the same manner as the signal terminal 6. However, the main terminal 5 is Figure 1 The left side of the radiator is suspended above the heat sink 1, and the signal terminal 6 is Figure 1 The right side of the signal terminal 6 is suspended above the heat sink 1. In this way, the signal terminal 6 is suspended above the heat sink 1 from a direction different from the main terminal 5 by 180 degrees.

[0032] Figure 3 This is a cross-sectional view showing the structure of the semiconductor device 100 related to the comparative example. Figure 4 This is a top view showing the structure of the semiconductor device 100. As Figure 3 and Figure 4 shown, in the semiconductor device 100, the end of the signal terminal 6 that is joined to the metal wire 7 is arranged so as not to overlap with the heat sink 1 when viewed from above.

[0033] <A-2. Manufacturing Process>

[0034] Figure 5 This is a cross-sectional view showing the manufacturing process of the semiconductor device 100. In the manufacturing process of the semiconductor device 100, the semiconductor chip 3 is joined to the heat sink 1 via the chip bonding material 2. After that, the main terminal 5 is joined to the main electrode of the semiconductor chip 3. After that, the signal electrode 31 on the semiconductor chip 3 and the signal terminal 6 are joined by the metal wire 7.

[0035] At this time, as Figure 5 shown, the signal terminal 6 is joined to the metal wire 7 in a state of being clamped and fixed by the lower fixing jig 21 and the upper fixing claw 22. Since the fixing jig 21 is arranged directly below the region where the signal terminal 6 is joined to the metal wire 7, it is impossible to make the front end of the signal terminal 6 hang over the heat sink 1. Therefore, when the heat sink 1 is laterally enlarged to improve the heat dissipation of the semiconductor device 100, it is necessary to arrange the signal terminal 6 on the outer side in a non-overlapping manner with the heat sink 1, which results in the enlargement of the semiconductor device 100. In addition, since the distance between the signal terminal 6 and the semiconductor chip 3 becomes larger, the wiring length of the metal wire 7 becomes longer. As a result, the metal wire 7 is likely to be deformed during the transportation or resin encapsulation in the middle of the manufacturing of the semiconductor device 100. If the metal wire 7 is deformed, it may cause abnormal characteristics such as short circuit due to contact with components at different potentials.

[0036] Figure 6 and Figure 7 This is a cross-sectional view showing the manufacturing process of the semiconductor device 101 related to Embodiment 1. In the manufacturing process of the semiconductor device 101, the semiconductor chip 3 is joined to the heat sink 1 via the chip bonding material 2. After that, the main terminal 5 is joined to the main electrode of the semiconductor chip 3. After that, the signal electrode 31 on the semiconductor chip 3 and the signal terminal 6 are joined by the metal wire 7.

[0037] At this time, as Figure 6As shown in the figure, the signal terminal 6 is clamped by the lower heat sink 1 and the upper fixing claw 22, and the end of the signal terminal 6 is pressed onto the heat sink 1, and the metal wire 7 is bonded. In addition, the heat sink 1 is supported from below by the fixing jig 21. That is, in the manufacturing process of the semiconductor device 100 of the comparative example, the fixing jig 21 plays the role of supporting the signal terminal 6 from below, but in the manufacturing process of the semiconductor device 101 involved in the first embodiment, the heat sink 1 plays this role.

[0038] If the bonding of the metal wire 7 is completed, Figure 7 As shown, the push of the signal terminal 6 by the fixing claw 22 is released. Then, the elastic deformation of the signal terminal 6 caused by the push of the fixing claw 22 is restored, and the signal terminal 6 is separated from the heat sink 1 again. In addition, it is described here that the fixing claw 22 is pushed to the signal terminal 6 from above in a state where the fixing clamp 21 is arranged on the lower side of the heat sink 1, thereby fixing the signal terminal 6 relative to the heat sink 1. However, it is also possible to fix the signal terminal 6 relative to the heat sink 1 by raising the fixing clamp 21 and pushing up the heat sink 1 from below in a state where the fixing claw 22 is arranged on the upper side of the signal terminal 6. Alternatively, the signal terminal 6 may be fixed relative to the heat sink 1 by simultaneously raising the fixing clamp 21 and pushing the fixing claw 22.

[0039] In the semiconductor device 101, the signal terminal 6 is suspended above the heat sink 1 in a state separated from the heat sink 1. Therefore, even if the heat sink 1 is expanded laterally to improve the heat dissipation, it will not interfere with the signal terminal 6, so there is no need to move the signal terminal 6 to the outside of the heat sink 1. Therefore, the semiconductor device 101 can improve the heat dissipation without increasing the size. In addition, in the semiconductor device 101, since it is not necessary to move the signal terminal 6 to the outside of the heat sink 1, the wiring length of the metal wire 7 will not increase. As a result, the occurrence of characteristic abnormalities associated with the deformation of the metal wire 7 is suppressed. In the semiconductor device 101, since the signal terminal 6 is separated from the heat sink 1, the two will not be short-circuited, and malfunction will not occur.

[0040] Figure 8FIG. 0 is a plan view showing the manufacturing process of the semiconductor device 101, illustrating the process of bonding the metal wire 7 to the signal terminal 6. In the process of bonding the metal wire 7 to the signal terminal 6, the main terminal 5 and the signal terminal 6 are integrated as a lead frame. This lead frame is fixed to the heat sink 1 via the semiconductor chip 3 at the portion where the main terminal 5 is bonded to the semiconductor chip 3. When bonding the metal wire 7 to the signal terminal 6, as described above, the front end of the signal terminal 6 is pressed against the heat sink 1. As a result, the portion of the lead frame from the front end of the signal terminal 6 to the bonding portion of the main terminal 5 with the semiconductor chip 3 (hereinafter, simply referred to as "the bonding portion of the main terminal 5") is deformed. The longer the distance from the front end of the signal terminal 6 to the bonding portion of the main terminal 5, the more the damage to the bonding portion of the main terminal 5 caused by pressing the signal terminal 6 is reduced. In the semiconductor device 101, as described above, the signal terminal 6 hangs over the heat sink 1 from a direction 180° different from that of the main terminal 5, so the distance from the front end of the signal terminal 6 to the bonding portion of the main terminal 5 becomes long, and the damage to the bonding portion of the main terminal 5 is suppressed to the minimum.

[0041] <A-3. First Modified Example>

[0042] Fig. 9 FIG. 7 is a cross-sectional view of the semiconductor device 101A according to the first modified example of Embodiment 1. The difference between the semiconductor device 101A and the semiconductor device 101 according to Embodiment 1 is that the semiconductor chip 3 is bonded to the insulating substrate 11 instead of the heat sink 1. That is, in the semiconductor device 101A, the base material bonded to the semiconductor chip 3 is the insulating substrate 11 instead of the heat sink 1. The insulating substrate 11 is composed of an insulating layer 12, a conductive pattern 14, and a conductive pattern 13. The insulating layer 12 is made of ceramic, the conductive pattern 14 is formed on the upper surface of the insulating layer 12 and is made of Cu, and the conductive pattern 13 is formed on the lower surface of the insulating layer 12 and is made of Cu. At least a part of the lower surface of the conductive pattern 13, which is the surface opposite to the insulating layer 12, is exposed from the encapsulation material 8. A plurality of semiconductor chips 3 are bonded to the upper surface of the conductive pattern 14, which is the surface opposite to the insulating layer 12, via the chip bonding material 2. The insulating layer 12 may also be an insulating resin. In addition, other metals such as Al may be used for the conductive patterns 13 and 14.

[0043] In the semiconductor device 101A, miniaturization is also achieved by suspending the signal terminal 6 over the insulating substrate 11.

[0044] <A-4. Second Modified Example>

[0045] Fig.10It is a cross-sectional view of the semiconductor device 101B according to the second modification of Embodiment 1. The difference between the semiconductor device 101B and the semiconductor device 101 according to Embodiment 1 is that the semiconductor chip 3 is bonded to the chip pad 15 formed by the lead frame instead of being bonded to the heat sink 1. That is, in the semiconductor device 101B, the base material bonded to the semiconductor chip 3 is the lead frame instead of the heat sink 1.

[0046] In the semiconductor device 101B, miniaturization is also achieved by suspending the signal terminal 6 above the chip pad 15.

[0047] <A-5. Other Modifications>

[0048] The chip bonding material 2 and the main terminal bonding material 4 can be a conductive adhesive or a sintered bonding material containing Ag or Cu particles in addition to solder. By using the sintered bonding material as the chip bonding material 2 and the main terminal bonding material 4, the heat dissipation performance and the life of the bonding part can be improved compared with the case of solder bonding.

[0049] The semiconductor chip 3 is not limited to IGBT and FWD composed of Si. For example, it can also be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). As the semiconductor material of the semiconductor chip 3, a wide-bandgap semiconductor such as SiC (silicon carbide), GaN (gallium nitride), or diamond with a bandgap larger than that of Si can also be used. The bandgap of the wide-bandgap semiconductor is greater than or equal to 2 eV. In this case, in order to utilize the advantages of the material with a large bandgap and seek high-temperature operation of the semiconductor device 101, the effect of this embodiment of improving the heat dissipation performance will be more significantly obtained.

[0050] Above, the case where the signal terminal 6 is suspended above the heat sink at a spacing of 5 mm in a state where the signal terminal 6 is separated from the heat sink 1 by 1.5 mm has been described. However, the separation distance between the signal terminal 6 and the heat sink 1 is greater than or equal to 0.5 mm and less than or equal to 2 mm, and the overhang amount is less than or equal to 20 mm. The overhang amount is the length in the left-right direction of the overlapping part of the signal terminal 6 and the heat sink 1 in Figure 1 If this condition is satisfied, if the fixing is released after bonding the metal wire 7, the signal terminal 6 will be separated from the heat sink 1.

[0051] Above, the structure in which the insulating sheet 9 and the metal foil 10 are mounted on the lower surface of the heat sink 1 has been described. However, it is also possible to ensure insulation at the lower surface of the heat sink 1 by covering the lower surface of the heat sink 1 with the encapsulation material 8.

[0052] Above, the case where the signal terminal 6 is suspended above the heat sink 1 from a direction 180° different from the main terminal 5 has been described. However, even when the signal terminal 6 is suspended above the heat sink 1 from a direction 90° different from the main terminal 5, the distance from the tip of the signal terminal 6 to the joint portion of the main terminal 5 can be obtained, so that the damage to the joint portion of the main terminal 5 caused by pushing the signal terminal 6 can be suppressed.

[0053] Preferably, the area of the heat sink 1 is greater than or equal to twice the area of the semiconductor chip 3, and the distance from the end of the semiconductor chip 3 to the end of the heat sink 1 is greater than or equal to the thickness of the heat sink 1. With this configuration, the heat generated by the semiconductor chip 3 is effectively diffused laterally in the heat sink 1, resulting in high heat dissipation.

[0054] Above, the diameter of the metal wire 7 was set to 200 μm, and its main material was Al. However, the diameter and material of the metal wire 7 can be selected corresponding to the heat generation and deformation of the metal wire 7 during resin encapsulation. If the diameter of the metal wire 7 is greater than or equal to 100 μm and less than or equal to 500 μm, and its material is mainly Al or Cu, the occurrence of defects caused by the heat generation of the metal wire 7 and the deformation during resin encapsulation can be suppressed.

[0055] <B. Embodiment 2>

[0056] <B-1. Structure>

[0057] Fig.11 It is a cross-sectional view of the semiconductor device 102 according to Embodiment 2. Fig.12 It is a top view of the semiconductor device 102. Fig.13 It is a top view showing the signal terminal traces on the heat sink 1 of the semiconductor device 102.

[0058] The difference between the semiconductor device 102 and the semiconductor device 101 according to Embodiment 1 is only that a pit 16 is formed on the upper surface of the heat sink 1. The pit 16 is formed in at least a part of the upper surface of the heat sink 1 other than the region where the signal terminal 6 is suspended and the joint region of the semiconductor chip 3.

[0059] The purpose of forming the pits 16 is to improve the adhesion between the heat sink 1 and the encapsulation material 8. Since the pits 16 become holes in the chip bonding material 2, they are usually formed on the entire upper surface of the heat sink 1 except directly below the semiconductor chip 3. However, when the signal terminals 6 are pressed against the heat sink 1 and the metal wires 7 are bonded by wire bonding, if there are pits 16 directly below the bonding portions of the metal wires 7, the metal wires 7 will be bonded to the signal terminals 6 in a hollow state. Therefore, it is considered that the bonding of the metal wires 7 cannot be completed normally, peeling will occur, and the bonding reliability will be reduced.

[0060] To address this problem, in the semiconductor device 102, the area above the heat sink 1 where the signal terminals 6 are suspended is flat without pits 16. Therefore, even when the signal terminals 6 are pressed against the heat sink 1 to bond the metal wires 7, the bonding can be completed normally, and both the bonding reliability of the metal wires 7 and the adhesion of the encapsulation material 8 can be taken into account.

[0061] In addition, by pressing the signal terminals 6 against the heat sink 1, traces of pressing the signal terminals 6 are formed on the heat sink 1 as the signal terminal traces 17. The signal terminal traces are damages or depressions having the same shape as the signal terminals 6. When the metal wires 7 are bonded to the signal terminals 6 by wire bonding, if the signal terminals 6 are not sufficiently fixed, the bonding cannot be completed normally. In this regard, in the present embodiment, after the metal wires 7 are bonded by pressing the signal terminals 6 against the heat sink 1, by checking the signal terminal traces 17 on the heat sink 1, it can be confirmed that the signal terminals 6 are sufficiently fixed.

[0062] In the present embodiment, the case of mounting the semiconductor chip 3 on the heat sink 1 has been described, but the modification example of Embodiment 1 can also be applied to the present embodiment. That is, in the present embodiment, an insulating substrate 11 or a chip pad 15 can be used instead of the heat sink 1.

[0063] <B-2. Effects>

[0064] As described above, the preferred embodiments and the like have been described in detail, but are not limited to the above embodiments and the like. Various modifications and substitutions can be made to the above embodiments and the like without exceeding the scope described in the claims.

[0065] Next, the aspects of the present invention will be summarized and described as appendices.

[0066] (Appendix 1)

[0067] A semiconductor device, comprising:

[0068] A substrate;

[0069] a semiconductor chip mounted on the upper surface of the substrate;

[0070] A main electrode and a signal electrode, which are respectively formed in different areas on the semiconductor chip;

[0071] a main terminal joined to the main electrode; and

[0072] a signal terminal connected to the signal electrode via a metal wire,

[0073] The region of the signal terminal to which the metal wire is bonded is suspended above the substrate in a state of being separated from the substrate.

[0074] (Note 2)

[0075] The semiconductor device according to Supplementary Note 1, wherein:

[0076] The substrate is a heat sink, a lead frame or an insulating substrate.

[0077] (Note 3)

[0078] The semiconductor device according to Supplement 1 or 2, wherein:

[0079] A recess is formed in at least a portion of the upper surface of the substrate other than a region where the signal terminal is suspended and a region where the semiconductor chip is bonded.

[0080] (Note 4)

[0081] A semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0082] Traces resulting from pressing the signal terminals are formed on the substrate at positions corresponding to the signal terminals.

[0083] (Note 5)

[0084] A semiconductor device according to any one of Supplementary Notes 1 to 4, wherein:

[0085] The separation distance between the signal terminal and the substrate is greater than or equal to 0.5 mm and less than or equal to 2 mm,

[0086] The overhang amount of the signal terminal relative to the substrate is less than or equal to 20 mm.

[0087] (Note 6)

[0088] A semiconductor device according to any one of Supplementary Notes 1 to 5, wherein:

[0089] The signal terminal and the main terminal are suspended above the substrate from directions that differ by 90° or 180°.

[0090] (Note 7)

[0091] A semiconductor device according to any one of Supplementary Notes 1 to 6, wherein:

[0092] The semiconductor chip is made of a wide bandgap semiconductor.

[0093] (Note 8)

[0094] A semiconductor device according to any one of Supplementary Notes 1 to 7, wherein:

[0095] The area of ​​the substrate is greater than or equal to twice the area of ​​the semiconductor chip,

[0096] A distance from an end of the semiconductor chip to an end of the substrate is greater than or equal to a thickness of the substrate.

[0097] (Note 9)

[0098] A method for manufacturing a semiconductor device, comprising:

[0099] Step (a), bonding a semiconductor chip to a substrate;

[0100] Step (b), bonding a main terminal to a main electrode of the semiconductor chip; and

[0101] Step (c), bonding the signal terminal to the signal electrode of the semiconductor chip via a metal wire,

[0102] In the step (c), the metal wire is bonded to the end of the signal terminal in a state where the end of the signal terminal is pressed onto the substrate.

[0103] Description of the label

[0104] 1 heat sink, 2 chip bonding material, 3 semiconductor chip, 4 main terminal bonding material, 5 main terminal, 6 signal terminal, 7 metal wire, 8 packaging material, 9 insulating sheet, 10 metal foil, 11 insulating substrate, 12 insulating layer, 13, 14 conductive pattern, 15 chip pad, 16 pit, 17 signal terminal trace, 21 fixing fixture, 22 fixing claw, 31 signal electrode, 100, 101, 101A, 101B, 102 semiconductor device.

Claims

1. A semiconductor device comprising: Base material; a semiconductor chip mounted on the upper surface of the substrate; A main electrode and a signal electrode, which are respectively formed in different areas on the semiconductor chip; a main terminal joined to the main electrode; as well as a signal terminal connected to the signal electrode via a metal wire, The region of the signal terminal to which the metal wire is bonded is suspended above the substrate in a state of being separated from the substrate.

2. The semiconductor device according to claim 1, wherein The substrate is a heat sink, a lead frame or an insulating substrate.

3. The semiconductor device according to claim 1 or 2, wherein: A recess is formed in at least a portion of the upper surface of the substrate other than a region where the signal terminal is suspended and a region where the semiconductor chip is bonded.

4. The semiconductor device according to any one of claims 1 to 3, wherein: Traces resulting from pressing the signal terminals are formed on the substrate at positions corresponding to the signal terminals.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The separation distance between the signal terminal and the substrate is greater than or equal to 0.5 mm and less than or equal to 2 mm, The overhang amount of the signal terminal relative to the substrate is less than or equal to 20 mm.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The signal terminal and the main terminal are suspended above the substrate from directions that differ by 90° or 180°.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor chip is made of a wide bandgap semiconductor.

8. The semiconductor device according to any one of claims 1 to 7, wherein: The area of ​​the substrate is greater than or equal to twice the area of ​​the semiconductor chip, A distance from an end of the semiconductor chip to an end of the substrate is greater than or equal to a thickness of the substrate.

9. A method for manufacturing a semiconductor device, comprising: Step (a), bonding a semiconductor chip to a substrate; Step (b), bonding the main terminal to the main electrode of the semiconductor chip; as well as Step (c), bonding the signal terminal to the signal electrode of the semiconductor chip via a metal wire, In the step (c), the metal wire is bonded to the end of the signal terminal in a state where the end of the signal terminal is pressed onto the substrate.

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