Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes an encapsulation material that at least partially encapsulates a semiconductor component of the semiconductor device. The semiconductor device further includes a first lead protruding from a first side surface of the encapsulation material and a second lead protruding from a second side surface of the encapsulation material opposite the first side surface. The first lead includes a first notch aligned with a first side surface of the encapsulation material. The first notch faces away from other leads protruding from a first side surface of the encapsulation material.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and methods for manufacturing such semiconductor devices. Background Art

[0002] Semiconductor devices and applications using semiconductor devices may need to comply with electrical isolation requirements defined by associated safety standards. One or more components of a semiconductor device may be encapsulated in a package body. In order to ensure safe operation of the semiconductor device and comply with the electrical isolation requirements, one or more minimum creepage distances may need to be provided between conductive parts protruding from the package body.

[0003] Manufacturers and developers of semiconductor devices are constantly striving to improve their products and methods of manufacturing them. In this regard, it may be desirable to provide semiconductor devices with improved electrical performance and isolation performance. In particular, it may be desirable to protect semiconductor devices from harmful creepage along the surface of the package body. It may also be desirable to provide suitable methods for manufacturing such semiconductor devices. Summary of the invention

[0004] One aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes an encapsulation material that at least partially encapsulates a semiconductor component of the semiconductor device. The semiconductor device also includes a first lead protruding from a first side surface of the encapsulation material and a second lead protruding from a second side surface of the encapsulation material opposite to the first side surface. The first lead includes a first notch aligned with the first side surface of the encapsulation material. The first notch faces away from other leads protruding from the first side surface of the encapsulation material.

[0005] Another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes an encapsulation material that at least partially encapsulates a semiconductor component of the semiconductor device. The semiconductor device also includes a first lead protruding from a first side surface of the encapsulation material and a second lead protruding from a second side surface of the encapsulation material opposite to the first side surface. The cross-section of the first lead narrows toward the first side surface of the encapsulation material.

[0006] Another aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes an operation of providing a semiconductor component. The method also includes an operation of providing a first lead and a second lead, wherein the first lead includes a first recess. The method also includes an operation of at least partially encapsulating the semiconductor component, the first lead, and the second lead in an encapsulation material. The first lead protrudes from a first side surface of the encapsulation material, and the second lead protrudes from a second side surface of the encapsulation material opposite to the first side surface. The first recess is aligned with the first side surface of the encapsulation material. The first recess faces away from the other leads protruding from the first side surface of the encapsulation material.

[0007] Another aspect of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes an operation of providing a semiconductor component. The method also includes an operation of providing a first lead and a second lead. The method also includes an operation of at least partially encapsulating the semiconductor component, the first lead, and the second lead in an encapsulation material. The first lead protrudes from a first side surface of the encapsulation material, and the second lead protrudes from a second side surface of the encapsulation material opposite to the first side surface. The cross-section of the first lead narrows toward the first side surface of the encapsulation material. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The device and method according to the present disclosure are described in more detail below based on the accompanying drawings. The elements of the accompanying drawings are not necessarily drawn to scale relative to each other. Similar reference numerals may represent corresponding similar parts. The technical features of the various examples shown may be combined unless they exclude each other and / or may be selectively omitted if not described as necessary.

[0009] Figure 1 A perspective view of a semiconductor device 100 is schematically shown.

[0010] Figure 2 A top view of a semiconductor device 200 and details thereof according to the present disclosure are schematically shown.

[0011] Figure 3 A top view of a semiconductor device 300 according to the present disclosure is schematically shown.

[0012] Figure 4 A top view of a semiconductor device 400 according to the present disclosure is schematically shown.

[0013] Figure 5 A top view of a semiconductor device 500 according to the present disclosure is schematically shown.

[0014] Figure 6 A top view of a semiconductor device 600 according to the present disclosure is schematically shown.

[0015] Figure 7 A top view of a semiconductor device 700 according to the present disclosure is schematically shown.

[0016] Figure 8 A flow chart of a method for manufacturing a semiconductor device according to the present disclosure is shown.

[0017] Fig. 9 A flow chart of a method for manufacturing a semiconductor device according to the present disclosure is shown. DETAILED DESCRIPTION

[0018] In the following detailed description, reference is made to the accompanying drawings in which specific aspects of the disclosure may be practiced are illustrated by way of illustration. In this regard, directional terms such as "top," "bottom," "front," "rear," and the like may be used with reference to the orientation of the drawings being described. Because components of the described devices may be positioned in a number of different orientations, the directional terms may be used for illustrative purposes and are in no way limiting. Other aspects may be utilized and structural or logical changes may be made without departing from the concepts of the present disclosure. Therefore, the following detailed description should not be considered limiting, and the concepts of the present disclosure are defined by the appended claims.

[0019] Figure 1 The semiconductor device 100 may include an encapsulation material 2 at least partially encapsulating one or more semiconductor components (not shown) of the semiconductor device 100. In addition, the semiconductor device 100 may include a first plurality of first leads (or lead fingers or pins) 4' protruding from a first side surface 6A of the encapsulation material 2 and a second plurality of second leads (or lead fingers or pins) 4" protruding from a second side surface 6B of the encapsulation material 2 opposite to the first side surface 6A. In the example shown, for simplicity, the internal structure of the semiconductor device 100 is not shown.

[0020] The encapsulating material 2 may further include a third side surface 6C and a fourth side surface 6D opposite to the third side surface 6C. The third side surface 6C and the fourth side surface 6D may both connect the first side surface 6A and the second side surface 6B of the encapsulating material 2. In the example shown, each of the third side surface 6C and the fourth side surface 6D may not be provided with any leads protruding from the encapsulating material 2. Each of the four side surfaces 6A to 6D may extend between the top surface 14 and the opposite bottom surface of the encapsulating material 2. Figure 1 The bottom surface is not visible in the selected viewing angle of the image.

[0021] During operation of the semiconductor device 100, the potential of the lead 4A of the first plurality of leads 4', which is closest to the third side surface 6C, may be different from the potential of the lead 4B of the second plurality of leads 4" which is closest to the third side surface 6C. If the creepage distance between the first lead 4A and the second lead 4B is too small, a leakage current path may be formed on the surface of the encapsulation material 2. The creepage distance may be specified as the shortest distance along the surface of a (solid) insulating material between two conductive components. In the example shown, the creepage distance between the leads 4A and 4B is represented by a dotted line. If the leakage current path constitutes a conductive path, a short circuit between the leads 4A and 4B may occur and the semiconductor device 100 may be damaged.

[0022] Sufficiently large creepage distance can be considered one of the key requirements for developing semiconductor devices such as gate drivers, isolated drivers, digital isolators, current sensors, auxiliary power components, or the like. The longer the creepage distance provided by the semiconductor device, the more competitive the developed product may be. However, as the package size continues to decrease, achieving increased creepage distance may become a design challenge.

[0023] Figure 2 The semiconductor device 200 may include Figure 1 The semiconductor device 200 may include some or all of the features of the semiconductor device 100. The semiconductor device 200 may include an encapsulation material 2, a first plurality of first leads 4', a second plurality of second leads 4", a first die pad 8A and a second die pad 8B. In the example shown, the encapsulation material 2 may include four side surfaces 6A to 6D. The first plurality of first leads 4' may protrude from the first side surface 6A, and the second plurality of second leads 4" may protrude from the second side surface 6B opposite to the first side surface 6A. The third side surface 6C and the fourth side surface 6D may both connect the first side surface 6A and the second side surface 6B, and may not be provided with any leads protruding from the encapsulation material 2. Therefore, the semiconductor device 200 may correspond to a double-sided semiconductor device (or a double-sided semiconductor package). It should be noted that in practice, the die pads 8A and 8B may be covered by the (particularly opaque) encapsulation material 2, and may therefore be invisible.

[0024] The semiconductor device 200 may include one or more semiconductor components, which may be arranged on one or both of the die pads 8A and 8B. In the example shown, for simplicity, the semiconductor components are not shown. In particular, the semiconductor components may include or may correspond to semiconductor chips. Throughout the specification, the terms "chip", "semiconductor chip", "die", "semiconductor die" may be used interchangeably. The semiconductor chip may be made of elemental semiconductor materials (e.g., Si) or wide bandgap semiconductor materials or compound semiconductor materials (e.g., SiC, GaN, SiGe, GaAs). The semiconductor chip may be of any type and may include an integrated circuit with active electronic components and / or passive electronic components. The integrated circuit may be designed as a logic integrated circuit, an analog integrated circuit, a mixed signal integrated circuit, a power integrated circuit, a memory circuit, an integrated passive device, etc. For example, the semiconductor chip of the semiconductor device 200 may be configured to be able to operate as one of a gate driver, an isolation driver, a digital isolator, a current sensor, an auxiliary power component, etc.

[0025] One or more of the semiconductor chips may correspond to power semiconductor components, and therefore may be referred to as power semiconductor chips. In this article, the term "power semiconductor chip" may refer to a semiconductor chip that provides at least one of a high voltage blocking capability or a high current carrying capability. The power semiconductor chip may be configured for a high current with a maximum current value of several amperes (e.g., 10A) or a maximum current value of up to or exceeding 100A. Similarly, the voltage associated with such a current value may have a value of several volts to tens of volts or hundreds of volts. One or more of the semiconductor chips may correspond to a logic semiconductor chip. The logic semiconductor chip may be configured to be capable of driving and / or controlling one or more power semiconductor chips, for example, via the gate terminal of a power transistor chip. Therefore, some logic semiconductor chips may be referred to as driver semiconductor chips (or drivers) or control semiconductor chips (or controllers).

[0026] The leads 4′, 4″ and the die pads 8A, 8B may be part of a lead frame. The lead frame may be constructed such that the leads 4′, 4″ and the die pads 8A, 8B may be formed from the material of the lead frame. In the non-limiting case shown, an exemplary number of two die pads 8A, 8B and an exemplary number of four leads 4′, 4″ on each of the side surfaces 6A, 6B of the encapsulation material 2 are shown. In other examples, the number of die pads and leads may be different and may depend in particular on the specific type and functionality of the semiconductor device 200. In the example shown, the two groups of multiple leads 4′, 4″ may correspond to two rows (in particular linear) of leads protruding from opposite side surfaces 4A and 4B of the encapsulation material 2 and having a lead pitch p. One or both of the die pads 8A, 8B may be configured as a carrier for one or more semiconductor components. Throughout the specification, the terms “die pad” and “die area” may be used interchangeably.

[0027] The lead frame (and therefore the leads 4′, 4″ and the die pads 8A, 8B) may be made of a metal and / or a metal alloy, in particular at least one of copper, a copper alloy, nickel, iron-nickel, aluminum, an aluminum alloy, steel, stainless steel or the like. During manufacture of the semiconductor device 200, the leads 4′, 4″ and the die pads 8A, 8B may be connected to each other. In particular, the leads 4′, 4″ and the die pads 8A, 8B may be made from one piece during manufacture. The leads 4′, 4″ and the die pads 8A, 8B may be connected to each other by connecting means, with the aim of separating the die pads and some of the leads during the manufacturing process.

[0028] Figure 2 The semiconductor device 200 may not (yet) be separated from other semiconductor devices manufactured in the same batch process. In the example shown, the semiconductor device 200 may still include a plurality of dam bars 10 connecting adjacent leads. The dam bars may be used in the lead frame design to facilitate the molding or encapsulation operation and further provide support for the leads of the lead frame. During the encapsulation operation, the dam bars may be configured to act as a clamping surface for the edge of the molding tool and act as a barrier to prevent molding material from leaking or spilling from the molding tool onto the leads. It should be noted that the dam bars 10 may be removed later so that the leads 4′, 4″ may be physically and / or electrically individualized according to their respective functions.

[0029] The encapsulation material 2 may at least partially encapsulate one or more of the leads 4′, 4″, the die pads 8A, 8B, and the semiconductor components of the semiconductor device 200. The encapsulation material 2 may include or may be made of at least one of epoxy resin, filled epoxy resin, glass fiber filled epoxy resin, imide, thermoplastic, thermosetting polymer, polymer blend, laminate, or the like. Various techniques may be used to encapsulate the components of the semiconductor device 200 with the encapsulation material 2, such as at least one of compression molding, injection molding, powder molding, liquid molding, projection molding, lamination, or the like.

[0030] In the example shown, the encapsulation material 2 can form a body or encapsulation material having a top surface 14, an opposite bottom surface (not visible), and four side surfaces 6A to 6D extending between the top surface 14 and the bottom surface. Due to this packaging, the semiconductor device 200 can be referred to as a semiconductor package. The leads 4′ and 4″ can at least partially protrude from the encapsulation material 2 so that the encapsulated semiconductor components can be powered from outside the encapsulation material 2. In an example, the die pads 8A and 8B can be completely encapsulated in the encapsulation material 2. The bottom surface of the die pad 8A and the bottom surface of the die pad 8B can be (in particular, completely) covered by the encapsulation material 2.

[0031] The first plurality of leads 4′ may include a first lead 4A that is closest to the third side surface 6C of the encapsulation material 2 and protrudes from the first side surface 6A of the encapsulation material 2. In a similar manner, the second plurality of leads 4″ may include a second lead 4B that is closest to the third side surface 6C of the encapsulation material 2 and protrudes from the second side surface 6B of the encapsulation material 2. Due to the positions of the leads 4A and 4B, the leads 4A and 4B may be referred to as corner leads. In the example shown, the first lead 4A may be separated from and electrically insulated from the first die pad 8A. In this regard, the electrically insulating encapsulation material 2 may be configured to provide electrical isolation between the first lead 4A and the first die pad 8A. The second lead 4B may be electrically connected to the second die pad 8B. In this regard, the second lead 4B and the second die pad 8B may be made of a single metal piece or a single metal alloy piece.

[0032] At least one first semiconductor chip (not shown) can be arranged over the first die pad 8A. One or more leads 4' (and in particular the first lead 4A) can be electrically connected to the at least one first semiconductor chip via one or more electrical connection elements (not shown) such as wires, clips, strips, or the like. In addition, at least one second semiconductor chip (not shown) can be arranged over the second die pad 8B. In a similar manner, one or more leads 4" (and in particular the second lead 4B) can be electrically connected to at least one second semiconductor chip. In some examples, at least one first semiconductor chip and at least one second semiconductor chip can be configured to be able to operate as a gate driver, an isolation driver, a digital isolator, a current sensor, or an auxiliary power component.

[0033] At least one first semiconductor chip and the first lead 4A can be configured to operate in a low voltage domain. For example, the low voltage domain can be associated with an exemplary value range from about 0V to about 20V or can be specified by an exemplary value range from about 0V to about 20V. In this regard, the typical exemplary operating value of the low voltage domain can be about 3.3V or about 5V. At least one second semiconductor chip and the second lead 4B can be configured to operate in a high voltage domain. For example, the high voltage domain can be associated with an exemplary value range from about 50V to about 15000V or can be specified by an exemplary value range from about 50V to about 15000V. In this regard, the typical exemplary operating value of the high voltage domain can be about 600V or about 800V or about 1200V.

[0034] One or more of the leads 4' (and in particular the first lead 4A) may be configured as an input end (or input pin or input terminal) of the semiconductor device 200. In addition, one or more of the leads 4" (and in particular the second lead 4B) may be configured as an output end (or output pin or output terminal) of the semiconductor device 200. In one example, the input leads of the semiconductor device 200 may operate in a high voltage domain, while the output leads may operate in a low voltage domain.

[0035] Since the first lead 4A and the second lead 4B can operate under different voltage domains (e.g., in a high voltage domain and a low voltage domain), a sufficiently large creepage distance between the first lead 4A and the second lead 4B may be required. In this regard, it should be noted that the sufficient value of the first creepage distance between the leads 4A and 4B may depend on the maximum operating voltage of the semiconductor device 200. The higher the maximum operating voltage, the higher the first creepage distance may need to be. In an exemplary and non-limiting case, the maximum operating voltage of the semiconductor device 200 may have a value of about 600V. Here, the sufficient length of the first creepage distance may, for example, have a value of about 8mm. In the example shown, the first creepage distance between the corner leads 4A and 4B is represented by a dotted line. The first creepage distance may extend from the first lead 4A along a portion of the first side surface 6A, further along the entire third side surface 6C, and further along a portion of the second side surface 6B to the second lead 4B.

[0036] The first lead 4A may include a first notch (or recess or groove) 12A, which may be aligned with the first side surface 6A of the encapsulation material 2. Figure 2 In the top view of the encapsulation material 2, the first notch 12A and the first side surface 6A can be arranged in a row. The first notch 12A can face the direction toward the third side surface 6C. The first notch 12A can face away from other leads protruding from the first side surface 6A of the encapsulation material 2. In particular, the first notch 12A can face away from the lead arranged (directly) adjacent to the first lead 4A.

[0037] The first recess 12A may be arranged only partially inside the encapsulation material 2. A first portion of the first recess 12A may be arranged outside the encapsulation material 2, while a second portion of the first recess 12A may be encapsulated in the encapsulation material 2. Due to this partial arrangement in the encapsulation material 2, the first recess 12A may be configured to provide an interlock between the first lead 4A and the encapsulation material 2. This interlocking feature (or molded locking feature) may achieve a secure and stable mechanical connection between the lead 4A and the encapsulation material 2.

[0038] Compared with the same semiconductor device that does not include the first notch 12A, the first notch 12A can be configured to increase the first creepage distance between the first lead 4A and the second lead 4B. Therefore, the use of the first notch 12A in the first lead 4A can reduce the risk of leakage current and short circuit between the first lead 4A and the second lead 4B. Therefore, the safe operation of the semiconductor device 200 and the compliance with the electrical isolation requirements can be guaranteed. In addition, the increased creepage distance can provide the possibility of further reducing the size of the semiconductor package 200, especially the length of the package body 200 in the x direction. It should be noted that when the first notch 12A is used, it is possible to increase the first creepage distance without making major changes to the design of the semiconductor package 200, such as changing the lead width, lead pitch, molded body, etc. In particular, the first creepage distance can be increased without changing the coverage area of ​​the semiconductor device 200.

[0039] The shape or form of the first notch 12A may be arbitrarily selected as long as it can achieve the purpose of increasing the first creepage distance between the corner leads 4A and 4B. Figure 2 In the exemplary top view of FIG. 1 , the first recess 12A may be C-shaped. In other examples, when viewed in a direction perpendicular to the top surface 14, the first recess 12A may be v-shaped, u-shaped, square, rectangular, semicircular, semi-elliptical, narrowed, or the like.

[0040] The depth d of the first notch 12A may depend on the width w of the first lead 4A. The minimum depth of the first notch 12A may have a value of about 0.15 mm, while the maximum depth of the first notch 12A may have a value of about 30% of the width w of the first lead 4A. By providing the first notch 12A, the first creepage distance between the first lead 4A and the second lead 4B may be increased by a value corresponding to the depth d of the first notch 12A. In the example shown, the first notch 12A may have a semicircular shape. An exemplary and non-limiting value of the radius of such a semicircle may be about 0.2 mm.

[0041] The second lead 4B may include a second notch 12B that may be aligned with the second side surface 6B of the encapsulation material 2. The second notch 12B may be similar to the first notch 12A, so that all previous comments about the first notch 12A may also apply to the second notch 12B. In particular, the second notch 12B may be configured to further increase the first creepage distance between the first lead 4A and the second lead 4B along the third side surface 6C of the encapsulation material 2.

[0042] The first plurality of leads 4' may include a third lead 4C that is closest to the fourth side surface 6D of the encapsulation material 2 and protrudes from the first side surface 6A of the encapsulation material 2. In a similar manner, the second plurality of leads 4" may include a fourth lead 4D that is closest to the fourth side surface 6D of the encapsulation material 2 and protrudes from the second side surface 6B of the encapsulation material 2. The leads 4C and 4D may be referred to as corner leads and may be similar to the first lead 4A and the second lead 4B previously described. In the example shown, the third lead 4C may be electrically connected to the first die pad 8A. In this regard, the third lead 4C and the first die pad 8A may be made of a single metal piece or a single metal alloy piece. The fourth lead 4D may be separated and electrically insulated from the second die pad 8B. In this regard, the electrically insulating encapsulation material 2 may be configured to provide electrical isolation between the fourth lead 4D and the second die pad 8B.

[0043] The third lead 4C may include a third notch 12C, which may be aligned with the first side surface 6A of the encapsulation material 2. The third notch 12C may be, for example, similar to the first notch 12A described previously. The third notch 12C may be configured to increase the second creepage distance between the third lead 4C and the fourth lead 4D. The second creepage distance may extend from the third lead 4C along a portion of the first side surface 6A, further along the entire fourth side surface 6D, and further along a portion of the second side surface 6B to the fourth lead 4D. In the example shown, the second creepage distance between the corner leads 4C and 4D is represented by a dotted line.

[0044] The fourth lead 4D may include a fourth notch 12D, which may be aligned with the second side surface 6B of the encapsulation material 2. The fourth notch 12D may be similar to the second notch 12B described previously, for example. In particular, the fourth notch 12D may be configured to further increase the second creepage distance along the fourth side surface 6D of the encapsulation material 2 between the corner leads 4C and 4D.

[0045] Figure 3 The semiconductor device 300 may include some or all of the features of the previously described semiconductor devices. Figure 2 Compared to the example of , the first lead 4A can be electrically connected to the first die pad 8A. In this context, the first lead 4A and the first die pad 8A can be made of a single metal piece or a single metal alloy piece. Figure 2 In further contrast to the example of , the fourth lead 4D can be electrically connected to the second die pad 8B. In this context, the fourth lead 4D and the second die pad 8B can be made of a single metal piece or a single metal alloy piece. Therefore, in the example shown, each of the four corner leads 4A to 4D can be electrically connected to one of the die pads 8A and 8B.

[0046] Figure 4 The semiconductor device 400 may include some or all of the features of the previously described semiconductor devices. Figure 2 and Figure 3 Compared to the example of FIG. 4 , the semiconductor device 400 may include only one die pad 8A, which may be particularly similar to Figure 2 and Figure 3 of the die pad 8A. In addition, as shown in the previous example, the second plurality of leads 4" can extend further into the encapsulation material 2. The portions of the corner leads 4B and 4D extending into the encapsulation material 2 can be at least partially bent inward. Similar to the previous example, each of the four corner leads 4A to 4D can include a notch configured to increase the corresponding creepage distance between the leads.

[0047] Figure 5 The semiconductor device 500 may include some or all of the features of the previously described semiconductor device. Compared with the previous example, the semiconductor device 500 may include a greater number of die pads. In the illustrated case, the semiconductor device 500 may include an exemplary number of four die pads 8A to 8D. The first die pad 8A may be arranged at the first side surface 6A of the encapsulation material 2, and the other three die pads 8B to 8D may be arranged at the second side surface 6B of the encapsulation material 2 opposite to the first side surface 6A. The first plurality of leads 4' may protrude from the first side surface 6A. One or more of the leads 4' may be electrically connected to the first die pad 8A. These leads and the first die pad 8A may be made of a single metal piece or a single metal alloy piece. In the illustrated example, the first corner lead 4A and the third corner lead 4C may be separated and electrically insulated from the first die pad 8A.

[0048] A second plurality of leads 4" may protrude from a second side surface 6B of the encapsulation material 2. A second corner lead 4B may be arranged at a third side surface 6C of the encapsulation material 2 connecting the first side surface 6A and the second side surface 6B. The second lead 4B may be electrically connected to the second die pad 8B. In a similar manner, a fourth corner lead 4D may be arranged at a fourth side surface 6D of the encapsulation material 2 connecting the first side surface 6A and the second side surface 6B. The fourth lead 4D may be electrically connected to the fourth die pad 8D. One or more of the remaining leads 4" may be electrically connected to a third die pad 8C, which may be arranged between the second die pad 8B and the fourth die pad 8D. In the example shown, each of the four corner leads 4A to 4D may include a notch so that a corresponding creepage distance between corresponding leads may be increased, and the isolation characteristics of the semiconductor device 500 may be improved.

[0049] Figure 6The semiconductor device 600 may include some or all of the features of the previously described semiconductor devices. In the previous example, the first lead 4A may include a first notch 12A facing away from other leads protruding from the same first side surface 6A of the encapsulation material 2. In contrast, Figure 6 The first notch 12A of the first lead 4A may be formed not only in the side of the first lead 4A facing away from the adjacent lead, but may extend around the entire circumference of the first lead 4A. For example, the first notch 12A may be a radial or annular notch that may extend completely around the first lead 4A. One or more of the additional corner leads 4B to 4D may be designed in a similar manner and may also include corresponding notches. In the example shown, similar notches 12B to 12D may be formed in each of the additional three corner leads 4B to 4D.

[0050] Figure 7 The semiconductor device 700 may include some or all of the features of the previously described semiconductor devices. The semiconductor device 700 may include an encapsulation material 2 that at least partially encapsulates a semiconductor component (not shown) of the semiconductor device 700. The first lead 4A may protrude from a first side surface 6A of the encapsulation material 2, and the second lead 4B may protrude from a second side surface 6B of the encapsulation material 2 opposite to the first side surface 6A.

[0051] The cross-section (or cross-sectional area) of the first lead 4A may be associated with a cross-sectional plane that may extend substantially parallel to the yz plane. The cross-section of the first lead 4A may narrow toward the first side surface 6A of the encapsulation material 2. That is, the cross-sectional area of ​​the first lead 4A associated with the cross-sectional plane that is substantially parallel to the yz plane may decrease in a direction toward the first side surface 6A. Figure 7 In the exemplary top view of FIG. 1 , the first lead 4A may have a non-uniform lead width. In particular, the first lead 4A may include a first width w 1 The first portion and has a width less than the first width w 1 The second width w 2 The second portion of the first lead 4A may be arranged closer to the first side surface 6A than the first portion. In the example shown, the first portion of the first lead 4A may be arranged on the left side of the barrier 10, and the second portion of the first lead 4A may be arranged on the right side of the barrier 10. As the width decreases toward the first side surface 6A, the cross section of the first lead 4A may be narrowed.

[0052] The described narrowing of the first lead 4A toward the first side surface 6A may increase the creepage distance between the first lead 4A and the second lead 4B along the third side surface 6C of the encapsulation material 2. One or more of the three additional corner leads 4B to 4D may be similar to the first corner lead 4A and may also be narrowed toward the corresponding side surface of the encapsulation material 2, thereby increasing the creepage distance between the corresponding corner leads.

[0053] It should be noted that Figure 7 The example can be combined with any of the other examples discussed herein. That is, in a further example, one or more of the corner leads 4A to 4D can include both a notch and a narrowing toward a side surface from which the corresponding corner lead protrudes.

[0054] Figure 8 and Fig. 9 A flow chart of a method for manufacturing a semiconductor device according to the present disclosure is shown. Figure 8 and Fig. 9 The method is provided to qualitatively illustrate various aspects of the present disclosure. The method may include other aspects. For example, the method may be extended by any aspect described herein in conjunction with other examples. In particular, the method may be used to manufacture the previously described semiconductor device according to the present disclosure.

[0055] Figure 8 A first method for manufacturing a semiconductor device is shown. For example, Figure 8 The method can be used to manufacture Figures 2 to 6 At 20, a semiconductor component may be provided. At 22, a first lead and a second lead may be provided, wherein the first lead includes a first recess. At 24, the semiconductor component, the first lead, and the second lead may be at least partially encapsulated in an encapsulation material. The first lead may protrude from a first side surface of the encapsulation material, and the second lead may protrude from a second side surface of the encapsulation material opposite to the first side surface. The first recess may be aligned with the first side surface of the encapsulation material. The first recess may face away from other leads protruding from the first side surface of the encapsulation material.

[0056] Fig. 9 A second method for manufacturing a semiconductor device is shown. For example, Fig. 9 The method can be used to manufacture Figure 7At 26, a semiconductor component may be provided. At 28, a first lead and a second lead may be provided. At 30, the semiconductor component, the first lead, and the second lead may be at least partially encapsulated in an encapsulation material. The first lead may protrude from a first side surface of the encapsulation material, and the second lead may protrude from a second side surface of the encapsulation material opposite to the first side surface. The cross-section of the first lead may be narrowed toward the first side surface of the encapsulation material.

[0057] Example

[0058] In the following, a semiconductor device and a method for manufacturing such a semiconductor device according to the present disclosure are described by means of examples.

[0059] Example 1 is a semiconductor device, comprising: an encapsulation material that at least partially encapsulates a semiconductor component of the semiconductor device; a first lead protruding from a first side surface of the encapsulation material; and a second lead protruding from a second side surface of the encapsulation material opposite to the first side surface, wherein the first lead comprises a first recess aligned with the first side surface of the encapsulation material, and wherein the first recess faces away from the other leads protruding from the first side surface of the encapsulation material.

[0060] Example 2 is a semiconductor device according to Example 1, wherein a first portion of the first recess is arranged outside the encapsulation material, and a second portion of the first recess is encapsulated in the encapsulation material.

[0061] Example 3 is a semiconductor device according to Example 1 or 2, wherein the first recess is configured to increase a first creepage distance between the first lead and the second lead, and the first creepage distance extends at least partially along a first side surface of the encapsulation material, along a third side surface of the encapsulation material connecting the first side surface and the second side surface of the encapsulation material, and at least partially along the second side surface of the encapsulation material.

[0062] Example 4 is the semiconductor device according to Example 3, wherein the third side surface of the encapsulation material is not provided with any leads protruding from the encapsulation material.

[0063] Example 5 is a semiconductor device according to any one of the preceding examples, wherein: the first side surface and the second side surface are adjacent to the top surface of the encapsulation material, and when viewed in a direction perpendicular to the top surface, the first recess is one of a c-shape, a v-shape, a square, a rectangle, or a narrowed shape.

[0064] Example 6 is a semiconductor device according to any of the preceding examples, wherein the first notch extends around an entire circumference of the first lead.

[0065] Example 7 is a semiconductor device according to any of the preceding examples, wherein the first recess is configured to provide an interlock between the first lead and the encapsulation material.

[0066] Example 8 is a semiconductor device according to any of the preceding examples, wherein a minimum depth of the first notch is 0.15 mm and a maximum depth of the first notch is 30% of a width of the first lead.

[0067] Example 9 is a semiconductor device according to any one of Examples 3 to 8, wherein: the second lead includes a second recess aligned with the second side surface of the encapsulation material, and the second recess is configured to increase a first creepage distance between the first lead and the second lead along a third side surface of the encapsulation material.

[0068] Example 10 is a semiconductor device according to any one of Examples 3 to 9, wherein the semiconductor device includes: a first plurality of leads protruding from a first side surface of the encapsulation material, wherein the first lead is a lead among the first plurality of leads that is closest to a third side surface of the encapsulation material; and a second plurality of leads protruding from a second side surface of the encapsulation material, wherein the second lead is a lead among the second plurality of leads that is closest to the third side surface of the encapsulation material.

[0069] Example 11 is a semiconductor device according to any one of the preceding examples, wherein one of the first lead and the second lead is configured to be capable of operating in a low voltage domain, and the other of the first lead and the second lead is configured to be capable of operating in a high voltage domain.

[0070] Example 12 is a semiconductor device according to any one of the preceding examples, wherein one of the first lead and the second lead is configured as an input terminal of the semiconductor device, and the other of the first lead and the second lead is configured as an output terminal of the semiconductor device.

[0071] Example 13 is a semiconductor device according to any one of the preceding examples, wherein the semiconductor device includes: a first die pad, wherein one of the first lead and the second lead is separated from and electrically insulated from the first die pad; and a second die pad, wherein the other of the first lead and the second lead is electrically connected to the second die pad, and wherein the second die pad and the other of the first lead and the second lead are made of a single metal piece or a single metal alloy piece.

[0072] Example 14 is a semiconductor device according to Example 13, wherein the semiconductor device includes: at least one first semiconductor chip arranged on the first die pad, and at least one second semiconductor chip arranged on the second die pad, wherein the at least one first semiconductor chip and the at least one second semiconductor chip are configured to be able to operate as a gate driver, an isolation driver, a digital isolator, a current sensor, or an auxiliary power component.

[0073] Example 15 is a semiconductor device according to any one of Examples 3 to 14, wherein the semiconductor device includes: a third lead protruding from a first side surface of the encapsulation material; and a fourth lead protruding from a second side surface of the encapsulation material, wherein the third lead includes a third recess aligned with the first side surface of the encapsulation material, wherein the fourth lead includes a fourth recess aligned with the second side surface of the encapsulation material, and wherein the third recess and the fourth recess are configured to increase a second creepage distance between the third lead and the fourth lead, the second creepage distance extending at least partially along the first surface of the encapsulation material, along a fourth side surface of the encapsulation material opposite to the third side surface of the encapsulation material, and at least partially along the second side surface of the encapsulation material, the fourth side surface connecting the first side surface and the second side surface of the encapsulation material.

[0074] Example 16 is the semiconductor device according to Example 15, wherein the fourth side surface of the encapsulation material is not provided with any leads protruding from the encapsulation material.

[0075] Example 17 is a semiconductor device according to Example 15 or 16, wherein: the third lead is the lead among the first plurality of leads that is closest to the fourth side surface of the encapsulation material, and the fourth lead is the lead among the second plurality of leads that is closest to the fourth side surface of the encapsulation material.

[0076] Example 18 is a semiconductor device, comprising: an encapsulation material that at least partially encapsulates a semiconductor component of the semiconductor device; a first lead protruding from a first side surface of the encapsulation material; and a second lead protruding from a second side surface of the encapsulation material opposite to the first side surface, wherein a cross-section of the first lead narrows toward the first side surface of the encapsulation material.

[0077] Example 19 is a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor component; providing a first lead and a second lead, wherein the first lead includes a first recess; and at least partially encapsulating the semiconductor component, the first lead, and the second lead in an encapsulation material, wherein the first lead protrudes from a first side surface of the encapsulation material, wherein the second lead protrudes from a second side surface of the encapsulation material opposite to the first side surface, wherein the first recess is aligned with the first side surface of the encapsulation material, and wherein the first recess faces away from other leads protruding from the first side surface of the encapsulation material.

[0078] Example 20 is a method for manufacturing a semiconductor device, the method comprising: providing a semiconductor component; providing a first lead and a second lead; and at least partially encapsulating the semiconductor component, the first lead, and the second lead in an encapsulation material, wherein the first lead protrudes from a first side surface of the encapsulation material, wherein the second lead protrudes from a second side surface of the encapsulation material opposite to the first side surface, and wherein a cross-section of the first lead narrows toward the first side surface of the encapsulation material.

[0079] As used in this specification, the terms "connected", "coupled", "electrically connected" and / or "electrically coupled" may not necessarily mean that elements must be directly connected or coupled together. Intermediate elements may be provided between the elements that are "connected", "coupled", "electrically connected" or "electrically coupled".

[0080] In addition, the term "on" used in relation to, for example, a material layer formed on or located "on" a surface of an object may be used herein to mean that the material layer may be "directly" located (e.g., formed, deposited, etc.) on the surface, e.g., in direct contact with the surface. The term "on" used in relation to, for example, a material layer formed on or located "on" a surface may also be used herein to mean that the material layer may be "indirectly" located (e.g., formed, deposited, etc.) on the surface, with, for example, one or more additional layers disposed between the surface and the material layer.

[0081] In addition, to the extent the terms "having," "including," "comprising," "with," or variations thereof are used in either the detailed description or the claims, these terms are intended to be inclusive in a manner similar to the term "comprising." That is, as used herein, the terms "having," "including," "containing," "with," "including," and the like are open-ended terms that indicate the presence of stated elements or features but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly dictates otherwise.

[0082] In addition, the word "exemplary" is used herein to mean used as an example, instance or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as superior to other aspects or designs. On the contrary, the use of the word exemplary is intended to present concepts in a concrete way. As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X adopts A or B" is intended to mean any natural inclusive arrangement. That is, if X adopts A; X adopts B; or X adopts both A and B, then "X adopts A or B" is satisfied in any of the aforementioned instances. In addition, unless otherwise specified or clear from the context that it is for a singular form, the articles "one" and "an" used in this application and the appended claims can generally be interpreted as meaning "one or more". In addition, at least one of A and B or similar expressions generally refer to A or B or both A and B.

[0083] Devices and methods for making the devices are described herein. Comments made in connection with the described devices may also apply to the corresponding methods, and vice versa. For example, if specific components of a device are described, the corresponding methods for making the device may include operations for providing the components in a suitable manner, even if such operations are not explicitly described or shown in the drawings.

[0084] Although the present disclosure has been shown and described for one or more embodiments, other technical personnel in the art will think of equivalent changes and modifications based at least in part on the reading and understanding of this specification and the drawings. The present disclosure includes all such modifications and changes and is limited only by the concepts of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise specified, the terms used to describe these components are intended to correspond to any component (e.g., functionally equivalent) that performs the specific functions of the described components, even if they are not structurally equivalent to the disclosed structures that perform the functions in the exemplary embodiments of the present disclosure shown herein. In addition, although the specific features of the present disclosure may be disclosed only with respect to one of the multiple embodiments, such features may be combined with one or more other features of other embodiments, as may be desirable and advantageous for any given or specific application.

Claims

1. A semiconductor device, comprising: An encapsulation material (2) at least partially encapsulating a semiconductor component of the semiconductor device, the encapsulation material (2) comprising a first side surface (6A), a second side surface (6B) opposite to the first side surface (6A), and a third side surface (6C) connecting the first side surface (6A) and the second side surface (6B); a first plurality of leads (4') protruding from the first side surface (6A), the first lead (4A) being a lead among the first plurality of leads (4') closest to the third side surface (6C); and a second plurality of leads (4") protruding from the second side surface (6B), the second leads (4B) being leads of the second plurality of leads (4") closest to the third side surface (6C), wherein the first lead (4A) comprises a first notch (12A) aligned with the first side surface (6A) and facing the third side surface (6C), The first notch (12A) faces away from other leads protruding from the first side surface (6A) of the encapsulation material (2), The second lead (4B) includes a second notch (12B) aligned with the second side surface (6B) and facing the third side surface (6C), and The third side surface (6C) is not provided with any leads or metal.

2. The semiconductor device according to claim 1, wherein A first portion of the first recess (12A) is arranged outside the encapsulating material (2), and a second portion of the first recess (12A) is encapsulated in the encapsulating material (2).

3. The semiconductor device according to claim 1 or 2, wherein: The first notch (12A) is configured to increase a first creepage distance between the first lead (4A) and the second lead (4B), the first creepage distance extending at least partially along a first side surface (6A) of the encapsulating material (2), along a third side surface (6C) of the encapsulating material (2), and at least partially along a second side surface (6B) of the encapsulating material (2).

4. A semiconductor device according to any one of the preceding claims, wherein: The first notch (12A) extends completely along the thickness of the first lead (4A), and The second notch (12B) extends completely along the thickness of the second lead (4B).

5. A semiconductor device according to any one of the preceding claims, wherein: The first side surface (6A) and the second side surface (6B) are adjacent to the top surface (14) of the encapsulating material (2), and When viewed in a direction perpendicular to the top surface (14), the first recess (12A) is one of a c-shape, a v-shape, a square, a rectangle, or a narrowed shape.

6. A semiconductor device according to any one of the preceding claims, wherein: The first notch (12A) extends around the entire circumference of the first lead (4A).

7. A semiconductor device according to any one of the preceding claims, wherein: The first notch (12A) is configured to provide an interlock between the first lead (4A) and the encapsulation material (2).

8. A semiconductor device according to any one of the preceding claims, wherein: The minimum depth of the first notch (12A) is 0.15 mm, and the maximum depth of the first notch (12A) is 30% of the width of the first lead (4A).

9. The semiconductor device according to any one of claims 3 to 8, wherein: The second notch (12B) is configured to increase the first creepage distance between the first lead (4A) and the second lead (4B) along the third side surface (6C) of the encapsulation material (2).

10. A semiconductor device according to any one of the preceding claims, wherein: One of the first lead (4A) and the second lead (4B) is configured to be operable in a low voltage domain, and the other of the first lead (4A) and the second lead (4B) is configured to be operable in a high voltage domain.

11. A semiconductor device according to any one of the preceding claims, wherein: One of the first lead (4A) and the second lead (4B) is configured as an input terminal of the semiconductor device, and the other of the first lead (4A) and the second lead (4B) is configured as an output terminal of the semiconductor device.

12. A semiconductor device according to any one of the preceding claims, wherein: The semiconductor device comprises: a first die pad (8A), one of the first lead (4A) and the second lead (4B) being separated from and electrically insulated from the first die pad (8A); and A second die pad (8B), the other of the first lead (4A) and the second lead (4B) is electrically connected to the second die pad (8B), and the second die pad (8B) and the other of the first lead (4A) and the second lead (4B) are made of a single metal piece or a single metal alloy piece.

13. The semiconductor device according to claim 12, wherein: The semiconductor device comprises: at least one first semiconductor chip arranged on the first die pad (8A), and at least one second semiconductor chip arranged on the second die pad (8B), The at least one first semiconductor chip and the at least one second semiconductor chip are configured to be able to operate as a gate driver, an isolation driver, a digital isolator, a current sensor, or an auxiliary power component.

14. The semiconductor device according to any one of claims 3 to 13, wherein: The semiconductor device comprises: a third lead (4C) protruding from the first side surface (6A) of the encapsulation material (2); and a fourth lead (4D) protruding from the second side surface (6B) of the encapsulation material (2), The third lead (4C) includes a third notch (12C) aligned with the first side surface (6A) of the encapsulation material (2), The fourth lead (4D) includes a fourth notch (12D) aligned with the second side surface (6B) of the encapsulation material (2), and The third recess (12C) and the fourth recess (12D) are configured to increase a second creepage distance between the third lead (4C) and the fourth lead (4D), the second creepage distance extending at least partially along the first surface (6A) of the encapsulating material (2), along a fourth side surface (6D) of the encapsulating material (2) opposite to the third side surface (6C) of the encapsulating material (2), and at least partially along the second side surface (6B) of the encapsulating material (2), the fourth side surface (6D) connecting the first side surface (6A) and the second side surface (6B) of the encapsulating material (2).

15. The semiconductor device according to claim 14, wherein: The fourth side surface (6D) of the encapsulation material (2) is not provided with any leads protruding from the encapsulation material (2).

16. The semiconductor device according to claim 14 or 15, wherein: The third lead (4C) is a lead among the first plurality of leads (4') that is closest to the fourth side surface (6D) of the encapsulation material (2), and The fourth lead (4D) is a lead among the second plurality of leads (4") that is closest to the fourth side surface (6D) of the encapsulation material (2).

17. A semiconductor device comprising: An encapsulation material (2) at least partially encapsulating a semiconductor component of the semiconductor device; a first lead (4A) protruding from a first side surface (6A) of the encapsulation material (2); a second lead (4B) protruding from a second side surface (6B) of the encapsulation material (2) opposite to the first side surface (6A), wherein the cross section of the first lead (4A) narrows toward the first side surface (6A) of the encapsulation material (2), and the cross section of the second lead (4B) narrows toward the second side surface (6B) of the encapsulation material (2), The first lead (4A) includes a first portion having a first width and a second portion having a second width smaller than the first width, the second portion being arranged closer to the first side surface (6A) than the first portion, the first portion and the second portion being separated by a barrier strip (10), and The second lead (4B) includes a first portion having a first width and a second portion having a second width smaller than the first width, the second portion being arranged closer to the second side surface (6B) than the first portion, and the first portion and the second portion being separated by a barrier bar (10).

18. A method for manufacturing a semiconductor device, the method comprising: Providing semiconductor components; providing a first plurality of leads (4') and a second plurality of leads (4"); as well as at least partially encapsulating the semiconductor component, the first plurality of leads (4') and the second plurality of leads (4") in an encapsulation material (2), the encapsulation material (2) comprising a first side surface (6A), a second side surface (6B) opposite to the first side surface (6A) and a third side surface (6C) connecting the first side surface (6A) and the second side surface (6B), wherein the first plurality of leads (4') protrude from the first side surface (6A), the first lead (4A) is the lead closest to the third side surface (6C) among the first plurality of leads (4'), The second plurality of leads (4") protrude from the second side surface (6B), the second lead (4B) being a lead among the second plurality of leads (4") that is closest to the third side surface (6C), The first lead (4A) includes a first notch (12A) aligned with the first side surface (6A) and facing the third side surface (6C), The first notch (12A) faces away from other leads protruding from the first side surface (6A) of the encapsulation material (2), The second lead (4B) includes a second notch (12B) aligned with the second side surface (6B) and facing the third side surface (6C), and The third side surface (6C) is not provided with any leads or metal.

19. A method for manufacturing a semiconductor device, the method comprising: Providing semiconductor components; Providing a first lead (4A) and a second lead (4B); as well as At least partially encapsulating the semiconductor component, the first lead (4A) and the second lead (4B) in an encapsulation material (2), wherein the first lead (4A) protrudes from a first side surface (6A) of the encapsulation material (2), The second lead (4B) protrudes from a second side surface (6B) of the encapsulation material (2) opposite to the first side surface (6A), The cross section of the first lead (4A) narrows toward the first side surface (6A) of the encapsulation material (2), and the cross section of the second lead (4B) narrows toward the second side surface (6B) of the encapsulation material (2). The first lead (4A) includes a first portion having a first width and a second portion having a second width smaller than the first width, the second portion being arranged closer to the first side surface (6A) than the first portion, the first portion and the second portion being separated by a barrier strip (10), and The second lead (4B) includes a first portion having a first width and a second portion having a second width smaller than the first width, the second portion being arranged closer to the second side surface (6B) than the first portion, and the first portion and the second portion being separated by a barrier bar (10).

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