Semiconductor device including semiconductor die sandwiched between two lead frames and method of manufacturing same

Abstract

A first aspect of the present disclosure relates to a semiconductor device including: a first lead frame including a first die pad and one or more first leads integrally formed with the first die pad and extending outwardly from the first die pad in a first direction; a second lead frame including a second die pad and one or more second leads integrally formed with the second die pad and extending outward from the second die pad in a second direction different from the first direction; a semiconductor die disposed between the first die pad and the second die pad; and an encapsulation material in which the semiconductor die is embedded, in which the first lead and the second lead are disposed outside the encapsulation material.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] A power semiconductor package includes a power semiconductor die embedded in a molding compound. A major problem with semiconductor power packages is the dissipation of the excess heat generated by the semiconductor power die during operation. The heat generated by the semiconductor power die needs to be efficiently dissipated from the semiconductor package to the environment. In the case of a leadless surface mounted semiconductor package, the heat can be dissipated via the bottom side PCB. However, additional top side cooling is a major trend in manufacturing semiconductor power packages. In this case, the metal contacts connected to the semiconductor die are exposed to the outside, allowing a heat sink to be connected to the metal contacts.

[0003] However, surface mounted semiconductor packages have a general disadvantage of providing no compensation mechanism in case of mechanical stress, e.g. due to different thermal expansion coefficients, due to the lack of flexibility of the metal contacts located on the PCB surface, resulting in a lack of board level reliability (BLR). Summary of the invention

[0004] A first aspect of the present disclosure relates to a semiconductor device, comprising: a first lead frame, comprising a first die pad and one or more first leads integrally formed with the first die pad and extending outward from the first die pad along a first direction; a second lead frame, comprising a second die pad and one or more second leads integrally formed with the second die pad and extending outward from the second die pad along a second direction different from the first direction; a semiconductor die disposed between the first die pad and the second die pad; and an encapsulation material embedded with the semiconductor die, wherein the first lead and the second lead are disposed outside the encapsulation material.

[0005] Due to the fact that the first and second leads are disposed outside the encapsulation material after mounting the semiconductor device on the PCB, the leads are more flexible to absorb any type of mechanical stress between the semiconductor device and the PCB, which may increase board-level reliability.

[0006] According to an embodiment of the semiconductor device of the first aspect, the first die pad of the first lead frame is at least partially exposed to the outside, so that the heat sink can be mounted on the surface of the first die pad away from the semiconductor die. The installation of the heat sink can be completed during the manufacturing process of the semiconductor device or on the customer side. The first die pad can be completely exposed to the outside. In addition, the first die pad can be partially exposed, and in the remaining part, the encapsulation material is exposed to the outside.

[0007] According to an embodiment of the semiconductor device of the first aspect, the first die pad is arranged in a first plane, the second die pad is arranged in a second plane, the first lead extends from the first plane to a third plane outside the encapsulation material, and the second lead extends from the second plane to the third plane outside the encapsulation material.

[0008] According to an embodiment of the semiconductor device of the first aspect, the encapsulation material includes a lower surface, and after the semiconductor device is mounted on the PCB, the lower surface faces the PCB. In some embodiments, the lower surface can be located in a third plane, so that after the semiconductor device is mounted on the PCB, the encapsulation material will contact the surface of the PCB, thereby allowing heat dissipation through the PCB when the semiconductor device is operated. In addition, the lower surface of the encapsulation material can be arranged above the third plane, in which case bottom side cooling is not possible.

[0009] According to an embodiment of the semiconductor device of the first aspect, the first lead is bent from the first die pad at a first angle, and the second lead is bent from the second die pad at a second angle. According to another example of the semiconductor device of the first aspect, the second angle is different from the first angle. According to another example of the semiconductor device of the first aspect, both the first angle and the second angle are not zero.

[0010] According to an embodiment of the semiconductor device of the first aspect, the semiconductor die is a semiconductor transistor die. In particular, the semiconductor die can be one or more of a vertical semiconductor transistor die, a semiconductor power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, and a wide bandgap semiconductor transistor die (in particular, a SiC transistor die).

[0011] According to an embodiment of the semiconductor device of the first aspect, the semiconductor transistor die includes a first main surface and a second main surface opposite to the first main surface, and a source pad disposed on the first main surface and a drain pad disposed on the second main surface. According to one embodiment, the drain pad is connected to the first lead frame and the source pad is connected to the second lead frame. According to another example of the semiconductor device of the first aspect, the semiconductor device further includes a gate pad disposed on the first main surface and may also include a source / sense pad also disposed on the first main surface.

[0012] A second aspect of the present disclosure relates to a method for manufacturing a semiconductor device, the method comprising: providing a first lead frame; providing a semiconductor die comprising a first main surface and a second main surface opposite to the first main surface; connecting the first main surface of the semiconductor die to a first portion of the first lead frame; providing a second lead frame; connecting the first portion of the second lead frame to the second main surface of the semiconductor die; applying an encapsulation material to the semiconductor die and to the first portion of the first lead frame and the first portion of the second lead frame, so that the second portion of the first lead frame and the second portion of the second lead frame are arranged outside the encapsulation material.

[0013] When the method is performed as described above, the first portion of the first lead frame and the first portion of the second lead frame become the die pad, and the second portion of the first lead frame and the second portion of the second lead frame become the leads of the semiconductor device according to the first aspect.

[0014] The method according to the second aspect can be performed in different ways with respect to the order of the method steps. All embodiments have in common that the semiconductor device to be manufactured has a first portion of a lead frame used as a die pad and a second portion bent from the first portion used as a lead. In a very practical manufacturing method, a lead frame supplier pre-bends the lead frame and then sends the pre-bent lead frame to the customer for semiconductor package assembly. In general, the method can be performed so that when the lead frame is initially provided, the second portion is already partially or completely bent from the first portion. Finally, the method can be performed so that bending the second portion from the first portion is performed after the encapsulation material has been fully attached.

[0015] According to an embodiment of the method of the second aspect, the second portion of the first lead frame is bent at a first angle, and the second portion of the second lead frame is bent at a second angle. According to another example of the method of the second aspect, the second angle is different from the first angle.

[0016] According to an embodiment of the method of the second aspect, the method is performed such that a surface of the first portion of the first leadframe remote from the semiconductor die is exposed to the outside.

[0017] According to one embodiment of the method of the second aspect, two semiconductor devices are manufactured in parallel by connecting two semiconductor dies to a first lead frame, providing two second lead frames, connecting each of the two second lead frames to one of the semiconductor dies, applying two encapsulation materials to each of the semiconductor dies and to a first portion of the first lead frame and a first portion of the second lead frame, and singulating into two independent semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate the embodiments and, together with the description, are used to explain the principles of the embodiments. Other embodiments and many of the expected advantages of the embodiments will be readily understood as they become better understood by reference to the following detailed description.

[0019] The elements in the drawings are not necessarily drawn to scale relative to each other. The same or similar reference numbers indicate the same or similar parts.

[0020] Figure 1 A cross-sectional view showing one example of the semiconductor device according to the first aspect is shown.

[0021] FIG. 2A to FIG. 2C A cross-sectional view showing other examples of the semiconductor device according to the first aspect.

[0022] FIG. 3A to FIG. 3C A cross-sectional view is shown to illustrate the method for manufacturing the Figure 1 An example method of a semiconductor device is shown.

[0023] Figures 4A to 4C A cross-sectional view is shown to explain another example method for manufacturing a semiconductor device.

[0024] FIG. 5A to FIG. 5E Cross-sectional views are shown to illustrate a method for manufacturing two or more semiconductor devices in a parallel process. DETAILED DESCRIPTION

[0025] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific embodiments of the present disclosure may be practiced are shown by way of illustration. In this regard, directional terms such as "top", "bottom", "front", "rear", etc. are used with reference to the orientation of the drawings described. Because the components of the embodiments can be positioned in a plurality of different orientations, the directional terms are used for illustrative purposes and are by no means limiting. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description should not be considered restrictive, and the scope of the present disclosure is defined by the appended claims.

[0026] It should be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically stated otherwise.

[0027] As used in this specification, the terms "joined", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" do not mean that the elements or layers must be directly in contact together; intervening elements or layers may be provided between the elements that are "joined", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" accordingly. However, according to the present disclosure, the above-mentioned terms may optionally also have a specific meaning that the elements or layers are directly in contact together, that is, no intervening elements or layers are provided between the elements that are "joined", "attached", "connected", "coupled" and / or "electrically connected / electrically coupled" accordingly.

[0028] In addition, the term "on" used in relation to a component, element or material layer formed or located "on" a surface may be used herein to indicate that the component, element or material layer is "indirectly" located (e.g., placed, formed, deposited, etc.) on the surface, wherein one or more additional components, elements or layers are arranged between the surface and the component, element or material layer. However, the term "on" used in relation to a component, element or material layer formed or located "on" a surface may optionally also have a specific meaning, i.e., the component, element or material layer is "directly" located (e.g., placed, formed, deposited, etc.) on the surface, such as in direct contact with the surface.

[0029] Figure 1 A cross-sectional view showing one example of the semiconductor device according to the first aspect is shown.

[0030] In particular, Figure 1 A semiconductor device 10 is shown, which includes: a first lead frame 11, which includes a first die pad 11A and one or more first leads 11B formed integrally with the first die pad 11A and extending outward from the first die pad 11A in a first direction; a second lead frame 12, which includes a second die pad 12A and one or more second leads 12B formed integrally with the second die pad 12A and extending outward from the second die pad 12A in a second direction different from the first direction; a semiconductor die 13, which is arranged between the first die pad 11A and the second die pad 12A; and an encapsulation material 14, which embeds the semiconductor die 13, wherein the first lead 11B and the second lead 12B are substantially or mostly arranged outside the encapsulation material 14.

[0031] The semiconductor die 13 may be connected to the first die pad 11A with its upper main face by means of the first conductive layer 15, and the semiconductor die 13 may be connected to the upper main face of the second die pad 12A with its lower main face by means of the second conductive layer 16. The first conductive layer 15 and the second conductive layer 16 may include, for example, solder layers or sintering layers.

[0032] The first lead 11B and the second lead 12B each have an end attachment member 11B.1 and 12B.1 having a horizontal bottom surface located in a common horizontal plane PP and by means of which the semiconductor device 10 can be attached to a substrate such as a PCB. In general, different types of lead shapes can be used, such as a gull-wing type, a J-lead type, a C-lead type, or a through-hole type.

[0033] like Figure 1 As shown in the example of the semiconductor device 10 of FIG. 1 , the encapsulation material 14 may include a lower horizontal surface 14A and a chamfered sidewall 14B disposed between the first die pad 11A and the lower horizontal surface 14A. Figure 1 As further shown in the example of FIG. 1 , the lower horizontal surface 14A of the encapsulating material 14 is located above the horizontal plane PP. Other embodiments will be further described below, in which the lower horizontal surface of the encapsulating material is coplanar with the horizontal plane PP.

[0034] Therefore, in Figure 1 In the example shown, when the semiconductor device 10 is mounted on a substrate such as a PCB, the semiconductor device 10 contacts the PCB only via its first conductor 11B and second conductor 12B, while the encapsulation material 14 does not contact the PCB. In the example shown, heat is mainly dissipated through the top side, and heat is dissipated only to the bottom side via the leads.

[0035] As will also be shown later, the first lead 11B and the second lead 12B may be created by bending a first corresponding portion from the first die pad 11A and a second corresponding portion from the second die pad 12A. Figure 1 It can be seen from the figure that there is a first angle α between the first lead 11B and the first die pad 11A, and there is a second angle β between the second lead 11B and the second die pad 11A.

[0036] Figure 1 A further feature of the example shown in is that the first pad 11A is completely exposed to the outside. As will be shown in other examples, the first pad may also be only partially exposed to the outside. In any case, this provides the possibility of attaching an external heat sink to achieve top-side cooling during operation. The first lead 11B is bent from the first die pad 11A at a first angle, and the second lead 12B is bent from the second die pad 12A at a second angle.

[0037] Furthermore, the semiconductor die 13 may be a semiconductor transistor die 13 , and in particular one or more of a vertical semiconductor transistor die, a semiconductor power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, and a wide bandgap semiconductor transistor (in particular a SiC transistor die).

[0038] More specifically, the semiconductor transistor bare chip 13 may include a first main surface and a second main surface opposite to the first main surface, and a source pad arranged on the first main surface and a drain pad arranged on the second main surface, and may also include a gate pad and a source / sense pad both arranged on the first main surface.

[0039] The encapsulation material 14 may be composed of a conventional molding compound, such as a resin material, in particular an epoxy material. In addition, the encapsulation material 14 may be made of a thermally conductive material to allow efficient heat dissipation to an externally applied heat sink. In particular, the material of the encapsulation material 14 may include a resin, such as an epoxy material, filled with particles, such as SiO or other ceramic particles, or thermally conductive particles, such as Al2O3, BN, AlN, Si3N4, diamond or any other thermally conductive particles.

[0040] FIG. 2A to FIG. 2C A cross-sectional view showing other examples of the semiconductor device according to the first aspect.

[0041] Figure 2A An example of a semiconductor device 20 is shown, which includes: a first lead frame 21, which includes a first die pad 21A and one or more first leads 21B formed integrally with the first die pad 21A and extending outward from the first die pad 21A in a first direction; a second lead frame 22, which includes a second die pad 22A and one or more second leads 22B formed integrally with the second die pad 22A and extending outward from the second die pad 22A in a second direction different from the first direction; a semiconductor die 23, which is arranged between the first die pad 21A and the second die pad 22A; and an encapsulation material 24, which embeds the semiconductor die 23, wherein the first lead 21B and the second lead 22B are substantially or mostly arranged outside the encapsulation material 24.

[0042] With Figure 1 The example shown in FIG. 1 differs in that the lower main surface 24A of the encapsulation material 24 is aligned with the plane PP (see FIG. 1 ). Figure 1 ) and are therefore coplanar with the lower main faces of the end attachment members 21B.1 and 22B.1 of the first lead 21B and the second lead 22B. As a further distinction, the first die pad 21A is connected to an extended metal connector 21A.1 provided on the encapsulation material 24. In another embodiment, the first die pad 21A and the extended metal connector 21A.1 can be made of an integral metal piece. Due to the process, the following situation may occur: after packaging, the surface area of ​​the encapsulation material laterally close to the first pad 21A is exposed to the outside. If this situation is not desired, this surface area can be subsequently removed and replaced by the metal connector 21A.1, which can be deposited, for example, by electroplating.

[0043] for Figure 2A For the semiconductor device 20 shown in FIG. 1 , both bottom side cooling and top side cooling for heat dissipation during operation are possible.

[0044] Figure 2B An example of a semiconductor device 30 is shown, which includes: a first lead frame 31, which includes a first die pad 31A and one or more first leads 31B formed integrally with the first die pad 31A and extending outward from the first die pad 31A in a first direction; a second lead frame 32, which includes a second die pad 32A and one or more second leads 32B formed integrally with the second die pad 32A and extending outward from the second die pad 32A in a second direction different from the first direction; a semiconductor die 33, which is disposed between the first die pad 31A and the second die pad 32A; and an encapsulation material 34, which embeds the semiconductor die 33, wherein the first lead 31B and the second lead 32B are substantially or mostly disposed outside the encapsulation material 34.

[0045] With Figure 1 The example shown in FIG. 1 differs in that the lower main surface of the encapsulation material 34 is aligned with the plane PP (see FIG. 1 ). Figure 1 ) and thus are coplanar with the lower main faces of the end attachment members 31B.1 and 32B.1 of the first lead 31B and the second lead 32B. As a further distinction, a surface area of ​​the encapsulation material 34 laterally adjacent to the first pad 31A is exposed to the outside. As a further distinction, a portion of the die pad 31A has a greater thickness than the lead 31B. This portion of the die pad 31A completely covers the semiconductor die 33. The first lead frame 31 may therefore include a double-gauge lead frame.

[0046] Generally speaking, the lead frame can be a single-gauge lead frame with a relatively low thickness or a double-gauge lead frame with a relatively high thickness. In the present case, the first lead frame and the second lead frame can both be single-gauge lead frames with the same low thickness or double-gauge lead frames with the same high thickness. In addition, the first lead frame and the second lead frame have different thicknesses, in particular, one of them is a single-gauge lead frame and the other is a double-gauge lead frame.

[0047] for Figure 2B With the semiconductor device 30 shown in FIG. 3 , both bottom side cooling and top side cooling for heat dissipation are possible during operation, with bottom side cooling also occurring via the encapsulation material and not just via the leads.

[0048] Figure 2CAn example of a semiconductor device 40 is shown, which includes: a first lead frame 41, which includes a first die pad 41A and one or more first leads 41B formed integrally with the first die pad 41A and extending outward from the first die pad 41A in a first direction; a second lead frame 42, which includes a second die pad 42A and one or more second leads 42B formed integrally with the second die pad 42A and extending outward from the second die pad 42A in a second direction different from the first direction; a semiconductor die 43, which is arranged between the first die pad 41A and the second die pad 42A; and an encapsulation material 44, which embeds the semiconductor die 43, wherein the first lead 41B and the second lead 42B are substantially or mostly arranged outside the encapsulation material 44.

[0049] With Figure 1 The example shown in FIG. 1 differs in that the lower main surface of the encapsulation material 44 is aligned with the plane PP (see FIG. Figure 1 ) and are therefore coplanar with the lower main faces of the end attachment members 41B.1 and 42B.1 of the first lead 41B and the second lead 42B. As a further distinction, the surface area of ​​the encapsulation material 44 laterally adjacent to the first pad 41A is exposed to the outside. As a further distinction, the first die pad 41A and the first lead 41B have a greater thickness over their entire lengths than the second die pad 42A and the second lead 42B.

[0050] for Figure 2C In the semiconductor device 40 shown in FIG. 4 , both bottom side cooling and top side cooling for heat dissipation during operation are possible.

[0051] FIG. 3A to FIG. 3C A cross-sectional view is shown to illustrate the method for manufacturing the Figure 1 An example method of a semiconductor device is shown.

[0052] Figure 3A It is shown that the first lead frame 11 is provided in the form of a Cu metal plate. The semiconductor die 13 includes a first main surface and a second main surface opposite to the first main surface, and the semiconductor die 13 is connected to the first part of the upper surface of the first lead frame by means of a first conductive layer 15 with its first main surface. A second lead frame 12 is provided, which also has the form of a Cu metal plate. The second lead frame 12 is connected to the second main face of the semiconductor die 13 by means of a second conductive layer 16 with its first part. The first conductive layer 15 and the second conductive layer 16 can be a solder layer 16 or a sintered layer 16.

[0053] Figure 3BThe encapsulation material 14 is shown to be applied to the semiconductor die 13 and to the first part of the first lead frame 11 and the first part of the second lead frame 12. As already mentioned before, the encapsulation material 14 can be composed of a conventional molding compound, such as a resin material, in particular an epoxy resin material, and the encapsulation material 14 can be filled with thermally conductive particles. The encapsulation material 14 is applied so that it only embeds the semiconductor die 13 and the first part of the first lead frame 11 and the first part of the second lead frame 12, leaving the second part. In terms of the application process, the encapsulation material 14 can be applied by transfer molding or compression molding.

[0054] Figure 3C It is shown that the second portion 11B of the first lead frame 11 and the second portion 12B of the second lead frame 12 are bent so that the outer ends of the second portions 11B and 12B are located in a plane parallel to the first portion 11A of the first lead frame 11 and the first portion 12A of the second lead frame 12. Thus, the first portions 11A and 12A of the lead frames 11 and 12 become the die pads 11A and 12A, and the second portions 11B and 12B become the leads 11B and 12B. The end attachment members 11B.1 and 12B.1 can be formed by appropriately bending the end portions of the first lead 11B and the second lead. As described above, Figure 3C The bending shown in can also be performed before molding. It is also possible to bend only one of the leads 11B or 12B, then perform molding, and then bend the other of the leads 11B or 12B.

[0055] Figures 4A to 4C A cross-sectional view is shown to explain another example method for manufacturing a semiconductor device.

[0056] Figure 4A and Figure 3A are similar, so all the details will not be repeated here. Figure 3A Differently, the second lead frame 12 is provided from the beginning such that the second lead frame 12 includes a die pad 12A and one or more leads 12B bent from the die pad 12A.

[0057] Figure 4B The encapsulation material 24 is shown applied to the semiconductor die 13 and to the first portion of the first lead frame 11 and the first portion of the second lead frame 12. The encapsulation material 24 may have a FIG. 3A to FIG. 3C The encapsulation material 24 has the same or similar properties as the encapsulation material 14. Unlike the encapsulation material 14, the encapsulation material 24 is applied so that it includes an additional portion 24.1 at one side of the semiconductor die 13. This additional area provides a more robust encapsulation and can also provide increased high voltage tolerance, i.e. the ability of the semiconductor device to withstand high voltages. Therefore, devices manufactured in this way are particularly suitable for high voltage applications.

[0058] Figure 4C The second portion 11B is shown bent from the first portion 11A, so it can now be said that the first portion 11A serves as the die pad 11A, and it can now be said that the second portion 11B serves as the lead 11B of the first lead frame 11 .

[0059] FIG. 5A to FIG. 5E Cross-sectional views are shown to illustrate a method for manufacturing two or more semiconductor devices in a parallel process.

[0060] Figure 5A A first lead frame 51 is shown, which includes two regions 51.1 and 51.2 arranged opposite to each other and a region 51.3, which is configured so that the two regions 51.1 and 51.2 can be easily separated from each other in a subsequent step. The region 51.3 basically includes a plurality of interconnection ridges located between the regions 51.1 and 51.2, which are used as leads of the semiconductor device to be manufactured after being cut in the final process step.

[0061] Figure 5B The connection of two semiconductor dies 53 . 1 and 53 . 2 to two regions 51 . 1 and 51 . 2 of the first leadframe 51 is shown.

[0062] Figure 5C The connection of two second lead frames 52.1 and 52.2 to the upper surfaces of two semiconductor dies 53.1 and 53.2 is shown.

[0063] Figure 5D The application of encapsulation material to two semiconductor dies 53.1 and 53.2 and parts of two lead frames 52.1 and 52.2 is shown.After cutting the interconnect ridges of the area 51.3, two semiconductor devices may be obtained.

[0064] Figure 5E Another solution is shown, in which even four semiconductor devices can be obtained. Here, two Figure 5C The components shown are placed side by side and an encapsulation material is applied to each of the upper and lower regions of the combined component. Subsequently, four semiconductor devices are obtained by singulation.

[0065] Example

[0066] Specific examples of the present disclosure are described below.

[0067] Example 1 is a semiconductor device, comprising: a first lead frame, comprising a first die pad and one or more first leads integrally formed with the first die pad and extending outward from the first die pad along a first direction; a second lead frame, comprising a second die pad and one or more second leads integrally formed with the second die pad and extending outward from the second die pad along a second direction different from the first direction; a semiconductor die disposed between the first die pad and the second die pad; and an encapsulation material embedded with the semiconductor die, wherein the first lead and the second lead are disposed outside the encapsulation material.

[0068] Example 2 is a semiconductor device according to Example 1, wherein a first die pad is arranged on a first level, a second die pad is arranged on a second level, a first lead extends from the first level to a third level outside the encapsulation material, and a second lead extends from the second level to the third level outside the encapsulation material.

[0069] Example 3 is the semiconductor device according to Example 1 or 2, wherein the first die pad of the first lead frame is at least partially exposed at the top surface of the package body.

[0070] Example 4 is a semiconductor device according to any of the preceding examples, wherein the semiconductor die is a vertical semiconductor transistor die, in particular a semiconductor power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die (in particular a SiC transistor die).

[0071] Example 5 is a semiconductor device according to Example 4, wherein the semiconductor transistor die includes a first main surface and a second main surface opposite to the first main surface, and a source pad disposed on the first main surface and a drain pad disposed on the second main surface.

[0072] Example 6 is the semiconductor device according to Example 5, wherein the drain pad is connected to the first die pad of the first lead frame, and the source pad is connected to the second die pad of the second lead frame.

[0073] Example 7 is the semiconductor device according to Example 5 or 6, further comprising a gate pad disposed on the first main surface.

[0074] Example 8 is a semiconductor device according to any of the preceding examples, wherein the device is a leaded package, in particular a gull-wing package, a J-lead package, a C-lead or a through-hole package.

[0075] Example 9 is a method for manufacturing a semiconductor device, the method comprising: providing a first lead frame; providing a semiconductor die comprising a first main surface and a second main surface opposite to the first main surface; connecting the first main surface of the semiconductor die to a first portion of the first lead frame; providing a second lead frame; connecting the first portion of the second lead frame to the second main surface of the semiconductor die; applying an encapsulation material to the semiconductor die and to the first portion of the first lead frame and the first portion of the second lead frame, so that the second portion of the first lead frame and the second portion of the second lead frame are arranged outside the encapsulation material.

[0076] Example 10 is a method according to Example 9, which further includes: after applying the encapsulation material, bending at least a portion of the second part of the first lead frame and at least a portion of the second part of the second lead frame so that the outer end of the second part is located in a plane parallel to the first part of the first lead frame and the first part of the second lead frame, or providing one or both of the first lead frame and the second lead frame in the form of a pre-bent lead frame.

[0077] Example 11 is the method of Example 10, wherein the second portion of the first lead frame is bent at a first angle, and the second portion of the second lead frame is bent at a second angle.

[0078] Example 12 is the method of any one of Examples 9 to 11, wherein the method is performed such that a surface of the first portion of the first leadframe remote from the semiconductor die is exposed at a top surface of the package.

[0079] Example 13 is a method according to any one of Examples 9 to 12, wherein at least two semiconductor devices are manufactured in parallel by: connecting two semiconductor dies to a first lead frame, providing two second lead frames, connecting each of the two second lead frames to one of the semiconductor dies, applying two encapsulation materials to each of the semiconductor dies and to a first portion of the first lead frame and a first portion of the second lead frame, and singulating into two independent semiconductor devices.

[0080] In addition, although a particular feature or aspect of an embodiment of the present disclosure may be disclosed only with respect to one of the multiple embodiments, this feature or aspect may be combined with one or more other features or aspects of other embodiments, which may be desirable and advantageous for any given or specific application. In addition, with respect to the terms "including," "having," "with," or other variations thereof used in the specific embodiments or claims, these terms are intended to be inclusive in a manner similar to the term "including." In addition, it should be understood that embodiments of the present disclosure may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programming devices. In addition, the term "exemplary" is meant only as an example, not the best or optimal. It should also be understood that, for the purpose of simplicity and ease of understanding, the features and / or elements depicted herein are shown as having specific dimensions relative to each other, and the actual dimensions may be significantly different from the dimensions shown herein.

[0081] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that various alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the present disclosure. The present application is intended to cover any modifications or variations of the specific embodiments discussed herein. Therefore, the present disclosure is intended to be limited only by the claims and their equivalents.

Claims

1. A semiconductor device (10), comprising: - a first lead frame (11) comprising a first die pad (11A) and one or more first leads (11B) formed integrally with the first die pad (11A) and extending outwardly from the first die pad (11A) in a first direction; - a second lead frame (12) comprising a second die pad (12A) and one or more second leads (12B) formed integrally with the second die pad (12A) and extending outwardly from the second die pad (12A) in a second direction different from the first direction; - a semiconductor die (13) disposed between the first die pad (11A) and the second die pad (12A); and - an encapsulation material (14) in which the semiconductor die (13) is embedded, and the first lead (11B) and the second lead (12B) are arranged outside the encapsulation material (14); It is characterized in that The first die pad (11A) of the first lead frame (11) is completely exposed at the top surface of the device (10).

2. The semiconductor device (10) according to claim 1, wherein: A first die pad (11A) is disposed on a first level, a second die pad (12A) is disposed on a second level, and The first lead (11B) extends from the first level to the third level outside the encapsulation material (14), and the second lead (12B) extends from the second level to the third level outside the encapsulation material (14).

3. The semiconductor device (10) according to claim 1 or 2, wherein: The semiconductor die (13) is a vertical semiconductor transistor die, in particular a semiconductor power transistor die; an IGBT die; a MOSFET die; CoolMOS die; wide bandgap semiconductor transistor die, in particular SiC transistor die.

4. The semiconductor device (10) according to claim 3, wherein: The semiconductor transistor die (13) comprises a first main surface and a second main surface opposite to the first main surface, and A source pad is provided on the first main surface, and a drain pad is provided on the second main surface.

5. The semiconductor device (10) according to claim 4, wherein: The drain pad is connected to a first bare chip pad (11A) of a first lead frame (11), and the source pad is connected to a second bare chip pad (12A) of a second lead frame (12).

6. The semiconductor device (10) according to claim 4 or 5, wherein: The semiconductor device (10) further comprises: A gate pad is provided on the first main surface.

7. A semiconductor device according to any one of the preceding claims, wherein: The device is a leaded package, in particular a gull-wing package, a J-lead package, a C-lead or a through-hole package.

8. A method for manufacturing a semiconductor device, the method comprising: - providing a first lead frame (11) comprising a first die pad (11A) and one or more first leads (11B); - providing a semiconductor die (13) comprising a first main surface and a second main surface opposite to the first main surface; - connecting a first main surface of the semiconductor die (13) to a first portion of a first lead frame (11); - providing a second lead frame (12); - connecting a first portion of a second lead frame (12) to a second main face of the semiconductor die (13); - applying an encapsulation material (14, 24) to the semiconductor die (13) and to a first portion of the first lead frame (11) and a first portion of the second lead frame (12), such that a second portion of the first lead frame (11) and a second portion of the second lead frame (12) are disposed outside the encapsulation material (14, 24), and a first die pad (11A) of the first lead frame (11) is completely exposed at a top surface of the device.

9. The method according to claim 8, wherein: The method further comprises: After applying the encapsulation material (14, 24), bending at least a portion of the second portion of the first lead frame (11) and at least a portion of the second portion of the second lead frame (12) so that outer ends of the second portions are located in a plane parallel to the first portion of the first lead frame and the first portion of the second lead frame, or One or both of the first lead frame and the second lead frame are provided in the form of a pre-bent lead frame.

10. The method according to claim 9, wherein: The second portion of the first lead frame is bent at a first angle, and the second portion of the second lead frame is bent at a second angle.

11. The method according to any one of claims 8 to 10, wherein: The method is performed so that a surface of the first portion of the first lead frame (11) away from the semiconductor die (13) is exposed at the top surface of the package.

12. The method according to any one of claims 8 to 11, wherein: At least two semiconductor devices are fabricated in parallel by: - connecting two semiconductor dies to the first lead frame; - providing two second lead frames; - connecting each of the two second lead frames to one of the semiconductor dies; - applying two encapsulation materials to each of the semiconductor dies and to the first portion of the first leadframe and to the first portion of the second leadframe; as well as - Singulated into two independent semiconductor devices.

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