Board-level packaging structure and packaging system

Abstract

The embodiment of the invention provides a board-level packaging structure and a packaging system, and the board-level packaging structure comprises a plurality of board-level packaging units which are electrically connected with each other. Each board-level packaging unit packaging structure comprises a square panel, a plastic packaging layer, a plurality of bridging chips, a chip operation module, a first connection module, a power management module and a second connection module; the square panel is provided with a first vertical interconnection structure penetrating through the thickness of the square panel; the plastic package layer is arranged on the first surface of the square panel, and the plastic package layer is provided with a second vertical interconnection structure which penetrates through the thickness of the plastic package layer and is electrically connected with the first vertical interconnection structure; the bridging chip is arranged on the first surface of the square panel and wraps the plastic package layer; the chip operation module and the first connection module are arranged on one side, deviating from the square panel, of the plastic package layer; the power management module and the second connection module are arranged on the second surface of the square panel. The structure adopts a square panel, so that the system performance is remarkably improved, and high computing power integration is realized; the double-sided connection structure realizes back vertical power supply, and effectively shortens the transmission path.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of semiconductor packaging technology, and specifically relate to a board-level packaging structure and a packaging system. Background Art

[0002] SoW (System on wafer) integrates a certain number of computing chips onto a whole wafer as a whole to form an ultra-high performance (HPC) chip system.

[0003] SoW uses FO technology to reconstruct the computing chip into a wafer with a glass carrier as the carrier, completes the interconnection between chips through plastic packaging and rewiring, peels off the carrier, and interconnects the power device with the computing chip through flip-chip on the reconstructed wafer to form the entire on-wafer system.

[0004] Due to the limitation of wafer size, the overall performance of a single SoW system is limited.

[0005] In view of the above problems, it is necessary to propose a board-level packaging structure and packaging system that are reasonably designed and effectively solve the above problems. Summary of the invention

[0006] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a board-level packaging structure and a packaging system.

[0007] The present disclosure provides a board-level packaging structure, including:

[0008] a square panel provided with a plurality of first vertical interconnect structures extending through the thickness thereof;

[0009] A plastic encapsulation layer, disposed on the first surface of the square panel, wherein the plastic encapsulation layer is provided with a plurality of second vertical interconnection structures penetrating through the thickness thereof and electrically connected to the first vertical interconnection structure;

[0010] A plurality of bridge chips are arranged on the first surface of the square panel and wrapped in the plastic packaging layer;

[0011] A chip operation module and a first connection module are arranged on a side of the plastic packaging layer away from the square panel, and are electrically connected to the bridge chip and the second vertical interconnection structure respectively;

[0012] The power management module and the second connection module are arranged on the second surface of the square panel and are electrically connected to the first vertical interconnection structure.

[0013] Optionally, the chip operation module includes a first redistribution wiring pattern layer and a chip operation layer;

[0014] The first redistribution layer is disposed on a surface of the plastic packaging layer away from the square panel, and is electrically connected to the bridge chip and the second vertical interconnect structure respectively;

[0015] The chip operation layer is arranged on the first redistribution layer and is electrically connected to the first redistribution layer.

[0016] Optionally, the chip computing layer includes a plurality of computing chips, or the chip computing layer includes a plurality of the computing chips and a plurality of storage chips.

[0017] Optionally, the first connection module includes a plurality of first connectors arranged on the first redistribution layer and a first cable arranged on the first connectors.

[0018] Optionally, the first connection module further includes a plurality of photoelectric conversion chips arranged in the first redistribution layer and optical fibers arranged in the photoelectric conversion chips.

[0019] Optionally, the power management module includes a second redistribution layer and a power management chip;

[0020] The second redistribution layer is disposed on the second surface of the square panel and is electrically connected to the first vertical interconnect structure;

[0021] The power management chip is disposed in the second redistribution layer and is electrically connected to the second redistribution layer.

[0022] Optionally, the second connection module is disposed in the second redistribution layer and is electrically connected to the second redistribution layer.

[0023] Optionally, the second connection module includes a plurality of second connectors arranged on the second redistribution layer and a second cable arranged on the second connectors.

[0024] Optionally, the square panel is a glass panel.

[0025] Another aspect of the present disclosure provides a board-level packaging system, which includes at least one board-level packaging structure as described above; wherein:

[0026] When the board-level packaging system includes a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected to each other through the first connection module and the second connection module respectively.

[0027] The board-level packaging structure and packaging system of the embodiments of the present disclosure adopt a large-area square panel, which significantly improves the chip capacity, area utilization and I / O density, significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration; the chip operation module realizes high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a fine line structure in the RDL; the first surface of the square panel is provided with a chip operation module and a first connection module, and the second surface of the square panel is provided with a power management module and a second connection module, and the back of the square panel is vertically powered by the first vertical interconnection structure and the second vertical interconnection structure, effectively shortening the transmission path. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A cross-sectional view of a board-level packaging structure according to an embodiment of the present disclosure;

[0029] Figure 2 A cross-sectional view of a board-level packaging structure of another embodiment of the disclosed embodiments;

[0030] Figure 3 It is a plan view of a board-level packaging structure of another embodiment of the disclosed embodiments;

[0031] Figure 4 It is a structural schematic diagram of a board-level packaging system of another embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0033] like Figures 1 to 3 As shown, the embodiment of the present disclosure provides a board-level packaging structure 100, including a square panel 22, a plurality of bridge chips 24, a plastic layer 26, a chip operation module, a first connection module, a power management module and a second connection module.

[0034] The square panel 22 is provided with a plurality of first vertical interconnect structures 46 extending through the thickness thereof.

[0035] Specifically, preferably, in this embodiment, the square panel 22 is a glass panel. In the prior art, the carrier is peeled off during the packaging process, and the final packaging structure does not contain the carrier. However, the board-level packaging structure of the disclosed embodiment retains the square glass panel, and the rigidity of the glass panel is used to effectively control the warping of the board-level packaging structure, solve the problem of large-area EMC and chip CTE mismatch, and improve the reliability of the board-level packaging structure.

[0036] That is to say, in this embodiment, the first vertical interconnection structure 46 may be a TGV through hole, and the electrical connection of components on both sides of the square panel 22 may be achieved through the TGV through hole.

[0037] The plastic encapsulation layer 26 is disposed on the first surface of the square panel 22 . The plastic encapsulation layer 26 is provided with a plurality of second vertical interconnect structures 48 that penetrate through the thickness of the plastic encapsulation layer 26 and are electrically connected to the first vertical interconnect structures 46 .

[0038] Specifically, Figure 1 and Figure 2 As shown, the plastic encapsulation layer 26 is disposed on the top surface of the square panel 22. In this embodiment, the second vertical interconnection structure 48 may be a TMV through hole. The electrical connection of components on both sides of the plastic encapsulation layer 26 may be achieved through the TMV through hole.

[0039] A plurality of bridge chips 24 are disposed on the first surface of the square panel 22 and wrapped in a plastic packaging layer 26. Specifically, Figure 1 and Figure 2 As shown, a plurality of bridge chips 24 are disposed on the top surface of the square panel 22 and wrapped in a plastic packaging layer 26 .

[0040] The chip operation module and the first connection module are disposed on a side of the plastic packaging layer 26 away from the square panel 22 , and are electrically connected to the bridge chip 24 and the second vertical interconnection structure 48 , respectively.

[0041] The power management module and the second connection module are disposed on the second surface of the square panel 22 and are electrically connected to the first vertical interconnection structure 46. Figure 2 and Figure 3 As shown, the power management module and the second connection module are disposed on the bottom surface of the square panel 22 and are electrically connected to the first vertical interconnection structure 46 .

[0042] It should be noted that the first connection module and the second connection module are used for electrical connection between multiple board-level packaging structures.

[0043] The board-level packaging structure of the disclosed embodiment adopts a large-area square panel, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration; the chip operation module realizes high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a fine line structure in the RDL; the first surface of the square panel is provided with a chip operation module and a first connection module, and the second surface of the square panel is provided with a power management module and a second connection module, and the back of the square panel is vertically powered by the first vertical interconnection structure and the second vertical interconnection structure, thereby effectively shortening the transmission path.

[0044] For example, Figures 1 to 3As shown, the chip computing module is disposed in the central area of ​​the plastic layer 26, and the first connection module is disposed in the edge area of ​​the plastic layer 26. That is, the chip computing module is located in the central area of ​​the first surface of the square panel 22, and the first connection module is located in the edge area of ​​the first surface of the square panel 22.

[0045] For example, Figure 1 and Figure 2 As shown, the chip computing module includes a first redistribution layout layer and a chip computing layer 32 .

[0046] The first redistribution layer is disposed on the surface of the plastic layer 26 away from the square panel 22 and is electrically connected to the bridge chip 24 and the second vertical interconnect structure 48 respectively.

[0047] The chip computing layer 32 is disposed on the first redistribution layer and is electrically connected to the first redistribution layer.

[0048] In this embodiment, the chip computing layer 32 may include only a plurality of computing chips, or the chip computing layer 32 may include a plurality of computing chips and a plurality of storage chips. Of course, the chip computing layer 32 may also use other types of chips. The chips in the chip computing layer 32 are electrically interconnected through the first redistribution layer and the bridge chip 24. According to the area of ​​the square panel 22, the chip computing layer 32 is distributed in a matrix, which can significantly improve the chip capacity, area utilization and I / O density of the entire packaging structure.

[0049] It should be noted that there is no specific limitation on the type and quantity of the chip operation layer 32 , and they can be selected according to actual needs.

[0050] For example, Figure 1 and Figure 2 As shown, the first redistribution layer includes a first dielectric layer 28 and a first metal layer 30. The first dielectric layer 28 is disposed on the surface of the plastic encapsulation layer 26 away from the square panel 22, the functional surface of the bridge chip 24, and the surface of the second vertical interconnection structure 48 away from the square panel 22. The first dielectric layer 28 is provided with a plurality of first openings, and the first metal layer 30 is disposed in the first openings. The first metal layer 30 is electrically connected to the bridge chip 24 and the second vertical interconnection structure 48, respectively. In this embodiment, the first dielectric layer 28 can be a PI layer, and the first metal layer 30 can be a metal copper layer.

[0051] In this embodiment, by providing the first redistribution layer, high-density interconnection of the chip computing layer can be achieved.

[0052] For example, Figure 1 As shown, in one embodiment, the first connection module includes a plurality of first connectors 34 disposed on a first redistribution layer and a first cable 36 disposed on the first connectors 34 .

[0053] Specifically, Figure 1 As shown, a plurality of first connectors 34 are disposed on the first metal layer 30 at an edge region of the square panel 22 , and a first cable 36 is disposed on each first connector 34 .

[0054] It should be noted that the present embodiment does not specifically limit the number of the first connectors 34 and can be selected according to actual needs.

[0055] For example, Figure 2 As shown, in another embodiment, the first connection module further includes a plurality of photoelectric conversion chips 38 disposed in the first redistribution layer and optical fibers 40 disposed in the photoelectric conversion chips 38 .

[0056] Specifically, Figure 2 As shown, a plurality of photoelectric conversion chips 38 are disposed on the first metal layer 30 at the edge region of the square panel 22 , and an optical fiber 40 is disposed on each photoelectric conversion chip 38 .

[0057] It should be noted that there is no specific limitation on the number of the photoelectric conversion chips 38 , and the number can be selected according to actual needs.

[0058] It should be further explained that there is no specific limitation on the specific type of the first connection module, and it can be selected according to actual needs.

[0059] For example, Figure 1 and Figure 2 As shown, the power management module includes a second redistribution layer and a power management chip 56. The second redistribution layer is disposed on the second surface of the square panel 22 and is electrically connected to the first vertical interconnection structure 46. The power management chip 56 is disposed on the second redistribution layer and is electrically connected to the second redistribution layer.

[0060] In this embodiment, high-density interconnection of power management chips can be achieved through the second redistribution layer, and vertical power supply to the back of the square panel can be achieved by arranging multiple power management chips on the second surface of the square panel, effectively shortening the transmission path.

[0061] For example, Figure 1 and Figure 2 As shown, the second redistribution layer includes a second dielectric layer 52 and a second metal layer 53. The second dielectric layer 52 is disposed on the second surface of the square panel 22 and the surface of the first vertical interconnect structure 46 facing the power management chip 56. The second dielectric layer 52 is provided with a plurality of second openings, and a second metal layer 54 is disposed in the second openings. In this embodiment, the second dielectric layer 52 can be a PI layer, and the second metal layer 54 can be a metal copper layer.

[0062] For example, Figure 1 and Figure 2 As shown, the second connection module is disposed in the second redistribution layer and is electrically connected to the second redistribution layer. Specifically, the second connection module is disposed in the second metal layer 54 and is electrically connected to the second metal layer 54.

[0063] For example, Figure 1 and Figure 2 As shown, the second connection module includes a plurality of second connectors 34 ′ disposed on the second redistribution layer and a second cable 36 ′ disposed on the second connectors 34 ′.

[0064] It should be noted that if Figure 1 and Figure 2 As shown, in this embodiment, the plurality of second connectors 34' can be distributed at intervals from the power management chip 56. Of course, the plurality of second connectors 34' can be arranged at the edge area of ​​the second surface of the square panel 22. The number and distribution of the second connectors 34' are not specifically limited in this embodiment and can be selected according to actual needs.

[0065] Exemplarily, in this embodiment, the square panel 22 may be a glass panel.

[0066] In the prior art, the carrier is peeled off during the packaging process, and the final packaging structure does not contain the carrier. However, the board-level packaging structure of the embodiment of the present disclosure retains the square glass panel, and effectively controls the warping of the board-level packaging structure by using the rigidity of the glass panel, solves the problem of large-area EMC and chip CTE mismatch in the prior art, and improves the reliability of the board-level packaging structure. In addition, a plurality of first vertical interconnect structures are arranged on the retained square panel to realize vertical interconnection of the packaging structure, effectively shortening the transmission path.

[0067] like Figure 4 As shown, another aspect of the embodiment of the present disclosure provides a board-level packaging system A, comprising at least one board-level packaging structure 100 as described above. The specific structural features of the board-level packaging structure 100 have been described in detail above and will not be repeated here.

[0068] When the board-level packaging system A includes a plurality of board-level packaging structures 100 , the plurality of board-level packaging structures 100 are electrically connected to each other through a first connection module and a second connection module, respectively.

[0069] like Figure 1 As shown, in one embodiment, a plurality of board-level packaging structures 100 are electrically connected through a first cable 36 and a second cable 36', respectively, to form Figure 4 Board-level packaging system A is shown.

[0070] like Figure 2As shown, in another embodiment, a plurality of board-level packaging structures 100 are electrically connected to each other through optical fibers 40 and second cables 36', forming Figure 4 Board-level packaging system A is shown.

[0071] It should be noted that, in this embodiment, there is no specific limitation on the electrical connection method between the multiple board-level packaging structures 100, and it can be selected according to actual needs.

[0072] It should be further explained that there is no specific requirement for the number of board-level packaging structures 100 in the board-level packaging system A, and the number can be selected according to the size of the board-level packaging structure.

[0073] The board-level packaging system of the disclosed embodiment includes at least one board-level packaging structure as described above. The board-level packaging structure adopts a large-area square panel, which significantly improves the chip capacity, area utilization and I / O density, and significantly improves the system performance, thereby solving the problem of limited performance of a single SoW system and realizing high computing power integration; the chip operation layer realizes high-density interconnection with the help of multiple bridge chips, and no longer needs to rely on building a fine line structure in RDL. The first surface of the square panel is provided with a chip operation module and a first connection module, and the second surface of the square panel is provided with a power management module and a second connection module. The back of the square panel is vertically powered by the first vertical interconnection structure and the second vertical interconnection structure, effectively shortening the transmission path.

[0074] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A board-level packaging structure, characterized in that: include: a square panel provided with a plurality of first vertical interconnect structures extending through the thickness thereof; A plastic encapsulation layer, disposed on the first surface of the square panel, wherein the plastic encapsulation layer is provided with a plurality of second vertical interconnection structures penetrating through the thickness thereof and electrically connected to the first vertical interconnection structure; A plurality of bridge chips are arranged on the first surface of the square panel and wrapped in the plastic packaging layer; A chip operation module and a first connection module are arranged on a side of the plastic packaging layer away from the square panel, and are electrically connected to the bridge chip and the second vertical interconnection structure respectively; The power management module and the second connection module are arranged on the second surface of the square panel and are electrically connected to the first vertical interconnection structure.

2. The board-level packaging structure according to claim 1, characterized in that: The chip operation module includes a first redistribution wiring layer and a chip operation layer; The first redistribution layer is disposed on a surface of the plastic packaging layer away from the square panel, and is electrically connected to the bridge chip and the second vertical interconnect structure respectively; The chip operation layer is arranged on the first redistribution layer and is electrically connected to the first redistribution layer.

3. The board-level packaging structure according to claim 2, characterized in that: The chip operation layer includes a plurality of computing chips, or the chip operation layer includes a plurality of the computing chips and a plurality of storage chips.

4. The board-level packaging structure according to claim 2, characterized in that: The first connection module includes a plurality of first connectors disposed on the first redistribution layer and a first cable disposed on the first connectors.

5. The board-level packaging structure according to claim 2, characterized in that: The first connection module further includes a plurality of photoelectric conversion chips disposed on the first redistribution layer and optical fibers disposed on the photoelectric conversion chips.

6. The board-level packaging structure according to any one of claims 1 to 5, characterized in that: The power management module includes a second redistribution layer and a power management chip; The second redistribution layer is disposed on the second surface of the square panel and is electrically connected to the first vertical interconnect structure; The power management chip is disposed in the second redistribution layer and is electrically connected to the second redistribution layer.

7. The board-level packaging structure according to claim 6, characterized in that: The second connection module is disposed on the second redistribution layer and is electrically connected to the second redistribution layer.

8. The board-level packaging structure according to claim 7, characterized in that: The second connection module includes a plurality of second connectors disposed on the second redistribution layer and a second cable disposed on the second connectors.

9. The board-level packaging structure according to any one of claims 1 to 5, characterized in that: The square panel is a glass panel.

10. A board-level packaging system, characterized in that: Comprising at least one board-level packaging structure according to any one of claims 1 to 9; wherein, When the board-level packaging system includes a plurality of board-level packaging structures, the plurality of board-level packaging structures are electrically connected to each other through the first connection module and the second connection module respectively.

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