Semiconductor chip and semiconductor device

Abstract

A semiconductor chip (1) is provided with: a semiconductor substrate (2) having a first surface (2A) and on which a semiconductor element is formed; and a plurality of pads (3) which are electrically connected to the semiconductor element and are arranged on the first surface at intervals. The plurality of pads include a first control pad (6) and a second control pad (7). In a plan view, the second control pad includes an irregularly-shaped portion (7A) having an irregularly-shaped outer shape than the first control pad.

Description

Technical Field

[0001] The present invention relates to a semiconductor chip and a semiconductor device. Background Art

[0002] A semiconductor device is known that includes a singulated semiconductor chip and a mounting substrate on which the semiconductor chip is mounted. The semiconductor chip is provided with an alignment mark for positioning the semiconductor chip in the semiconductor device.

[0003] Generally, alignment marks are formed as two or more patterns in a region different from a wiring region such as a pad for electrical connection to an external component on a semiconductor chip (for example, see International Publication No. 2002 / 082540).

[0004] In order to properly position a semiconductor chip in a semiconductor device, it is necessary to form a large alignment mark having high visibility on the semiconductor chip.

[0005] Therefore, when an alignment mark showing high visibility is formed in a region different from a wiring region such as a pad as described above, it is difficult to achieve miniaturization of a semiconductor chip.

[0006] In particular, as power semiconductor chips made of silicon carbide (SiC) or the like have become increasingly smaller in recent years, it has become difficult to form alignment marks that have high visibility on the power semiconductor chips. Summary of the invention

[0007] A main object of the present invention is to provide a semiconductor chip and a semiconductor device having an alignment mark showing high visibility and capable of being miniaturized.

[0008] The semiconductor chip of the present invention comprises: a semiconductor substrate having a first surface, on which a semiconductor element is formed; and a plurality of pads electrically connected to the semiconductor element and arranged on the first surface at intervals. The plurality of pads include a first pad and a second pad. When viewed from above, the second pad includes a shaped portion having a shaped shape compared to the first pad.

[0009] The above and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a plan view for explaining the semiconductor chip involved in the first embodiment.

[0011] Figure 2 This is a partially enlarged plan view for explaining the semiconductor chip involved in the first embodiment.

[0012] Figure 3 This is a plan view for explaining the semiconductor device according to the first embodiment.

[0013] Figure 4 This is a plan view for explaining a first modification of the semiconductor chip according to the first embodiment.

[0014] Figure 5 This is a partially enlarged plan view for explaining a second modification of the semiconductor chip according to the first embodiment.

[0015] Figure 6 This is a partially enlarged plan view for explaining a third modified example of the semiconductor chip according to the first embodiment.

[0016] Figure 7 This is a partially enlarged plan view for explaining a fourth modified example of the semiconductor chip according to the first embodiment.

[0017] Figure 8 This is a top view for explaining the semiconductor chip involved in the second embodiment.

[0018] Fig. 9 This is a top view for explaining the semiconductor chip involved in the third embodiment.

[0019] Fig.10 It is a top view for explaining the semiconductor chip involved in the fourth embodiment.

[0020] Fig.11 is from Fig.10 A partially enlarged cross-sectional view as observed by arrows XI-XI. DETAILED DESCRIPTION

[0021] Hereinafter, the embodiment of the present invention will be described with reference to the accompanying drawings. In addition, in the following, the same reference numerals are attached to the same or corresponding parts, and repeated descriptions are omitted.

[0022] Implementation Method 1

[0023] <Structure of semiconductor chip>

[0024] like Figure 1 and Figure 2 As shown, the semiconductor chip 1 according to the first embodiment includes a semiconductor substrate 2 and a plurality of pads 3 .

[0025] The semiconductor substrate 2 has a first surface 2A and a second surface 2B located on the opposite side of the first surface 2A. The top view in this specification refers to the viewing angle observed from a direction orthogonal to the first surface 2A. The semiconductor substrate 2 has an arbitrary element structure formed on the semiconductor substrate having the first surface 2A and the second surface 2B. When viewed from above, the outer shape of the semiconductor substrate 2 is, for example, rectangular. The semiconductor substrate 2 includes, for example, silicon carbide (SiC) as a base material.

[0026] The semiconductor element is, for example, a vertical semiconductor element. The semiconductor element is, for example, a power semiconductor element. The semiconductor element is, for example, a switching element such as an IGBT (Insulated Gate Bipolar Transistor), a GCT (Gate Commutated Turn-off Thyristor), or a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor). The semiconductor element is, for example, configured to control the main current flowing through the main pad 4 in response to a signal input to the first control pad 6 and the second control pad 7 described later.

[0027] In addition, the shape of the semiconductor substrate 2 is not limited to a rectangle when viewed from above. The semiconductor substrate 2 is not limited to a vertical semiconductor element. The semiconductor substrate 2 may also include a compound semiconductor material other than silicon (Si) or SiC as a base material. The semiconductor substrate 2 is not limited to a switching element, but may also be a rectifying element such as a diode.

[0028] A plurality of pads 3 are arranged on the first surface 2A of the semiconductor substrate 2 at intervals. Each of the plurality of pads 3 is electrically connected to the semiconductor element. The plurality of pads 3 include, for example, a main pad 4, a first control pad 6, and a second control pad 7. A main current of the semiconductor element flows through the main pad 4. A signal for controlling the main current is input and output to the first control pad 6 and the second control pad 7.

[0029] When viewed from above, the first control pad 6 and the second control pad 7 are arranged in a manner spaced apart from the main pad 4 in the first direction X along the first surface 2A. When viewed from above, the first control pad 6 and the second control pad 7 are arranged in a manner spaced apart from each other in the second direction Y along the first surface 2A and orthogonal to the first direction X. When viewed from above, the first control pad 6 and the second control pad 7 are each arranged in a manner spaced apart from each other. When viewed from above, the first control pad 6 and the second control pad 7 are each arranged in a rectangular area corresponding to a field of view FV described later. The interval between the first control pad 6 and the second control pad 7 is, for example, greater than or equal to the width of the first control pad 6 in the Y direction.

[0030] In a plan view, the second control pad 7 includes a deformed portion 7A having an outer shape different from that of the first control pad 6. From a different perspective, the first control pad 6 includes a deformed portion 6A having an outer shape different from that of the second control pad 7 in a plan view.

[0031] The irregular portion 7A is, for example, a part of the outer edge of the second control pad 7. From a different perspective, when viewed from above, the first control pad 6 and the second control pad 7 each further include congruent portions 6B and 7B that are located at positions corresponding to each other between the first control pad 6 and the second control pad 7 and have congruent shapes. In addition, the outer edge of the second control pad 7 may be entirely formed as the irregular portion 7A.

[0032] The deformed portions 6A and 7A are formed at positions corresponding to each other between the first control pad 6 and the second control pad 7 in a plan view.

[0033] In this specification, when viewed from above, two irregularly shaped portions are formed at positions corresponding to each other between two pads, which means that when viewed from above, the directions from the center toward the irregularly shaped portions of the two pads are the same. When viewed from above, the relative positions of the congruent portions and the irregularly shaped portions of the two pads are the same. When viewed from above, the imaginary straight lines connecting the center and the irregularly shaped portions of the two pads are, for example, parallel to each other.

[0034] When viewed from above, the direction from the center toward the irregular portion 6A in the first control pad 6 is the same as the direction from the center toward the irregular portion 7A in the second control pad 7. When viewed from above, the relative positions of the congruent portions 6B, 7B and the irregular portions 6A, 7A of the first control pad 6 and the second control pad 7 are the same. When viewed from above, the imaginary straight line A connecting the center and the irregular portion 6A in the first control pad 6 is parallel to, for example, the imaginary straight line B connecting the center and the irregular portion 7A in the second control pad 7.

[0035] When the irregular portion 7A is identified at least together with the irregular portion 6A, the position and orientation of the semiconductor chip 1 in a plan view can be indicated. Figure 1 In the semiconductor chip 1 shown, the irregular portion 7A is identified together with the irregular portion 6A and the congruent portions 6B and 7B, and can indicate that the direction in which the imaginary straight line A and the imaginary straight line B are arranged is the Y direction, and when viewed from above, the direction in a direction orthogonal to the Y direction relative to the center of the second control pad 7 toward the side where the irregular portion 7A is formed is the X direction.

[0036] When viewed from above, the outer shape of the first control pad 6 is, for example, a rounded rectangle with rounded corners at four corners. The first control pad 6 has a plurality of corners 61, 62, 63, 64 and a plurality of sides connecting two adjacent corners. When viewed from above, the first control pad 6 has, for example, rotational symmetry about the center of the first control pad 6.

[0037] When viewed from above, the second control pad 7 has a plurality of corners 71, 72, 73, 74 and a plurality of sides connecting two adjacent corners. The corner 71 is composed of, for example, a plurality of corners 75, 76, 77 and a plurality of sides connecting them. When viewed from above, the plurality of corners 71, 72, 73, 74 are respectively located at positions corresponding to the plurality of corners 61, 62, 63, 64. When viewed from above, the second control pad 7 does not have rotational symmetry around the center of the second control pad 7.

[0038] The second control pad 7 includes, for example, one irregular portion 7A. The irregular portion 7A is formed, for example, at a corner 71 of the second control pad 7. From a different point of view, the irregular portion 6A is formed, for example, at a corner 61 of the first control pad 6. When viewed from above, the corner 71 is located, for example, at a position closest to a corner of the semiconductor substrate 2 among the plurality of corners of the second control pad 7.

[0039] The irregular portion 7A has a recessed portion whose outer shape is concave compared to the first control pad 6, for example. The irregular portion 7A includes a plurality of corners 75, 76, and 77. The number of corners of the second control pad 7 is greater than the number of corners of the first control pad 6. The shape of the recessed portion is not particularly limited. As long as the mounting device used in the step of mounting the semiconductor chip 1 on the mounting substrate in the manufacturing method of the semiconductor device 100 described later can be recognized as an alignment mark, the size of the recessed portion is not particularly limited.

[0040] The congruent portions 6B and 7B are composed of the remaining portions of the outer edge portions of the first control pad 6 and the second control pad 7, except the irregular portions 6A and 7A. The congruent portion 7B includes the other corner portions 72, 73, 74 and a plurality of side portions of the outer edge portion of the second control pad 7, except the corner portion 71. The congruent portion 6B includes the other corner portions 62, 63, 64 and a plurality of side portions of the outer edge portion of the first control pad 6, except the corner portion 61.

[0041] When viewed from above, the main pad 4 has an outer shape of, for example, a rounded rectangle with four rounded corners. When viewed from above, the first control pad 6 and the main pad 4 have an outer shape of, for example, a rounded rectangle with four rounded corners.

[0042] In plan view, the main pad 4 occupies a larger area than each of the first control pad 6 and the second control pad 7. In plan view, the main pad 4 occupies a larger area than the total of the first control pad 6 and the second control pad 7, for example.

[0043] The plurality of pads 3 may further include a third control pad 8. The third control pad 8 is arranged to be spaced apart from the main pad 4 in the first direction X, and is arranged to be spaced apart from the first control pad 6 in the second direction Y, for example.

[0044] The semiconductor chip 1 has no alignment mark which is not electrically connected to the semiconductor element on the first surface 2A, that is, a pattern which functions only as an alignment mark.

[0045] The semiconductor chip 1 further includes, for example, a protective film (not shown) formed on the first surface 2A so as to surround the peripheries of the plurality of pads 3 .

[0046] <Method for manufacturing semiconductor chip>

[0047] Semiconductor chip 1 can be manufactured in the same manner as conventional semiconductor chips. Second control pad 7 having irregular shape portion 7A can be formed by any method, but can be formed, for example, by patterning a conductive film formed on first surface 2A using a mask corresponding to irregular shape portion 7A.

[0048] <Structure of semiconductor device>

[0049] like Figure 3 As shown, the semiconductor device 100 according to the first embodiment includes a semiconductor chip 1, a mounting substrate 110, a first connecting member 111, a second connecting member 112, a third connecting member 113, a fourth connecting member 114, and a packaging member (not shown).

[0050] The semiconductor chip 1 is mounted on a mounting substrate 110. An area where the semiconductor chip 1 is to be mounted is pre-specified on the mounting substrate 110, and the semiconductor chip 1 is bonded to the area by a bonding material. The mounting substrate 110 may be a substrate formed of a metal such as copper or aluminum. In addition, the mounting substrate 110 may also be a substrate using ceramics or resin as a base material.

[0051] The first connecting member 111 is electrically connected to the first control pad 6. The second connecting member 112 is electrically connected to the second control pad 7. The third connecting member 113 is electrically connected to the main pad 4. The fourth connecting member 114 is electrically connected to the third control pad 8. The first connecting member 111, the second connecting member 112, the third connecting member 113, and the fourth connecting member 114 are each electrically connected to, for example, other components not shown in the figure included in the semiconductor device 100. The first connecting member 111, the second connecting member 112, and the fourth connecting member 114 are, for example, wires or ribbons. The third connecting member 113 is, for example, a lead terminal.

[0052] In the semiconductor device 100 , a semiconductor chip 1 is packaged by a packaging member.

[0053] <Method for manufacturing semiconductor device>

[0054] The semiconductor device 100 can be manufactured in the same manner as a conventional semiconductor device. The method for manufacturing the semiconductor device 100 includes a first step of preparing a semiconductor chip 1 and a second step of mounting the semiconductor chip 1 prepared in the first step on a mounting substrate 110 .

[0055] In the second step, the first control pad 6 and the second control pad 7 are simultaneously recognized by the mounting device and used as alignment marks. The mounting device uses the field of view FV (refer to Figure 3 ) while identifying the irregular-shaped portions 6A and 7A, thereby being able to grasp the position and orientation of the semiconductor chip 1 when viewed from above.

[0056] The manufacturing method of the semiconductor device 100 further includes a third step of electrically connecting the first connecting component 111, the second connecting component 112, the third connecting component 113 and the fourth connecting component 114 to the first control pad 6, the second control pad 7, the third control pad 8 and the main pad 4 respectively after the second step.

[0057] <Effect>

[0058] In the semiconductor chip 1, the second control pad 7 (second pad) includes a shaped portion 7A having a shaped shape compared to the first control pad 6 (first pad). Therefore, the first control pad 6 and the second control pad 7 are wiring components for electrically connecting the semiconductor element in the semiconductor chip 1 and the external component in the semiconductor device 100, and can function as alignment marks. Therefore, the occupied area of ​​the first control pad 6 and the second control pad 7 is smaller than the total occupied area of ​​the pad having the same occupied area as them and the alignment mark formed in a region different from the pad. As a result, according to the semiconductor chip 1, compared with a conventional semiconductor chip having a pad electrically connected to an external component and an alignment mark formed in a region different from the pad, miniaturization can be achieved.

[0059] Furthermore, the first control pad 6 and the second control pad 7 that can function as alignment marks are wiring components as described above, and thus can be configured to be larger than alignment marks that are formed separately from pads in conventional semiconductor chips. Therefore, according to the semiconductor chip 1, compared with the conventional semiconductor chips described above, alignment marks that show higher recognition can be achieved, and miniaturization can be achieved. Such a semiconductor chip 1 is suitable for power semiconductor chips that are being miniaturized, such as power semiconductor chips that use silicon carbide (SiC) as a base material.

[0060] In the semiconductor chip 1, the first control pad 6 and the second control pad 7 each further include congruent portions 6B and 7B. In this case, the orientation of the semiconductor chip 1 can be identified based on the relative position information of the irregular portion 7A with respect to the irregular portion 6A and the congruent portion 7B. In this case, the second control pad 7 including the irregular portion 7A and the congruent portion 7B includes at least one concave portion compared to the first control pad 6, and can be easily formed.

[0061] In the semiconductor chip 1, the first control pad 6 and the second control pad 7 are adjacent to each other among the plurality of pads 3. In this way, the field of view FV required for simultaneously identifying the first control pad 6 and the second control pad 7 of the semiconductor chip 1 can be reduced compared to the case where the first control pad 6 and the second control pad 7 are not adjacent to each other. Therefore, the first control pad 6 and the second control pad 7 can be observed at a higher magnification, so the recognition of the irregular portion 7A is high, and the above-mentioned installation of the semiconductor chip 1 can be performed more efficiently. In addition, the above-mentioned conventional semiconductor chip usually has one alignment mark formed at one end of the chip when viewed from above, and another alignment mark formed at the other end of the chip when viewed from above. Therefore, in the process of mounting the conventional semiconductor chip on the mounting substrate, the mounting device usually recognizes the two alignment marks separately and in sequence to align the semiconductor chip. On the other hand, according to the semiconductor chip 1, since alignment can be performed by simultaneously recognizing the first control pads 6 and the second control pads 7, the above-mentioned mounting can be performed more efficiently than the above-mentioned conventional semiconductor chip.

[0062] Since the semiconductor device 100 includes the semiconductor chip 1, it can be miniaturized compared to a semiconductor device including a conventional semiconductor chip. In addition, in the manufacturing method of the semiconductor device 100, the semiconductor chip 1 is mounted on the mounting substrate 110 using the first control pad 6 and the second control pad 7 as alignment marks. Therefore, the manufacturing efficiency of the semiconductor device 100 is higher than that of conventional semiconductor devices.

[0063] <Modification>

[0064] like Figure 4 As shown, the third control pad 8 may be arranged between the first control pad 6 and the second control pad 7. The first control pad 6 and the second control pad 7 may not be adjacent to each other. The second control pad 7 may be arranged adjacent to the third control pad 8. In this case, similarly, the first control pad 6 and the second control pad 7 are larger than the alignment mark of the above-mentioned conventional semiconductor chip, and can be configured as an alignment mark showing high recognition.

[0065] In the semiconductor chip 1, the irregular-shaped portion 7A can be formed at any position on the outer edge of the second control pad 7 as a member having any shape. Figure 5 As shown, the irregular portion 7A may also be formed at the corner portion 72. In this case, the corner portion 71 may also be included in the congruent portion 7B. Figure 6 As shown, the irregular portion 7A may be formed on one side. In this case, a plurality of corners may be included in the congruent portion 7B.

[0066] like Figure 7As shown, the irregular portion 7A may also have a convex portion having a convex shape compared to the first control pad 6. When viewed from above, the outer shape of the second control pad 7 has, for example, an outer shape achieved when one corner of a relatively small rounded rectangle overlaps one corner of a relatively large rounded rectangle. The corner portion 71 is composed of, for example, a plurality of corner portions 75, 76, 77, 78, 79 and a plurality of side portions connecting them.

[0067] The irregularly shaped portion 7A may also have both the above-mentioned concave portion and the above-mentioned convex portion. Figure 7 At least any one of the illustrated corners 77 , 78 , 79 has a recess.

[0068] It is preferred that the irregular portion 7A is formed at least one of the plurality of corner portions 71, 72, 73, and 74 of the second control pad 7. In this way, when the area that the irregular portion 7A can occupy is limited, the degree of freedom in the shape and arrangement of the irregular portion 7A can be increased compared to the case where the irregular portion 7A is formed at any of the plurality of side portions.

[0069] Implementation Method 2

[0070] Unless otherwise specified, the semiconductor chip and semiconductor device according to Embodiment 2 have the same structure and effects as those of Embodiment 1. Therefore, the same reference numerals are given to the same structures as those of Embodiment 1, and the description thereof will not be repeated.

[0071] like Figure 8 As shown, in the semiconductor chip 12 involved in the second embodiment, the interval between the second control pad 7 and the first control pad 6 in the second direction Y is narrower than the width of the second control pad 7 in the second direction Y. The interval between the second control pad 7 and the first control pad 6 in the second direction Y is, for example, the smallest among the intervals between two pads adjacent to each other in the first direction X or the second direction Y among the plurality of pads 3.

[0072] According to the semiconductor chip 12, the interval between the second control pad 7 and the first control pad 6 in the second direction Y can be shorter than that of the semiconductor chip 1, so the field of view FV required for simultaneously recognizing the first control pad 6 and the second control pad 7 of the semiconductor chip 12 can be smaller than the field of view FV required for simultaneously recognizing the first control pad 6 and the second control pad 7 of the semiconductor chip 1. Therefore, according to the semiconductor chip 12, the recognizability of the irregular-shaped portion 7A is further improved compared with the semiconductor chip 1, and the above-mentioned mounting of the semiconductor chip 1 can be performed more efficiently.

[0073] The semiconductor chip 12 according to the second embodiment can also be modified in the same manner as the semiconductor chip 1 according to the first embodiment.

[0074] Implementation 3

[0075] Unless otherwise specified, the semiconductor chip and semiconductor device according to Embodiment 3 have the same structure and effects as those of Embodiment 1. Therefore, the same reference numerals are given to the same structures as those of Embodiment 1, and the description thereof will not be repeated.

[0076] like Fig. 9 As shown, in the semiconductor chip 13 according to the third embodiment, the plurality of pads 3 include a first main pad 4 (first pad), a second main pad 5 (second pad), and a plurality of control pads 8. The second main pad 5 is arranged to be spaced apart from the first main pad 4 in the second direction Y. The first main pad 4 and the second main pad 5 are arranged to be spaced apart from the plurality of control pads 8 in the first direction X. The occupied area of ​​each of the first main pad 4 and the second main pad 5 is larger than the occupied area of ​​each of the plurality of control pads 8.

[0077] In a plan view, the second main pad 5 includes a deformed portion 5A having an outer shape different from that of the first main pad 4. From a different viewpoint, the first main pad 4 includes a deformed portion 4A having an outer shape different from that of the second main pad 5 in a plan view.

[0078] The irregular portion 5A is formed, for example, at a corner of the second main pad 5. The irregular portion 5A is formed, for example, at one corner located on the control pad 8 side among the plurality of corners of the second main pad 5 in a plan view.

[0079] The deformed portion 5A has, for example, a recessed portion whose outer shape is recessed relative to the first main pad 4 .

[0080] The irregular portion 5A is, for example, a portion of the outer edge of the second main pad 5. From a different point of view, when viewed from above, the first main pad 4 and the second main pad 5 each further include congruent portions 4B and 5B that are located at positions corresponding to each other between the first main pad 4 and the second main pad 5 and have congruent shapes.

[0081] The irregular portions 4A and 5A may have the same structure as the irregular portions 6A and 7A of the semiconductor chip 1. The congruent portions 4B and 5B may have the same structure as the congruent portions 6B and 7B of the semiconductor chip 1. In addition, the entire outer edge of the second main pad 5 may be configured as the irregular portion 5A.

[0082] In the semiconductor chip 13, the first main pad 4 and the second main pad 5 are simultaneously recognized by the mounting device and used as alignment marks. Since the first main pad 4 and the second main pad 5 are larger than the first control pad 6 and the second control pad 7, they can be configured as alignment marks showing higher recognition than the first control pad 6 and the second control pad 7.

[0083] The semiconductor chip 13 according to the third embodiment can also be modified in the same manner as the semiconductor chip 1 according to the first embodiment.

[0084] Implementation 4

[0085] Unless otherwise specified, the semiconductor chip and semiconductor device according to Embodiment 4 have the same structure and effects as those of Embodiment 1. Therefore, the same reference numerals are given to the same structures as those of Embodiment 1, and the description thereof will not be repeated.

[0086] like Fig.10 and Fig.11 As shown, the semiconductor chip 14 involved in the fourth embodiment further includes an outer edge portion 9, which is arranged on the first surface 2A of the semiconductor substrate 2 so as to surround the second control pad 7 (second pad). The outer edge portion 9 can be visually recognized together with the second control pad 7 and its irregular portion 7A when viewed from above. The outer edge portion 9 is at least arranged within the field of view FV.

[0087] The material constituting the outer edge portion 9 has a lower reflectivity of visible light than the material constituting the second control pad 7. The material constituting the second control pad 7 is a conductive material, for example, at least one selected from the group consisting of gold (Au), copper (Cu), nickel (Ni) and aluminum (Al). The material constituting the outer edge portion 9 may be any material as long as the reflectivity of visible light is lower than that of the material constituting the second control pad 7, but preferably a material having electrical insulation. The material constituting the outer edge portion 9 is, for example, polyimide or a nitride film. In this case, the outer edge portion 9 may also be, for example, a part of a protective film around each of the plurality of pads 3.

[0088] In addition, the semiconductor chip 14 may further include a protective film arranged so as to surround each of the plurality of pads 3 and the outer edge portion 9 .

[0089] According to the semiconductor chip 14 , since the color difference between the irregular-shaped portion 7A of the second control pad 7 and the outer edge portion 9 is large, the first control pad 6 , the second control pad 7 , and the outer edge portion 9 can function as an alignment mark showing high visibility.

[0090] As described above, the embodiments of the present invention have been described, but various modifications can be made to the above embodiments. In addition, the scope of the present invention is not limited to the above embodiments. The scope of the present invention is indicated by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

[0091] Although the embodiments of the present invention have been described, it should be understood that the embodiments disclosed this time are illustrative in all aspects and are not restrictive. The scope of the present invention is indicated by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor chip comprising: A semiconductor substrate having a first surface, and a semiconductor element is formed on the semiconductor substrate; and a plurality of pads electrically connected to the semiconductor element and arranged on the first surface at intervals from each other, The plurality of pads include a first pad and a second pad, The second pad includes a deformed portion having an outer shape different from that of the first pad in a plan view.

2. The semiconductor chip according to claim 1, wherein: In the plan view, each of the first pad and the second pad further includes a congruent portion located at a position corresponding to each other between the first pad and the second pad and having outer shapes that are congruent to each other.

3. The semiconductor chip according to claim 1, wherein: In the plan view, the first pad and the second pad each have a corner portion, and the corner portion is located at a position corresponding to each other between the first pad and the second pad. The irregular-shaped portion is provided at the corner portion of the second pad.

4. The semiconductor chip according to claim 1, wherein: The irregular-shaped portion of the second pad has a concave portion having a concave shape or a convex portion having a convex shape compared to the first pad.

5. The semiconductor chip according to claim 1, wherein: The first pad and the second pad are adjacent to each other among the plurality of pads.

6. The semiconductor chip according to claim 1, wherein: The plurality of pads further include a third pad, in which a main current of the semiconductor element flows. A signal for controlling the main current is input and output to and from the first pad and the second pad.

7. The semiconductor chip according to claim 1, wherein: A main current of the semiconductor element flows through the first pad and the second pad, The plurality of pads further include a third pad and a fourth pad for inputting and outputting a signal for controlling the main current.

8. The semiconductor chip according to claim 1, wherein: The device further comprises an outer edge portion, which is arranged on the first surface around the second pad and can be visually recognized when viewed from above. The reflectance of visible light of the material constituting the outer edge portion is lower than the reflectance of visible light of the material constituting the second pad.

9. The semiconductor chip according to claim 1, wherein: The semiconductor element includes silicon carbide.

10. A semiconductor device comprising: The semiconductor chip according to any one of claims 1 to 9; A mounting substrate on which the semiconductor chip is mounted; a first connection member electrically connected to the first pad; and A second connecting member is electrically connected to the second pad.

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