Test structure and test method of trench gate transistor

Abstract

The embodiment of the invention relates to a test structure and a test method of a trench gate transistor, and the test structure comprises a semiconductor material layer; a gate trench extending from the upper surface of the semiconductor material layer to the inside of the semiconductor material layer; the gate dielectric layer and the gate are located in the gate groove, the gate dielectric layer covers the side wall and the bottom wall of the gate groove, and the gate is located in the gate dielectric layer; the body region is adjacent to the gate trench outside the gate trench, the extension depth of the gate trench is deeper than the position of the lower interface of the body region, and the body region has the first conduction type; the drift region is in contact with the lower interface of the body region and the part, except the adjacent body region, of the gate trench, and the drift region is of the second conduction type; the first electrode is conductively connected with the grid electrode and the body region and is used for applying low potential; the second electrode is conductively connected with the drift region and is used for applying high potential; therefore, the weak point problem at the bottom of the gate trench can be detected, and the reliability risk is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a test structure and a test method for a trench gate transistor. Background Art

[0002] Compared with planar gate transistors, trench gate transistors can greatly reduce the cell size, thereby greatly improving the current density. For example, compared with planar gate MOSFET, the performance of trench gate metal-oxide-semiconductor field-effect transistor (MOSFET) has been greatly improved. It can not only obtain higher channel mobility, but also reduce the on-resistance, and improve the on-current density and conduction performance of the device.

[0003] However, the gate trench in the trench gate transistor often has a high aspect ratio, which makes it difficult for the reaction gas source to reach the bottom of the gate trench in the process of forming the gate dielectric layer. The gate dielectric layer formed in the end is prone to have weak points at the bottom of the trench; especially when the flow rate of the reaction gas source is abnormal, it is more likely to cause weak points. The existence of weak points in the gate dielectric layer will lead to low withstand voltage (BV), affecting device performance.

[0004] How to monitor the process and provide feedback on whether there are weak points in the gate dielectric layer is crucial for the preparation of trench gate transistors. Summary of the invention

[0005] In view of this, embodiments of the present application provide a test structure and a test method for a trench gate transistor to solve at least one problem existing in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a test structure of a trench gate transistor, including:

[0007] a semiconductor material layer;

[0008] A gate trench extending from the upper surface of the semiconductor material layer to the interior of the semiconductor material layer;

[0009] A gate dielectric layer and a gate located in the gate trench, wherein the gate dielectric layer covers the sidewalls and the bottom wall of the gate trench, and the gate is located in the gate dielectric layer;

[0010] a body region, adjacent to the gate trench outside the gate trench, the extension depth of the gate trench is deeper than the position where the lower interface of the body region is located, and the body region has a first conductivity type;

[0011] a drift region, contacting a lower interface of the body region and a portion of the gate trench other than a portion adjacent to the body region, the drift region having a second conductivity type;

[0012] A first electrode, conductively connected to the gate and the body region, for applying a low potential;

[0013] The second electrode is conductively connected to the drift region and is used for applying a high potential.

[0014] In conjunction with the first aspect of the present application, in an optional implementation manner, the method further includes:

[0015] A first conductive plug connected between the first electrode and the gate;

[0016] A second conductive plug connected between the second electrode and the drift region;

[0017] A field plate structure is located on the semiconductor material layer between the first conductive plug and the second conductive plug.

[0018] In combination with the first aspect of the present application, in an optional embodiment, the body region is formed by doping the semiconductor material layer with a first conductive type, the upper surface side of the semiconductor material layer also includes a first portion that is not doped into the body region, and the drift region extends to the first portion; the second conductive plug is formed by forming an opening on the semiconductor material layer to expose the first portion and filling the opening with a conductive material, and the second conductive plug is conductively connected to the drift region by directly contacting the first portion.

[0019] In combination with the first aspect of the present application, in an optional implementation manner, the gate trench includes a first side and a second side opposite to each other, the body region is adjacent to the first side, and the field plate structure is located on the second side;

[0020] The field plate structure includes a field oxide layer and a field plate layer, wherein the field oxide layer is located on the semiconductor material layer on the second side; a portion of the gate material used to form the gate is filled in the gate trench, and a portion extends onto the field oxide layer to form the field plate layer.

[0021] In combination with the first aspect of the present application, in an optional implementation, the field oxide layer is formed by a LOCOS process.

[0022] In combination with the first aspect of the present application, in an optional embodiment, the gate groove includes a plurality of first gate grooves extending along a first direction and a plurality of second gate grooves extending along a second direction, the first direction intersects with the second direction, and the plurality of first gate grooves and the plurality of second gate grooves are connected by intersection.

[0023] In combination with the first aspect of the present application, in an optional implementation, the first direction intersects the second direction perpendicularly.

[0024] In combination with the first aspect of the present application, in an optional implementation, the test structure of the trench gate transistor is located in a saw street area of ​​a wafer.

[0025] In a second aspect, an embodiment of the present application provides a method for testing a trench gate transistor, the method comprising:

[0026] Providing a test structure of a trench gate transistor as described in any one of the first aspects;

[0027] Applying a low potential to a first electrode of the test structure of the trench gate transistor and a high potential to a second electrode to perform an electrical performance test on the test structure of the trench gate transistor;

[0028] According to the result of the electrical performance test, feedback is provided on the deposition condition of the gate dielectric layer at the bottom wall of the gate trench.

[0029] In conjunction with the second aspect of the present application, in an optional implementation, the testing method is performed during a wafer acceptance test (WAT) stage.

[0030] The test structure and test method of the trench gate transistor provided in the embodiment of the present application can not only realize the withstand voltage test of the gate dielectric layer by optimizing the test structure, but also eliminate the withstand voltage influence of the portion of the gate dielectric layer located between the gate and the body region. The withstand voltage condition of the portion of the gate dielectric layer located below the lower interface of the body region can be tested, which is more conducive to feedback of the weak point problem at the bottom of the gate trench, and further can realize monitoring of whether the flow rate of the reaction gas source introduced in the gate dielectric layer formation process is abnormal, which greatly reduces the reliability risk of the device and avoids the influence of the weak point on the device performance.

[0031] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0033] Figure 1 This is an electron microscope image of the gate trench portion of a trench gate transistor;

[0034] Figure 2 for Figure 1 A local enlarged view of the location of the weak point;

[0035] Figure 3 A cross-sectional view of a test structure of a trench gate transistor provided in an embodiment of the present application;

[0036] Figure 4 A layout of a test structure of a trench gate transistor provided in an embodiment of the present application;

[0037] Figure 5 is a cross-sectional view of a test structure of a trench gate transistor in the related art;

[0038] Figure 6 A flowchart of the steps of a method for testing a trench gate transistor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0039] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0040] In the following description, a large number of specific details are given to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features known in the art are not described; that is, all features of the actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0041] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0042] When an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. Although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below may be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application necessarily has the first element, component, region, layer or part.

[0043] Spatially relative terms such as "under", "below", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. In addition to the orientation shown in the figure, the spatially relative terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0044] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] In order to thoroughly understand the present application, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0046] Figure 1 This is an electron microscope image of the gate trench portion of a trench gate transistor; Figure 2 for Figure 1 A local enlarged view of the location of the weak point in the gate trench. For gate trenches with a high aspect ratio, weak points are prone to appear in the gate dielectric layer at the bottom, resulting in low withstand voltage of the gate dielectric layer, which ultimately affects device performance.

[0047] During and after the semiconductor manufacturing process, various tests are required to verify the performance of the product. WAT (Wafer Acceptance Test) is to measure the electrical parameters of specific test structures after the wafer product is taped out and before quality inspection. The purpose of WAT is to detect the process conditions of each wafer product by testing the electrical parameters of specific test structures on the wafer, evaluate the quality and stability of the semiconductor manufacturing process, and determine whether the wafer product meets the electrical specifications of the process technology platform. CP (Chip Probing) is to use a probe card to contact the chips on the wafer after the semiconductor manufacturing is completed and before the chips are separated and packaged, and perform electrical tests to ensure that they meet the specifications.

[0048] However, all current tests (whether WAT or CP) are unable to provide feedback on the problem of weak points in the gate dielectric layer at the bottom of the gate trench due to insufficient reaction gas source. This is mainly because: the withstand voltage of the gate dielectric layer is generally higher than the bias voltage of the GE leakage test in CP, which makes it impossible to detect the weak points of the gate dielectric layer, and the bias voltage cannot be increased to the limit during the test, otherwise it will cause chip damage; and the opening area of ​​the gate trench of the conventional WAT test structure is small, and the requirements for the content of the reaction gas source are relatively small. Even if the flow rate of the reaction gas source is abnormal, the WAT test structure may not be able to reflect the problem in the chip area, resulting in the bottom weak point of the gate dielectric layer cannot be detected. However, this weak point will lead to the risk of HTGB (High Temperature Gate Bias, high temperature gate bias - accelerated aging physical model for environmental reliability testing of power devices) failure.

[0049] Based on this, the present application embodiment provides a test structure of a trench gate transistor, please refer to Figure 3 and Figure 4The test structure includes: a semiconductor material layer 100; a gate trench 110 extending from an upper surface 1001 of the semiconductor material layer 100 to the interior of the semiconductor material layer 100; a gate dielectric layer 111 and a gate 112 located in the gate trench 110, wherein the gate dielectric layer 111 covers a sidewall 1101 and a bottom wall 1102 of the gate trench 110, and the gate 112 is located in the gate dielectric layer 111; a body region 101 adjacent to the gate trench 110 outside the gate trench 110, and the gate trench 110 is provided with a gate dielectric layer 111; and a gate region 101 extending from an upper surface 1001 of the semiconductor material layer 100 to the interior of the semiconductor material layer 100. The extension depth of 110 is deeper than the position of the lower interface 1012 of the body region 101, and the body region 101 has a first conductivity type; the drift region 102 is in contact with the lower interface 1012 of the body region 101 and the portion of the gate trench 110 other than the adjacent body region 101, and the drift region 102 has a second conductivity type; the first electrode 121 is conductively connected to the gate 112 and the body region 101, and is used to apply a low potential; the second electrode 122 is conductively connected to the drift region 102, and is used to apply a high potential.

[0050] It can be understood that the embodiment of the present application optimizes the test structure so that the gate 112 and the body region 101 are commonly connected to the first electrode 121, that is, the gate 112 and the body region 101 are at the same potential and are specifically connected to a low potential. In addition, the drift region 102 is also conductively led out through the second electrode 122, so that another electrical signal can be applied to the drift region 102, specifically applying a high potential; in this way, not only can the withstand voltage test of the gate dielectric layer 111 be achieved, but also the withstand voltage influence of the portion of the gate dielectric layer 111 located between the gate 112 and the body region 101 is eliminated, and the withstand voltage condition of the portion of the gate dielectric layer 111 located below the lower interface 1012 of the body region 101 can be tested, which is more conducive to feedback of the weak point problem at the bottom of the gate trench 110, and further, it can be realized to monitor whether the flow rate of the reaction gas source introduced in the gate dielectric layer 111 formation process is abnormal, which greatly reduces the reliability risk of the device and avoids the influence of the weak point on the device performance.

[0051] In practical applications, the test structure can also be called a WAT ​​test structure; the test structure and the trench gate transistor chip are located on the same wafer and are formed synchronously under the same preparation conditions. The wafer has a chip area and a dicing area, and the trench gate transistor test structure is located in the dicing area of ​​the wafer.

[0052] The semiconductor material layer 100 includes an upper surface 1001 and a lower surface 1002 opposite to each other; the upper surface 1001 of the semiconductor material layer 100 is an operation surface in the process of forming the gate trench 110. Ignoring the flatness of the upper and lower surfaces of the semiconductor material layer 100, the direction perpendicular to the upper surface 1001 is defined as the thickness direction of the semiconductor material layer 100, or the thickness direction / height direction of the device.

[0053] The semiconductor material layer 100 may be made of silicon, germanium, silicon carbide, etc., which is not specifically limited in the present application. The semiconductor material layer 100 may be a growth substrate, or an epitaxial layer formed on a growth substrate by an epitaxial growth process.

[0054] The semiconductor material layer 100 may be a doped layer, and may specifically have a second conductivity type. The second conductivity type is different from the first conductivity type, and when the first conductivity type is P type, the second conductivity type is N type; correspondingly, when the first conductivity type is N type, the second conductivity type is P type.

[0055] In some embodiments, the second conductivity type is N-type. The semiconductor material layer 100 is an N-type semiconductor material layer, specifically an N-semiconductor material layer.

[0056] The gate trench 110 extends from the upper surface 1001 of the semiconductor material layer 100 to the interior of the semiconductor material layer 100; the gate trench 110 includes a sidewall 1101 and a bottom wall 1102. Exemplarily, the gate trench 110 can be formed by a photolithography process. Specifically, a mask material is first deposited on the semiconductor material layer 100, and then a preset formation position of the gate trench 110 is defined in the mask material by a photolithography process, thereby forming a patterned mask layer. Next, the semiconductor material layer 100 is etched using the patterned mask layer as a mask until the gate trench 110 is formed. This process is well known to those skilled in the art and will not be described in detail here.

[0057] The gate dielectric layer 111 is located in the gate trench 110 and covers the sidewalls 1101 and the bottom wall 1102 of the gate trench 110. In an actual device, the gate dielectric layer 111 may be an oxide layer, and therefore, may also be referred to as a gate oxide layer (GOX); specifically, for example, a silicon dioxide layer. In the actual preparation process, the gate oxide layer may be formed by an oxidation process, or by a deposition process, or by a process of oxidation followed by deposition. In the process of forming the gate oxide layer, oxygen (i.e., the aforementioned reaction gas source) needs to be introduced. On the one hand, for a trench with a high aspect ratio, it is difficult for oxygen to reach the bottom of the trench itself; on the other hand, in a specific process procedure, an abnormal flow rate of oxygen may occur, resulting in insufficient oxygen; and finally, a weak point of the gate oxide layer is formed at the bottom of the deep trench. Therefore, the test structure provided in the embodiment of the present application can monitor whether there is sufficient oxygen during the gate oxide layer process.

[0058] The gate 112 is located in the gate dielectric layer 111, and is insulated and isolated from the semiconductor material layer 100 by the gate dielectric layer 111. Exemplarily, the material of the gate 112 includes polysilicon (poly).

[0059] Please refer to Figure 4 , Figure 4 A layout of a test structure of a trench gate transistor provided in an embodiment of the present application, wherein: Figure 3 It can be understood as along Figure 4 As an optional specific implementation, the gate trench 110 includes a plurality of first gate trenches 1110 extending along a first direction and a plurality of second gate trenches 1120 extending along a second direction, and the first direction intersects with the second direction, so that the plurality of first gate trenches 1110 and the plurality of second gate trenches 1120 are connected by intersecting.

[0060] In this way, by changing the layout of the gate groove 110 in the test structure, the setting of multiple second gate grooves 1120 in the second direction is increased, thereby forming a superimposed structure of multiple first gate grooves 1110 extending along the first direction and multiple second gate grooves 1120 extending along the second direction, thereby increasing the exposure area of ​​the photolithography process, and then increasing the area of ​​the bottom of the gate groove 110 in the test structure. If the flow rate of the reaction gas source is insufficient, the weak point problem in the test structure will be magnified, making it easier to detect.

[0061] It should be understood that both the first direction and the second direction are parallel to the plane where the semiconductor material layer 100 is located.

[0062] Specifically, optionally, the first direction intersects the second direction perpendicularly, thereby reducing the complexity of the layout and making it easier to arrange the conductive plug 130 .

[0063] In practical applications, the spacing between the plurality of first gate trenches 1110 may be equal; the spacing between the plurality of second gate trenches 1120 may be equal; and the spacing between the plurality of first gate trenches 1110 may be equal to the spacing between the plurality of second gate trenches 1120. The line widths of the plurality of first gate trenches 1110 may be equal; the line widths of the plurality of second gate trenches 1120 may be equal; and the line widths of the plurality of first gate trenches 1110 may be equal to the line widths of the plurality of second gate trenches 1120.

[0064] In a specific process, a plurality of first gate trenches 1110 and a plurality of second gate trenches 1120 can be formed simultaneously in the same process; thus, the preparation of a plurality of staggered gate trenches 110 can be achieved by only changing the pattern corresponding to the test structure area on the mask, without adding additional process steps. It should be understood that after forming the gate trenches 110 including the plurality of first gate trenches 1110 and the plurality of second gate trenches 1120, the process of depositing the gate dielectric layer 111 and the gate 112 can continue to use the original process without affecting the preparation of the chip area.

[0065] The body region 101 is adjacent to the gate trench 110 outside the gate trench 110 . The extension depth of the gate trench 110 is deeper than the position where the lower interface 1012 of the body region 101 is located. The body region 101 has a first conductivity type.

[0066] It can be understood that in the corresponding chip, the portion of the body region 101 close to the gate trench 110 is used to form a channel.

[0067] The body region 101 may be formed by doping the semiconductor material layer 100 with the first conductivity type, for example, by ion implantation. In some embodiments, the first conductivity type is P-type; the body region 101 may be a P-type body region, and the body region 101 may also be referred to as a Pbody region.

[0068] The extension depth of the gate trench 110 is deeper than the position of the lower interface 1012 of the body region 101, that is, the distance between the bottom wall 1102 of the gate trench 110 and the upper surface 1001 of the semiconductor material layer 100 is greater than the distance between the lower interface 1012 of the body region 101 and the upper surface 1001 of the semiconductor material layer 100. The bottom wall 1102 of the gate trench 110 is closer to the lower surface 1002 of the semiconductor material layer 100 than the lower interface 1012 of the body region 101.

[0069] The drift region 102 has the second conductivity type. In an actual device, the semiconductor material layer 110 has the second conductivity type, and the remaining portion of the semiconductor material layer 110 that has not been further doped or removed / oxidized forms the drift region 102 of the device.

[0070] Please refer to Figure 3 The upper surface 1001 side of the semiconductor material layer 100 also includes a first portion that is not doped into the body region 101 (as shown in the elliptical dotted box in the figure), and the drift region 102 extends to the first portion; in this way, conditions are provided for the subsequent formation of the second conductive plug 132 and then conductively leading out the drift region 102.

[0071] The first electrode 121 is conductively connected to the gate 112 and the body region 101 for applying a low potential; the second electrode 122 is conductively connected to the drift region 102 for applying a high potential. In specific applications, the first electrode 121 and the second electrode 122 may also be referred to as a low potential electrode pad (Lowpad) and a high potential electrode pad (Highpad), respectively. Figure 3 As shown, the first electrode 121 and the second electrode 122 are insulated and isolated from the semiconductor material layer 100 by an interlayer dielectric layer 150 (ILD layer).

[0072] Please refer to Figure 5 , Figure 51 is a cross-sectional view of a test structure of a trench gate transistor in the related art. In the related art, the gate 112 of the test structure is connected to the second electrode 122 (Highpad), and the body region 101 is connected to the first electrode 121 (Lowpad). Therefore, when a voltage is applied to the first electrode 121 and the second electrode 122, the breakdown range is the entire gate trench 110. Therefore, the withstand voltage detected is the withstand voltage of the entire gate dielectric layer 111, which makes it difficult to monitor the bottom. The test structure provided in the embodiment of the present application changes the conductive connection mode of the electrodes so that the gate 112 and the body region 101 are at the same potential and are connected to the Lowpad together, and the body The drift region 102 below the region 101 is conductively led out and connected to the Highpad, so that the body region 101 forms a PN junction with the drift region 102 and reversely suppresses the body region 101. The body region 101 can withstand the high voltage (e.g., 100V) used in the test, thereby eliminating the influence of the withstand voltage of the portion of the gate dielectric layer 111 located between the gate 112 and the body region 101, and the withstand voltage of the portion of the gate dielectric layer 111 located below the lower interface 1012 of the body region 101 can be tested, which is more conducive to feedback of the weak point problem at the bottom of the gate trench 110. In summary, the test structure provided in the embodiment of the present application can realize the withstand voltage of the gate dielectric layer 111 in the bottom area of ​​the gate trench 110 only, eliminating the interference of the withstand voltage of the gate dielectric layer 111 at other positions of the gate trench 110.

[0073] The test structure of the trench gate transistor further includes: a first conductive plug 131 connected between the first electrode 121 and the gate 112 ; and a second conductive plug 132 connected between the second electrode 122 and the drift region 102 .

[0074] In actual preparation, an opening exposing a predetermined formation area of ​​the conductive plug 130 (including the first conductive plug 131, the second conductive plug 132, the third conductive plug 133, etc.) can be formed on the interlayer dielectric layer 150 by a photolithography-etching process, and then a conductive material is filled in the opening to form the conductive plug 130. The conductive plug can also be referred to as (Contact, CT).

[0075] As for the position of the second conductive plug 132, when the upper surface 1001 side of the semiconductor material layer 100 also includes a first portion that is not doped into the body region 101, the second conductive plug 132 is located directly above the first portion. Specifically, the second conductive plug 132 is formed by forming an opening on the semiconductor material layer 100 to expose the first portion and filling the opening with a conductive material, and the second conductive plug 132 is conductively connected to the drift region 102 by directly contacting the first portion.

[0076] As an optional specific implementation, the test structure of the trench gate transistor also includes: a field plate structure 140, which is located on the semiconductor material layer 100 between the first conductive plug 131 and the second conductive plug 132. In this way, the field plate structure 140 compresses the electric field, adjusts the electric field distribution, improves the withstand voltage, and ensures the detection of the weak point at the bottom of the gate trench 110. Specifically, the portion of the semiconductor material layer 100 located between the first conductive plug 131 and the second conductive plug 132 needs to withstand lateral withstand voltage and longitudinal withstand voltage. Generally speaking, the longitudinal withstand voltage is sufficient, but there may be problems with the lateral withstand voltage, resulting in the breakdown of the PN junction, and ultimately the problem of being unable to measure the weak point at the bottom of the gate trench 110. Adding a field plate structure 140 to the test structure can solve this problem well, and ultimately ensure the detection of the weak point at the bottom of the gate trench 110.

[0077] Please continue to refer to Figure 3 The gate trench 110 includes a first side (shown as 1103 in the figure) and a second side (shown as 1104 in the figure) opposite to each other, the body region 101 is adjacent to the first side, and the field plate structure 140 is located on the second side.

[0078] The field plate structure 140 includes a field oxide layer 141 and a field plate layer 142 . The field oxide layer 141 is located on the semiconductor material layer 100 on the second side. A portion of the gate material used to form the gate 112 is filled in the gate trench 110 , and a portion extends onto the field oxide layer 141 to form the field plate layer 142 .

[0079] It can be understood that the field plate layer 142 is connected to the gate 112 , and both are connected to the first electrode 121 .

[0080] Optionally, the field oxide layer 142 is formed by a LOCOS (Local Oxidation of Silicon) process.

[0081] On this basis, the present application also provides a method for testing a trench gate transistor. Figure 6 , the method comprising:

[0082] Step S601, providing a test structure of a trench gate transistor in any of the aforementioned embodiments of the present application;

[0083] Step S602, applying a low potential to the first electrode of the test structure of the trench gate transistor and a high potential to the second electrode, so as to perform an electrical performance test on the test structure of the trench gate transistor;

[0084] Step S603 , providing feedback on the deposition status of the gate dielectric layer at the bottom wall of the gate trench according to the result of the electrical performance test.

[0085] It can be understood that the test method of the trench gate transistor provided by the embodiment of the present application can not only realize the withstand voltage test of the gate dielectric layer 111, but also eliminate the interference of the withstand voltage of the portion of the gate dielectric layer 111 located between the gate 112 and the body region 101, and can test the withstand voltage of the portion of the gate dielectric layer 111 located below the lower interface 1012 of the body region 101, so as to be more conducive to feedback of the weak point problem at the bottom of the gate trench 110, and further realize monitoring of whether the flow rate of the reaction gas source introduced in the process of forming the gate dielectric layer 111 is abnormal. The field plate structure 140 compresses the electric field, adjusts the electric field distribution, solves the lateral withstand voltage problem, and further ensures the detection of the weak point at the bottom of the gate trench 110. By changing the layout of the gate groove 110 in the test structure, a plurality of second gate grooves 1120 are added in the second direction, thereby forming a superimposed structure of a plurality of first gate grooves 1110 extending along the first direction and a plurality of second gate grooves 1120 extending along the second direction, thereby increasing the exposure area of ​​the photolithography process, and further increasing the area of ​​the bottom of the gate groove 110 in the test structure. If the flow rate of the reaction gas source is insufficient, the weak point problem in the test structure will be magnified, thereby being easier to detect.

[0086] After feasibility evaluation, the inventor adopted the test structure of the trench gate transistor provided in the embodiment of the present application and changed the oxygen flow rate introduced in the gate oxide layer formation process. Finally, the reduction in oxygen flow rate was reflected in both the WAT test data and the CPVramp test data.

[0087] Among them, the Vramp test is the full name of Voltage Ramp Test, which is a test method used to evaluate the performance and reliability of semiconductor devices under voltage change conditions.

[0088] As an optional specific implementation, the test method is performed in the WAT stage. It can be understood that since the embodiment of the present application improves the test structure of the trench gate transistor, it is possible to detect weak point problems in the WAT stage, thereby shortening the cycle time for problem discovery, which is conducive to rapid processing in the process.

[0089] It should be noted that the test method embodiments and the test structure embodiments provided in the present application belong to the same concept; the technical features in the technical solutions recorded in the embodiments can be arbitrarily combined without conflict.

[0090] It should be understood that the above embodiments are exemplary and are not intended to include all possible implementations. Various modifications and changes may also be made on the basis of the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may also be combined arbitrarily to form other embodiments of the present application that may not be clearly described. Therefore, the above embodiments only express several implementations of the present application and do not limit the scope of protection of the patent of this application.

Claims

1. A test structure for a trench gate transistor, characterized in that: include: a semiconductor material layer; A gate trench extending from the upper surface of the semiconductor material layer to the interior of the semiconductor material layer; A gate dielectric layer and a gate located in the gate trench, wherein the gate dielectric layer covers the sidewalls and the bottom wall of the gate trench, and the gate is located in the gate dielectric layer; a body region, adjacent to the gate trench outside the gate trench, the extension depth of the gate trench is deeper than the position where the lower interface of the body region is located, and the body region has a first conductivity type; a drift region, contacting a lower interface of the body region and a portion of the gate trench other than a portion adjacent to the body region, the drift region having a second conductivity type; A first electrode, conductively connected to the gate and the body region, for applying a low potential; The second electrode is conductively connected to the drift region and is used for applying a high potential.

2. The test structure of the trench gate transistor according to claim 1, characterized in that: Also includes: A first conductive plug connected between the first electrode and the gate; a second conductive plug connected between the second electrode and the drift region; A field plate structure is located on the semiconductor material layer between the first conductive plug and the second conductive plug.

3. The test structure of the trench gate transistor according to claim 2, characterized in that: The body region is formed by doping the semiconductor material layer with a first conductivity type, the upper surface side of the semiconductor material layer also includes a first portion that is not doped into the body region, and the drift region extends to the first portion; The second conductive plug is formed by forming an opening on the semiconductor material layer to expose the first portion and filling the opening with a conductive material, and the second conductive plug is conductively connected to the drift region by directly contacting the first portion.

4. The test structure of the trench gate transistor according to claim 2, characterized in that: The gate trench comprises a first side and a second side opposite to each other, the body region is adjacent to the first side, and the field plate structure is located on the second side; The field plate structure comprises a field oxide layer and a field plate layer, wherein the field oxide layer is located on the semiconductor material layer on the second side; A portion of the gate material used to form the gate is filled in the gate trench, and a portion thereof extends onto the field oxide layer to form the field plate layer.

5. The test structure of the trench gate transistor according to claim 4, characterized in that: The field oxide layer is formed by a LOCOS process.

6. The test structure of the trench gate transistor according to claim 1, characterized in that: The gate trenches include a plurality of first gate trenches extending along a first direction and a plurality of second gate trenches extending along a second direction, the first direction intersects with the second direction, and the plurality of first gate trenches and the plurality of second gate trenches are connected by intersecting.

7. The test structure of the trench gate transistor according to claim 6, characterized in that: The first direction intersects the second direction perpendicularly.

8. The test structure of the trench gate transistor according to claim 1, characterized in that: The test structure of the trench gate transistor is located in the saw road area of ​​the wafer.

9. A method for testing a trench gate transistor, characterized in that: The method comprises: Providing a test structure of a trench gate transistor as claimed in any one of claims 1 to 8; Applying a low potential to a first electrode of the test structure of the trench gate transistor and a high potential to a second electrode to perform an electrical performance test on the test structure of the trench gate transistor; According to the result of the electrical performance test, feedback is provided on the deposition condition of the gate dielectric layer at the bottom wall of the gate trench.

10. The method for testing a trench gate transistor according to claim 9, characterized in that: The test method is performed at the wafer acceptance test (WAT) stage.

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