High performance microelectronic assembly including through-silicon via

Abstract

Microelectronic assemblies, related devices and methods are disclosed herein. In some embodiments, a microelectronic component may include: a first layer having a first die in a first insulating material; a second layer on the first layer, the second layer comprising a second die having a first thickness and a third die having a second thickness different from the first thickness, the second die and the third die being in a second insulating material, where the second die and the third die have a first surface and an opposite second surface, and where the first surface and the second surface are opposite to each other. The first surfaces of the second die and the third die have a combined surface area between 3000 square millimeters (mm2) and 9000 mm2; and a redistribution layer (RDL) between the first layer and the second layer, the RDL including a conductive via, where the first die is electrically coupled to the second die and the third die through the conductive via and through an interconnect.

Description

Background Art

[0001] Integrated circuit (IC) devices (eg, dies) are often coupled together in multi-die IC packages to integrate features or functionality and to facilitate connections to other components (eg, a package substrate). BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments can be easily understood by considering the following detailed description in conjunction with the accompanying drawings. To facilitate this description, similar reference numerals represent similar structural elements. The embodiments are shown in the figures of the accompanying drawings by way of example and not by way of limitation.

[0003] Figure 1 is a side cross-sectional view of an exemplary microelectronic assembly according to various embodiments.

[0004] Figures 2A-2F is a top view of an exemplary microelectronic assembly according to various embodiments.

[0005] Figures 3A-3C is a side cross-sectional view of another exemplary microelectronic assembly according to various embodiments.

[0006] Figure 3D yes Figure 3C Schematic cross-sectional view of a portion of an exemplary microelectronic assembly.

[0007] Figures 4A-4I are side cross-sectional views of various stages in an exemplary process for fabricating a microelectronic assembly according to various embodiments.

[0008] Figures 5A-5H are side cross-sectional views of various stages in an exemplary process for fabricating a microelectronic assembly according to various embodiments.

[0009] Figure 6 is a flow chart of an exemplary method of making an exemplary microelectronic assembly according to various embodiments.

[0010] Figure 7 is a flow chart of another exemplary method of making an exemplary microelectronic assembly according to various embodiments.

[0011] Figure 8 is a cross-sectional view of a device package including one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0012] Fig. 9 is a cross-sectional side view of a device assembly including one or more microelectronic assemblies according to any of the embodiments disclosed herein.

[0013] Fig.10is a block diagram of an exemplary computing device including one or more microelectronic assemblies according to any of the embodiments disclosed herein. DETAILED DESCRIPTION

[0014] Overview

[0015] For the purpose of illustrating the IC packaging described herein, it will be important to understand the phenomena that come into play during the assembly and packaging of the IC. The basic information below can be considered as the basis on which the present disclosure can be properly interpreted. Such information is provided for the purpose of explanation only, and accordingly, it should not be interpreted in any way to limit the broad scope of the present disclosure and its potential applications.

[0016] As the demand for high-performance computing (HPC) continues to increase, heterogeneous integration has become an important performance driver. The focus on achieving heterogeneous integration scaling will drive interconnect density along with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been developed to increase the density of planar and three-dimensional (3D) input / output (I / O) lines per unit area to achieve higher data bandwidth requirements and enable more efficient die disaggregation and heterogeneous integration to reduce time to market. Recently, the industry has rapidly moved into 2.5D / 3D advanced packaging technologies, such as die embedding and / or silicon interposers, to achieve significantly higher package I / O counts and densities to meet HPC market segment needs and product performance requirements.

[0017] At the same time, system-level heterogeneous integration has attracted great attention because it has extremely high potential in supercomputing, autonomous driving and machine learning applications. Extremely high performance computing has driven significant packaging innovations and pioneering system-level architectures. Such high-performance computing needs have driven the development of very large form factor packaging and the development of system-level heterogeneous integration of computing tiles, I / O, memory, power delivery and thermal cooling solutions. The microelectronic components disclosed herein can realize structures of very large form factors, which have improved interconnection density, shortened wiring distances and improved signal and power integrity compared to conventional solutions without the need for high-cost manufacturing operations. In addition, the microelectronic structures and components disclosed herein provide new flexibility for electronic device designers and manufacturers, allowing them to achieve their device goals without excessive cost or manufacturing complexity.

[0018] Accordingly, microelectronic assemblies, related devices, and methods are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first layer, the first layer including a first tube core located in a first insulating material; a second layer located on the first layer, the second layer including a second tube core having a first thickness and a third tube core having a second thickness different from the first thickness, wherein the second tube core and the third tube core are located in the second insulating material, wherein the second tube core and the third tube core have a first surface and an opposite second surface, and wherein the first surface of the second tube core and the third tube core has an area of ​​3000 square millimeters (mm 2 ) and 9000mm 2 and a redistribution layer (RDL) between the first layer and the second layer, the RDL comprising a conductive path, wherein the first die is electrically coupled to the second die and the third die through the conductive path and through the interconnect.

[0019] Each of the structures, components, packaging, methods, devices, and systems disclosed herein may have several innovative aspects, no single one of which is solely responsible for all of the desirable properties disclosed herein. The details of one or more implementations of the subject matter described in this specification are set forth in the following description and the accompanying drawings.

[0020] In the following description, terms commonly used by those skilled in the art may be used to describe various aspects of the exemplary embodiments in order to convey the substance of their work to others skilled in the art.

[0021] The terms "circuit" and "circuitry" may refer to one or more passive and / or active electrical and / or electronic components that are arranged to cooperate with each other to provide the intended functionality. These terms refer to analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, microcontroller circuitry, and / or any other type of physical hardware electrical and / or electronic components.

[0022] The term "integrated circuit" refers to an electrical circuit that is integrated into a monolithic semiconductor or similar material.

[0023] In some embodiments, the IC die disclosed herein may include a substantially single-crystal semiconductor such as silicon or germanium as a base material (e.g., substrate, body) on which integrated circuits are fabricated using conventional semiconductor processing methods. The semiconductor base material may include, for example, an N-type or P-type material. The die may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor material) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more of the IC dies may include an alternative material, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium indium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV materials. In yet other embodiments, the base material may include a compound semiconductor, for example, a first sub-lattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In still further embodiments, the base material may include an intrinsic Group IV or Group III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In still further embodiments, the die may include an amorphous material, such as a polymer; for example, the base material may include a silicone-filled epoxy. In other embodiments, the base material may include a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the base material may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N-type or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. Although a few examples of materials for the die are described here, any material or structure that can serve as a substrate (e.g., a base material) on which IC circuits and structures as described herein can be built falls within the spirit and scope of the present disclosure.

[0024] Unless otherwise described, an IC die described herein includes one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a certain function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs that implement memory circuitry (e.g., an IC that implements one or more of a memory device, a memory array, a control logic unit configured to control the memory device and array, etc.). In another such example, the term "compute die" may be used to describe a die that includes one or more ICs that implement logic / compute circuitry (e.g., an IC that implements one or more of IO functions, arithmetic operations, data pipelining operations, etc.).

[0025] In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die.” Note that the terms “chip,” “die,” and “IC die” are used interchangeably herein.

[0026] The term "optical structure" includes various forms of arrangements made in the IC structure as described herein for receiving, transforming and / or transmitting optical signals. It can include optical conductors such as waveguides, electromagnetic radiation sources such as lasers and light emitting diodes (LEDs), and electro-optical devices such as photodetectors.

[0027] In various embodiments, any of the photonic ICs (PICs) described herein may include semiconductor materials, such as N-type or P-type materials. The PICs may include, for example, crystalline base materials formed using bulk silicon (or other bulk semiconductor materials) or SOI structures (or more generally semiconductor-on-insulator structures). In some embodiments, the PICs may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to lithium niobate, indium phosphide, silicon dioxide, germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, gallium aluminum arsenide, aluminum arsenide, aluminum indium arsenide, aluminum indium antimonide, gallium indium arsenide, gallium nitride, gallium indium nitride, aluminum indium nitride, or gallium antimonide, or other combinations of III-N or IV group materials. In some embodiments, the PICs may include amorphous materials, such as polymers. In some embodiments, the PICs may be formed on a printed circuit board (PCB). In some embodiments, the PIC may be an inhomogeneous material that includes a carrier material (e.g., glass or silicon carbide) as a base material and has a thin semiconductor layer above which is an active side including transistors and similar components. Although several examples of materials for PICs are described herein, any material or structure that can serve as a substrate on which a PIC can be built falls within the spirit and scope of the present disclosure.

[0028] The term "insulation" means "electrical insulation" and the term "conduction" means "conductive conduction" unless otherwise specified. With reference to optical signals and / or devices, components and elements that operate on or use optical signals, the term "conduction" may also mean "optical conduction".

[0029] The terms "oxide", "carbide", "nitride" and the like refer to compounds containing oxygen, carbon, nitrogen and the like, respectively.

[0030] The term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide.

[0031] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") refers to a solid material (and / or a liquid material that solidifies after processing as described herein) that is substantially non-conductive. By way of example and not limitation, they may include organic polymers and plastics, and inorganic materials such as ionic crystals, ceramics, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and aluminum oxide, or combinations thereof. They may include dielectric materials, high polarizability materials, and / or piezoelectric materials. They may be transparent or opaque without departing from the scope of the present disclosure. Other examples of insulating materials are underfills and moldings or molding-like materials used in packaging applications, including, for example, materials used in organic interposers, package supports, and other such components.

[0032] In various embodiments, elements associated with an IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, elements associated with an IC may include those elements integrated into the IC in a monolithic form, those elements mounted on the IC, or those elements connected to the IC. The IC described herein may be analog or digital, and may be used in many applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC described herein may be used in a single IC die, or may be used as part of a chipset for performing one or more related functions in a computer.

[0033] In various embodiments of the present disclosure, the transistor described herein may be a field effect transistor (FET), such as a MOSFET. In many embodiments, the FET is a four-terminal device. In a silicon-on-insulator or nanoribbon or gate-all-around (GAA) FET, the FET is a three-terminal device including a source, a drain, and a gate terminal and uses an electric field to control the current flowing through the device. A FET typically includes a channel material, a source region and a drain region provided in and / or on the channel material, and a gate stack, the gate stack including a gate electrode material (alternatively referred to as a "work function" material) provided on a portion of the channel material located between the source region and the drain region ("channel portion"), and optionally also including a gate dielectric material located between the gate electrode material and the channel material.

[0034] In a general sense, an "interconnect" refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, thereby facilitating the communication of electrical signals between them; an optical interconnect provides an optical connection between two optical components, thereby facilitating the communication of optical signals between them. As used herein, both electrical and optical interconnects are included in the term "interconnect". The nature of the interconnect described herein should be understood with reference to the signal medium associated with the interconnect. Thus, when used with reference to an electronic device (e.g., an IC that operates using electrical signals), the term "interconnect" describes any element formed of a conductive material for providing an electrical connection to one or more elements associated with the IC or / and between various such elements. In such a case, the term "interconnect" can refer to both electrical traces (sometimes referred to as "wires", "conductors", "metal wires" or "trench") and electrical vias (sometimes referred to as "vias" or "metal vias"). Sometimes, conductive traces and vias may be referred to as "conductive traces" and "conductive vias", respectively, thereby emphasizing the fact that these elements include conductive materials such as metals. Similarly, when used with reference to a device that also operates on optical signals (e.g., a PIC), "interconnect" may also describe any element formed of light-conducting materials for providing an optical connection to one or more elements associated with the PIC. In such cases, the term "interconnect" may refer to optical waveguides, including optical fibers, optical splitters, optical combiners, optical couplers, and optical vias.

[0035] The term "waveguide" refers to any structure used to guide light to propagate from one location to another, typically through a substrate material such as silicon or glass. In various examples, the waveguide can be formed from silicon, doped silicon, silicon nitride, glass (e.g., silica (e.g., silicon dioxide or SiO2)), borosilicate (e.g., 70-80 wt% SiO2, 7-13 wt% B2O3, 4-8 wt% Na2O or K2O, and 2-8 wt% Al2O3), and the like. The waveguide can be formed using various techniques including, but not limited to, forming the waveguide in situ. For example, in some embodiments, the waveguide can be formed in situ in glass using low temperature glass-to-glass bonding or by laser direct writing. The waveguide formed in situ can have lower loss characteristics.

[0036] The term "conductive trace" may be used to describe conductive elements that are isolated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics provided into the IC die. Within a package substrate and PCB, such insulating materials include organic materials such as Ajinomoto Build-Up Film (ABF), polyimide, or epoxy. Such conductive lines are typically arranged in several levels or layers of a metallization stack.

[0037] The term "conductive via" may be used to describe a conductive element that interconnects two or more conductive lines at different levels of a metallization stack. To this end, the via may be provided substantially perpendicular to the plane of the IC die / chip or to the plane of a support structure on which the IC structure is provided, and the via may interconnect two conductive lines in adjacent levels or two conductive lines in non-adjacent levels.

[0038] The term "package substrate" may be used to describe any substrate material that helps package together any collection of semiconductor dies and / or other electrical components (e.g., passive electrical components). As used herein, a package substrate may be formed of any material, including, but not limited to, insulating materials such as resin-impregnated fiberglass (e.g., PCB or printed wiring board (PWB)), glass, ceramic, silicon, silicon carbide, etc. In addition, as used herein, a package substrate may refer to a substrate including a build-up layer (e.g., ABF layer).

[0039] The term "metallization stack" may be used to refer to a stack of one or more interconnects used to provide connections to different circuit components of an IC die / chip and / or a package substrate.

[0040] As used herein, the term "pitch" of interconnects refers to the center-to-center distance between adjacent interconnects.

[0041] In the context of a stack of mutually coupled dies or in the context of a die coupled to a package substrate, the term "interconnect" may also refer to a die-to-die (DTD) interconnect and a die-to-package substrate (DTPS) interconnect, respectively. A DTD interconnect may also be referred to as a first level interconnect (FLI). A DTPS interconnect may also be referred to as a second level interconnect (SLI). Although not specifically shown in all presented illustrations to avoid cluttering the drawings, when describing a DTD or DTPS interconnect, the surface of the first die may include a first set of conductive contacts, and the surface of the second die or package substrate may include a second set of conductive contacts. Thus, one or more conductive contacts of the first group may be electrically and mechanically coupled to some conductive contacts of the second group via a DTD or DTPS interconnect. In some embodiments, the spacing of the DTD interconnect may be different from the spacing of the DTPS interconnect, although in other embodiments, these spacings may be substantially the same.

[0042] It should be appreciated that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy) may be provided in the IC packages described herein and may not be labeled to avoid cluttering the drawings. In various embodiments, each level of underfill may include the same or different insulating materials. In some embodiments, each level of underfill may include a thermosetting epoxy with silicon oxide particles; in some embodiments, each level of underfill may include any suitable material capable of performing an underfill function (such as supporting the die and reducing thermal stresses acting on the interconnects). In some embodiments, the selection of underfill material may be based on design considerations, such as form factor, size, stress, operating conditions, etc.; in other embodiments, the selection of underfill material may be based on material properties and processing conditions, such as curing temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the selection of underfill material may be based on both design considerations and processing considerations.

[0043] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic, solvent) may be provided in the IC packages described herein and may not be labeled or illustrated to avoid cluttering the drawings. The solder resist may be a liquid or dry film material including a photoimageable polymer. In some embodiments, the solder resist may not be photoimageable.

[0044] The terms "substantially," "close," "approximately," and "approximately" generally mean within + / - 20% of a target value (e.g., within + / - 5% or + / - 10% of a target value), based on the context of the specific values ​​described herein or as known in the art.

[0045] Terms indicating the orientation of various elements, such as "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between elements, are generally meant to be within + / - 5%-20% of the target value, based on the context of the specific values ​​described herein or as known in the art.

[0046] The term "connected" refers to a direct connection between the connected objects (which may be one or more of mechanical, electrical and / or thermal connections) without any intermediate devices, while the term "coupled" refers to a direct connection between the connected objects, or an indirect connection through one or more passive or active intermediate devices.

[0047] The description uses the phrase "in an embodiment," which may refer to one or more of the same embodiment or different embodiments.

[0048] Furthermore, the terms "comprising," "including," "having," and the like used with respect to embodiments of the present disclosure are synonymous.

[0049] The present disclosure may use perspective-based descriptions, such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0050] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layer, or may have one or more intervening layers. Additionally, a layer disposed between two layers may be in direct contact with one or both of the two layers, or may have one or more intervening layers. In contrast, a first layer described as being "above" a second layer refers to the layer that is in direct contact with the second layer. Similarly, unless expressly stated otherwise, a feature disposed between two features may be in direct contact with the adjacent feature, or may have one or more intervening layers.

[0051] As used herein, the term "disposed" refers to placing, positioning, placing, and / or arranging, rather than any particular method of formation.

[0052] When used in reference to a range of measurements, the term "between" includes the end values ​​of the range of measurements.

[0053] For purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0054] Although some elements may be referred to in the singular form herein, such elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0055] Unless otherwise indicated, the use of ordinal adjectives such as "first," "second," and "third" to describe common objects simply indicates that different instances of similar objects are being referenced and does not imply that the objects described must be in a given order temporally, spatially, ordinalally, or in any other manner.

[0056] In the detailed description below, reference is made to the accompanying drawings which form a part thereof, and in the accompanying drawings, embodiments that can be practiced are shown by way of example. It should be understood that other embodiments can be utilized and structural and logical changes can be made without departing from the scope of the present disclosure. Therefore, the detailed description below should not be understood in a limiting sense.

[0057] The drawings are not necessarily drawn to scale.

[0058] In the drawings, the same reference numerals refer to the same or similar elements / materials illustrated, and unless otherwise stated, the explanation of an element / material with a given reference numeral provided in the context of one of the drawings applies to other drawings in which the element / material with the same reference numeral may be illustrated. In addition, reference numerals in singular or plural form may be used in conjunction with a reference numeral to denote a single or multiple instances of the same or similar type, class or kind of element, respectively.

[0059] Additionally, in the accompanying drawings, some schematic illustrations of exemplary structures of various devices and components described herein may be shown with exact right angles and straight lines, but it should be understood that such schematic illustrations may not reflect real-life process limitations that may cause the features to appear less than "ideal" when any of the structures described herein are examined using, for example, images of appropriate characterization tools (such as scanning electron microscope (SEM) images, transmission electron microscope (TEM) images, or non-contact surface profilometers). In such images of real structures, possible processing and / or surface defects may also be visible, such as surface roughness, deviations in curvature or profile, pits or scratches, imperfectly straight edges of materials, tilted vias or other openings, unintended rounding of corners or thickness variations of different material layers, occasional screw dislocations, edge dislocations or combined dislocations within (multiple) crystal regions, and / or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but common in the field of device fabrication and / or packaging.

[0060] Note that in the drawings, various components (e.g., interconnects) are shown as aligned (e.g., at corresponding interfaces) only for ease of illustration; in reality, some or all of them may be misaligned. In addition, there may be other components in the assembly, such as bonding pads, landing pads, metallizations, etc., which are not shown in the drawings to avoid confusion. In addition, the drawings are intended to show the relative arrangement of the components within their assemblies, and in general such assemblies may include other components that are not shown (e.g., various interface layers or various other components related to optical functions, electrical connections, or thermal relief). For example, in some other embodiments, the assemblies shown in the drawings may include more dies along with other electrical components. In addition, although some components of the assemblies are shown as planar rectangles or formed by rectangular entities in the drawings, this is only for ease of illustration, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped, which is determined by the manufacturing processes used to make the various components and is sometimes unavoidable due to these manufacturing processes.

[0061] In the drawings, specific numbers and arrangements of structures and components are presented for purposes of illustration, and any desired number or arrangement of such structures and components may be present in various embodiments.

[0062] Furthermore, unless otherwise stated, the structures shown in the drawings may take any appropriate form or shape depending on material properties, manufacturing processes and operating conditions.

[0063] For convenience, if there is a collection of drawings designated by different letters (e.g. Figures 4A-4I ), then such a set may be referred to herein without a letter (e.g., referred to as "FIG. 4"). Similarly, if there is a set of reference numerals designated with different numbers (e.g., 148-1, 148-2), then such a set may be referred to herein without a number (e.g., referred to as "148").

[0064] Each operation may be described in turn as a plurality of discrete actions or operations in a manner that is most helpful for understanding the subject matter claimed for protection. However, the order of description should not be interpreted as implying that these operations are necessarily sequence-dependent. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed, and / or the described operations may be omitted.

[0065] Exemplary Embodiments

[0066] Figure 11 is a side cross-sectional view of an exemplary microelectronic assembly according to various embodiments. The microelectronic assembly 100 may include a die 114 of multiple layers 104 coupled by an RDL 148. Specifically, the microelectronic assembly 100 may include a first layer die 114-1 of a first layer 104-1 and a conductive pillar 152, as well as a first RDL 148-1 located at a bottom surface and a second RDL 148-2 located at a top surface, and the microelectronic assembly 100 may also include a second layer die 114-2, 114-3 of a second layer 104-2 located on the second RDL 148-2. The first layer die 114-1 may include a double-sided die 114-1A and a single-sided die 114-1B. The double-sided first layer die 114-1A may include a bottom surface and a top surface having a conductive contact portion, and a through-silicon via (TSV) 117. The single-sided first layer die 114-1B may include a top surface having a conductive contact portion. In this context, a double-sided die refers to a die that has connections on both surfaces. The active surface of a double-sided die is the surface that contains one or more active devices and most of the interconnects, which can be oriented in either direction, depending on the design requirements and electrical requirements. The first layer die 114-1 (e.g., the first layer die 114-1A and 114-1B) may include a conductive contact 124 located at the top surface. The first layer die 114-1A may also include a conductive contact 122 located at the bottom surface and TSV 117. The conductive contacts 122, 124 may have a single pitch or may have a mixed pitch. The second layer die 114-2, 114-3 may include a conductive contact 126 located on the bottom surface. The conductive contact 126 may have a single pitch or may have a mixed pitch. In some embodiments, the second layer die 114-2, 114-3 may include a double-sided die to (for example) electrically couple to a third layer die (not shown). The second layer dies 114-2, 114-3 may include dies having a single pitch (e.g., as shown for die 114-3) and / or dies having a mixed pitch (e.g., as shown for die 114-2). In some embodiments, the first layer die 114-1 may include an active / passive bridge die (e.g., with or without a metal-insulator-metal (MIM) capacitor) for enabling communication between the second layer dies 114-2 and 114-3. In some embodiments, the second layer die 114-2 may include a central processing unit (CPU), a graphics processing die (GPU), a system-on-chip die (SOC), an input / output (I / O) die, or other similar die, and the second layer die 114-3 may include a high bandwidth memory (HBM) die. In some embodiments, the first layer die 114-1 may have different thicknesses (e.g., the first layer die 114-1A may have a greater thickness than the first layer die 114-1B, as shown).In some embodiments, the second layer dies 114 - 2 , 114 - 3 may have different thicknesses (eg, the second layer die 114 - 3 may have a greater thickness than the second layer die 114 - 2 , as shown).

[0067] The first RDL 148-1 and the second RDL 148-2 may include a conductive path 196 passing through a dielectric material. The first layer of the tube core 114-1 may be electrically coupled to the second layer of tube cores 114-2, 114-3 through the conductive path 196 passing through the second RDL 148-1 and through the interconnect 120. In this article, the interconnect 120 may also be referred to as a DTD interconnect. The interconnect 120 may have a single pitch or may have a mixed pitch. In some embodiments, the interconnect 120 may have a pitch between 1 micron and 75 microns (e.g., between 1 micron and 10 microns, between 10 microns and 25 microns, or between 25 microns and 75 microns). In some embodiments, the interconnect 120 may include a solder 132 (e.g., a solder bump or solder ball that is subjected to thermal reflow to form the interconnect 120, as shown). In such an embodiment, the microelectronic assembly 100 may also include a bottom fill material 127-1 surrounding the interconnect 120 between the top surface of the first layer of the tube core 114-1 and the second RDL 148-1. The underfill material 127 - 1 may have an inverted trapezoidal shape (eg, a trapezoidal shape having a smaller length (ie, y-scale) adjacent to the top surface of the first tier die 114 - 1 and a larger length away from the top surface of the first tier die 114 - 1 (eg, toward the second RDL 148 - 2 )).

[0068] The first layer of die 114-1A can be electrically coupled to the package substrate 102 by a conductive via 196 passing through the first RDL 148-1 and by an interconnect 130. The second layer of die 114-2 can be electrically coupled to the package substrate 102 by a conductive via passing through the first RDL 148-1 and the second RDL 148-2, a conductive pillar 152 in the first layer, and by an interconnect 130. In this document, the interconnect 130 may also be referred to as a DTPS interconnect. In some embodiments, the interconnect 130 disclosed herein may have a pitch between 50 microns and 350 microns. In some embodiments, the interconnect 130 may include solder 134, and the bottom fill material 127-2 may be located between the bottom surface of the first RDL 148-1 and the top surface of the package substrate 102, surrounding the interconnect 130.

[0069] The bottom fill material 127 may be an insulating material, for example, a suitable epoxy material. In some embodiments, the bottom fill material 127 may include a capillary bottom filler, a non-conductive film (NCF), or a molded bottom filler. In some embodiments, the bottom fill material 127 may include an epoxy flux that assists soldering when forming the interconnects 120, 130, and then polymerizes and encapsulates the interconnects 120, 130. The bottom fill material 127 may be and is selected to have such a coefficient of thermal expansion (CTE) that can relieve or minimize stress between the die 114, the RDL 148, and the package substrate 102 caused by uneven thermal expansion in the microelectronic assembly 100. In some embodiments, the CTE of the bottom fill material 127 may have a value between the CTE of the package substrate 102 (e.g., the CTE of the dielectric material of the package substrate 102) and the CTE of the insulating material of the die 114 and / or the RDL 148.

[0070] Interconnect 120 may have a finer pitch than interconnect 130. In some embodiments, interconnect 120 may include a solder interconnect having a solder having a higher melting point than the solder included in interconnect 130. For example, when interconnect 120 is formed before interconnect 130 is formed, interconnect 120 may use a higher temperature solder (e.g., having a melting point of more than 200 degrees Celsius) while interconnect 130 may use a lower temperature solder (e.g., having a melting point of less than 200 degrees Celsius). In some embodiments, the higher temperature solder may include: tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (e.g., eutectic tin-bismuth) or tin, silver, and bismuth. In some embodiments, the lower temperature solder may include indium, indium and tin, or gallium.

[0071] As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an electrical interface between different components (e.g., portions of a conductive interconnect); a conductive contact may be recessed into a surface of a component, flush with a surface of a component, or extend from a surface of a component (e.g., as shown in FIG. Figure 1 ), and may take any suitable form (e.g., a conductive pad or slot, or a portion of a conductive line or via). For example, any of the conductive contacts disclosed herein may include a bonding pad, a solder bump, a conductive post, or any other suitable conductive contact. Figure 1, the second layer of dies 114-2, 114-3 are depicted as having conductive contacts extending from the surface of the die, and may be referred to herein as "bumped dies" or "micro-bumped dies", and the first layer of dies 114-1 are depicted as having conductive contacts flush with the surface of the die, and may be referred to herein as "bumpless dies". The die 114 may include other conductive pathways (e.g., including lines and vias) and / or other circuitry (not shown) coupled to corresponding conductive contacts on the surface of the die 114.

[0072] The microelectronic assembly 100 may also include a first insulating material 133-1 surrounding the first layer of tube cores 114-1 and the conductive pillars 152, and a second insulating material 133-2 surrounding the second layer of tube cores 114-2, 114-3. In some embodiments, the insulating material 133 may include a molding material, for example, an organic polymer, a resin material, or an epoxy material having inorganic silicon oxide. In some embodiments, the insulating material 133 may include a molding material, a resin material, or an epoxy material, and may also include a thermally conductive material (e.g., metal particles), such as silver and oxygen (e.g., in the form of silver oxide particles) or aluminum and oxygen (e.g., in the form of aluminum oxide particles) or a combination thereof. In some embodiments, the first insulating material 133-1 and the second insulating material 133-2 are the same material. In some embodiments, the first insulating material 133-1 and the second insulating material 133-2 are different materials.

[0073] The RDL 148 may include an insulating material (e.g., a dielectric material formed into multiple layers, as known in the art) and one or more conductive paths 196 (e.g., including conductive vias as shown, or including conductive traces and / or conductive vias) passing through the dielectric material. In some embodiments, the RDL 148 may include multiple layers having a conductive fan-out structure. In some embodiments, the insulating material of the RDL 148 may be composed of a dielectric material, a bismaleimide triazine (BT) resin, a polyimide material, an epoxy material (e.g., a glass reinforced epoxy matrix material, an epoxy build film, etc.), a molding material, an oxide-based material (e.g., silicon dioxide or spin-on oxide), or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). The RDL 148 may have any suitable thickness, for example, in some embodiments, the RDL 148 may have a thickness between 1 micron and 35 microns.

[0074] For example, the conductive pillar 152 can be formed of any suitable conductive material such as copper, silver, nickel, gold, aluminum or other metals or alloys. The conductive pillar 152 can be formed using any suitable process, for example, including a photolithography process or an additive process such as cold spray or three-dimensional printing. In some embodiments, the conductive pillar 152 disclosed herein can have a spacing between 50 microns and 150 microns. As used herein, the spacing is measured from center to center (for example, from the center of the conductive pillar to the center of the adjacent conductive pillar). The conductive pillar 152 can have any suitable size and shape. In some embodiments, the conductive pillar 152 can have a circular, rectangular or other shaped cross-section. The second layer of die 114-2 can be electrically coupled to the conductive path 196 in the RDL 148 and electrically coupled to the conductive pillar 152 in the first layer through a metal-to-metal interconnect 125 (for example, a copper-to-copper interconnect or a plated interconnect).

[0075] The tube core 114 disclosed herein may include an insulating material (e.g., a dielectric material formed into multiple layers, as known in the art) and multiple conductive paths formed through the insulating material. In some embodiments, the insulating material of the tube core 114 may include a dielectric material such as silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or a low-k or ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, an organic polymer dielectric, a photoimageable dielectric, and / or a benzocyclobutene-based polymer). In some embodiments, the insulating material of the tube core 114 may include a semiconductor material such as silicon, germanium, or a III-V group material (e.g., gallium nitride) and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive paths in the tube core 114 may include conductive traces and / or conductive vias, and any conductive contacts in the tube core 114 may be connected in any appropriate manner (e.g., connecting multiple conductive contacts located on the same surface or different surfaces of the tube core 114). Conductive paths in die 114 may be appropriately adjacent to liner materials (such as adhesive liners and / or barrier liners). In some embodiments, die 114 is a wafer. In some embodiments, die 114 is a single crystal silicon, fan-out or fan-in package die, or a die stack (e.g., a stacked wafer, a stacked die, or a stacked multi-layer die). In some embodiments, die 114 may include conductive paths for routing power, ground, and / or signals to / from other die 114 included in microelectronic assembly 100. For example, first layer die 114-1 may include TSVs 117 (e.g., as shown in die 114-1A) or other conductive paths, through which power, ground, and / or signals may be transmitted between package substrate 102 and second layer die 114-2, 114-3. In some embodiments, second layer die 114-2 may be directly coupled to power lines and / or ground lines in package substrate 102 via conductive pillars 152.

[0076] The package substrate 102 may include an insulating material (e.g., a dielectric material formed into multiple layers, as known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias, as shown) for routing power, ground, and signals through the dielectric material. In some embodiments, the insulating material of the package substrate 102 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a BT resin, a polyimide material, a glass-reinforced epoxy matrix material, an organic dielectric with an inorganic filler, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). Specifically, when the package substrate 102 is formed using a standard printed circuit board (PCB) process, the package substrate 102 may include FR-4, and the conductive paths in the package substrate 102 may be formed by patterned copper sheets separated by build-up layers of FR-4. The conductive paths in the package substrate 102 may be appropriately bordered with a liner material (such as an adhesive liner and / or a barrier liner). In some embodiments, the package substrate 102 may be formed using a photolithographically defined via package process. In some embodiments, the package substrate 102 may be manufactured using a standard organic package manufacturing process, and thus the package substrate 102 may take the form of an organic package. In some embodiments, the package substrate 102 may be a set of redistribution layers formed on a panel carrier, formed by laminating or spinning dielectric materials, and by laser drilling and plating to establish conductive vias and conductive lines. In some embodiments, the package substrate 102 may be formed on a removable carrier using any suitable technology (e.g., redistribution layer technology). Any method known in the art for making the package substrate 102 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

[0077] In some embodiments, the package substrate 102 may be a lower density medium, and the die 114 may be a higher density medium or include an area with a higher density medium. As used herein, the terms "lower density" and "higher density" are relative terms indicating that the conductive paths (e.g., including conductive interconnects, conductive lines, and conductive vias) in the lower density medium are larger and / or have a larger spacing than the conductive paths in the higher density medium. In some embodiments, the higher density medium may be manufactured using a modified semi-additive process or a semi-additive build process with advanced lithography (with small vertical interconnect features formed by advanced laser or photolithography processes), while the lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etching chemicals to remove unwanted copper areas and having coarse vertical interconnect features formed by a standard laser process). In other embodiments, the higher density medium may be manufactured using a semiconductor manufacturing process such as a single heavy metal damascene process or a dual metal damascene process. In some embodiments, additional die may be disposed on the top surface of the second layer of die 114-2, 114-3. In some embodiments, additional components may be disposed on the top surface of the second layer dies 114 - 2 , 114 - 3 .Additional passive components such as surface mount resistors, capacitors and / or inductors may be disposed on the top or bottom surface of the package substrate 102 , or embedded in the package substrate 102 .

[0078] Figure 1 The microelectronic assembly 100 may also include a circuit board (not shown). The package substrate 102 may be coupled to the circuit board via an interconnect located at the bottom surface of the package substrate 102. The interconnect may include solder balls for a ball grid array arrangement, pins in a pin grid array arrangement, or connection pads in a connection pad grid array arrangement. For example, the circuit board may be a motherboard and may have other components attached thereto. As is known in the art, the circuit board may include conductive pathways and other conductive contacts for routing power, ground, and signals through the circuit board. In some embodiments, the package substrate 102 may not be coupled to the circuit board, but the package substrate 102 may be coupled to another IC package, an interposer, or any other appropriate component. In some embodiments, the microelectronic assembly 100 may not include the package substrate 102, instead, the dies of each layer may be electrically coupled to the circuit board via the first RDL 148-1.

[0079] although Figure 1 The microelectronic assembly 100 is shown with a particular number and arrangement of dies 114 and RDLs 148 of the layers 104 , but this number and arrangement is merely illustrative and the microelectronic assembly 100 can include any desired number and arrangement of dies 114 and RDLs 148 .

[0080] Figures 2A-2F 1 is a top view of an exemplary microelectronic assembly according to various embodiments. Microelectronic assembly 100 can have any suitable size, any suitable number of layers, any suitable number of dies, and any suitable die arrangement. Package substrate 102 can have an area greater than 2500 square millimeters (mm 2 In some embodiments, the package substrate 102 may have a surface area (eg, xy scale, also referred to as a “form factor”) greater than 3600 mm. 2 (eg, 60 mm by 60 mm). In some embodiments, the package substrate 102 may have a surface area greater than 10,000 mm. 2 (e.g., 100 mm by 100 mm). In some embodiments, the package substrate 102 may have a surface area greater than 14400 mm. 2 The surface area of ​​the second layer dies 114-2, 114-3 is 120 mm by 120 mm. Typically, the reticle size is equal to 26 mm by 33 mm. The equivalent silicon content of the second layer dies 114-2, 114-3 can be calculated with respect to the reticle size. For example, the total surface area of ​​the second layer dies 114-2, 114-3 is divided by 858 mm 2 (e.g., 26 mm by 33 mm) is equal to the equivalent silicon content of the second layer dies 114-2, 114-3 relative to the mask size. In some embodiments, the equivalent silicon content of the second layer dies 114-2, 114-3 may be between 3.5 and 6.5 times the mask size. For example, the equivalent silicon content of the second layer dies 114-2, 114-3 may be between 3003 mm and 33 mm. 2 (e.g. 3.5×26mm×33mm) and 5577mm 2 (e.g., 6.5×26 mm×33 mm). The equivalent silicon content is based on the mask size, so this value can be even larger, for example, between 6.5 times and 10 times, or even greater than 10 times. In some embodiments, the combined surface area of ​​the second layer dies 114-2, 114-3 (e.g., the sum of the xy dimensions of each second layer die 114-2, 114-3) or the combined surface area of ​​the second layer die 114-2 (e.g., the sum of the xy dimensions of each second layer die 114-2, 114-3) Figure 3A ) at 3000mm 2 and 9000mm 2 between. Figure 2AA top view of a microelectronic assembly 100 is shown including a first layer die 114-1A located on and coupled to a package substrate 102 and second layer dies 114-2, 114-3 located on and coupled to the first layer die 114-1A. The first layer die 114-1A and the second layer die 114-2, 114-3 are shown as a repeating unit located on and coupled to the package substrate 102. The second layer die 114-2 can be electrically coupled to the package substrate 102 via a conductive pillar 152 (not shown). Although Figure 2A Only two repeating units are shown in FIG. 1 , but the microelectronic assembly 100 can have any suitable number of repeating units and can be based on the surface area (eg, xy scale) of the package substrate 102 . Figure 2B A top view of a microelectronic assembly 100 including three first-tier dies 114-1 (e.g., two first-tier dies 114-1A including TSVs and a single first-tier die 114-1B without TSVs 117) and four second-tier dies 114-2, 114-3 (e.g., two of each of the second-tier dies 114-2, 114-3) on a package substrate 102 is shown. Figure 2C Shown include Figure 2B A top view of a microelectronic assembly 100 with a repeating unit of a first layer die 114-1 and a second layer die 114-2, 114-3 is shown in FIG. Figure 2C As shown in FIG. 1 , the microelectronic assembly 100 may include twelve (12) first tier dies 114 - 1 , eight (8) second tier dies 114 - 2 , and eight (8) second tier dies 114 - 3 . Figure 2D A top view of a microelectronic assembly 100 is shown including nine (9) first tier dies 114-1, six (6) second tier dies 114-2, and twelve (12) second tier dies 114-3 on a package substrate 102, with two (2) second tier dies 114-3 coupled to the first tier dies 114-1. Figure 2E A top view of a microelectronic assembly 100 is shown including nineteen (19) first layer dies 114-1 (e.g., twelve (12) first layer dies 114-1A and seven (7) first layer dies 114-1B coupled to second layer dies 114-2), six (6) second layer dies 114-2, and twelve (12) second layer dies 114-3 on a package substrate 102, wherein each second layer die 114-3 is coupled to each first layer die 114-1A. Although Figure 2E First tier dies 114 - 1A and 114 - 1B are shown, but first tier dies 114 - 1 may include a different arrangement, and in some embodiments may include only first tier die 114 - 1A. Figure 2FA top view of a microelectronic assembly 100 is shown including twenty (20) first tier dies 114-1A, one (1) second tier die 114-2, and twenty (20) second tier dies 114-3 on a package substrate 102, wherein each second tier die 114-3 is coupled to each first tier die 114-1. Figure 2F Twenty (20) first tier dies 114 - 1 and twenty (20) second tier dies 114 - 3 are shown, but the microelectronic assembly 100 may include fewer, for example, sixteen (16) first tier dies 114 - 1 and sixteen (16) second tier dies 114 - 3 .

[0081] Figure 1 Many elements of the microelectronic assembly 100 are included in other figures; the discussion of these elements will not be repeated when discussing these figures, and any of these elements can take any form disclosed herein. Figure 1 100, several elements are illustrated as being included in the microelectronic assembly 100, but several of these elements may not be present in the microelectronic assembly 100. For example, in various embodiments, the underfill material 127-2 and the package substrate 102 may not be included. In some embodiments, each of the microelectronic assemblies 100 disclosed herein may function as a system-in-package (SiP), including multiple dies 114 having different functions. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP.

[0082] Figure 3A is a side cross-sectional view of another exemplary microelectronic assembly according to various embodiments. Figure 1 1A, except that the first layer 104-1 includes only the first layer die 114-1A having TSVs 117, the second material 104-2 includes only the second layer die 114-2 having the same thickness (e.g., z-height), the second layer die 114-2 has a conductive contact portion located on the bottom surface and flush with the bottom surface, and the microelectronic assembly 100 also includes a thermal interface material (TIM) 183 and a heat sink 181. The heat sink 181 can be used to dissipate heat from the second layer dies 114-2, 114-3 (e.g., so that the heat can be more easily dissipated by a heat sink or other thermal management device). The heat sink 181 can include any suitable thermally conductive material (e.g., metal, suitable ceramic, etc.) and can include any suitable features (e.g., fins). In some embodiments, the heat sink 181 can be an integrated heat sink. In some embodiments, the heat sink 181 can include an extension, or a base along the z-height (as shown) to provide physical contact with the TIM 183.

[0083] Figure 3AThe microelectronic assembly 100 may also include a TIM 183 located between the second layer dies 114-2, 114-3 and the heat sink 181. The TIM 183 may include a thermally conductive material (e.g., metal particles) in a polymer or other binder. The TIM 183 may be a thermal interface material paste or a thermally conductive epoxy (which may be fluid when applied and may harden when cured, as known in the art). The TIM may include a solder TIM. The TIM 183 may provide a path for the heat generated by the second layer dies 114-2, 114-3 to easily flow to the heat sink 181, where the heat may be diffused and / or dissipated.

[0084] Figure 3B is a side cross-sectional view of another exemplary microelectronic assembly according to various embodiments. Figure 3A 114-3, except that the microelectronic assembly 100 also includes a spacer 182 located between the second layer die 114-2 and the TIM 183. The spacer 182 may include any suitable material, for example, a metal such as copper, aluminum, nickel, and a metal alloy. In some embodiments, the spacer 182 may be physically attached to the top surface of the second layer die 114-2 by an adhesive 184 or other similar material. The thickness (e.g., z height) of the spacer 182 and the second layer die 114-2 may be substantially equal to the thickness of the second layer die 114-3. For example, the second layer die 114-2 may include a CPU having a thickness of 370 microns, and the second layer die 114-3 may include an HBM having a thickness of 750 microns, and the spacer 182 may have a thickness of 380 microns.

[0085] Figure 3C is a side cross-sectional view of another exemplary microelectronic assembly according to various embodiments. Figure 3A 1, except that the microelectronic assembly 100 includes a hybrid bonding interconnect 106 to electrically couple the first tier die 114-1 with the second tier dies 114-2, 114-3. Figure 3D1 is a schematic cross-sectional view of the details of a specific one of the interconnects 106 in the microelectronic assembly 100. In some embodiments, the example of the interconnect 106 is a hybrid bond including a metal-metal bond and a dielectric-dielectric bond. In a general sense, the interconnect 106 may include a metal-metal bond between a bonding pad 136 of the layer 106-1 and a bonding pad 137 of the layer 106-2 at an interface 138 between the layer 106-1 and the layer 106-2, and a dielectric-dielectric bond in the layer 106-1 and the layer 106-2. The bonding pad 136 of the layer 106-1 can be bonded with the bonding pad 137 of the layer 106-2. The bonding pads 136, 137 may also be referred to as conductive contacts or metal contacts in this article. The material of the metal-metal bond (e.g., the bonding pads 136, 137) may include copper-copper. The dielectric material 105 in the layer 106-1 and the layer 106-2 may be bonded to each other. The dielectric material 105 may include an inorganic dielectric (e.g., silicon and oxygen in the form of silicon oxide) or an organic dielectric (e.g., polyimide). The bonded metallic material and dielectric material form an interconnect 106 including a hybrid bond that provides electrical and mechanical coupling between layer 106-1 and layer 106-2. In some embodiments, the interconnect 106 may have a pitch between 1 micron and 75 microns.

[0086] Exemplary Methods

[0087] The microelectronic assembly 100 disclosed herein may be manufactured using any suitable technique. For example, Figures 4A-4I According to various embodiments, Figure 1 The following are side cross-sectional views of various stages in an exemplary process of a microelectronic assembly 100. Figures 4A-4I The operations discussed in the present disclosure (and other figures showing the manufacturing process) are shown in a particular order, but these operations can be performed in any suitable order. In addition, additional operations not shown can be performed without departing from the scope of the present disclosure. Moreover, the present disclosure can be modified according to the present disclosure. Figures 4A-4I Various of the operations discussed may be performed to fabricate other of the microelectronic assemblies 100 disclosed herein.

[0088] Figure 4AThe assembly is shown after mounting the second layer dies 114-2, 114-3 onto the first carrier 401-1, with the conductive contacts facing the first carrier 401-1. The second layer dies 114-2, 114-3 may be placed using any suitable method, such as automated pick and place. The carrier 401 may include any suitable material for providing mechanical stability during manufacturing operations, and in some embodiments may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The second layer dies 114-2, 114-3 may be attached to the first carrier 401-1 using any suitable technique, such as a removable adhesive 403.

[0089] Figure 4B The assembly is shown after depositing the second insulating material 133-2 onto and around the second layer of dies 114-2, 114-3 and planarizing the top surface of the second insulating material 133-2. The second insulating material 133-2 can be formed using any suitable process, including a molding process. In some embodiments, the second insulating material 133-2 can be dispensed in liquid form to flow around and conform to various shapes of components and metallizations, and can then be subjected to a process that makes the second insulating material 133-2 solid, such as curing. The second insulating material 133-2 can be removed (e.g., planarized) using any suitable technique, including grinding or chemical mechanical polishing (CMP).

[0090] Figure 4C The second carrier 401-2 is attached to Figure 4B The second carrier 401-2 may include any suitable carrier, as described above with reference to Figure 4A As described, and may be attached using any suitable technique (eg, removable adhesive 403).

[0091] Figure 4D The assembly is shown after removing the first carrier 401-1, turning the assembly upside down, and forming a second RDL 148-2 having a conductive path 196 and a conductive pillar 152 on the top surface of the assembly. The second RDL 148-2 can be manufactured using any suitable technology such as PCB technology or redistribution layer technology. The conductive pillar 152 can be formed using any suitable technology, for example, a photolithography process or an additive process such as cold spraying or 3-dimensional printing.

[0092] Figure 4E The first layer of tube die 114-1 is placed in Figure 4DThe assembly after forming interconnects 120 between the first layer die 114-1 and the second layer dies 114-2, 114-3 on the top surface of the assembly and depositing underfill material 127-1 around the interconnects 120. The first layer die 114-1 may be placed using any suitable method, such as automated pick and place. Figure 4E The components can be subjected to solder reflow process.

[0093] Figure 4F The assembly is shown after depositing the first insulating material 133-1 on and around the first layer die 114-1 and the conductive pillars 152, and planarizing the top surface of the first insulating material 133-1. The first insulating material 133-1 may be formed and planarized using any suitable process, including the process described above with reference to Figure 4B The process described.

[0094] Figure 4G Shown in Figure 4F The component after forming the first RDL 148-1 having the conductive via 196 and the conductive contact 174 on the top surface of the component. The first RDL 148-1 can be manufactured using any suitable technology, as described above with reference to Figure 4D described.

[0095] Figure 4H The assembly is shown after solder 134 is deposited on the conductive contacts 174. In some embodiments, other finishing operations may be performed. An exemplary finishing operation includes depositing a solder resist (not shown).

[0096] Fig. 4I The assembly is shown after the second carrier 401-2 has been removed and the assembly has been turned upside down. If multiple assemblies are manufactured together, the assemblies may be singulated after the second carrier 401-2 has been removed. Fig. 4I The component itself can be a microelectronic component 100, as shown. Fig. 4I The microelectronic assembly 100 is further fabricated to form other microelectronic assemblies 100; for example, solder 134 may be used to interconnect 130. Fig. 4I The microelectronic assembly 100 is coupled to a packaging substrate 102, which is Figure 1 The microelectronic assembly 100 is similar to the microelectronic assembly 100, and the TIM 183 and the heat sink 181 are attached, which is similar to the microelectronic assembly 100 of FIG. Figure 3A Similar to microelectronic components.

[0097] Figures 5A-5H According to various embodiments, Figure 3B 1 is a side cross-sectional view of various stages in an exemplary process of microelectronic assembly 100. Figure 5AThe assembly is shown after mounting the spacer 182 on the carrier 501. The carrier 501 may include any suitable material for providing mechanical stability during manufacturing operations, and in some embodiments, may include a semiconductor wafer (e.g., a silicon wafer) or glass (e.g., a glass panel). The spacer 182 may be attached to the carrier 501 using any suitable technique, such as a removable adhesive 503. In some embodiments, the adhesive 184 may be located on the top surface of the spacer 182 or may be deposited thereon.

[0098] Figure 5B The assembly is shown after mounting the second layer dies 114-2, 114-3 onto the carrier 501, with the conductive contacts facing away from the carrier 501. The second layer die 114-2 may be attached to the adhesive 184 on the top surface of the spacer 182, and the second layer die 114-3 may be attached to the adhesive 503 on the top surface of the carrier 501. The second layer dies 114-2, 114-3 may be placed using any suitable method, such as automated pick and place.

[0099] Figure 5C The assembly is shown after depositing the second insulating material 133-2 on and around the spacer 182 and the second layer of dies 114-2, 114-3, and planarizing the top surface of the second insulating material 133-2. The second insulating material 133-2 can be formed using any suitable process including a molding process. In some embodiments, the second insulating material 133-2 can be dispensed in liquid form, flowing around and conforming to various shapes of components and metallizations, and can then be subjected to a process that solidifies the second insulating material 133-2, such as curing. The second insulating material 133-2 can be removed (e.g., planarized) using any suitable technique, including grinding or CMP.

[0100] Figure 5D Shown in Figure 5C The component after forming the second RDL 148-2 having the conductive path 196 and the conductive pillar 152 on the top surface of the component. The second RDL 148-2 can be manufactured using any suitable technology such as PCB technology or redistribution layer technology. The conductive pillar 152 can be formed using any suitable technology, for example, the technology is a photolithography process or an additive process such as cold spraying or 3-dimensional printing.

[0101] Figure 5E The first layer of tube die 114-1 is shown in Figure 5DThe assembly after forming interconnects 120 between the first layer die 114-1 and the second layer dies 114-2, 114-3 on the top surface of the assembly and depositing underfill material 127-1 around the interconnects 120. The first layer die 114-1 may be placed using any suitable method, such as automated pick and place. Figure 5E The components can be subjected to solder reflow process.

[0102] Fig. 5F The assembly is shown after depositing the first insulating material 133-1 on and around the first layer die 114-1 and the conductive pillars 152, and planarizing the top surface of the first insulating material 133-1. The first insulating material 133-1 may be formed and planarized using any suitable process, including the process described above with reference to Figure 5C The process described.

[0103] Figure 5G Shown in Fig. 5F The component after forming a first RDL 148-1 having a conductive via 196 and a conductive contact 174 on the top surface of the component, performing a finishing operation, and depositing solder 134 on the conductive contact 174. The first RDL 148-1 can be manufactured using any suitable technique, as described above with reference to Figure 5D An exemplary finishing operation includes depositing a solder resist (not shown).

[0104] Figure 5H The assembly is shown after the carrier 501 has been removed and the assembly has been turned upside down. If multiple assemblies are manufactured together, the individual assemblies can be singulated after the carrier 501 has been removed. Figure 5H The component itself can be a microelectronic component 100, as shown. Figure 5H The microelectronic assembly 100 is further fabricated to form other microelectronic assemblies 100; for example, solder 134 may be used to interconnect 130. Figure 5H The microelectronic assembly 100 is coupled to the package substrate 102, and the TIM 183 and the heat sink 181 are attached, which is similar to Figure 3B Similar to microelectronic components.

[0105] Figure 64 is a flow chart of an exemplary method of making an exemplary microelectronic assembly according to various embodiments. At 602, the second layer of tube cores 114-2, 114-3 can be attached to the first carrier (e.g., the first carrier 401-1 in Figure 4), wherein the conductive contacts are facing the first carrier, the second layer of tube cores 114-2, 114-3 can be encapsulated with a second insulating material 133-2, and the top surface of the second insulating material 133-2 can be planarized. At 604, a second carrier opposite to the first carrier (e.g., the second carrier 401-2 in Figure 4) can be attached, the first carrier can be removed, the assembly can be turned upside down, and the second RDL 148-2 and the conductive pillars 152 can be formed on the top surface of the assembly. At 606, the first layer die 114-1 can be electrically coupled to the second layer die 114-2, 114-3 through the interconnect 120, the underfill material 127-1 can be deposited around the interconnect 120, and the first insulating material 133-1 can be deposited and planarized on and around the first layer die 114-1. At 608, a first RDL 148-1 having a conductive via 196 can be formed on the first insulating material 133-1. At 610, finishing operations can be performed, including depositing solder resist and attaching solder 134 to the conductive contacts 174, the second carrier can be removed, and the assembly can be inverted.

[0106] Figure 75 is a flow chart of an exemplary method of making an exemplary microelectronic assembly according to various embodiments. At 702, a spacer 182 can be attached to a carrier (e.g., carrier 501 in FIG. 5). The spacer 182 can include an adhesive 184 located on a top surface, or an adhesive can be deposited on the top surface of the spacer. At 704, a second layer of dies 114-2, 114-3 can be attached to the carrier, wherein the conductive contacts are oriented away from the carrier, the second layer of dies 114-2, 114-3 can be encapsulated with a second insulating material 133-2, and the top surface of the second insulating material 133-2 can be planarized. The second layer of dies 114-2 can be attached to the top surface of the spacer 182, and the second layer of dies 114-3 can be attached to the top surface of the carrier. At 706, a second RDL 148-2 and a conductive pillar 152 can be formed on the top surface of the assembly. At 708, the first layer die 114-1 can be electrically coupled to the second layer die 114-2, 114-3 through the interconnect 120, the underfill material 127-1 can be deposited around the interconnect 120, and the first insulating material 133-1 can be deposited and planarized on and around the first layer die 114-1. At 710, a first RDL 148-1 having a conductive via 196 can be formed on the first insulating material 133-1. At 712, finishing operations can be performed, including depositing solder resist and attaching solder 134 to the conductive contacts 174, the carrier can be removed, and the assembly can be inverted.

[0107] Exemplary Devices and Components

[0108] The packages disclosed herein (e.g., Figure 1 -Any of the embodiments shown in FIG. 3 or any other embodiment described herein) may be included in any suitable electronic component. Figure 8-10 Various examples of packages, components, and devices are shown that may be used in conjunction with or include any of the IC packages disclosed herein.

[0109] Figure 8 is a side cross-sectional view of an exemplary IC package 2200 that may include an IC package according to any of the embodiments disclosed herein. In some embodiments, IC package 2200 may be a SiP.

[0110] As shown in the figure, package substrate 2252 may be formed of an insulator (e.g., ceramic, build film, epoxy film with filler particles therein, etc.) and may have conductive pathways extending through the insulator between first side 2272 and second side 2274, or extending between different locations on first side 2272 and / or between different locations on second side 2274. These conductive pathways may take the form of any of the interconnect structures including wires and / or vias.

[0111] The packaging substrate 2252 may include conductive contacts 2263 coupled to conductive pathways 2262 passing through the packaging substrate 2252, thereby allowing the circuit system within the die 2256 and / or the interposer 2257 to be electrically coupled to individual ones of the conductive contacts 2264 (or to other devices not shown included in the packaging substrate 2252).

[0112] IC package 2200 may include an interposer 2257 coupled to a package substrate 2252 via conductive contacts 2261 of interposer 2257, first level interconnects 2265, and conductive contacts 2263 of package substrate 2252. The first level interconnects 2265 shown in the figure are solder bumps, but any suitable first level interconnects 2265 may be used, such as solder bumps, solder columns, or bond wires.

[0113] The IC package 2200 may include one or more dies 2256 coupled to an interposer 2257 via conductive contacts 2254 of the die 2256, first-level interconnects 2258, and conductive contacts 2260 of the interposer 2257. The conductive contacts 2260 may be coupled to conductive pathways (not shown) that extend through the interposer 2257, thereby allowing the circuitry within the die 2256 to be electrically coupled to individual conductive contacts 2261 in the conductive contacts 2261 (or to other devices not shown included in the interposer 2257). The first-level interconnects 2258 shown in the figure are solder bumps, but any suitable first-level interconnects 2258 may be used, such as solder bumps, solder columns, or bonding wires. As used herein, "conductive contacts" may refer to portions of a conductive material (e.g., metal) that act as an interface between different components; the conductive contacts may be recessed into, flush with, or extend from the surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

[0114] In some embodiments, an underfill material 2266 may be disposed between the package substrate 2252 and the interposer 2257, surrounding the first level interconnect 2265, and a molding 2268 may be disposed surrounding the die 2256 and the interposer 2257, and in contact with the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the molding 2268. An exemplary material that may be used for the underfill material 2266 and the molding 2268, where appropriate, is epoxy. A second level interconnect 2270 may be coupled to the conductive contacts 2264. The second level interconnect 2270 shown in this figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second level interconnect 2270 may be used (e.g., a pin in a pin grid array arrangement or a land in a land grid array arrangement). The second level interconnect 2270 may be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as is known in the art and as described below with reference Fig. 9 described.

[0115] In embodiments where the IC package 2200 includes multiple dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). The dies 2256 may include circuitry that performs any intended function. For example, in addition to one or more of the dies 2256 being a microelectronic assembly 100 as described herein, one or more of the dies 2256 may be a logic die (e.g., a silicon-based die), and one or more of the dies 2256 may be a memory die (e.g., an HBM), and so on. In some embodiments, any of the dies 2256 may be implemented as discussed with reference to any of the preceding figures. In some embodiments, at least some of the dies 2256 may not include an implementation as described herein.

[0116] Although the IC package 2200 shown in the figure is a flip chip package, other packaging architectures can be used. For example, the IC package 2200 can be a BGA package, for example, an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 can be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are shown in the IC package 2200, the IC package 2200 can include any desired number of dies 2256. The IC package 2200 can include additional passive components, such as surface mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, the IC package 2200 can include any other active or passive components known in the prior art.

[0117] In some embodiments, interposer 2257 may not be included in IC package 2200 ; instead, die 2256 may be coupled directly to conductive contacts 2263 at first side 2272 by first level interconnects 2265 .

[0118] Fig. 9 is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes several components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first side 2340 of the circuit board 2302 and an opposite second side 2342 of the circuit board 2302; in general, the components may be disposed on one or both of the sides 2340 and 2342. In particular, any appropriate component of the components of the IC device assembly 2300 may include any of the microelectronic components in one or more microelectronic assemblies 100 according to any of the embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form of a microelectronic assembly as described above with reference to the IC package. Figure 8 The IC package 2200 may be in the form of any of the embodiments discussed.

[0119] In some embodiments, circuit board 2302 may be a PCB that includes multiple metal layers separated from each other by insulator layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between components coupled to circuit board 2302. In other embodiments, circuit board 2302 may be a non-PCB packaging substrate.

[0120] As shown in the figure, in some embodiments, the IC device assembly 2300 can include a package-on-interposer structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling feature 2316. The coupling feature 2316 can electrically and mechanically couple the package-on-interposer structure 2336 to the circuit board 2302 and can include solder balls (as shown), male and female portions of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0121] Package-on-interposer structure 2336 may include IC package 2320 coupled to interposer 2304 via coupling feature 2318. Coupling feature 2318 may take any suitable form, such as the forms discussed above with reference to coupling feature 2316, depending on the intended functionality. In some embodiments, IC package 2320 may be or may include IC package 2200, such as described above with reference to FIG. Figure 8 as described.

[0122] Although a single IC package 2320 is shown in the figure, multiple IC packages can be coupled to interposer 2304; indeed, additional interposers can be coupled to interposer 2304. Interposer 2304 can provide an intermediate package substrate for bridging circuit board 2302 and IC package 2320. In general, interposer 2304 can redistribute connections to a wider spacing or reroute connections to different connections. For example, interposer 2304 can couple IC package 2320 to a BGA of coupling component 2316 for coupling to circuit board 2302.

[0123] In the embodiment shown in the figure, IC package 2320 and circuit board 2302 are attached to opposite sides of interposer 2304. In other embodiments, IC package 2320 and circuit board 2302 can be attached to the same side of interposer 2304. In some embodiments, three or more components can be interconnected through interposer 2304.

[0124] The interposer 2304 may be formed of epoxy, glass fiber reinforced epoxy, ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 2304 may be formed of alternating rigid or flexible materials, which may include the same materials as those used in the semiconductor substrate described above, such as silicon, germanium, and other III-V and IV materials. The interposer 2304 may include metal interconnects 2308 and vias 2310, which include but are not limited to TSVs 2306. The interposer 2304 may also include embedded devices 2314, which include both passive devices and active devices. Such devices may include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the interposer 2304. Package-on-interposer structure 2336 may take the form of any package-on-interposer structure known in the art.

[0125] In some embodiments, IC device assembly 2300 may include an IC package 2324 coupled to first side 2340 of circuit board 2302 via coupling component 2322. Coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0126] In some embodiments, IC device assembly 2300 may include a package-on-package structure 2334 coupled to second side 2342 of circuit board 2302 via coupling component 2328. Package-on-package structure 2334 may include IC package 2326 and IC package 2332 coupled together via coupling component 2330 such that IC package 2326 is disposed between circuit board 2302 and IC package 2332. Coupling components 2328 and 2330 may take the form of any of the embodiments of coupling component 2316 discussed above, and IC package 2326 and / or 2332 may take the form of any of the embodiments of IC package 2320 discussed above. Package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0127] Fig.10 2400 may include one or more components having one or more IC packages according to any of the embodiments disclosed herein. For example, any suitable one of the components of computing device 2400 may include microelectronic assembly 100 according to any of the embodiments disclosed herein. In another example, any one or more of the components of computing device 2400 may include any embodiment of IC package 2200 (e.g., Figure 8 In yet another example, any one or more of the components of the computing device 2400 may include the IC device assembly 2300 (e.g., as shown in Fig. 9 shown in ).

[0128] Several components are shown in the figure as included in computing device 2400, but any one or more of these components may be omitted or duplicated, depending on the application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single system-on-chip (SoC) die.

[0129] In addition, in various embodiments, computing device 2400 may not include one or more of the components shown in the figure, but computing device 2400 may include interface circuitry for coupling to the one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuitry (e.g., connector and driver circuitry) to which display device 2406 may be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuitry (e.g., connector and support circuitry) to which audio input device 2418 or audio output device 2408 may be coupled.

[0130] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to transform the electronic data into other electronic data that can be stored in registers and / or memory. The processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (special processors that execute cryptographic algorithms in hardware), server processors, or any other appropriate processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the memory 2404 may include a memory that shares a die with the processing device 2402. This memory may be used as a cache memory and may include an embedded dynamic random access memory (eDRAM) or a spin transfer torque magnetic random access memory (STT-MRAM).

[0131] In some embodiments, computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communications for transmitting data to and from computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can transmit data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not.

[0132] The communication chip 2412 can implement any of a wide variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards (including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision)), LTE plans together with any revisions, updates and / or adaptations thereof (e.g., Advanced LTE plan, Ultra Mobile Broadband (UMB) plan (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, and WiMAX is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication chip 2412 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 2412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher. In other embodiments, the communication chip 2412 may operate in accordance with other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0133] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 can include multiple communication chips. For example, the first communication chip 2412 can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and the second communication chip 2412 can be dedicated to longer-range wireless communications, such as global positioning systems (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO and others. In some embodiments, the first communication chip 2412 can be dedicated to wireless communications, and the second communication chip 2412 can be dedicated to wired communications.

[0134] Computing device 2400 may include battery / power circuitry 2414. Battery / power circuitry 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of computing device 2400 to an energy source separate from computing device 2400 (e.g., AC line power).

[0135] Computing device 2400 may include display device 2406 (or corresponding interface circuitry, as discussed above). Display device 2406 may include any visual indicator, such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0136] Computing device 2400 may include audio output device 2408 (or corresponding interface circuitry, as discussed above). Audio output device 2408 may include any device that generates an audible indication, such as a speaker, headphones, or earbuds.

[0137] The computing device 2400 may include an audio input device 2418 (or corresponding interface circuitry, as discussed above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0138] Computing device 2400 may include a GPS device 2416 (or corresponding interface circuitry, as discussed above). GPS device 2416 may communicate with a satellite-based system and may receive the location of computing device 2400, as is known in the art.

[0139] Computing device 2400 may include other output devices 2410 (or corresponding interface circuitry, as discussed above). Examples of other output devices 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or additional storage.

[0140] The computing device 2400 may include other input devices 2420 (or corresponding interface circuitry, as discussed above). Examples of other input devices 2420 may include an accelerometer, a gyroscope, a compass, an image acquisition device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0141] The computing device 2400 may have any desired form factor, such as a portable or mobile computing device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a notebook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device that processes data.

[0142] Selected Examples

[0143] The description of the illustrated embodiments of the present disclosure (including what is described in the Abstract) is not intended to be exhaustive or to limit the present disclosure to the exact form disclosed. Although specific embodiments and examples of the present disclosure are described herein for illustrative purposes, various equivalent modifications may exist within the scope of the present disclosure, which will be recognized by those skilled in the art.

[0144] The following paragraphs provide various examples of the embodiments disclosed herein.

[0145] Example 1 is a microelectronic assembly comprising: a first layer, the first layer comprising a first die in a first insulating material; a second layer on the first layer, the second layer comprising a second die having a first thickness and a third die having a second thickness different from the first thickness, wherein the second die and the third die are in a second insulating material, wherein the second die and the third die have a first surface and an opposite second surface, wherein the first surface of the second die and the third die has an area of ​​3000 square millimeters (mm 2 ) and 9000mm 2 and a redistribution layer (RDL) between the first layer and the second layer, the RDL comprising a conductive path passing through the RDL, wherein the first die is electrically coupled to the second die and the third die through the conductive path passing through the RDL and through interconnections.

[0146] Example 2 may include the subject matter of Example 1, and may further specify that the interconnect comprises solder.

[0147] Example 3 may include the subject matter of Example 2, and may further include: an underfill material between the second surface of the first die and the RDL and surrounding the interconnect, wherein the underfill material has an inverted trapezoidal shape.

[0148] Example 4 may include the subject matter of Example 1, and may further specify that the interconnect comprises a metal-to-metal bond and a dielectric-to-dielectric bond.

[0149] Example 5 may include the subject matter of any of Examples 1-4, and may further specify that the pitch of the interconnects is between 1 micron and 75 microns.

[0150] Example 6 may include the subject matter of any of Examples 1-5, and may further specify that some of the first dies further include through silicon vias (TSVs).

[0151] Example 7 may include the subject matter of any of Examples 1-6, and may further specify that the first layer further includes a conductive pillar passing through the first insulating material and electrically coupled to the second die.

[0152] Example 8 may include the subject matter of any of Examples 1-7, and may further specify that the first insulating material or the second insulating material includes conductive particles in a molding material, a resin material, or an epoxy material.

[0153] Example 9 may include the subject matter of Example 8, and may further specify that the conductive particles include silver and oxygen, aluminum and oxygen, or a combination thereof.

[0154] Example 10 may include the subject matter of any of Examples 1-9, and may further specify that the first die includes a bridge die.

[0155] Example 11 may include the subject matter of any of Examples 1-10, and may further specify that the second die includes a central processing unit (CPU), a graphics processing unit (GPU), an input / output (I / O) block, or a system on a chip (SOC) die, and the third die includes a high bandwidth memory (HBM) die.

[0156] Example 12 may include the subject matter of any of Examples 1-11, and may further include: a spacer on the second die in the second layer.

[0157] Example 13 may include the subject matter of Example 12, and may further specify that the material of the spacer includes one or more of: copper, aluminum, nickel, or a metal alloy.

[0158] Example 14 may include the subject matter of any of Examples 1-13, and may further specify that the RDL is a second RDL including a second conductive via, and the microelectronic assembly may further include a first RDL including a first conductive via, wherein the first layer is located on the first RDL.

[0159] Example 15 may include the subject matter of Example 14, and may further include: a packaging substrate electrically coupled to the first RDL.

[0160] Example 16 may include the subject matter of Example 15, and may further specify that: the surface area of ​​the packaging substrate is within 2500 square millimeters (mm 2 ) and 14400mm 2 between.

[0161] Example 17 may include the subject matter of Example 15, and may further specify that the surface area of ​​the packaging substrate is greater than 2500 square millimeters.

[0162] Example 18 may include the subject matter of Example 15, and may further include: a heat sink located on the second layer.

[0163] Example 19 may include the subject matter of Example 18, and may further include: a thermal interface material (TIM) between the heat spreader and the second layer.

[0164] Example 20 is a microelectronic assembly comprising: a first die surrounded by a first insulating material; a redistribution layer (RDL) on the first die, comprising a conductive path through the RDL; and a second die on the RDL surrounded by a second insulating material, the second die having a first surface and an opposite second surface, wherein the first surface of the second die has an area of ​​3000 square millimeters (mm 2 ) and 9000mm 2 and a combined surface area between the first and second dies, and may further specify: the first die is electrically coupled to the second die through an interconnect comprising solder, and wherein the interconnect is surrounded by an underfill material having an inverted trapezoidal shape.

[0165] Example 21 may include the subject matter of Example 20, and may further specify that the pitch of the interconnects is between 25 microns and 75 microns.

[0166] Example 22 includes the subject matter of Example 20 or 21, and may further specify that some of the first dies further include through silicon vias (TSVs).

[0167] Example 23 may include the subject matter of any of Examples 20-22, and may further include: conductive pillars passing through the first insulating material and electrically coupled to ones of the second dies.

[0168] Example 24 may include the subject matter of any of Examples 20-23, and may further specify that the first insulating material or the second insulating material includes conductive particles in a molding material, a resin material, or an epoxy material.

[0169] Example 25 may include the subject matter of Example 24, and may further specify that the conductive particles include silver and oxygen, aluminum and oxygen, or a combination thereof.

[0170] Example 26 includes the subject matter of any of Examples 20-25, and may further specify that the first die comprises a bridge die.

[0171] Example 27 may include the subject matter of any of Examples 20-26, and may further specify that some of the second dies include a central processing unit (CPU), a graphics processing die (GPU), an input / output (I / O) block, or a system on a chip (SOC) die, and some of the second dies include a high bandwidth memory die.

[0172] Example 28 may include the subject matter of any of Examples 20-26, and may further specify that some of the second dies have a first thickness, and some of the second dies have a second thickness greater than the first thickness.

[0173] Example 29 may include the subject matter of Example 28, and may further include: spacers located on some of the second dies having the first thickness and surrounded by the second insulating material.

[0174] Example 30 may include the subject matter of any of Examples 20-29, and may further specify that: the first die includes a third surface and an opposite fourth surface, wherein the RDL is a second RDL located at the fourth surface of the first die including a second conductive path, and the microelectronic assembly may also include: a first RDL located at the third surface of the first die including the first conductive path, and a packaging substrate electrically coupled to the first conductive path in the first RDL, wherein the surface area of ​​the packaging substrate is within 2500 square millimeters (mm 2 ) and 14400mm 2 between.

[0175] Example 31 may include the subject matter of Example 30, and may further include: a heat spreader on the second insulating material surrounding the second die.

[0176] Example 32 may include the subject matter of Example 31, and may further include a thermal interface material (TIM) positioned between the heat sink and the second insulating material.

[0177] Example 33 is a microelectronic assembly comprising: a first redistribution layer (RDL) comprising a first conductive path; a first layer located on the first RDL, the first layer comprising a first die located in a first insulating material; a second RDL located on the first layer, the second RDL comprising a second conductive path; and a second layer located on the second RDL, the second layer comprising a second die having a first thickness and a third die having a second thickness different from the first thickness, wherein the second die and the third die are located in a second insulating material, wherein the second die and the third die have a first surface and an opposite second surface, and the first surfaces of the second die and the third die have an area of ​​3000 square millimeters (mm 2 ) and 9000mm 2 A combined surface area between the first die and the third die, and wherein the first die is electrically coupled to the second die and the third die through a second conductive via passing through the second RDL and through an interconnect.

[0178] Example 34 may include the subject matter of Example 33, and may further specify that the interconnect comprises solder.

[0179] Example 35 may include the subject matter of Example 34, and may further specify that: the first tube core includes a third surface and an opposite fourth surface, and the microelectronic assembly may also include: an underfill material located between the fourth surface of the first tube core and the second RDL and surrounding the interconnect, wherein the underfill material has an inverted trapezoidal shape.

[0180] Example 36 may include the subject matter of Example 33, and may further specify that the interconnect comprises a metal-to-metal bond and a dielectric-to-dielectric bond.

[0181] Example 37 may include the subject matter of any of Examples 33-36, and may further specify that the pitch of the interconnects is between 1 micron and 75 microns.

[0182] Example 38 may include the subject matter of any of Examples 33-37, and may further specify that the first layer further includes a conductive pillar passing through the first insulating material and electrically coupled to the second die through a second conductive via.

[0183] Example 39 may include the subject matter of any of Examples 33-38, and may further specify that the first insulating material or the second insulating material includes conductive particles in a molding material, a resin material, or an epoxy material.

[0184] Example 40 may include the subject matter of Example 39, and may further specify that the conductive particles include silver and oxygen, aluminum and oxygen, or a combination thereof.

[0185] Example 41 may include the subject matter of any of Examples 33-40, and may further specify that the first die includes a bridge die.

[0186] Example 42 may include the subject matter of any of Examples 33-41, and may further specify that the second die includes a central processing unit (CPU), a graphics processing unit (GPU), an input / output (I / O) block, or a system on a chip (SOC) die, and the third die includes a high bandwidth memory (HBM) die.

[0187] Example 43 may include the subject matter of any of Examples 33-42, and may further specify that the equivalent silicon content of the second die and the third die is greater than 3000 square millimeters (mm 2 ).

[0188] Example 44 may include the subject matter of any of Examples 33-42, and may further specify that the equivalent silicon content of the second die and the third die is greater than 5500 square millimeters (mm 2 ).

[0189] Example 45 may include the subject matter of any of Examples 33-44, and may further include: a spacer on the second die in the second layer.

[0190] Example 46 may include the subject matter of any of Examples 33-45, and may further include: a packaging substrate electrically coupled to the first conductive via in the first RDL, wherein the surface area of ​​the packaging substrate is within 2500 square millimeters (mm 2 ) and 14400mm 2 between.

[0191] Example 47 may include the subject matter of Example 46, and may further include a heat sink located on the second layer.

[0192] Example 48 may include the subject matter of Example 47, and may further include a thermal interface material (TIM) positioned between the heat spreader and the second layer.

Claims

1. A microelectronic assembly comprising: a first layer, the first layer comprising a first die in a first insulating material; A second layer located on the first layer, the second layer comprising a second tube core having a first thickness and a third tube core having a second thickness different from the first thickness, wherein the second tube core and the third tube core are located in a second insulating material, wherein the second tube core and the third tube core have a first surface and an opposite second surface, and wherein the first surface of the second tube core and the third tube core has an area of ​​3000 square millimeters (mm 2 ) and 9000mm 2 The combined surface area between A redistribution layer (RDL) is located between the first layer and the second layer, the RDL including a conductive via through the RDL, wherein the first die is electrically coupled to the second die and the third die through the conductive via through the RDL and through interconnects.

2. The microelectronic assembly according to claim 1, wherein: The interconnect comprises solder, and the microelectronic assembly further comprises: An underfill material is located between the second surface of the first die and the RDL and surrounds the interconnect, wherein the underfill material has an inverted trapezoidal shape.

3. The microelectronic assembly according to claim 1, wherein: The interconnects include metal-metal bonding and dielectric-dielectric bonding.

4. The microelectronic assembly according to claim 1, wherein: The interconnects have a pitch between 1 micron and 75 microns.

5. The microelectronic assembly according to any one of claims 1 to 4, wherein: The first layer also includes a conductive pillar that passes through the first insulating material and is electrically coupled to the second die.

6. The microelectronic assembly according to any one of claims 1 to 4, wherein: The first insulating material or the second insulating material includes conductive particles in a molding material, a resin material, or an epoxy material.

7. The microelectronic assembly according to claim 6, wherein: The conductive particles include silver and oxygen, aluminum and oxygen, or a combination thereof.

8. The microelectronic assembly according to any one of claims 1 to 4, wherein: The first die comprises a bridge die, and wherein the second die comprises a central processing unit (CPU), a graphics processing unit (GPU), an input / output (I / O) block, or a system on chip (SOC) die, and the third die comprises a high bandwidth memory (HBM) die.

9. The microelectronic assembly according to any one of claims 1 to 4, further comprising: A spacer is located on the second die in the second layer.

10. The microelectronic assembly of claim 9, wherein: The material of the spacer includes one or more of the following: copper, aluminum, nickel, or a metal alloy.

11. The microelectronic assembly according to any one of claims 1 to 4, wherein: The RDL is a second RDL including a second conductive via, and the microelectronic assembly further includes: a first RDL including a first conductive via, wherein the first layer is located on the first RDL; and A package substrate electrically coupled to the first conductive via in the first RDL.

12. The microelectronic assembly of claim 11, wherein: The surface area of ​​the package substrate is 2500 square millimeters (mm 2 ) and 14400mm 2 between.

13. A microelectronic assembly comprising: a first die surrounded by a first insulating material; a redistribution layer (RDL) on the first die, the redistribution layer (RDL) comprising a conductive via passing through the RDL; as well as A second tube core surrounded by a second insulating material on the RDL, the second tube core having a first surface and an opposite second surface, wherein the first surface of the second tube core has an area of ​​3000 square millimeters (mm 2 ) and 9000mm 2 A combined surface area between the first die and the second die, wherein the first die is electrically coupled to the second die by an interconnect comprising solder, and wherein the interconnect is surrounded by an underfill material having an inverted trapezoidal shape.

14. The microelectronic assembly of claim 13, further comprising: Conductive pillars pass through the first insulating material and are electrically coupled to some of the second dies.

15. The microelectronic assembly of claim 13, wherein: The first die comprises a bridge die, and wherein the second die comprises a central processing unit (CPU), a graphics processing unit (GPU), an input / output (I / O) block, or a system on chip (SOC) die.

16. The microelectronic assembly of claim 13, wherein: Some of the second dies have a first thickness, and some of the second dies have a second thickness greater than the first thickness.

17. The microelectronic assembly of claim 16, further comprising: A spacer is located on the some of the second dies having the first thickness and is surrounded by the second insulating material.

18. The microelectronic assembly of claim 17, wherein: The material of the spacer includes one or more of the following: copper, aluminum, nickel, or a metal alloy.

19. A microelectronic assembly according to any one of claims 13 to 18, wherein: The first die includes a third surface and an opposite fourth surface, wherein the RDL is a second RDL including a second conductive path at the fourth surface of the first die, and the microelectronic assembly further includes: a first RDL including a first conductive via at the third surface of the first die, and A package substrate electrically coupled to the first conductive path in the first RDL, wherein the surface area of ​​the package substrate is within 2500 square millimeters (mm 2 ) and 14400mm 2 between.

20. A microelectronic assembly comprising: a first redistribution layer (RDL), the first redistribution layer (RDL) comprising a first conductive path; a first layer on the first RDL, the first layer comprising a first die in a first insulating material; a second RDL on the first layer, the second RDL comprising a second conductive path; as well as A second layer on the second RDL, the second layer comprising a second die having a first thickness and a third die having a second thickness different from the first thickness, wherein the second die and the third die are located in a second insulating material, wherein the second die and the third die have a first surface and an opposite second surface, and the first surface of the second die and the third die has an area of ​​3000 square millimeters (mm 2 ) and 9000mm 2 and wherein the first die is electrically coupled to the second die and the third die through the second conductive via passing through the second RDL and through interconnects.

21. The microelectronic assembly of claim 20, wherein: The interconnect comprises solder, wherein the first die comprises a third surface and an opposite fourth surface, and the microelectronic assembly further comprises: An underfill material is located between the fourth surface of the first die and the second RDL and surrounds the interconnect, wherein the underfill material has an inverted trapezoidal shape.

22. The microelectronic assembly of claim 20, wherein: The first die includes a bridge die, the second die includes a central processing unit (CPU), a graphics processing die (GPU), an input / output (I / O) block, or a system on chip (SOC) die, and the third die includes a high bandwidth memory (HBM) die.

23. The microelectronic assembly according to any one of claims 20 to 22, further comprising: a conductive pillar passing through the first insulating material in the first layer and electrically coupled to the second die; as well as A package substrate electrically coupled to the first conductive path in the first RDL, wherein the surface area of ​​the package substrate is within 2500 square millimeters (mm 2 ) and 14400mm 2 between.

24. The microelectronic assembly of any one of claims 20 to 22, further comprising: A heat sink is located on the second layer.

25. The microelectronic assembly of claim 24, further comprising: A thermal interface material (TIM) is located between the heat spreader and the second layer.

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