Transmitting device, digital predistorter and predistortion method thereof

Abstract

The invention discloses a transmitting device, a digital predistorter and a predistortion method thereof. The transmitting apparatus includes: a multi-mode digital predistorter circuit configured to precompensate an input baseband signal in one of a plurality of digital predistortion modes according to a selection signal; a power amplifier configured to amplify the pre-compensated baseband signal and output the amplified baseband signal as an output signal of a distributed frequency band; and a digital pre-distortion mode selector circuit configured to determine the one of the plurality of digital pre-distortion modes corresponding to the allocated frequency band using a feedback signal obtained from the output signal, and setting the multi-mode digital predistorter circuit to the determined one of the plurality of digital predistortion modes.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate generally to a communication device, and more particularly to a transmission device that predistorts a signal input to a power amplifier, a digital predistorter, and a training method thereof. Background Art

[0002] The power amplifier within the transmitter can be biased to achieve high efficiency, but at the expense of nonlinear operation with degraded signal quality. To counteract this degradation in signal quality, digital pre-distortion (DPD) techniques can be used to adjust the input signal in a manner complementary to the nonlinear characteristics of the amplifier and achieve a substantially linearized amplification system. However, even with such a pre-distorted input signal, it is difficult to ensure the overall linearity of the amplification system. As a result, performance parameters such as adjacent channel leakage ratio (ACLR) and error vector magnitude (EVM) may be degraded.

[0003] Therefore, there is a need for improved digital pre-distortion techniques to ensure linearity while maintaining the high efficiency characteristics of non-linear power amplifiers (eg, Doherty power amplifiers employed in mobile devices). Summary of the invention

[0004] According to an embodiment, a transmitting device includes: a multi-mode digital predistorter circuit, which is configured to pre-compensate an input baseband signal in one digital predistortion mode among multiple digital predistortion modes according to a selection signal; a power amplifier, which is configured to amplify the pre-compensated baseband signal and output the amplified baseband signal as an output signal of an allocated frequency band; a digital predistortion mode selector circuit, which is configured to: determine the one digital predistortion mode among the multiple digital predistortion modes using a feedback signal obtained from the output signal, the one digital predistortion mode corresponding to the allocated frequency band; and set the multi-mode digital predistorter circuit to the determined one digital predistortion mode among the multiple digital predistortion modes.

[0005] According to an embodiment, a predistortion method of a digital predistorter for compensating for nonlinearity of a power amplifier includes: evaluating the performance of the digital predistorter in each of a plurality of digital predistortion modes; selecting one of the plurality of digital predistortion modes based on the evaluated performance; and setting the digital predistorter to the selected one of the plurality of digital predistortion modes, wherein the digital predistorter includes: a first core processing circuit ("first core") configured to process an input baseband signal in one of a memoryless polynomial mode and a memory polynomial mode in response to a first enable signal; a second core processing circuit ("second core") configured to perform a dynamic deviation reduction mode operation on the input baseband signal in response to a second enable signal; and an adder configured to add a first signal output from the first core and a second signal output from the second core in the dynamic deviation reduction mode to provide a precompensated baseband signal.

[0006] According to an embodiment, a digital predistorter for precompensating nonlinearity in a power amplifier includes: a first core, the first core being configured to process an input baseband signal in one of a memoryless polynomial mode and a memory polynomial mode in response to a first enable signal; a second core, the second core being configured to perform an operation on the input baseband signal in a dynamic deviation reduction mode in response to a second enable signal; an adder, the adder being configured to add a first signal output from the first core and a second signal output from the second core in the dynamic deviation reduction mode to provide a precompensated baseband signal; and a selector, the selector being configured to select one of the first signal and the output of the adder in response to a selection signal,

[0007] The first signal corresponds to Among them, a k,m represents the polynomial coefficients of the diagonal terms, M is the maximum order of the memory length, K is the nonlinear order, and m is the memory depth, and the second term signal corresponds to Among them, b k,l are the polynomial coefficients of the off-diagonal terms, and x*(nl) is the complex conjugate of x(nl). BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0009] Figure 1 is a block diagram illustrating a transmitting device according to an embodiment of the present disclosure.

[0010] Figure 2 It is shown Figure 1 A block diagram of an embodiment of a sending device.

[0011] Figure 3 It is shown Figure 1 or Figure 2 Block diagram of the structure of a multi-mode digital pre-distorter.

[0012] Figure 4 is a diagram briefly illustrating example operating characteristics of a multi-mode digital predistorter of the present disclosure.

[0013] Figure 5 is a table showing the types of processing operations for each DPD operation mode of the multi-mode digital predistorter of the present disclosure.

[0014] Figure 6 is a block diagram illustrating an operation method of a first core and a second core of the present disclosure.

[0015] Figure 7 is a flow chart illustrating a setup process of a multi-mode digital predistorter performed during a training operation of the transmitter of the present disclosure.

[0016] Figure 8 is a flowchart illustrating a setting process of a multi-mode digital predistorter performed during a training operation of a transmitter according to another embodiment of the present disclosure.

[0017] Fig. 9 is a block diagram showing a transmitting device with a multi-mode digital predistorter according to another embodiment of the present disclosure.

[0018] Fig.10 The adjacent channel leakage ratio ACLR performance in the mid-high band MHB of the multi-mode digital predistorter of the present disclosure is shown.

[0019] Fig.11 The adjacent channel leakage ratio (ACLR) performance of the multi-mode digital predistorter of the present disclosure in the ultra-high frequency band (UHB) is shown.

[0020] Fig.12 is a block diagram illustrating a mobile device that transmits transmission signals in multiple frequency bands according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings in order to describe them in sufficient detail so that those skilled in the art can easily realize the technical idea of ​​the present disclosure.

[0022] Figure 1 is a block diagram showing a transmitting device 1000 according to an embodiment of the present disclosure. Figure 1, the transmitting apparatus 1000 may include a power amplifier 1200 and corresponding circuits (e.g., processing circuits) forming a multi-mode digital predistorter (DPD) circuit 1100 and a digital predistorter (DPD) mode selector circuit 1300 ("DPD mode selector 1300"). Here, the multi-mode digital predistorter 1100 operates in one of a plurality of digital predistortion (hereinafter also referred to as DPD) modes according to a transmission band, a bias setting of the power amplifier 1200, and / or various operating environments.

[0023] The multi-mode digital predistorter circuit 1100 (hereinafter interchangeably referred to as "DPD 1100" or "multi-mode digital predistorter 1100") performs a digital predistortion operation to pre-compensate the nonlinearity of the power amplifier 1200. The DPD 1100 performs filtering / dynamic amplitude adjustment on an input baseband signal x(n) (in a discrete time system) as pre-compensation for the nonlinear characteristics of the power amplifier 1200, and provides the input baseband signal x(n) to the power amplifier 1200. The DPD 1100 performs a digital operation to compensate for the nonlinear characteristics of the power amplifier 1200 and the resulting distortion. In general, a digital predistorter can be implemented by modeling an inverse function of an output function of the power amplifier 1200. However, the power amplifier 1200 may only operate effectively in a specific operating environment. Therefore, the DPD 1100 of the present disclosure can perform a digital predistortion (DPD) mode optimized for a transmission band or bias setting of the power amplifier 1200. (Note that the transmission frequency band of the power amplifier 1200 may be a microwave frequency band or a millimeter wave frequency band. The power amplifier 1200 may include an up-converter, a local oscillator, etc. for up-converting the baseband signal u(n) to a microwave or millimeter wave frequency band.)

[0024] The DPD mode driven by the DPD 1100 may be derived through behavioral modeling based on Volterra series. Examples of DPD modes may include a memoryless (ML) polynomial mode, a memory polynomial (MP) mode, and a dynamic deviation reduction (DDR) mode.

[0025] The Memory Polynomial (MP) mode uses a digital predistortion model that takes into account the "off-diagonal" terms of the Volterra series. The MP mode takes into account that the power amplifier may exhibit memory effects, where the current output signal of the amplifier is a function of both the current input signal value and the previous input signal value. The Memoryless (ML) Polynomial mode may only consider the current input signal and use a model that removes memory effects due to previous input signals. The Dynamic Deviation Reduction DDR mode uses a motion model combined with additional terms to compensate for the off-diagonal terms that are not fully considered in the MP model.

[0026] The multi-mode digital predistorter (DPD) 1100 of the present disclosure has a core structure similar to a dynamic deviation reduction (DDR) model. However, the DPD mode selector 1300 can switch the multi-mode digital predistorter 1100 to any DPD mode among the ML polynomial mode, the MP mode and the DDR mode. The multi-mode digital predistorter 1100 may include a first core processing circuit ("first core") responsible for processing the first term of the ML polynomial mode and the MP mode. However, the first term of the Volterra series processed by the first core of the present disclosure is different from the polynomial form of the general MP mode. This will be explained in more detail with reference to the mathematical formula described later. In addition, the multi-mode digital predistorter 1100 may include a second core processing circuit ("second core") that processes the second term corresponding to the non-diagonal term.

[0027] Here, the first core performs operation in the ML polynomial mode or the MP mode according to the selection signal SEL. On the other hand, the second core can be activated or deactivated according to the selection signal SEL. If the multi-mode digital predistorter 1100 operates in a dynamic deviation reduction (DDR) mode, the memory polynomial MP mode of the first core and the second core can be activated. By adding the output signals of the first core and the second core, the DPD 1100 can operate in the dynamic deviation reduction DDR mode.

[0028] On the other hand, when the DPD 1100 operates in the ML polynomial mode, the first core is activated under a specific condition (a condition in which the memory depth is set to "0"), and the second core is deactivated. Then, the predistortion signal u(n) output from the first core can provide a digital predistortion characteristic corresponding to the ML polynomial mode. In addition, if the DPD 1100 is to operate in the MP mode, the MP mode of the first core is activated and the second core is deactivated. Then, the signal output from the first core can provide a digital predistortion characteristic corresponding to the MP mode.

[0029] The power amplifier 1200 may be a high-efficiency Doherty power amplifier applicable to the transmitting device 1000. The Doherty power amplifier may use a bias setting method to improve efficiency. In conventional transmitting devices using a Doherty power amplifier, it is difficult to ensure the linearity of the amplification chain, which may result in degradation of adjacent channel leakage ratio (ACLR) or error vector magnitude (EVM) performance. In contrast, the multi-mode digital predistorter 1100 disclosed in the present invention is a circuit for ensuring the linearity of the amplification chain while maintaining the high efficiency characteristics of the power amplifier 1200. Here, the power amplifier 1200 is not limited to a Doherty power amplifier, and may be any of a variety of power amplifiers that benefit from pre-compensation of nonlinearity or distortion.

[0030] In one embodiment, the DPD mode selector 1300 analyzes the output signal y(n) of the power amplifier 1200 by analyzing the feedback signal FB representing the output signal y(n) obtained from the output signal y(n) through the coupler 1005. In another embodiment, shown by path 1007 (and described below with respect to Fig. 9 Description), the DPD mode selector 1300 analyzes the output signal u(n) of the DPD 1100. The DPD mode selector 1300 can select the operation mode of the multi-mode digital predistorter 1100 using the analysis result. The DPD mode selector 1300 operates according to the bias setting or transmission band of the power amplifier 1200 and / or various operating environments during the training process of the transmitting device 1000 or when the digital predistortion is applied. To this end, the DPD mode selector 1300 receives a feedback signal FB, which can be a signal coupled from the amplifier output signal y(n) of the power amplifier 1200 (e.g., a lower amplitude version of y(n)). The DPD mode selector 1300 can detect the gain, EVM and / or ACLR according to the bias setting or transmission band from the feedback signal FB. And, the DPD mode selector 1300 can determine the DPD operation mode that provides the best performance by referring to the detection result. Once the DPD operation mode is determined, the DPD mode selector 1300 transmits a selection signal SEL for selecting the DPD operation mode to the DPD 1100. The selection signal SEL may include an enable signal for activating or deactivating each operation mode.

[0031] According to the above configuration, the transmitting device 1000 of the present disclosure includes the DPD 1100, which may include a first kernel for memory polynomial MP mode operation and a second kernel that is selectively activated. The second kernel may perform an operation corresponding to the second term to process the non-diagonal terms of the Volterra series. Therefore, the transmitting device 1000 may run various DPD operation modes while minimizing hardware costs.

[0032] Figure 2 is shown as Figure 1 The transmitting device 1000 a of the embodiment of the transmitting device 1000 is a block diagram of the transmitting device 1000 a. The transmitting device 1000 a includes a DPD mode selector 1300 , which may include a performance evaluation circuit 1310 and an algorithm selector 1330 .

[0033] The multi-mode digital predistorter 1100 operates in one of a plurality of DPD operation modes according to a selection signal SEL. For example, the DPD 1100 operates in one of a memoryless ML polynomial mode, a memory polynomial (MP) mode, and a dynamic deviation reduction (DDR) mode. During a training sequence or setup, the DPD 1100 may sequentially change the DPD operation mode. And, the performance in each DPD operation mode may be measured by the DPD mode selector 1300.

[0034] The power amplifier 1200 receives the predistortion signal u(n) output from the DPD 1100, and applies the digital predistortion DPD to the predistortion signal u(n) according to the DPD operation mode selected by the DPD mode selector 1300. The power amplifier 1200 can then amplify the predistortion signal u(n) under a preset bias setting condition and output the amplified signal y(n). When the DPD 1100 is set to a DPD operation mode that can most effectively compensate for the nonlinearity or distortion characteristics of the power amplifier 1200, the linearity or efficiency of the amplification chain of the transmitting device 1000a (the amplification chain from the input of the DPD 1100 to the output of the power amplifier 1200) can be maximized.

[0035] The performance evaluation circuit 1310 receives a feedback signal FB (a coupled portion of the output signal y(n)), which feeds back a representation of the amplifier output signal y(n) of the power amplifier 1200. The performance evaluation circuit 1310 detects the performance of the multi-mode digital predistorter 1100 to select a DPD operation mode with the best performance in the channel environment, transmission band, and / or bias state of the power amplifier 1200. The performance evaluation circuit 1310 can detect at least one of the gain, EVM, and ACLR of the power amplifier 1200 for each bias setting of the power amplifier 1200 and a plurality of DPD operation modes in the transmission band.

[0036] For example, the performance evaluation circuit 1310 sets the DPD operation mode of the multi-mode digital predistorter 1100 to the memoryless (ML) polynomial mode. Subsequently, the performance evaluation circuit 1310 may calculate at least one of the gain, EVM, and ACLR of the power amplifier 1200 in the memoryless (ML) polynomial mode. In addition, even in the memory polynomial (MP) mode and the dynamic deviation reduction (DDR) mode of the multi-mode digital predistorter 1100, the performance evaluation circuit 1310 evaluates at least one of the gain, EVM, and ACLR of the power amplifier 1200. Here, the performance evaluation circuit 1310 may also change the bias setting and / or transmission band of the power amplifier 1200 to calculate the gain, EVM, and ACLR corresponding to different bias settings / transmission bands.

[0037] The algorithm selector 1330 refers to the performance of each DPD operation mode provided by the performance evaluation circuit 1310 to select the best DPD operation mode in the current transmission environment. For example, the algorithm selector 1330 uses at least one of the gain, EVM and ACLR of the power amplifier 1200 for each DPD operation mode to select the DPD operation mode. Here, the algorithm selector 1330 can determine the DPD operation mode that provides the best performance among the memoryless (ML) polynomial mode, the memory polynomial (MP) mode and the dynamic deviation reduction (DDR) mode. Then, the DPD operation mode of the DPD 1100 is set to operate in the determined DPD operation mode. The algorithm selector 1330 can output a selection signal SEL to activate the DPD operation mode of the DPD 1100 in the selected mode. The selection signal SEL may include a plurality of enable signals to set the DPD 1100 to one of the DPD operation modes.

[0038] Above, the configuration and operation of the DPD mode selector 1300 are briefly described. Although it has been described that the performance of the DPD mode selector 1300 is evaluated using the output signal of the power amplifier 1200 as the feedback signal FB, the inventive concept is not limited thereto. The signal for performance evaluation may be the predistortion signal u(n) output from the multi-mode digital predistorter 1100, as shown below. Fig. 9 The embodiments described herein.

[0039] Figure 3 It is shown Figure 1 or Figure 2 A block diagram of an example structure of a multi-mode digital predistorter. Figure 3 , the multi-mode digital predistorter (DPD) 1100 may include a first core processing circuit ("first core") 1110, a second core processing circuit ("second core") 1130, an adder 1150, and a selector 1170. Here, the enable signal (MP_En, DDR_En) and the output selection signal (O_SEL) are Figure 1 or Figure 2 An example of the selection signal SEL in .

[0040] The first core 1110 performs a DPD operation on the baseband signal x(n) in a memory polynomial (MP) mode or a memoryless (ML) polynomial mode in response to an input memory polynomial mode enable signal MP_En. For example, when the memory polynomial mode enable signal MP_En is deactivated from the DPD mode selector 1300, the first core 1110 processes the baseband signal x(n) in the ML polynomial mode. On the other hand, when the memory polynomial mode enable signal MP_En from the DPD mode selector 1300 is activated, the first core 1110 processes the baseband signal x(n) in the MP mode. The baseband signal x(n) processed in the memoryless ML polynomial mode or the memory polynomial MP mode can be provided as a first DPD output ML / MP_DPD_Out.

[0041] The digital pre-distortion DPD formula structure of variably running the ML polynomial mode and the MP mode in the first core 1110 according to the memory polynomial mode enable signal MP_En can be expressed as Formula 1 (the ML polynomial case is described below in conjunction with Formula 2).

[0042] [Formula 1]

[0043]

[0044] Here, a k,m represents the polynomial coefficients, m represents the memory depth or length, M represents the maximum order of the memory length, and K represents the nonlinear order of the truncated Volterra series.

[0045] When the memory polynomial mode enable signal MP_En is activated, the first core 1110 may perform a digital predistortion operation in a memory polynomial (MP) mode of Formula 1. On the other hand, if the memory polynomial mode enable signal MP_En is deactivated, the first core 1110 may perform a digital predistortion operation in a memoryless (ML) polynomial mode without considering a previous input in Formula 1. In Formula 1, the digital predistortion operation in the ML polynomial mode may be expressed as in the following Formula 2, where a memory depth "m" is set to "0" to remove the influence of a previous input.

[0046] [Formula 2]

[0047]

[0048] Here, a k,0 Denotes the polynomial coefficients in the ML polynomial mode. In the polynomial of equation 2, the previous input signal is excluded, and only the current baseband signal x(n) is considered.

[0049] In addition, when the multi-mode digital predistorter 1100 processes the baseband signal x(n) in the dynamic deviation reduction (DDR) mode, the first core 1110 can provide the operation result of Formula 1 as the first term of the DDR operation. That is, the first core 1110 processes the first term of the DDR operation in the DDR mode. In the DDR mode, the second term of the DDR operation can be processed in the second core 1130.

[0050] The second core 1130 processes the second term of the DDR operation for the input baseband signal x(n) in the DDR mode. For example, when the DDR mode enable signal DDR_En is activated by the DPD mode selector 1300, the second core 1130 processes the second term of the DDR operation for the input baseband signal x(n). At this time, in order to process the first term of the DDR operation, the DPD mode selector 1300 may also activate the memory polynomial mode enable signal MP_En provided to the first core 1110.

[0051] The second term of the DDR operation on the baseband signal x(n) processed by the second core 1130 can be expressed as the following Equation 3.

[0052] [Formula 3]

[0053]

[0054] Here, b k,l represents the polynomial coefficients of the off-diagonal terms, and x*(nl) represents the complex conjugate of x(nl).

[0055] In order to perform the DDR mode, the DPD mode selector 1300 may activate the memory polynomial mode enable signal MP_En and the DDR mode enable signal DDR_En. Then, the first core 1110 performs the digital predistortion operation in the MP mode of Formula 1. And, the second core 1130 will generate the second term of the DDR operation. Therefore, the digital predistortion function in the DDR mode output by the adder 1150 can be expressed as the following Formula 4.

[0056] [Formula 4]

[0057]

[0058] Note that the absolute value term of the first term |x(nm)| in Equation 4 has a slight difference from the general DDR equation, but has minimal impact on performance.

[0059] The selector 1170 outputs one of the first DPD output MP_DPD_Out and the second DPD output DDR_DPD_Out from the first core 1110 according to the output selection signal O_SEL, and the second DPD output DDR_DPD_Out is the sum of the output of the first core 1110 and the output of the second core 1130. For example, the selector 1170 selects the first DPD output ML / MP_DPD_Out processed by the first core 1110 as the DPD output signal u(n) in the ML polynomial mode or the MP mode. On the other hand, in the DDR mode, the selector 1170 selects the second DPD output DDR_DPD_Out, which is the sum of the output of the first core 1110 and the output of the second core 1130, as the DPD output signal u(n). The output selection signal O_SEL is included as a part of the selection signal SEL provided by the above-mentioned DPD mode selector 1300.

[0060] In the ML polynomial mode or the MP mode, the second core 1130 is disabled. Therefore, the DPD mode selector 1300 will deactivate the DDR mode enable signal DDR_En in the ML polynomial mode or the MP mode. Then, the second core 1130 is deactivated and will not perform any processing on the input baseband signal x(n). Therefore, power consumption can be minimized by activating only the minimum hardware configuration required according to the DPD operation mode.

[0061] The above describes a brief structure of the multi-mode digital predistorter 1100. The multi-mode digital predistorter 1100 can use the first core 1110 to perform digital predistortion processing in the ML polynomial mode or the MP mode. In addition, the multi-mode digital predistorter 1100 enables the first core 1110 to process the first item of the DDR operation in the DDR mode, and enables the second core 1130 to process the second item of the DDR operation. Finally, the multi-mode digital predistorter 1100 applies any one of the DPD operation modes in the ML polynomial mode, the MP mode, and the DDR mode in various transmission environments.

[0062] Figure 4 FIG. 1 is a diagram briefly illustrating an example operating characteristic of a multi-mode digital predistorter of the present disclosure. Figure 4 , the input signal components of Equation 4 showing the operating characteristics of the multi-mode digital predistorter 1100 are arranged in a matrix form.

[0063] The first column is an arrangement of the current input baseband signal x(n) and the harmonics or modulation distortion signal components of x(n). For example, the first column corresponds to the input in the memoryless (ML) polynomial mode, where no delay is applied to the input baseband signal x(n). If the multi-mode digital predistorter (1100, see Figure 3) operates in ML polynomial mode, then the first kernel (1110, see Figure 3 ) uses the first column {x(n), │x(n)│, │x(n)│ 2 …} to perform the predistortion operation of Formula 2.

[0064] The second column is arranged with x(n-1) delayed by the memory depth "1" of the current input baseband signal x(n) and the harmonic or modulation distortion signal component of the input baseband signal x(n-1). And, in the third column, the input baseband signal x(n-2) delayed by the memory depth "2" of the current input baseband signal x(n) and the harmonic or modulation distortion signal component of x(n-2) are arranged. The fourth column contains the input baseband signal x(n-3) delayed by the memory depth "3" of the current input baseband signal x(n) and the harmonic or modulation distortion signal component of x(n-3). When the multi-mode digital predistorter 1100 is set to the memory polynomial (MP) mode, the first kernel 1110 can use all input signal sets of each column to perform the predistortion operation of Formula 1.

[0065] In addition, the off-diagonal terms define the correlation between input signals of different memory depths. For example, Figure 4 As shown, the memoryless polynomial term used in Equation 3 │x(n)│ 2 The input baseband signal x(n-1) delayed by the memory depth "1" is a non-diagonal term for the second term of the DDR operation (the conjugate x*(n-1) of x(n-1) is used in equations 3 and 4). In DDR mode, the first core 1110 is used to process the first term of the DDR operation, and the second core 1130 is used to process the second term of the DDR operation.

[0066] As a result, the multi-mode digital predistorter 1100 can apply any one of the ML polynomial mode, the MP mode, or the DDR mode in various transmission environments. In a specific environment, there may be no difference in performance between the DDR mode that consumes relatively high power and the MP mode or the ML polynomial mode. In this case, low power performance can be improved in a mobile environment by activating the MP mode or the ML polynomial mode instead of the DDR mode.

[0067] Figure 5 TABLE 1 is a table showing the types of processing operations for each DPD operation mode of the multi-mode digital predistorter of the present disclosure. Figure 5 , Multimode Digital Predistorter (1100, see Figure 3 ) performs digital pre-distortion operations in memoryless (ML) polynomial mode, memory polynomial (MP) mode, and dynamic deviation reduction (DDR) mode.

[0068] The multi-mode digital predistorter 1100 can implement various DPD operation modes using the first core 1110, the second core 1130, the adder 1150, and the selector 1170. To provide these various DPD operation modes, the first core 1110, the second core 1130, and the adder 1150 operate individually or jointly. Figure 5 The first and second terms of the formula in (a) of FIG. 1 are shown in FIG. 1 . The portion indicated as “variable” in the first term corresponds to a portion that is different from the general dynamic deviation reduction (DDR) DPD calculation formula. However, even if the pre-distortion is calculated according to the DPD operation mode of the present disclosure, the performance difference from the general DDR DPD formula is slight.

[0069] The formula in (b) shows the operation characteristics of the first core 1110 when the memory polynomial mode enable signal MP_En and the DDR mode enable signal DDR_En are deactivated. In other words, it shows the operation when the first core 1110 operates in the ML polynomial mode. When the DDR mode enable signal DDR_En is deactivated, the second core 1130 is deactivated. And, in order to perform the ML polynomial mode, the first core 1110 applies the memory depth m to "0", and can perform the operation of the ML polynomial mode in the form shown.

[0070] The formula in (c) shows the operation calculated by the first core 1110 in the MP mode. That is, it shows the operating characteristics of the first core 1110 when the memory polynomial mode enable signal MP_En is activated and the DDR mode enable signal DDR_En is deactivated. When the DDR mode enable signal DDR_En is deactivated, the second core 1130 is deactivated. And, in order to operate the memory polynomial MP mode, the first core 1110 will calculate the Volterra series corresponding to the first term. The DPD value output from the first core 1110 will be provided to the selector 1170 without passing through the adder 1150 (see Figure 3 ).

[0071] The equation in (d) shows the operation in the dynamic deviation reduction (DDR) mode. When the memory polynomial mode enable signal MP_En and the DDR mode enable signal DDR_En are activated, each of the first core 1110 and the second core 1130 runs the DDR mode operation. When the memory polynomial mode enable signal MP_En is activated, the first core 1110 will calculate the Volterra series corresponding to the first term. And, when the DDR mode enable signal DDR_En is activated, the second core 1130 processes the second term of the DDR operation for the input baseband signal x(n). And, the outputs of the first core 1110 and the second core 1130 can be summed and output in the adder 1150.

[0072] Figure 6 is a block diagram showing the operation method of the first core and the second core of the present disclosure. Figure 6 , the first core 1110 performs a memory polynomial DPD operation or a memoryless DPD operation on the input baseband signal x(n). And, the second core 1130 performs the second term of the DDR operation.

[0073] When the MP mode enable signal MP_En provided from the DPD mode selector 1300 is deactivated, the first core 1110 processes the input baseband signal x(n) in the ML polynomial mode. When the DDR mode enable signal DDR_En is deactivated, the second core 1130 is deactivated. And, when the first core 1110 sets the memory depth m to "0" to operate the memoryless ML polynomial mode, the memory polynomial MP mode is simplified to the operation 1115 of the memoryless ML polynomial mode in the form shown. The DPD value of the memoryless ML polynomial mode output from the first core 1110 will be output as the result value ML_DPD_Out without passing through the adder 1150.

[0074] When the MP mode enable signal MP_En is activated, the first kernel 1110 calculates the Volterra series corresponding to the first term expressed in Equation 1. The DPD value of the memory polynomial mode output from the first kernel 1110 is output as the result value MP_DPD_Out without passing through the adder 1150 .

[0075] When the MP mode enable signal MP_En and the DDR mode enable signal DDR_En are activated, the first core 1110 and the second core 1130 perform corresponding operations. When the MP mode enable signal MP_En is activated, the first core 1110 will calculate the Volterra series corresponding to the first term. And, when the DDR mode enable signal DDR_En is activated, the second core 1130 processes the second term of the dynamic deviation reduction (DDR) operation for the input baseband signal "x(n)". And, the outputs of the first core 1110 and the second core 1130 will be summed in the adder 1150 to output the result value DDR_DPD_Out in the dynamic deviation reduction (DDR) mode.

[0076] Figure 7 is a flow chart showing a setting process of a multi-mode digital predistorter performed during a training operation of a transmitting device of the present disclosure. Figure 7, a DPD mode with the best performance can be selected from a plurality of DPD modes according to the transmission band of the transmitting device 1000. Here, the training process performed by the multi-mode digital predistorter 1100 when the transmitting device 1000 is started will be described as an example. However, it should be understood that the resetting or training of the multi-mode digital predistorter 1100 can be performed under various conditions.

[0077] In operation S110, power may be supplied to the transmitting device 1000 through initialization or power supply. In this case, when driving power of the transmitting device 1000 is supplied, an initialization sequence will be applied.

[0078] In operation S120, a frequency band of the transmitting apparatus 1000 is set. For example, in the case where the power amplifier 1200 covers a plurality of frequency bands, impedance matching or bias may be set to optimize a target transmission frequency band.

[0079] In operation S130, a digital predistortion DPD mode is selected to compensate for nonlinearity or distortion characteristics of the power amplifier 1200 in a set frequency band. For example, the DPD mode selector 1300 may select the multi-mode digital predistorter 1100 in any one of the ML polynomial mode, the MP mode, and the DDR mode.

[0080] In operation S140, the DPD mode selector 1300 performs a performance evaluation of the power amplifier 1200 in the selected digital predistortion DPD mode. For example, the performance evaluation circuit 1310 (see Figure 2 ) evaluates at least one of the gain, error vector magnitude EVM and adjacent channel leakage ratio ACLR of the power amplifier 1200 according to the feedback signal FB, and the feedback signal FB feeds back the output of the power amplifier 1200.

[0081] In operation S150, the DPD mode selector 1300 determines whether the digital predistortion DPD mode set in operation S130 is the last mode selected for performance evaluation. For example, the DPD mode selector 1300 checks whether the mode set in operation S130 is the last mode among multiple digital predistortion DPD modes. If the digital predistortion DPD mode set in operation S130 is the last mode for evaluation ("yes" direction), the process moves to operation S160. On the other hand, if the digital predistortion DPD mode set in operation S130 is not the last mode for evaluation ("no" direction), the process returns to operation S130 and selects another digital predistortion DPD mode.

[0082] In operation S160, the DPD mode selector 1300 selects one of the evaluated memoryless ML polynomial mode, memory polynomial MP mode, and dynamic skew reduction DDR mode providing the best performance. The DPD mode selector 1300 compares gain, EVM, and ACLR for each case to select the DPD mode showing the best performance in the selected frequency band.

[0083] In operation S170 , the DPD mode selector 1300 sets the multi-mode digital predistorter 1100 to the selected DPD mode.

[0084] Hereinabove, the DPD mode selection process of the multi-mode digital predistorter 1100 performed during the training of the transmitting apparatus 1000 has been briefly described. According to the present disclosure, an optimal DPD mode may be selected according to the transmission band of the power amplifier 1200 or the transmitting apparatus 1000.

[0085] Figure 8 is a flowchart illustrating a setting process of a multi-mode digital predistorter performed during a training operation of a transmitting device according to another embodiment of the present disclosure. Figure 8 , according to the bias setting of the transmitting device 1000, a DPD mode with the best performance can be selected from multiple DPD modes.

[0086] In operation S210, power may be provided to the transmitting device 1000 through initialization or power supply. In this case, when driving power of the transmitting device 1000 is supplied, an initialization sequence will be applied.

[0087] In operation S220, a frequency band of the transmitting apparatus 1000 is set. For example, in the case where the power amplifier 1200 covers a plurality of frequency bands, impedance matching or bias may be set to optimize a target transmission frequency band.

[0088] In operation S225, a bias condition of the power amplifier 1200 is set. For example, a voltage or current bias of the power amplifier 1200 may be adjusted according to a transmission environment.

[0089] In operation S230, a digital predistortion DPD mode is selected to compensate for nonlinear or distortion characteristics of the power amplifier 1200 in a set frequency band. For example, the DPD mode selector 1300 may select the multi-mode digital predistorter 1100 in any one of the ML polynomial mode, the MP mode, and the DDR mode.

[0090] In operation S240, the DPD mode selector 1300 performs performance evaluation of the power amplifier 1200 in the selected digital predistortion DPD mode. For example, the performance evaluation circuit 1310 calculates at least one of the gain, EVM, and ACLR of the power amplifier 1200 according to the feedback signal FB, which feeds back the coupled output of the power amplifier 1200.

[0091] In operation S250, the DPD mode selector 1300 determines whether the digital predistortion DPD mode set in operation S230 is the last mode selected for performance evaluation. For example, the DPD mode selector 1300 checks whether the mode set in operation S230 is the last mode among multiple digital predistortion DPD modes. If the digital predistortion DPD mode set in operation S230 is the last mode for evaluation ("yes" direction), the process moves to operation S260. On the other hand, if the digital predistortion DPD mode set in operation S230 is not the last mode for evaluation ("no" direction), the process will return to operation S230 and select another digital predistortion DPD mode.

[0092] In operation S260, the DPD mode selector 1300 selects one of the evaluated ML polynomial mode, MP mode, and DDR mode providing the best performance. The DPD mode selector 1300 compares gain, EVM, and ACLR for each case to select the DPD mode showing the best performance in the selected frequency band.

[0093] In operation S270 , the DPD mode selector 1300 sets the multi-mode digital predistorter 1100 to the selected DPD mode.

[0094] In the above, the digital predistortion mode selection process of the multi-mode digital predistorter 1100 performed during the training of the transmitting apparatus 1000 of the present disclosure has been briefly described. According to the present disclosure, the optimal digital predistortion DPD mode may be selected according to the bias setting of the power amplifier 1200.

[0095] Fig. 9 is shown as Figure 1 The block diagram of another embodiment of the transmitting device 1000 of the transmitting device 1000 is shown in FIG. The transmitting device 1000b includes a DPD processing circuit 9100 that uses a predistortion signal u(n) output from the DPD 1100 (rather than the output of the power amplifier 1200) to evaluate the digital predistortion performance. The DPD processing circuit 9100 may include a DPD mode selector 1300′ and a multi-mode digital predistorter 1100.

[0096] The multi-mode digital predistorter 1100 ("DPD 1100") operates in one of a plurality of DPD operation modes according to a selection signal SEL. The DPD 1100 operates in any one of a memoryless (ML) polynomial mode, a memory polynomial (MP) mode, and a dynamic deviation reduction (DDR) mode. When the transmitting device 1000b is trained or set, the DPD processing circuit 9100 may sequentially change the DPD operation mode. And, the performance in each DPD operation mode may be measured by the DPD mode selector 1300'.

[0097] The performance evaluation circuit 1310' receives the predistortion signal u(n) output by the DPD 1100. The performance evaluation circuit 1310' analyzes the output signal u(n) to select the DPD operation mode with the best performance in the current transmission band of the transmitting device 1000 and / or the bias setting of the power amplifier 1200. The performance evaluation circuit 1310' determines at least one of the gain, error vector magnitude EVM, and adjacent channel leakage ratio ACLR of the power amplifier 1200 for each of the plurality of DPD operation modes in the transmission band and bandwidth of the current transmitting device 1000b. Here, the performance evaluation circuit 1310' may also change the bias setting and / or transmission band of the power amplifier 1200 to determine the gain, EVM, and ACLR corresponding to another band / bias setting. Because the output signal u(n) does not include the performance characteristics of the power amplifier 1200, the gain, EVM, and / or ACLR may be calculated by the performance evaluation circuit 1310' using the estimated or previously measured performance characteristics of the power amplifier 1200.

[0098] The algorithm selector 1330 selects the best DPD operation mode with reference to the performance of each DPD operation mode provided by the performance evaluation circuit 1310'. For example, the algorithm selector 1330 selects one of the ML polynomial mode, the MP mode, and the DDR mode using the calculated gain, EVM, and / or ACLR of the output signal y(n) of the power amplifier 1200 for each DPD operation mode. Then, the operation mode of the multi-mode digital predistorter 1100 is determined to operate in the determined DPD operation mode. The algorithm selector 1330 outputs a selection signal SEL to activate the determined DPD operation mode of the multi-mode digital predistorter 1100.

[0099] Fig.10 1 shows an example adjacent channel leakage ratio ACLR performance in the mid-high band MHB of the multi-mode digital predistorter of the present disclosure. Fig.10 The multi-mode digital predistorter 1100 of the present disclosure provides a performance improvement of greater than 2 dB by utilizing the digital predistortion operation of the power amplifier 1200 implemented with a Doherty power amplifier.

[0100] Curve "C0" shows the adjacent channel leakage ratio ACLR of the Doherty power amplifier when digital predistortion is not applied in the mid-high band MHB with a center frequency of 2593 MHz. In this case, depending on the change in the output of the power amplifier 1200, the adjacent channel leakage ratio ACLR is about -34 dBc.

[0101] The curve "C1" shows the adjacent channel leakage ratio ACLR of the Doherty power amplifier when only the digital predistortion in the memory polynomial MP mode is applied in the mid-high band MHB with a center frequency of 2593 MHz. In this case, the adjacent channel leakage ratio ACLR is about -38 dBc depending on the change in the output of the power amplifier 1200. That is, a relatively large performance improvement is apparent compared to when the digital predistortion is not applied.

[0102] Curve "C2" shows the adjacent channel leakage ratio ACLR of the Doherty power amplifier when only the digital predistortion in the dynamic deviation reduction DDR mode is applied in the mid-high band MHB with a center frequency of 2593 MHz. In this case, the adjacent channel leakage ratio ACLR is about -39.5 dBc depending on the change in the output of the power amplifier 1200. It can be seen that when the digital predistortion in the dynamic deviation reduction DDR mode is applied, a relatively large performance improvement is possible compared to when only the memory polynomial MP mode is applied.

[0103] Curve "C3" shows the adjacent channel leakage ratio ACLR of the Doherty power amplifier when the multi-mode digital predistorter 1100 of the present disclosure is used in the mid-high band MHB with a center frequency of 2593 MHz. In this case, although there is a difference in degree according to the change in the output of the power amplifier 1200, the adjacent channel leakage ratio ACLR is about -40.5 dBc. In other words, it can be seen that when the DPD operation mode can be changed under the mid-high band MHB condition, it is possible to improve the performance by more than 2 dB compared to when only the memory polynomial MP mode is used.

[0104] Fig.11 An example adjacent channel leakage ratio (ACLR) performance of the multi-mode digital predistorter of the present invention in the ultra-high frequency band (UHB) is shown. Fig.11 The multi-mode digital predistorter 1100 of the present invention provides a performance improvement of more than 2 dB by utilizing the digital predistortion operation of the power amplifier 1200 implemented by a Doherty power amplifier.

[0105] Curve "D0" shows the adjacent channel leakage ratio ACLR of the Doherty power amplifier when digital predistortion is not applied in the ultra-high frequency band UHB with a center frequency of 3550MHz. In this case, according to the change of the output Pout of the power amplifier 1200, the adjacent channel leakage ratio ACLR performance of -36dBm to -28dBm is shown.

[0106] Curve "D1" shows the adjacent channel leakage ratio ACLR of the Doherty power amplifier when only digital predistortion in the memory polynomial MP mode is applied in the ultra-high frequency band UHB with a center frequency of 3550 MHz. Curve "D2" shows the adjacent channel leakage ratio ACLR of the Doherty power amplifier when only digital predistortion in the dynamic deviation reduction DDR mode is applied in the ultra-high frequency band UHB with a center frequency of 3550 MHz. According to the curves "D1" and "D2", it can be seen that the performance is significantly improved compared to when digital predistortion is not applied according to the change of the output of the power amplifier 1200.

[0107] Curve "D3" shows an example adjacent channel leakage ratio ACLR of a Doherty power amplifier when the multi-mode digital predistorter 1100 of the present disclosure is used in an ultra-high frequency band UHB with a center frequency of 3550 MHz. In this case, although there is a difference in degree according to the change in the output of the power amplifier 1200, it can be seen that a performance improvement of about 0.6 dB to 1.5 dB is possible compared to curve "D1" where only the memory polynomial MP mode is applied.

[0108] Referring to the above performance evaluation results, when the multi-mode digital pre-distorter 1100 of the present disclosure is used, higher performance can be provided than when only the memory polynomial MP mode or the dynamic deviation reduction DDR mode is used.

[0109] Fig.12 is a block diagram illustrating a mobile device that transmits transmission signals in multiple frequency bands according to another embodiment of the present disclosure. Fig.12 , the mobile device 2000 may include a processor 2050 , a multi-mode digital pre-distorter circuit 2100 , a power amplifier circuit 2200 , and a training circuit 2300 .

[0110] The processor 2050 generates a baseband signal to be transmitted. For example, the processor 2050 may generate a baseband signal x 1 (n) to x k (n) is provided to the multi-mode digital pre-distorter circuit 2100.

[0111] The multi-mode digital predistorter circuit 2100 detects the nonlinearity of the power amplifier circuit 2200 and applies predistortion compensation to the baseband signal x1 (n) to baseband signal x k (n). The multi-mode digital predistorter circuit 2100 includes a first multi-mode digital predistorter (first MM DPD) to a k-th multi-mode digital predistorter (k-th MM DPD) for applying a predistortion operation to each frequency band. The first multi-mode digital predistorter (first MM DPD) performs a digital predistortion process to compensate for the nonlinearity of the first power amplifier PA1. To this end, the first multi-mode digital predistorter (first MM DPD) performs a digital predistortion process on the baseband signal x 1 (n) Performing a digital pre-distortion operation.

[0112] Specifically, the first multi-mode digital predistorter (first MM DPD) of the present disclosure selects a digital predistortion DPD mode optimized for the transmission band and bias setting of the first power amplifier PA1. For example, the first multi-mode digital predistorter (first MM DPD) can process the baseband signal x in any one of the memoryless ML polynomial mode, the memory polynomial MP mode, and the dynamic deviation reduction DDR mode. 1 (n) applying a digital predistortion operation. The selection of the digital predistortion DPD mode may be performed at startup or under the control of the training circuit 2300 when necessary. Similarly, the second multi-mode digital predistorter (second MMDPD) to the k-th multi-mode digital predistorter (k-th MM DPD) may also select a digital predistortion DPD mode optimized for the bias setting and / or transmission band of each corresponding power amplifier (PA2 to PAk). Each of the above-mentioned digital predistorters (first MM DPD to k-th MM DPD) may include the above-mentioned Figure 3 (Or, they all include the above Fig. 9 The structure of the training circuit 2300 is as follows: 1 (n) to u k (n) instead of the output signal y 1 (n) to y k (n)).

[0113] The power amplifier circuit 2200 may include a plurality of power amplifiers PA1 to PAk for power amplification of each frequency band. Each of the plurality of power amplifiers PA1 to PAk amplifies a predistortion signal u transmitted from a digital predistorter (first MM DPD to kth MM DPD). 1 (n) to u k (n), and provides a corresponding output as an output signal y 1 (n) to y k(n) Each of the plurality of power amplifiers PA1 to PAk may be a high efficiency Doherty power amplifier. Alternatively, each of the power amplifiers PA1 to PAk may be any suitable type of power amplifier that requires pre-compensation for nonlinearity or distortion.

[0114] The training circuit 2300 may select a DPD operation mode of the multi-mode digital predistorter circuit 2100 using an output of each of the plurality of power amplifiers PA1 to PAk or an output of the multi-mode digital predistorter circuit 2100. The training circuit 2300 may select a DPD operation mode according to bias settings, frequency bands, and / or various operations of the plurality of power amplifiers (PA1 to PAk) during a training process of the mobile device 2000 or when digital predistortion DPD is applied. To this end, the training circuit 2300 receives an output signal y of each of the plurality of power amplifiers PA1 to PAk by feeding back the output signal y of each of the plurality of power amplifiers PA1 to PAk. 1 (n) to y k (n) and the feedback signals FB1 to FBk obtained by the training circuit 2300. And, the training circuit 2300 analyzes the feedback signals FB1 to FBk to determine the bias setting, gain, EVM and / or ACLR according to the frequency band of each of the multiple power amplifiers PA1 to PAk. Using the analysis results, the training circuit 2300 can determine the DPD operation mode that can provide the best performance for each of the multiple power amplifiers PA1 to PAk. Once the DPD operation mode that can provide the best performance for each of the multiple power amplifiers PA1 to PAk is determined, the training circuit 2300 can set each of the digital predistorters (first MM DPD to kth MM DPD) to the selected DPD mode.

[0115] According to the above configuration, the mobile device 2000 of the present disclosure can compensate for the nonlinearity of each of the multiple power amplifiers PA1 to PAk according to various bias settings or frequency bands. Here, the digital predistorters (first MM DPD to kth MM DPD) in the multi-mode digital predistorter circuit 2100 each include a first kernel for operating the memory polynomial MP mode and a second kernel selectively activated. The second kernel can perform operations corresponding to the second term for processing the non-diagonal terms of the Volterra series. Therefore, the mobile device 2000 can run various DPD operation modes while minimizing hardware costs.

[0116] Exemplary embodiments of the inventive concept have been described herein with reference to signal arrows, block diagrams, and algorithmic expressions. Each block of the block diagram and the combination of blocks in the block diagram and the operation according to the algorithmic expression can be implemented by hardware (e.g., the processing circuit of the DPD mode selector 1300 or the multimode DPD 1100) in cooperation with a memory within the sending device 1000 storing computer program instructions. Such computer program instructions can be stored in a non-transitory computer-readable medium, which can guide a computer, other programmable data processing device, or other device to work in a specific manner so that the instructions stored in the computer-readable medium generate a product including instructions for implementing the functions / actions specified in the block diagram. The term "processor" or "processing circuit" used herein is intended to include any processing device, such as a processing device including a central processing unit (CPU) and / or other processing circuits (e.g., a digital signal processor (DSP), a microprocessor, an application specific gate array (ASIC), a field programmable gate array (FPGA), etc.). In addition, a "processor" includes computing hardware and may refer to a multi-core processor including multiple processing cores in a computing device. Various elements associated with a processing device may be shared by other processing devices.

[0117] The above is a specific embodiment for implementing the inventive concept. Although the inventive concept has been particularly shown and described with reference to the embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims and their equivalents.

Claims

1. A sending device, comprising: a multi-mode digital predistorter circuit configured to pre-compensate an input baseband signal in one of a plurality of digital predistortion modes according to a selection signal; a power amplifier configured to amplify the pre-compensated baseband signal and output the amplified baseband signal as an output signal of the allocated frequency band; a digital predistortion mode selector circuit, the digital predistortion mode selector circuit being configured to: determine the one digital predistortion mode of the plurality of digital predistortion modes using a feedback signal obtained from the output signal, the one digital predistortion mode corresponding to the allocated frequency band; and set the multi-mode digital predistorter circuit to the determined one digital predistortion mode of the plurality of digital predistortion modes.

2. The transmitting device according to claim 1, wherein: The plurality of digital pre-distortion modes include a memoryless polynomial mode, a memory polynomial mode, and a dynamic deviation reduction mode.

3. The transmitting device according to claim 2, wherein: The multi-mode digital predistorter circuit comprises: a first core processing circuit configured to process the input baseband signal in one of the memoryless polynomial mode and the memory polynomial mode in response to a first enable signal; a second core processing circuit configured to perform operations on the input baseband signal in the dynamic deviation reduction mode in response to a second enable signal; and An adder is configured to add a first signal output from the first core processing circuit and a second signal output from the second core processing circuit in the dynamic deviation reduction mode to provide the pre-compensated baseband signal.

4. The transmitting device according to claim 3, wherein: In the memoryless polynomial mode, the first enable signal and the second enable signal are deactivated, wherein, in the memory polynomial mode, the first enable signal is activated and the second enable signal is deactivated, and Wherein, in the dynamic deviation reduction mode, the first enable signal and the second enable signal are activated.

5. The transmitting device according to claim 4, wherein: The multi-mode digital predistorter circuit includes a selector configured to select one of an output of the first core processing circuit and an output of the adder according to the plurality of digital predistortion modes to provide the precompensated baseband signal.

6. The transmitting device according to claim 5, wherein: The selector selects the output of the first core processing circuit in the memoryless polynomial mode and the memory polynomial mode, and selects the output of the adder in the dynamic deviation reduction mode.

7. The transmitting device according to claim 3, wherein: The first signal corresponds to Among them, a k,m represents the polynomial coefficients of the diagonal terms, M is the maximum order of the memory length, K is the nonlinear order, and m is the memory depth, and the second term signal corresponds to Among them, b k,l are the polynomial coefficients of the off-diagonal terms, and x*(nl) is the complex conjugate of x(nl).

8. The transmitting device according to claim 7, wherein: In the memoryless polynomial mode, the memory depth m is set to "0".

9. The transmitting device according to claim 1, wherein: The digital predistortion mode selector circuit comprises: a performance evaluation circuit configured to evaluate the performance of the multi-mode digital predistorter circuit by analyzing the feedback signal; and An algorithm selector is configured to determine the one digital predistortion mode among the plurality of digital predistortion modes according to a performance evaluation result, and to set an operation mode of the multi-mode digital predistorter circuit to the one digital predistortion mode among the plurality of digital predistortion modes.

10. The transmitting device according to claim 9, wherein: The digital predistortion mode selector circuit determines the operation mode while changing a bias setting or a frequency band of the power amplifier.

11. A predistortion method of a digital predistorter, the predistortion method being used to compensate for nonlinearity of a power amplifier, the predistortion method comprising: evaluating the performance of the digital predistorter in each of a plurality of digital predistortion modes; selecting a digital predistortion mode from the plurality of digital predistortion modes based on the evaluated performance; as well as setting the digital predistorter to the one of the plurality of digital predistortion modes, Wherein, the digital predistorter comprises: a first core processing circuit configured to process an input baseband signal in one of a memoryless polynomial mode and a memory polynomial mode in response to a first enable signal; a second core processing circuit configured to perform a dynamic deviation reduction mode of operation on the input baseband signal in response to a second enable signal; and An adder is configured to add a first signal output from the first core processing circuit and a second signal output from the second core processing circuit in the dynamic deviation reduction mode to provide a pre-compensated baseband signal.

12. The predistortion method according to claim 11, further comprising: At least one of a transmission band or a bias setting of the power amplifier is adjusted, and the performance of the digital predistorter in each of the plurality of digital predistortion modes is again evaluated.

13. The predistortion method according to claim 11, wherein: The performance of the digital predistorter includes at least one of a gain, an adjacent channel leakage ratio, and an error vector magnitude of the power amplifier.

14. The predistortion method according to claim 11, wherein: The plurality of digital pre-distortion modes include a memoryless polynomial mode, a memory polynomial mode, and a dynamic deviation reduction mode.

15. The predistortion method according to claim 14, wherein: The first signal corresponds to Among them, a k,m represents the polynomial coefficients of the diagonal terms, M is the maximum order of the memory length, K is the nonlinear order, and m is the memory depth, and the second term signal corresponds to Among them, b k,l are the polynomial coefficients of the off-diagonal terms, and x*(nl) is the complex conjugate of x(nl).

16. The predistortion method according to claim 15, wherein: In the memoryless polynomial mode, the first enable signal and the second enable signal are deactivated, wherein, in the memory polynomial mode, the first enable signal is activated and the second enable signal is deactivated, and Wherein, in the dynamic deviation reduction mode, the first enable signal and the second enable signal are activated.

17. The predistortion method according to claim 16, wherein: In the memoryless polynomial mode, the memory depth m is set to "0".

18. A digital predistorter, the digital predistorter being used to pre-compensate nonlinearity in a power amplifier, the digital predistorter comprising: a first core processing circuit configured to process an input baseband signal in one of a memoryless polynomial mode and a memory polynomial mode in response to a first enable signal; a second core processing circuit configured to perform operations on the input baseband signal in a dynamic deviation reduction mode in response to a second enable signal; an adder configured to add a first signal output from the first core processing circuit and a second signal output from the second core processing circuit in the dynamic deviation reduction mode to provide a pre-compensated baseband signal; as well as a selector configured to select one of the first term signal and the output of the adder in response to a selection signal, The first signal corresponds to Among them, a k,m represents the polynomial coefficients of the diagonal terms, M is the maximum order of the memory length, K is the nonlinear order, and m is the memory depth, and the second term signal corresponds to Among them, b k,l are the polynomial coefficients of the off-diagonal terms, and x*(nl) is the complex conjugate of x(nl).

19. The digital predistorter according to claim 18, further comprising: a digital predistortion mode selector circuit configured to determine one digital predistortion mode corresponding to an allocated frequency band among a plurality of digital predistortion modes using a feedback output signal of the power amplifier, and to set the digital predistorter to the determined one digital predistortion mode among the plurality of digital predistortion modes.

20. The digital predistorter according to claim 18, wherein: In the memoryless polynomial mode, the first enable signal and the second enable signal are deactivated, and the memory depth m is set to "0", wherein, in the memory polynomial mode, the first enable signal is activated and the second enable signal is deactivated, and Wherein, in the dynamic deviation reduction mode, the first enable signal and the second enable signal are activated.

Images