Delay control circuit and method and semiconductor memory
By designing a delay control circuit including a temperature encoding module, an internal delay module and a timing generation module, the problem of delay value deviation under temperature changes is solved, and automatic compensation and stable performance are achieved.
Patent Information
- Application Number
- CN202411785156.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-06
- Publication Date
- 2025-03-28
AI Technical Summary
Under the temperature changes caused by changes in external environment and internal power consumption in existing DRAM chips, the internal delay value may deviate, resulting in chip function errors or performance degradation.
A delay control circuit is designed, including a temperature encoding module, an internal delay module and a timing generation module. By receiving the current temperature signal, encoding and outputting the instant temperature signal, selecting an appropriate delay unit to delay the input signal, and outputting the delay signal, thereby automatically compensating for the delay deviation caused by temperature changes.
It realizes automatic compensation of internal delay values under different temperature environments, avoids chip function errors or performance degradation, and maintains the working stability of the chip.
Smart Images
Figure CN119727671A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a delay control circuit, method and semiconductor memory. Background Art
[0002] Memory devices are widely used to store information, such as computers, wireless communication devices, cameras, digital displays, and other similar electronic devices, by programming different states of memory cells to store information. With the continuous development of semiconductor technology, people have put forward higher and higher requirements on the data transmission speed when manufacturing and using the above devices. In order to obtain faster data transmission speed, a series of memories that can transmit data at double the rate have emerged, such as Dynamic Random Access Memory (DRAM).
[0003] In DRAM, some key signals usually use internal delay units to generate fixed pulse widths. In order to keep the internal delay as constant as possible, the internal delay is usually adjusted to the expected value through fuses under specific temperature conditions during the test after the chip is generated to compensate for the deviation of the internal delay caused by the process. For the delay caused by internal voltage control, the internal voltage is also adjusted to the expected value through fuses to compensate for the deviation of the voltage generation module caused by the process.
[0004] However, when users use the chip, the temperature of the chip will not remain at a specific temperature but will change as the external environment and internal power consumption change. The delay inside the chip will also be affected by the operating temperature, which may cause chip functional errors or performance degradation.
[0005] In view of this, it is necessary to design an improved delay control circuit, method and semiconductor memory to solve the above problems. Summary of the invention
[0006] The object of the present invention is to provide a delay control circuit, method and semiconductor memory which can automatically compensate for internal delay values as the operating temperature changes.
[0007] To achieve the above-mentioned object of the invention, the present invention provides a delay control circuit, the delay control circuit comprising:
[0008] A temperature encoding module, used for encoding according to the current temperature and outputting an instant temperature signal, wherein the instant temperature signal includes category information divided according to the current temperature;
[0009] An internal delay module, comprising at least two different delay units, the internal delay module is used to receive a first input signal and an instant temperature signal, select a delay unit according to the instant temperature signal, and delay the first input signal through the delay unit to output a time-delay signal;
[0010] The timing generation module is used to process the target signal according to the time delay signal and output a pulse timing signal.
[0011] As a further improvement of the present invention, the category information is indicated in a three-bit binary form, and the real-time temperature signals are numbered from right to left as a first-bit signal, a second-bit signal, and a third-bit signal.
[0012] As a further improvement of the present invention, the temperature encoding module includes a plurality of gate circuits, and the gate circuits are arranged as follows:
[0013] The first bit signal and the second bit signal of the category information are respectively connected to the input end of the first NAND gate, the third bit signal is input to the first NAND gate, the output end of the first NAND gate and the output end of the first NAND gate are respectively connected to the input end of the first AND gate, and the first AND gate outputs a low temperature signal;
[0014] The third bit signal of the category information is input to the second NOT gate, the output end of the second NOT gate, the first bit signal, and the second bit signal are respectively connected to the input end of the second NAND gate, the second bit signal is input to the third NOT gate, the output end of the third NOT gate and the third bit signal are respectively connected to the input end of the third NAND gate, the output end of the second NAND gate and the output end of the third NAND gate are respectively connected to the input end of the fourth NAND gate, and the fourth NAND gate outputs a normal temperature signal;
[0015] The second bit signal and the third bit signal of the category information are respectively connected to the input terminals of the second AND gate, and the second AND gate outputs a high temperature signal.
[0016] As a further improvement of the present invention, the first input signal is connected to the input end of each delay unit, different delay units are connected to their corresponding instant temperature signals, and the delay unit corresponding to the instant temperature signal with an output signal of "1" outputs a delay signal.
[0017] As a further improvement of the present invention, the internal delay module includes a first delay unit, a second delay unit, and a third delay unit, and the first input signal is input to the input ends of the first delay unit, the second delay unit, and the third delay unit respectively;
[0018] The internal delay module further includes a third AND gate, a fourth AND gate, and a fifth AND gate, the output end of the first delay unit and the low temperature signal are input to the input end of the third AND gate, the output end of the second delay unit and the normal temperature signal are input to the input end of the fourth AND gate, and the output end of the third delay unit and the high temperature signal are input to the input end of the fifth AND gate;
[0019] The output ends of the third AND gate, the fourth AND gate and the fifth AND gate are connected to the input end of the first OR gate, and the first OR gate outputs a time-delay signal.
[0020] As a further improvement of the present invention, the first delay unit, the second delay unit and the third delay unit all use buffers, and different delay units use different numbers of buffers.
[0021] As a further improvement of the present invention, the timing generation module includes a fourth NOT gate and a sixth AND gate, the delay signal is connected to the input end of the fourth NOT gate, the output end of the fourth NOT gate and the target signal are both connected to the input end of the sixth AND gate, and the sixth AND gate outputs a pulse timing signal.
[0022] As a further improvement of the present invention, the delay control circuit further includes a temperature sensor for outputting the current temperature, and the temperature encoding module is arranged inside or outside the temperature sensor.
[0023] To achieve the above-mentioned object of the invention, the present invention provides a delay control method, which is applied to the above-mentioned delay control circuit, and the method comprises:
[0024] Encoding according to the current temperature, outputting an instant temperature signal, wherein the instant temperature signal includes category information divided according to the current temperature;
[0025] receiving a first input signal and an instantaneous temperature signal, selecting a delay unit according to the instantaneous temperature signal, performing delay processing on the first input signal through the delay unit, and outputting a time-delay signal;
[0026] The target signal is processed according to the time delay signal to output a pulse timing signal.
[0027] To achieve the above-mentioned object of the invention, the present invention provides a semiconductor memory, which includes the delay control circuit mentioned above.
[0028] The beneficial effects of the present invention are as follows: From the above contents, it can be seen that the delay control circuit, method and semiconductor memory provided by the present disclosure receive and encode the current temperature, and output an instant temperature signal to select the delay unit of the first input signal, so that the delay signal outputted is different under different temperatures, and further, the pulse width of the pulse timing signal outputted will also change with the change of the current temperature. Therefore, when the user uses the delay control circuit, method and semiconductor memory provided in the present disclosure, even if the external environment or internal power consumption causes the temperature of the chip to change, the internal delay value also changes with the temperature and different delay units can be selected under different temperature environments, thereby automatically compensating. Furthermore, it will not cause chip function errors or performance degradation, and the chip operation stability is maintained. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 A schematic diagram of the structure of a delay control circuit disclosed in an embodiment of the present invention;
[0030] Figure 2 Schematic diagram of the circuit structure of the temperature encoding module according to an embodiment of the present invention;
[0031] Figure 3 Schematic diagram of the circuit structure of the internal delay module of an embodiment of the present invention;
[0032] Figure 4 Schematic diagram of the circuit structure of the timing generation module according to an embodiment of the present invention;
[0033] Figure 5 It is a timing diagram of some signals of an embodiment of the present invention;
[0034] Reference numerals:
[0035] 11 - temperature sensor; 12 - temperature encoding module; 13 - internal delay module; 14 - timing generation module. DETAILED DESCRIPTION
[0036] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.
[0037] It should also be noted here that in order to avoid obscuring the present disclosure due to unnecessary details, only structures and / or processing steps closely related to the scheme of the present disclosure are shown in the accompanying drawings, while other details that are not very relevant to the present disclosure are omitted.
[0038] In addition, it should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0039] In order to make the purpose, technical scheme and advantages of the present disclosure clearer, the present disclosure is further described in detail below in conjunction with the accompanying drawings. It is hereby declared that the following embodiments are only special cases of the method proposed in the present disclosure, not all embodiments, and all other embodiments obtained by making detailed adjustments without creative labor based on the embodiments in the present disclosure are within the scope of protection of the present disclosure.
[0040] like Figures 1 to 5 As shown, the present disclosure provides a delay control circuit, method and semiconductor memory, wherein the delay control circuit comprises:
[0041] The temperature encoding module 12 is used to receive and encode the current temperature, and output an instant temperature signal dly_ctrl, wherein the instant temperature signal dly_ctrl includes category information divided according to the current temperature;
[0042] An internal delay module 13, comprising at least two different delay units, the internal delay module 13 is used to receive a first input signal A and an instantaneous temperature signal dly_ctrl, select a delay unit according to the instantaneous temperature signal dly_ctrl, and delay the first input signal through the delay unit to output a time-delay signal A_dly;
[0043] The timing generation module 14 is used to process the target signal B according to the delay signal A_dly and output a pulse timing signal C.
[0044] Specifically, the delay control circuit in the present invention can receive and encode the current temperature, and output the instant temperature signal dly_ctrl to select the delay unit of the first input signal A, so as to detect that when the current temperature is different, the output delay signal A_dly will also be selectively compensated due to passing through different delay units, so that the pulse width of the output pulse timing signal C will also automatically change with the change of the current temperature, thereby maintaining the stability of the chip operation.
[0045] For example, the target signal B is some key signals obtained from the dynamic random access memory DRAM described in the background art. The first input signal A can be any signal in the delay control circuit, which is not limited here.
[0046] In a specific embodiment of the present case, the delay control circuit further includes a temperature sensor 11 for acquiring and outputting the current temperature, and the temperature encoding module 12 can be disposed inside or outside the temperature sensor 11 .
[0047] The temperature sensor 11 is used to detect the current working temperature of the chip. Specifically, in this case, the current temperature sensed by the temperature sensor 11 ranges from -40°C to 120°C, and the temperature range is divided into eight temperature ranges. Among them, 0 represents -40°C to -20°C, 1 represents -20°C to 0°C, 2 represents 0°C to 20°C, 3 represents 20°C to 40°C, 4 represents 40°C to 60°C, 5 represents 60°C to 80°C, 6 represents 80°C to 100°C, and 7 represents 100°C to 120°C. It should be noted that, in one embodiment, the critical temperature value belongs to the previous temperature interval, for example, -20°C belongs to the temperature range of 0, but not to the temperature range of 1; of course, in another embodiment, the critical temperature value belongs to the next temperature interval, for example, -20°C belongs to the temperature range of 1, but not to the temperature range of 0.
[0048] Furthermore, the current temperature can be detected as the category information temp[2:0], and the number of categories of the instant temperature signal dly_ctrl is also consistent with the number of categories of the category information temp[2:0]. At the same time, only one category of the instant temperature signal dly_ctrl will output a signal "1".
[0049] The category information is indicated in a three-bit binary form, and the real-time temperature signal is numbered from right to left as a first-bit signal, a second-bit signal, and a third-bit signal.
[0050] Specifically, in the specific embodiment of the present disclosure, the instantaneous temperature signal dly_ctrl is divided into at least two categories according to the current temperature, and the number of categories of the instantaneous temperature signal dly_ctrl is also consistent with the number of categories of the category information temp[2:0], so the category of the category information temp[2:0] is also at least two, and the temperature encoding module 12 in this case divides the above eight temperature ranges into at least two temperature intervals. In addition, since only one category of the instantaneous temperature signal dly_ctrl will output a signal "1" at the same time, when passing through the internal delay module 13, the instantaneous temperature signal dly_ctrl with an output signal "1" selects the corresponding delay unit, so that the first input signal A is applicable to different delay units at different temperatures, so that the output delay signal A_dly can be adjusted and compensated at different temperatures.
[0051] Specifically, in this embodiment, the temperature encoding module 12 divides the eight temperature ranges into three temperature intervals, namely, a low temperature interval of -40°C to 20°C, a normal temperature interval of 20°C to 80°C, and a high temperature interval of 80°C to 120°C. The category information temp[2:0] is a three-bit binary number, where
[000] represents -40°C to -20°C,
[001] represents -20°C to 0°C,
[010] represents 0°C to 20°C,
[011] represents 20°C to 40°C,
[100] represents 40°C to 60°C,
[101] represents 60°C to 80°C,
[110] represents 80°C to 100°C, and
[111] represents 100°C to 120°C.
[0052] Therefore, corresponding to the above, the category information temp[2:0] can also be divided into low temperature interval information, normal temperature interval information, and high temperature interval information, and the low temperature interval information includes:
[000] ,
[001] ,
[010] , the normal temperature interval information includes:
[011] ,
[100] ,
[101] , and the high temperature interval information includes:
[110] ,
[111] .
[0053] Therefore, in this specific embodiment of the present disclosure, the temperature encoding module 12 divides the temperature range into three temperature intervals. If there are other requirements, the temperature range needs to be divided into two, or more than three temperature intervals, which is also within the protection scope of the present disclosure.
[0054] Correspondingly, since the temperature range is divided into three temperature intervals, namely, a low temperature interval, a normal temperature interval, and a high temperature interval, the instantaneous temperature signal dly_ctrl also includes a low temperature signal dly_ctrl[0], a normal temperature signal dly_ctrl[1], and a high temperature signal dly_ctrl[2]. When the current temperature is in different temperature intervals, the instantaneous temperature signal dly_ctrl output by the temperature encoding module 12 will also be different. Specifically, the category information is counted from right to left as the first signal temp[0], the second signal temp[1], and the third signal temp[3]. For example, when the category information temp[2:0] is
[011] , the first signal temp[0]=1, the second signal temp[1]=1, and the third signal temp[2]=0; for another example, when the temperature interval temp[2:0] is
[110] , the first signal temp[0]=0, the second signal temp[1]=1, and the third signal temp[2]=1.
[0055] Therefore, in order to achieve the above functions, the temperature encoding module 12 includes several gate circuits, which are arranged as follows:
[0056] The first bit signal temp[0] and the second bit signal temp[1] of the category information temp[2:0] are respectively connected to the input end of the first NAND gate N1, the third bit signal temp[2] is input to the first NAND gate P1, the output end of the first NAND gate N1 and the output end of the first NAND gate P1 are respectively connected to the input end of the first AND gate M1, and the first AND gate M1 outputs the low temperature signal dly_ctrl[0];
[0057] The third signal temp[2] of the category information temp[2:0] is input to the second NOT gate P2, the output end of the second NOT gate P2, the first signal temp[0], and the second signal temp[1] are respectively connected to the input end of the second NAND gate N2, the second signal temp[1] is input to the third NOT gate P3, the output end of the third NOT gate P3 and the third signal temp[2] are respectively connected to the input end of the third NAND gate N3, the output end of the second NAND gate N2 and the output end of the third NAND gate N3 are respectively connected to the input end of the fourth NAND gate N4, and the fourth NAND gate N4 outputs the normal temperature signal dly_ctrl[1];
[0058] The second bit signal temp[1] and the third bit signal temp[2] of the category information temp[2:0] are respectively connected to the input ends of the second AND gate M2, and the second AND gate M2 outputs the high temperature signal dly_ctrl[2].
[0059] Specifically, if the current temperature is in the low temperature range, taking the category information temp[2:0] as
[001] as an example, the first bit signal temp[0] outputs a signal "1", the second bit signal temp[1] outputs a signal "0", and after passing through the first NAND gate N1, it outputs a signal "1", and the third bit signal temp[2] outputs a signal "0", and after passing through the first NOT gate P1, it outputs a signal "1". After the first NAND gate N1 and the first NOT gate P1 both output a signal "1", they pass through the first AND gate M1 to output a signal "1", and then the low temperature signal dly_ctrl[0] outputs a signal "1". If the category information temp[2:0] is
[010] or
[000] , after passing through the above gate circuit, the low temperature signal dly_ctrl[0] will output a signal "1"; on the contrary, if the current temperature is in the normal temperature range or the high temperature range, after passing through the above gate circuit, the low temperature signal dly_ctrl[0] will output a signal "0", which will not be repeated here.
[0060] If the current temperature is in the normal temperature range, taking the category information temp[2:0] as
[011] as an example, the third signal temp[2] outputs a signal "0" and outputs a signal "1" after passing through the second NOT gate P2. It and the first signal temp[0] output signal "1" and the second signal temp[1] output signal "1" all pass through the second NAND gate N2 to output a signal "0". At the same time, the second signal temp[1] outputs a signal "1" and passes through the third NOT gate P3 to output a signal "0". It and the third signal temp[2] output signal "0" pass through the third NAND gate N3 to output a signal "1". The second NAND gate N2 outputs a signal "0" and the third NAND gate N3 outputs a signal "1" after passing through the fourth NAND gate N4 to output a normal temperature signal dly_ctrl[1] of "1". If the category information temp[2:0] is
[100] or
[101] , after passing through the above-mentioned gate circuit, the normal temperature signal dly_ctrl[1] will output a signal "1"; on the contrary, if the current temperature is in the low temperature range or the high temperature range, after passing through the above-mentioned gate circuit, the normal temperature signal dly_ctrl[1] will output a signal "0", which will not be repeated here.
[0061] If the current temperature is in the high temperature range, taking the category information temp[2:0] as
[111] as an example, the second bit signal temp[1] outputs a signal "1", the third bit signal temp[2] outputs a signal "1", and after passing through the second AND gate M2, the signal "1" is output, and the high temperature signal dly_ctrl[2] outputs a signal "1". If the category information temp[2:0] is
[110] , after passing through the above gate circuit, the normal temperature signal dly_ctrl[1] will output a signal "1"; on the contrary, if the current temperature is in the low temperature range or the normal temperature range, after passing through the above gate circuit, the high temperature signal dly_ctrl[2] will output a signal "0", which will not be repeated here.
[0062] Therefore, through the temperature encoding module 12, the current temperature can be detected and divided into at least two temperature intervals. When the current temperature is in different temperature intervals, the temperature encoding module 12 can output the corresponding instantaneous temperature signal dly_ctrl to select different delay units in the internal delay module 13. Therefore, the delay signal A_dly output by the internal delay module 13 can be compensated at different temperatures.
[0063] Further, such as Figure 3 As shown, the first input signal A is connected to the input end of each delay unit, different delay units are connected to their corresponding instant temperature signals dly_ctrl, and the delay unit corresponding to the instant temperature signal dly_ctrl with an output signal of "1" outputs a delay signal A_dly.
[0064] In this embodiment, the delay unit and the instantaneous temperature signal dly_ctrl are in a one-to-one correspondence. After the first input signal A is input into different delay units, the delay signal A_dly with different delay effects can be output. However, since only one type of the instantaneous temperature signal dly_ctrl will output a signal "1" at the same time, the instantaneous temperature signal dly_ctrl with the output signal "1" can select the delay unit corresponding to it and output the corresponding delay signal A_dly. Therefore, when the current temperature is different, the delay unit used to output the delay signal A_dly is also different, so the delay signal A_dly can be adjusted according to the temperature.
[0065] Specifically, Figure 4As shown, in this embodiment, the instantaneous temperature signal dly_ctrl includes a low temperature signal dly_ctrl[0], a normal temperature signal dly_ctrl[1] and a high temperature signal dly_ctrl[2]. Correspondingly, the delay unit also includes a first delay unit Q1, a second delay unit Q2 and a third delay unit Q3. The first input signal A is input to the input ends of the first delay unit Q1, the second delay unit Q2 and the third delay unit Q3 respectively. Specifically, the circuit configuration of the internal delay module 13 is as follows:
[0066] The internal delay module 13 further includes a third AND gate M3, a fourth AND gate M4, and a fifth AND gate M5, the output end of the first delay unit Q1 and the low temperature signal dly_ctrl[0] are input to the input end of the third AND gate M3, the output end of the second delay unit Q2 and the normal temperature signal dly_ctrl[1] are input to the input end of the fourth AND gate M4, and the output end of the third delay unit Q3 and the high temperature signal dly_ctrl[2] are input to the input end of the fifth AND gate M5;
[0067] The output terminals of the third AND gate M3 , the fourth AND gate M4 , and the fifth AND gate M5 are connected to the input terminal of the first OR gate O1 , and the first OR gate O1 outputs the delay signal A_dly.
[0068] When the operating temperature is in the low temperature range, the low temperature signal dly_ctrl[0] outputs a signal "1", and the normal temperature signal dly_ctrl[1] and the high temperature signal dly_ctrl[2] output a signal "0". At this time, the first input signal A is delayed by the first delay unit Q1 and then output from the third AND gate M3 and the first OR gate O1 to form a delayed signal A_dly.
[0069] When the operating temperature is in the normal temperature range, the normal temperature signal dly_ctrl[1] outputs a signal "1", and the low temperature signal dly_ctrl[0] and the high temperature signal dly_ctrl[2] output a signal "0". At this time, after the first input signal A is delayed by the second delay unit Q2, the fourth AND gate M4 and the first OR gate O1 output a delayed signal A_dly.
[0070] When the operating temperature is in the high temperature range, the high temperature signal dly_ctrl[2] outputs a signal "1", and the low temperature signal dly_ctrl[0] and the normal temperature signal dly_ctrl[1] output a signal "0". At this time, the first input signal A is delayed by the third delay unit Q3, and the delayed signal A_dly is output from the fifth AND gate M5 and the first OR gate O1.
[0071] In this embodiment, the delay unit uses a buffer, and different delay units use different numbers of buffers, so that the first input signal A is delayed to different degrees after passing through different delay units. In addition, it should be noted that the delay degree of the first input signal A passing through the delay unit does not necessarily increase or decrease with the increase of temperature, and can also present different delay degrees through user customization, which needs to be determined according to different needs of users.
[0072] Further, such as Figure 4 As shown, the timing generation module 14 includes a fourth NOT gate P4 and a sixth AND gate M6, the delay signal A_dly is connected to the input end of the fourth NOT gate P4, the output end of the fourth NOT gate P4 and the target signal B are both connected to the input end of the sixth AND gate M6, and the sixth AND gate M6 outputs a pulse timing signal C.
[0073] Specifically, Figure 5 As shown, the first input signal A forms a delayed signal A_dly after passing through the internal delay module 13, and the high-level pulse of the delayed signal A_dly is located at the rear side of the high-level pulse of the target signal B, so when the target signal B is "0", the pulse timing signal C also outputs "0"; when the target signal B is "1" and the delayed signal A_dly still outputs "0", the delayed signal A_dly outputs "1" after passing through the fourth NOT gate P4, and the pulse timing signal C output by the sixth AND gate M6 is "1"; when the target signal B is "1" and the delayed signal A_dly also outputs "1", the delayed signal A_dly outputs "0" after passing through the fourth NOT gate P4, and the delayed signal A_dly and the target signal B output "0" after passing through the sixth AND gate M6, so that the pulse timing signal C can be output as shown below. Figure 5 The pulse shown in the figure is determined by the delay signal A_dly, and the delay degree of the delay signal A_dly relative to the first input signal A is controlled by the internal delay module and determined by the instantaneous temperature signal dly_ctrl. Therefore, the width of the pulse will be different under different temperature conditions. Similarly, it should be noted that the width of the pulse does not necessarily increase or decrease with the increase of temperature, and can also present pulses of different widths through user customization, which needs to be determined according to different user needs.
[0074] For the convenience of description, the above device is described by dividing it into various modules according to its functions. Of course, when implementing the present disclosure, the functions of each module can be implemented in the same or multiple software and / or hardware.
[0075] The present disclosure also provides a delay control method, which is applied to the delay control circuit described above, and the method includes:
[0076] S1: Encode according to the current temperature and output an instant temperature signal dly_ctrl, wherein the instant temperature signal dly_ctrl includes category information temp[2:0] divided according to the current temperature;
[0077] S2: receiving a first input signal A and an instantaneous temperature signal dly_ctrl, selecting a delay unit according to the instantaneous temperature signal dly_ctrl, and delaying the first input signal A through the delay unit to output a time-delay signal A_dly;
[0078] S3: Process the target signal B according to the delay signal A_dly, and output a pulse timing signal C.
[0079] It should be noted that the above is a description of some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0080] In addition, the present disclosure also provides a semiconductor memory, the semiconductor memory includes the delay control circuit as described above, and the semiconductor memory includes a dynamic random access memory DRAM. Of course, the semiconductor memory can also be other types of memory, which is also within the protection scope of the present disclosure.
[0081] In summary, the delay control circuit, method and semiconductor memory provided in the present disclosure receive and encode the current temperature, and output the instant temperature signal dly_ctrl to select the delay unit of the first input signal A, so that the output delay signal A_dly is different under different temperatures, and further, the pulse width of the output pulse timing signal C will also change with the change of the current temperature. Therefore, when the user uses the delay control circuit, method and semiconductor memory provided in the present disclosure, even if the external environment or internal power consumption causes the chip temperature to change, the internal delay value also changes with the temperature and different delay units can be selected under different temperature environments, thereby automatically compensating. Furthermore, it will not cause chip function errors or performance degradation, and the chip operation stability is maintained.
[0082] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.
[0083] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description.
[0084] The embodiments of the present disclosure are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.
[0085] The above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.
Claims
1. A delay control circuit, characterized in that: The delay control circuit comprises: A temperature encoding module, used for encoding according to the current temperature and outputting an instant temperature signal, wherein the instant temperature signal includes category information divided according to the current temperature; An internal delay module, comprising at least two different delay units, the internal delay module is used to receive a first input signal and an instant temperature signal, select a delay unit according to the instant temperature signal, and delay the first input signal through the delay unit to output a time-delay signal; The timing generation module is used to process the target signal according to the time delay signal and output a pulse timing signal.
2. The delay control circuit according to claim 1, characterized in that: The category information is indicated in a three-bit binary form, and the real-time temperature signal is numbered from right to left as a first-bit signal, a second-bit signal, and a third-bit signal.
3. The delay control circuit according to claim 2, characterized in that: The temperature encoding module includes several gate circuits, and the settings of the gate circuits are as follows: The first bit signal and the second bit signal of the category information are respectively connected to the input end of the first NAND gate, the third bit signal is input to the first NAND gate, the output end of the first NAND gate and the output end of the first NAND gate are respectively connected to the input end of the first AND gate, and the first AND gate outputs a low temperature signal; The third bit signal of the category information is input to the second NOT gate, the output end of the second NOT gate, the first bit signal, and the second bit signal are respectively connected to the input end of the second NAND gate, the second bit signal is input to the third NOT gate, the output end of the third NOT gate and the third bit signal are respectively connected to the input end of the third NAND gate, the output end of the second NAND gate and the output end of the third NAND gate are respectively connected to the input end of the fourth NAND gate, and the fourth NAND gate outputs a normal temperature signal; The second bit signal and the third bit signal of the category information are respectively connected to the input terminals of the second AND gate, and the second AND gate outputs a high temperature signal.
4. The delay control circuit according to claim 3, characterized in that: The first input signal is connected to the input end of each delay unit, different delay units are connected to their corresponding instant temperature signals, and the delay unit corresponding to the instant temperature signal with an output signal of "1" outputs a delay signal.
5. The delay control circuit according to claim 4, characterized in that: The internal delay module comprises a first delay unit, a second delay unit and a third delay unit, and the first input signal is input to the input ends of the first delay unit, the second delay unit and the third delay unit respectively; The internal delay module further includes a third AND gate, a fourth AND gate, and a fifth AND gate, the output end of the first delay unit and the low temperature signal are input to the input end of the third AND gate, the output end of the second delay unit and the normal temperature signal are input to the input end of the fourth AND gate, and the output end of the third delay unit and the high temperature signal are input to the input end of the fifth AND gate; The output ends of the third AND gate, the fourth AND gate and the fifth AND gate are connected to the input end of the first OR gate, and the first OR gate outputs a time-delay signal.
6. The delay control circuit according to claim 5, characterized in that: The first delay unit, the second delay unit and the third delay unit all use buffers, and different delay units use different numbers of buffers.
7. The delay control circuit according to claim 1, characterized in that: The timing generation module includes a fourth NOT gate and a sixth AND gate, the delay signal is connected to the input end of the fourth NOT gate, the output end of the fourth NOT gate and the target signal are both connected to the input end of the sixth AND gate, and the sixth AND gate outputs a pulse timing signal.
8. The delay control circuit according to claim 1, characterized in that: The delay control circuit also includes a temperature sensor for outputting the current temperature, and the temperature encoding module is arranged inside or outside the temperature sensor.
9. A delay control method, characterized in that: Applied to the delay control circuit as described in any one of claims 1 to 8 above, the method comprises: Encoding according to the current temperature, outputting an instant temperature signal, wherein the instant temperature signal includes category information divided according to the current temperature; receiving a first input signal and an instantaneous temperature signal, selecting a delay unit according to the instantaneous temperature signal, performing delay processing on the first input signal through the delay unit, and outputting a time-delay signal; The target signal is processed according to the time delay signal to output a pulse timing signal.
10. A semiconductor memory, characterized in that: The semiconductor memory comprises the delay control circuit as claimed in any one of claims 1 to 8.