SiC mosfet gate drive circuit with low shutdown losses

Abstract

The embodiment of the present disclosure relates to the technical field of electronic circuit, and provides a SiC MOSFET gate drive circuit with low turn-off loss, which comprises a digital microcontroller, a push-pull circuit, a control circuit and a charge processing circuit, the signal output end of the digital microcontroller is led out in parallel with two paths, one path is connected with the push-pull circuit, and the other path is connected with the control circuit and the charge processing circuit; the digital microcontroller selects high level and low level signals to output; the push-pull circuit provides turn-on bias voltage VCC and turn-off bias voltage VEE according to the high level and low level signal options; the control circuit provides auxiliary turn-off voltage Vneg when receiving the low level signal, so that the charge processing circuit extracts a certain amount of charge from the SiC MOSFET gate. The embodiment of the present disclosure uses the control circuit to provide negative voltage to the charge processing circuit to extract a certain amount of gate charge, quickly reduces the drain channel current, reduces the turn-off low heat loss, speeds up the turn-off speed, and improves the safety.

Description

Technical Field

[0001] This disclosure relates to the field of electronic circuit technology, and more specifically to a SiC MOSFET gate drive circuit with low turn-off loss. Background Technology

[0002] SiC MOSFETs are metal-oxide-semiconductor field-effect transistors made from silicon carbide (SiC), a third-generation semiconductor material. They have significant advantages such as high voltage resistance, high temperature resistance, high frequency, and low loss. Compared with IGBTs made of Si material, they have lower on-resistance and almost no tail current, higher switching frequency, and lower requirements for energy storage components. They help reduce the size of equipment and increase power density, which can drive the transformation of power electronic equipment towards high efficiency, lightweight, and high reliability.

[0003] For SiC MOSFETs, higher switching speeds mean lower switching losses, which requires the drive circuit to provide a sufficiently large gate drive current. Traditional gate drive circuits charge and discharge the SiC MOSFET gate by connecting an external gate resistor in series with the push-off circuit and the SiC MOSFET gate. The switching speed can be controlled by adjusting the external gate resistor, but this will increase switching losses or introduce additional voltage and current stress, which is detrimental to the reliable operation of the device.

[0004] Existing SiC MOSFET gate drive circuits incorporate additional control methods, such as sampling feedback circuits and logic circuits, or direct application of digital microcontrollers, to dynamically adjust the drive loop parameters during the switching transient waveform of the SiC MOSFET, thereby achieving better switching performance. For example, variable gate resistance circuits dynamically adjust the equivalent external gate resistance value of the drive loop, thereby changing the magnitude of the drive current in each stage of the switching transient and controlling the turn-on and turn-off speeds of the SiC MOSFET in stages; variable drive voltage circuits select different gate drive voltages in different switching stages to control the switching speed of the device in stages; current source drives control the drive current, typically using energy storage inductors to provide a relatively stable current to drive the switching device.

[0005] However, due to limitations in the current chip structure and gate material, SiC MOSFETs have a relatively high internal gate resistance (around 4Ω to 10Ω). Using voltage source drive circuits such as variable gate resistance type and variable drive voltage type may not provide a sufficiently large drive current, failing to fully utilize the high switching speed characteristics of SiC devices, or abruptly increasing the drive voltage may increase the risk of gate breakdown. Using current source drive circuits may result in excessively long charging and discharging current durations, leading to excessively high or low gate voltages, posing significant safety risks and making it impossible to guarantee that the device gate voltage remains within the safe voltage range. Summary of the Invention

[0006] The purpose of this disclosure is to provide a SiC MOSFET gate drive circuit with low turn-off loss, in order to solve the problems of slow turn-off speed, insufficient drive current, or low safety of SiC MOSFETs in related technologies.

[0007] To address the aforementioned technical problems, this disclosure provides a low-turn-off-loss SiC MOSFET gate drive circuit, which includes a digital microcontroller, a push-pull circuit, a control circuit, and a charge handling circuit.

[0008] The digital microcontroller's signal output terminal leads to a first branch and a second branch connected in parallel. The first branch includes the push-pull circuit, and the second branch includes the control circuit and charge processing circuit connected in series. The junction of the first branch and the second branch is connected to the gate of a SiC MOSFET.

[0009] The digital microcontroller selectively outputs high-level signals and low-level signals.

[0010] When the push-pull circuit receives a high-level signal, it provides a positive voltage to the gate of the SiC MOSFET as the turn-on bias voltage VCC. When the push-pull circuit receives a low-level signal, it provides a negative voltage to the gate of the SiC MOSFET as the turn-off bias voltage VEE.

[0011] The control circuit includes a logic processing unit and a voltage output terminal. The charge processing circuit includes a charge pumping unit and a first diode. The voltage output terminal of the control circuit is connected to the charge pumping unit and then connected in series with the cathode of the first diode. The anode of the first diode is connected to the gate of the SiC MOSFET. When the control circuit receives a low-level signal, it provides an auxiliary turn-off voltage Vneg to turn on the first diode and causes the charge pumping unit to draw a fixed amount of charge from the gate of the SiC MOSFET.

[0012] The auxiliary shutdown voltage Vneg is less than the shutdown bias voltage VEE.

[0013] In some embodiments, the charge pumping unit includes a first capacitor and a current mirror.

[0014] One end of the first capacitor is connected to the first pin of the voltage output terminal of the control circuit, the other end of the first capacitor is connected to the input side of the current mirror, the output side of the current mirror is connected to the cathode of the first diode, and the emitter of the current mirror is connected to the second pin of the voltage output terminal of the control circuit.

[0015] When the control circuit receives a low-level signal, a potential difference is formed between the first pin and the second pin, and the control unit outputs an auxiliary shutdown voltage Vneg.

[0016] In some embodiments, the current mirror includes a first transistor and a second transistor with their emitters connected, the collector and base of the first transistor being short-circuited, and the emitters of the first transistor and the second transistor being connected to a second pin of the voltage output terminal of the control circuit; or,

[0017] The first transistor and the second transistor are replaced with a MOS driver transistor and a MOS load transistor.

[0018] In some embodiments, a charge-regulating resistor is connected in series between the current mirror and the first capacitor.

[0019] In some embodiments, the charge pumping unit includes a switched capacitor integrator, a current sampling resistor, and a first switching transistor.

[0020] One end of the switched capacitor integrator is connected to the first pin of the voltage output terminal of the control circuit, and the other end of the switched capacitor integrator is connected to the cathode of the first diode, and the anode of the first diode is connected to the gate of the SiCMOSFET.

[0021] One end of the first switching transistor is connected to the second pin of the voltage output terminal of the control circuit, and the other end of the first switching transistor is connected in series with one end of the current sampling resistor. The other end of the current sampling resistor is connected to the cathode of the first diode. The third end of the first switching transistor is connected to the third pin of the control circuit. When the control circuit receives a low-level signal, a potential difference is formed between the third pin and the second pin, providing an auxiliary turn-off voltage Vneg to turn on the first switching transistor.

[0022] In some embodiments, the first switching transistor is selected from NMOS transistor, bipolar transistor, and field-effect transistor.

[0023] In some embodiments, the gate drive circuit further includes a variable gate resistor circuit, which is disposed between the voltage output terminal of the push-pull circuit and the gate of the SiC MOSFET.

[0024] The variable gate resistor circuit includes a gate turn-on resistor and a gate turn-off resistor connected in parallel. A second switching transistor for controlling the on / off state is provided in the branch where the gate turn-on resistor is located, and a third diode for controlling the on / off state is provided in the branch where the gate turn-off resistor is located.

[0025] In some embodiments, the cathode of the third diode is connected to the voltage output terminal of the push-pull circuit, the anode of the third diode is connected to one end of the gate turn-off resistor, the other end of the gate turn-off resistor is connected to the gate of the SiC MOSFET, and the third diode is turned off by reverse voltage when the control voltage outputs an auxiliary turn-off voltage Vneg.

[0026] In some embodiments, the second switching transistor is selected as a PMOS transistor or a bipolar transistor. The first end of the second switching transistor is connected to the voltage output terminal of the push-pull circuit, and the other end of the second switching transistor is connected to one end of the gate turn-on resistor. The other end of the gate turn-on resistor is connected to the gate of the SiC MOSFET. The second switching transistor is turned on when the push-pull circuit outputs a positive drive voltage VCC and turned off when the push-pull circuit outputs a negative drive voltage VEE.

[0027] In some embodiments, the resistance value of the gate turn-on resistor Rgon is greater than that of the gate turn-off resistor Rgoff.

[0028] This embodiment of the invention utilizes the gate charge characteristic curve of SiC MOSFETs to control the gate charge through a driving circuit. By extracting the gate charge when the SiC MOSFET is turned off, the internal gate-source voltage is controlled, thereby reducing the internal gate-source voltage and rapidly decreasing the drain-channel current, thus reducing the switching losses of the SiC MOSFET. By applying an auxiliary turn-off voltage Vneg that is lower than the conventional negative turn-off voltage VEE, a higher gate turn-off current is achieved, resulting in a faster SiC MOSFET turn-off speed and further reducing the switching losses. An automatic switching of the turn-off drive voltage from Vneg to VEE is achieved using a diode-equipped gate charge processing circuit, ensuring safe and reliable operation. Overall, by increasing the turn-off drive current to accelerate the decrease in the internal gate-source voltage of the MOSFET, the charging and discharging characteristics of the parasitic capacitance Coss are fully utilized, reducing the total switching losses of the SiC MOSFET and improving safety. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of the overall structure of a low turn-off loss SiC MOSFET gate drive circuit according to an embodiment of the present disclosure.

[0031] Figure 2 This is a schematic diagram of the structure of a low turn-off loss SiC MOSFET gate drive circuit according to an embodiment of the present disclosure.

[0032] Figure 3 This is a schematic diagram of the operating waveforms of a low turn-off loss SiC MOSFET gate drive circuit according to an embodiment of the present disclosure.

[0033] Figure 4 This is a schematic diagram of the channel current and drain current of a SiC MOSFET.

[0034] Figure 5 This is a schematic diagram of the gate charge characteristic curve of a SiC MOSFET.

[0035] Figure 6 This is a schematic diagram of a low-turn-off-loss SiC MOSFET gate drive circuit, which is another embodiment of the present disclosure. Detailed Implementation

[0036] Various embodiments and features of this disclosure are described herein with reference to the accompanying drawings.

[0037] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this disclosure will be apparent to those skilled in the art.

[0038] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present disclosure and, together with the general description of the disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the disclosure.

[0039] These and other features of this disclosure will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.

[0040] It should also be understood that although this disclosure has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this disclosure, which have the features described in the claims and are therefore all within the scope of protection defined herein.

[0041] The above and other aspects, features and advantages of this disclosure will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.

[0042] Specific embodiments of this disclosure are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this disclosure, which may be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure this disclosure. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely to serve as the basis and representative basis for the claims to teach those skilled in the art to use this disclosure in a variety of substantially any suitable detailed structures.

[0043] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in still another embodiment,” all of which may refer to one or more of the same or different embodiments according to this disclosure.

[0044] It is worth noting in advance that research shows that SiC MOSFETs have parasitic capacitance, which is the equivalent capacitance caused by their own structure. This equivalent capacitance should not be considered as the actual capacitor structure. The following parasitic capacitances are mentioned in this specification and the accompanying drawings: gate-source capacitance Cgs, gate-drain capacitance Cgd, and drain-source capacitance Cds. These can be further divided into input capacitance Ciss (equal to the sum of gate-source capacitance Cgs and drain-source capacitance Cds), output capacitance Coss (equal to the sum of gate-drain capacitance Cgd and drain-source capacitance Cds), and reverse transmission capacitance Crss (equal to gate-drain capacitance Cgd).

[0045] Example 1

[0046] See Figure 1 , Figure 2 This disclosure provides a low turn-off loss SiC MOSFET gate drive circuit (hereinafter referred to as "gate drive circuit"), wherein the source of SiC MOSFET 10 is grounded and the gate G is provided with the gate drive circuit.

[0047] The gate drive circuit includes: a digital microcontroller for outputting PWM level signals, a push-pull circuit 20, a control circuit 1, and a charge processing circuit 2. The signal output terminal of the digital microcontroller has a first branch and a second branch connected in parallel. The first branch is connected to the push-pull circuit 20, and the second branch is connected to the control circuit 1 and the charge processing circuit 2. The junction of the two branches is connected to the gate of the SiCMOSFET 10.

[0048] The push-pull circuit 20 has a signal input terminal and a voltage output terminal. The signal input terminal is connected to a digital microcontroller to receive PWM level signals, and the voltage output terminal is connected to the gate of a SiC MOSFET. It amplifies the drive current according to the PWM level signal and provides a turn-on bias voltage VCC to the SiC MOSFET gate when the PWM level signal is high, and a turn-off bias voltage VEE to the SiC MOSFET gate when the PWM level signal is low. Specifically, the push-pull circuit 20 can be a transistor push-pull circuit or a MOSFET push-pull circuit, or it can be replaced by a MOSFET half-bridge circuit. Different output levels and power amplification capabilities are achieved by alternately turning on the upper and lower MOSFETs of the half-bridge using complementary drive signals.

[0049] Control circuit 1 has a signal input terminal and a voltage output terminal. The signal input terminal is connected to a digital microcontroller to receive PWM level signals, and the voltage output terminal is connected to charge processing circuit 2. Control circuit 1 includes logic processing elements such as a DSP processor or FPGA processor, which can perform logic processing on the PWM level signals input from the signal input terminal. When the received PWM level signal is low, it provides a negative voltage for a certain period of time to charge processing circuit 2 as an auxiliary turn-off voltage Vneg. The following will describe the charge processing circuit 2 in conjunction with the above.

[0050] The charge processing circuit 2 includes a charge extraction unit and a first diode D1, which can extract a fixed amount of charge from the gate of the SiC MOSFET when the control circuit 1 provides an auxiliary turn-off voltage Vneg.

[0051] In this embodiment, the charge pumping unit includes a first capacitor Cq and a current mirror.

[0052] Specifically, one end of the first capacitor Cq is connected to the first pin of the voltage output terminal of the control circuit 1, the other end of the first capacitor Cq is connected to the input side (Q1 side) of the current mirror, the output side (Q2 side) of the current mirror is connected to the cathode of the first diode D1, and the anode of the first diode D1 is connected to the gate of the SiC MOSFET.

[0053] The current mirror includes a paired first transistor Q1 and a second transistor Q2. The collector and base of the first transistor Q1 are short-circuited. The emitters of the first transistor Q1 and the second transistor Q2 in the current mirror are connected to the second pin of the voltage output terminal of the control circuit 1. During a period when the PWM level signal is low, there is a potential difference between the first pin and the second pin of the voltage output terminal of the control circuit 1, which can apply a negative voltage for a certain period of time to the first capacitor Cq and the input side of the current mirror as an auxiliary turn-off voltage Vneg.

[0054] In one specific embodiment, the first transistor Q1 and the second transistor Q2 in the current mirror are bipolar transistors. A charge adjustment resistor Rq is connected in series between the first capacitor Cq and the control circuit to limit the current magnitude, thereby achieving quantitative charge extraction. In other specific embodiments, the current mirror can be a MOSFET current mirror or other current amplification circuits. Any circuit that can track or amplify the charging and discharging current of capacitor Cq can be used for quantitative gate charge extraction.

[0055] Figure 3 The diagram illustrates the operating waveforms of the SiC MOSFET gate drive circuit according to an embodiment of this disclosure. Specifically, it shows the timing diagrams of the PWM level signal, the SiC MOSFET gate drive voltage Vdr, the external gate-source voltage Vgs(ext) of the SiC MOSFET, the internal gate-source voltage Vgs(int) of the SiC MOSFET, the drain voltage Vds of the SiC MOSFET, the drain channel current ich of the SiC MOSFET, and the drain current id of the SiC MOSFET. Figure 3 As shown:

[0056] like Figure 3 As shown, t0 to t4 represent the turn-on process of the SiC MOSFET:

[0057] At time t0, the PWM level signal changes from low level to high level, and the push-pull circuit outputs a positive drive voltage VCC. At this time, the gate drive voltage Vdr is the positive drive voltage VCC.

[0058] During the time period t0 to t1, the gate drive voltage Vdr begins to charge the gate capacitance Cgs, and the external gate-source voltage Vgs(ext) and internal gate-source voltage Vgs(int) of the SiC MOSFET begin to rise.

[0059] At time t1, the internal gate-source voltage Vgs(int) reaches the threshold.

[0060] During the time period t1 to t2, the drain current id of the SiC MOSFET begins to rise, the drain voltage Vds begins to fall, and the SiC MOSFET begins to turn on and enters the saturation region.

[0061] At time t2, the internal gate-source voltage vgs(int) reaches the threshold, and the drain current id approaches the threshold.

[0062] During the time period t2 to t3, due to the Miller plateau effect, the internal gate-source voltage vgs(int) remains unchanged at the Miller plateau Vmiller, while the drain voltage Vds decreases to charge the gate-drain capacitance Cgd.

[0063] At time t3, the drain voltage Vds drops to 0, the gate-drain capacitance Cgd is fully charged, and the drain current id reaches the load current value IL.

[0064] During the time period t3 to t4, the internal gate-source voltage Vgs(int) continues to rise;

[0065] At time t4, the internal gate-source voltage Vgs(int) reaches the threshold, after which the SiC MOSFET is fully turned on.

[0066] like Figure 3 As shown, t5 to t8 represent the turn-off process of the SiC MOSFET:

[0067] At time t5, the PWM level signal changes from high level to low level. At this time, the push-pull circuit 20 provides the turn-off bias voltage VEE to the gate of the SiC MOSFET, and the control circuit 1 provides a negative voltage lower than the turn-off bias voltage VEE to the charge processing circuit 2 as an auxiliary turn-off voltage Vneg. At this time, the gate drive voltage Vdr drops to the auxiliary turn-off voltage Vneg.

[0068] During the time period t5 to t6, under the action of the auxiliary turn-off voltage Vneg, the first capacitor Cq is charged. The current mirror draws an equal amount of charge from the gate of the SiCMOSFET to form a mirror current, which causes the external gate-source voltage Vgs(ext) of the SiCMOSFET to drop to a negative value until the auxiliary turn-off voltage Vneg, which in turn causes the internal gate-source voltage Vgs(int) to drop rapidly, and the drain channel current ich to drop rapidly.

[0069] At time t6, the voltage supplied by control circuit 1 to charge processing circuit 2 becomes 0V, the first diode D1 turns off, the current mirror stops working, and the gate drive voltage Vdr of SiC MOSFET becomes the turn-off bias voltage VEE provided by push-pull circuit 20. At this time, the drain channel current ich has dropped to almost zero.

[0070] During the time period t6 to t7, the gate drive voltage Vdr of the SiC MOSFET remains at the turn-off bias voltage VEE, the external gate-source voltage Vgs(ext) is still negative, the internal gate-source voltage Vgs(int) continues to decrease, the gate-drain capacitance Cgd discharges, the drain voltage Vds increases, and the drain current id decreases.

[0071] At time t7, the drain voltage Vds reaches the threshold, and the drain current id drops to almost zero.

[0072] During the time interval t7 to t8, the external gate-source voltage Vgs(ext) and internal gate-source voltage Vgs(int) of the SiC MOSFET gradually decrease to synchronization. When they reach steady state, they are equal to the turn-off bias voltage VEE, and the SiC MOSFET is completely turned off.

[0073] In this embodiment, the control circuit 1 provides a negative voltage to the charge processing circuit 2 to extract a certain amount of gate charge, thereby rapidly reducing the drain channel current ich(i) before the drain voltage Vds rises. Figure 3 During the t5-t6 time period, extremely low heat loss during the turn-off process can be achieved, accelerating the turn-off speed of SiC MOSFETs. To facilitate understanding of these beneficial effects, the following section combines... Figure 4 , Figure 5 A brief explanation of the relevant research:

[0074] See Figure 4 The drain current id of a SiC MOSFET is the sum of the drain channel current ich and the charging / discharging current ioss of the output capacitor Coss. The drain channel current ich is generated due to the asynchronous changes in the external gate-source voltage Vgs(ext) and the internal gate-source voltage Vgs(int) of the SiC MOSFET, and the current is the actual current that causes heat loss. Reducing the drain channel current ich can reduce the switching losses of the SiC MOSFET.

[0075] See Figure 5 The provided characteristic curve of SiC MOSFET gate charge characterizes the relationship between the total charge injected / extracted by the drive circuit to the device gate and the actual gate-source voltage Vgs inside the device. Specifically, for MOSFET devices, when the operating voltage remains constant while the load current iL changes, the Miller plateau voltage of the charge characteristic curve changes; the larger the load current, the higher the Miller plateau voltage, but the total gate charge required for full turn-on remains unchanged. When the operating voltage changes while the load current iL remains constant, the Miller plateau of the charge characteristic curve does not change, but the total gate charge increases. The gate charge Qg of SiC MOSFET satisfies the following formula (where Rds_on is the MOSFET on-resistance, gm is the device transconductance, and since Rds_on is generally in the milliohm range, its influence on the gate charge characteristics can be ignored):

[0076] Q g =(V dc +VCC-VEE-I L ·R ds_on C gd +(VCC-VEE)C gs

[0077] V miller =I L / g m

[0078] In other words, under the premise that the operating voltage provided to the device is stable, even if the load current conditions are different, the amount of SiC MOSFET gate charge Qg required for the device to turn on and off is fixed. That is to say, as long as the amount of SiC MOSFET gate charge Qg is controlled, the magnitude of the internal gate-source voltage Vgs(int) can be controlled.

[0079] Therefore, during the SiC MOSFET turn-off process, when the PWM level signal changes from high to low, the control circuit 1 provides voltage to the first capacitor Cq in the charge processing circuit 2 to charge it. This allows the current mirror in the charge processing circuit 2 to quickly extract the gate charge of the SiC MOSFET, thereby reducing the internal gate-source voltage Vgs(int) and thus rapidly reducing the drain channel current ich, thereby reducing the switching losses of the SiC MOSFET.

[0080] Meanwhile, due to the influence of the internal gate resistance Rg(in) of the SiC MOSFET, see [reference needed]. Figure 3 During the turn-on process of a SiC MOSFET, the change in its internal gate-source voltage Vgs(int) lags behind the change in its external gate voltage Vgs(ext). Therefore, during the turn-off process, a higher drive voltage (i.e., the auxiliary turn-off voltage Vneg) is applied for a short period of time, and then switched back to a safer low drive voltage (i.e., the turn-off bias voltage VEE) before the internal gate-source voltage exceeds the safe range. This not only achieves a faster turn-off speed but also ensures turn-off safety, thus significantly improving the turn-off performance of the SiC MOSFET.

[0081] As long as the amount of gate charge extracted is controlled within a safe range, regardless of the driving voltage and driving current used during the gate charge extraction process, the internal gate-source voltage of the SiC MOSFET will not exceed the safe range, causing gate breakdown damage, thus providing higher safety.

[0082] like Figure 1 , Figure 2 As shown, preferably, the gate drive circuit of this embodiment further includes a variable gate resistor circuit 30. The variable gate resistor circuit 30 is connected in series between the voltage output terminal of the push-pull circuit and the gate G of the SiC MOSFET, and is used to adjust the external gate resistance value according to the operating characteristics of the SiC MOSFET, thereby adjusting the push-pull current when the SiC MOSFET is turned on and off.

[0083] The variable gate resistor circuit 30 includes a gate turn-on resistor Rgon and a gate turn-off resistor Rgoff connected in parallel. A second switch S2 for controlling the on and off states is provided in the branch where the gate turn-on resistor Rgon is located, and a third diode D3 for controlling the on and off states is provided in the branch where the gate turn-off resistor Rgoff is located.

[0084] Specifically, such as Figure 2 As shown, there are two paths leading out from the voltage output terminal of the push-pull circuit. One path is connected in series with the second switch S2 and the gate turn-on resistor Rgon, and the other path is connected in series with the third diode D3 and the gate turn-off resistor Rgoff. The junction of the variable gate resistor circuit 30 is connected to the gate of the SiC MOSFET.

[0085] Furthermore, the second switch S2 is a PMOS transistor with its gate grounded. The source of the second switch S2 is connected to the voltage output terminal of the push-pull circuit 20, and the drain of the second switch S2 is connected to the gate turn-on resistor Rgon. The second switch S2 can be turned on when the PWM level signal is high and the push-pull circuit outputs a positive drive voltage VCC, and turned off when the PWM level signal is low and the push-pull circuit outputs a negative drive voltage VEE.

[0086] The cathode of the third diode D3 is connected to the voltage output terminal of the push-pull circuit 20, and the anode of the third diode D3 is connected to one end of the gate turn-off resistor Rgoff. The other end of the gate turn-off resistor Rgoff is connected to the gate of the SiC MOSFET.

[0087] Furthermore, the gate turn-on resistor Rgon is greater than the gate turn-off resistor Rgoff. Setting a larger gate turn-on resistor Rgon can protect the gate of the SiC MOSFET and prevent turn-on oscillation, overcurrent, and overvoltage phenomena. Setting a smaller gate turn-off resistor Rgoff can maximize the turn-off speed of the SiC MOSFET, thereby reducing turn-off losses.

[0088] See Figure 3 During the switching process of the SiC MOSFET in this preferred embodiment:

[0089] During the time period t0 to t4, the PWM level signal is high, and the push-pull circuit 20 provides positive voltage (turn-on bias voltage VCC), which turns on the second switch S2 and turns off the third diode D3. The push-pull current flows from the gate turn-on resistor Rgon to charge the gate capacitor Cgs until the SiC MOSFET turns on.

[0090] During the time period t5 to t6, the push-pull circuit 20 provides a turn-off bias voltage VEE. The control circuit 1 provides a voltage that is more negative than the turn-off bias voltage VEE (auxiliary turn-off voltage Vneg), which turns off the second switch S2 and causes D1 to be turned off under reverse voltage. The gate charge of the SiC MOSFET is extracted by the charge processing circuit 2, and no current flows through the gate turn-on resistor Rgon and the gate turn-off resistor Rgoff.

[0091] During the time period t6 to t8, the push-pull circuit 20 provides a negative voltage (turn-off bias voltage VEE), and the control circuit 1 no longer provides voltage, causing the second switch S2 to turn off and D1 to turn on, with current flowing through the gate turn-off resistor Rgoff.

[0092] This embodiment not only allows for adjusting the external gate resistance of the SiC MOSFET according to its characteristics, resulting in higher switching performance, but also, when the control circuit 1 provides the auxiliary turn-off voltage Vneg (during the time period t5 to t6), the third diode D3 can temporarily isolate the gate turn-off resistor Rgoff, preventing the auxiliary turn-off voltage Vneg from affecting the circuit. This further ensures that the internal gate voltage Vgs(int) of the SiC MOSFET is always within a safe range, improving the turn-off safety of the SiC MOSFET.

[0093] This invention utilizes the correspondence between the gate-source voltage and gate charge inside the MOSFET. Under the premise of ensuring safety through gate charge control, the driving circuit of this invention adopts an auxiliary turn-off voltage Vneg that is lower than the conventional negative turn-off voltage VEE, which can provide a larger driving current, have stronger driving capability, and achieve higher turn-off speed and lower switching loss.

[0094] In summary, this embodiment of the present disclosure, based on the gate charge characteristic curve of SiC MOSFET, controls the gate charge through a driving circuit, extracts the gate charge when the SiC MOSFET is turned off, thereby controlling the internal gate-source voltage, reducing the internal gate-source voltage Vgs(int), rapidly reducing the magnitude of the drain-channel current ich, and thus reducing the switching losses of the SiC MOSFET. By applying an auxiliary turn-off voltage Vneg that is lower than the conventional negative turn-off voltage VEE, a higher gate turn-off current is achieved, resulting in a faster turn-off speed for the SiC MOSFET, further reducing the switching losses of the SiC MOSFET. The automatic switching of the turn-off drive voltage from Vneg to VEE is achieved using a diode-equipped gate charge processing circuit, ensuring safe and reliable operation. Overall, by increasing the turn-off drive current to accelerate the decrease rate of the internal gate-source voltage of the MOSFET, the charging and discharging characteristics of the parasitic capacitance Coss are fully utilized, reducing the total switching losses of the SiC MOSFET and improving safety.

[0095] Example 2

[0096] like Figure 6 As shown, the gate drive circuit of this embodiment includes the same digital microcontroller for outputting PWM level signals and push-pull circuit 20 and variable gate resistor circuit 30 as in Embodiment 1, and also includes another control circuit 1a and charge processing circuit 2a with a different structure from Embodiment 1.

[0097] In the charge processing circuit 2a, the charge pumping unit includes a switched capacitor integrator 201, a current sampling resistor Rsense, and a first switching transistor S1.

[0098] Specifically, one end of the switched capacitor integrator 201 is connected to the first pin of the voltage output terminal of the control circuit 1a, and the other end of the switched capacitor integrator 201 is connected to the cathode of the first diode D1a. The anode of the first diode D1a is connected to the gate of the SiC MOSFET. The switched capacitor integrator 201 is a common circuit structure that contains a switch and a capacitor, and can charge and discharge according to the signal sent by the control circuit 1a.

[0099] In this embodiment, the first switching transistor S1 is an NMOS transistor. The gate of the first switching transistor S1 is connected to the second pin of the voltage output terminal of the control circuit 1a. One end of the current sampling resistor Rsense is connected in series with the drain of the first switching transistor S1, and the other end of the current sampling resistor Rsense is connected to the cathode of the first diode D1a. The resistance value of the current sampling resistor Rsense is very small and can be ignored. It is used to sample the current in its path, so that the control circuit 1a can control the switched capacitor integrator 201 to draw a certain amount of charge from the gate of the SiC MOSFET according to the sampled value.

[0100] The source of the first switching transistor S1 is connected to the third pin of the output terminal of the control circuit 1a, and the gate of the first switching transistor S1 is connected to the second pin of the voltage output terminal of the control circuit 1a. When the control circuit 1a receives a low-level PWM signal, a potential difference is formed between the third pin and the second pin to provide a negative voltage as an auxiliary turn-off voltage Vneg, thus turning on the first switching transistor S1. In other specific embodiments, the switching transistor S2 can also be a transistor or other types of field-effect transistors.

[0101] During the period when the PWM level signal is low, there is a potential difference between the second and third pins of the voltage output terminal of the control circuit 1a, which can apply a negative voltage between the gate and source of the first switching transistor S1 for a certain period of time to make it conduct; when the first switching transistor S1 is conducting, the switched capacitor integrator 201 is connected in parallel with the current sampling resistor Rsense, so the switched capacitor integrator 201 can extract a certain amount of charge according to the sampling value of the current sampling resistor Rsense.

[0102] The operating waveform of the SiC MOSFET gate drive circuit in this embodiment is the same as that in Embodiment 1, and can also be used. Figure 3 Indicates. For example... Figure 3 As shown, t5 to t8 represent the turn-off process of the SiC MOSFET:

[0103] At time t5, the PWM signal changes from high to low. At this time, the push-pull circuit 20 provides a turn-off bias voltage VEE to the gate of the SiC MOSFET. Simultaneously, the control circuit 1a provides a negative voltage lower than the turn-off bias voltage VEE to the charge processing circuit 2a as an auxiliary turn-off voltage Vneg, turning on the first diode D1a and the first switch S1. Current begins to flow through the current sampling resistor Rsense, and the control circuit 1a turns on the switched capacitor integrator 201. At this time, because the auxiliary turn-off voltage Vneg < the turn-off bias voltage VEE, the gate drive voltage Vdr drops to the auxiliary turn-off voltage Vneg.

[0104] During the time period t5 to t6, the switched capacitor integrator 201 calculates the amount of charge extracted, causing the external gate-source voltage Vgs(ext) of the SiC MOSFET to drop to a negative value until the auxiliary turn-off voltage Vneg, which in turn causes the internal gate-source voltage Vgs(int) to drop rapidly, and the drain channel current ich to drop rapidly.

[0105] At time t6, the switched capacitor integrator 201 reaches the expected charge amount, the control circuit 1a turns off the switched capacitor integrator 201 and no longer provides the auxiliary turn-off voltage Vneg, the first diode D1a and the first switch S1 turn off, and the SiC MOSFET gate drive voltage Vdr becomes the turn-off bias voltage VEE provided by the push-pull circuit 20. At this time, the drain channel current ich has dropped to almost zero.

[0106] This embodiment uses a different circuit structure than Embodiment 1, but achieves the same beneficial effects, and will not be described in detail here.

[0107] Furthermore, any circuit scheme that can monitor and control the amount of charge can be applied to the gate drive circuit to achieve the same function as the gate charge control type SiC MOSFET drive technology proposed in this invention.

[0108] In the description of this disclosure, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is generally based on the orientation or positional relationship shown in the accompanying drawings and is only for the convenience of describing this disclosure and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this disclosure; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0109] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0110] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore should not be construed as limiting the scope of protection of this disclosure.

[0111] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

[0112] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0113] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0114] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

[0115] The foregoing has provided a detailed description of several embodiments of this disclosure. However, this disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications based on the concept of this disclosure, and all such variations and modifications should fall within the scope of protection claimed by this disclosure.

Claims

1. A low turn-off loss SiC MOSFET gate drive circuit, characterized in that, The gate drive circuit includes a digital microcontroller, a push-pull circuit, a control circuit, and a charge processing circuit. The digital microcontroller outputs a first branch and a second branch connected in parallel. The first branch includes the push-pull circuit, and the second branch includes the control circuit and the charge processing circuit connected in series. The junction of the first branch and the second branch is connected to the gate of the SiC MOSFET. The digital microcontroller selectively outputs high-level signals and low-level signals; When the push-pull circuit receives a high-level signal, it provides a positive voltage to the gate of the SiC MOSFET as the turn-on bias voltage VCC. When the push-pull circuit receives a low-level signal, it provides a negative voltage to the gate of the SiC MOSFET as the turn-off bias voltage VEE. The control circuit includes a logic processing unit and a voltage output terminal. The charge processing circuit includes a charge extraction unit and a first diode. The voltage output terminal of the control circuit is connected to the charge extraction unit and then connected in series with the cathode of the first diode. The anode of the first diode is connected to the gate of the SiC MOSFET. When the control circuit receives a low-level signal, it provides an auxiliary turn-off voltage Vneg to turn on the first diode and causes the charge extraction unit to extract a certain amount of charge from the gate of the SiC MOSFET. The auxiliary shutdown voltage Vneg is less than the shutdown bias voltage VEE.

2. The low turn-off loss SiC MOSFET gate drive circuit according to claim 1, characterized in that, The charge pumping unit includes a first capacitor and a current mirror; One end of the first capacitor is connected to the first pin of the voltage output terminal of the control circuit, the other end of the first capacitor is connected to the input side of the current mirror, the output side of the current mirror is connected to the cathode of the first diode, and the emitter of the current mirror is connected to the second pin of the voltage output terminal of the control circuit. When the control circuit receives a low-level signal, a potential difference is formed between the first pin and the second pin, and an auxiliary shutdown voltage Vneg is output.

3. The low turn-off loss SiC MOSFET gate drive circuit according to claim 2, characterized in that, The current mirror includes a first transistor and a second transistor with their emitters connected. The collector and base of the first transistor are short-circuited. The emitters of the first and second transistors are connected to the second pin of the voltage output terminal of the control circuit; or, The first transistor and the second transistor are replaced with a MOS driver transistor and a MOS load transistor.

4. The low turn-off loss SiC MOSFET gate drive circuit according to claim 2, characterized in that, A charge adjustment resistor is connected in series between the current mirror and the first capacitor.

5. The low turn-off loss SiC MOSFET gate drive circuit according to claim 1, characterized in that, The charge pumping unit includes a switched capacitor integrator, a current sampling resistor, and a first switching transistor. One end of the switched capacitor integrator is connected to the first pin of the voltage output terminal of the control circuit, and the other end of the switched capacitor integrator is connected to the cathode of the first diode, and the anode of the first diode is connected to the gate of the SiCMOSFET. One end of the first switching transistor is connected to the second pin of the voltage output terminal of the control circuit, and the other end of the first switching transistor is connected in series with one end of the current sampling resistor. The other end of the current sampling resistor is connected to the cathode of the first diode. The third end of the first switching transistor is connected to the third pin of the control circuit. When the control circuit receives a low-level signal, a potential difference is formed between the third pin and the second pin, providing an auxiliary turn-off voltage Vneg to turn on the first switching transistor.

6. The low turn-off loss SiC MOSFET gate drive circuit according to claim 5, characterized in that, The first switching transistor is selected from one of NMOS transistor, bipolar transistor, and field-effect transistor.

7. The low turn-off loss SiC MOSFET gate drive circuit according to any one of claims 5 and 6, characterized in that, The gate drive circuit further includes a variable gate resistor circuit, which is disposed between the voltage output terminal of the push-pull circuit and the gate of the SiC MOSFET. The variable gate resistor circuit includes a gate turn-on resistor and a gate turn-off resistor connected in parallel. A second switching transistor for controlling the on / off state is provided in the branch where the gate turn-on resistor is located, and a third diode for controlling the on / off state is provided in the branch where the gate turn-off resistor is located.

8. The low turn-off loss SiC MOSFET gate drive circuit according to claim 7, characterized in that, The cathode of the third diode is connected to the voltage output terminal of the push-pull circuit, the anode of the third diode is connected to one end of the gate turn-off resistor, the other end of the gate turn-off resistor is connected to the gate of the SiC MOSFET, and the third diode is turned off by reverse voltage when the control circuit outputs the auxiliary turn-off voltage Vneg.

9. The low turn-off loss SiC MOSFET gate drive circuit according to claim 7, characterized in that, The second switching transistor is selected as a PMOS transistor or a bipolar transistor. The first end of the second switching transistor is connected to the voltage output terminal of the push-pull circuit, and the other end of the second switching transistor is connected to one end of the gate turn-on resistor. The other end of the gate turn-on resistor is connected to the gate of the SiC MOSFET. The second switching transistor is turned on when the push-pull circuit outputs a positive drive voltage VCC and is turned off when the push-pull circuit outputs a negative drive voltage VEE.

10. The low turn-off loss SiC MOSFET gate drive circuit according to claim 7, characterized in that, The resistance value of the gate turn-on resistor Rgon is greater than that of the gate turn-off resistor Rgoff.

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