Driving circuit, driving chip and electronic equipment
By designing a driving circuit including a negative feedback module and a current source, the problem that traditional driving circuits cannot achieve switching speed optimization under different load conditions is solved, and the consistency of wide-range switching speed control is achieved, and the system performance is improved.
Patent Information
- Application Number
- CN202411776054.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-03-28
AI Technical Summary
Traditional power tube driving circuits cannot optimize switching speeds under different load conditions, and cannot achieve consistent switching speed control over a wide load range.
A driving circuit including a negative feedback module, a first current source, a second current source, a first resistor, a second resistor, an NMOS transistor and a PMOS transistor are designed. The current on the first resistor is adjusted through the negative feedback module to achieve a stable output current efficient driving of the target transistor.
The consistency of wide-range switching speed control is achieved, the system performance is improved, and complex current detection and feedback circuits are not required, and the output pins are not required to be added or decreased, which has high compatibility.
Smart Images
Figure CN119727689A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a driving circuit, a driving chip, and an electronic device. Background Art
[0002] Traditional power tube drive circuits are mostly voltage-type outputs, which are combined with the gate resistance of MOSFET to adjust the turn-on and turn-off speeds to achieve optimization of switching loss, overshoot ringing, etc., and then optimize the efficiency, EMI and other characteristics of the system. However, under different application conditions, such as heavy load and light load, the use of voltage-type drive combined with gate resistance adjustment cannot achieve the optimization of switching speed at the same time, nor can it achieve the optimization of switching speed over a wide load range. Under different load current conditions, the overdrive voltage required by the power tube is different, the Miller platform voltage caused by the Miller effect is different, and the gate resistance value required to adjust to the same switching speed is also different.
[0003] In view of the above defects of the voltage-type power tube driving circuit, it is necessary to propose a new driving circuit to achieve consistency in wide range switching speed control and improve system performance. Summary of the invention
[0004] According to one aspect of the present disclosure, a driving circuit is provided, the circuit comprising: a negative feedback module, a first current source, a second current source, a first resistor, a second resistor, a zeroth NMOS transistor, a second NMOS transistor, a pull-down NMOS transistor and a third PMOS transistor, wherein:
[0005] The first end of the first current source, the first end of the second current source, the source of the third PMOS transistor, and the first end of the negative feedback module are used to receive a power supply voltage.
[0006] The second end of the first current source is connected to the first end of the second resistor and the second end of the negative feedback module.
[0007] The second end of the second current source is connected to the third end of the negative feedback module.
[0008] The drain of the third PMOS transistor is connected to the fourth terminal of the negative feedback module.
[0009] A common node between the fifth terminal of the negative feedback module and the first terminal of the first resistor is used to generate an output current, and the output current is used to drive the target transistor.
[0010] The second end of the second resistor is connected to the gate of the second NMOS transistor and the drain of the second NMOS transistor.
[0011] The source of the second NMOS transistor is connected to the second end of the first resistor and the drain of the pull-down NMOS transistor.
[0012] The sixth terminal of the negative feedback module is connected to the drain of the zeroth NMOS transistor.
[0013] The source of the pull-down NMOS transistor and the source of the zeroth NMOS transistor are grounded,
[0014] The negative feedback module is used to adjust the current on the first resistor.
[0015] In a possible implementation, the negative feedback module includes a current mirror, a pull-up NMOS transistor and a first NMOS transistor, wherein:
[0016] The drain of the pull-up NMOS transistor serves as the first terminal of the negative feedback module.
[0017] The gate of the first NMOS transistor serves as the second terminal of the negative feedback module.
[0018] The drain of the first NMOS transistor and the connection point of the current mirror serve as the third terminal of the negative feedback module.
[0019] The connection point between the source of the first NMOS transistor and the source of the pull-up NMOS transistor serves as the fifth terminal of the negative feedback module.
[0020] The power supply terminal of the current mirror serves as the fourth terminal of the negative feedback module.
[0021] The connection point of the current output terminal of the current mirror and the gate of the pull-up NMOS transistor serves as the sixth terminal of the negative feedback module.
[0022] In a possible implementation, the current mirror includes a first PMOS transistor and a second PMOS transistor, wherein:
[0023] The source of the first PMOS transistor and the source of the second PMOS transistor are connected to serve as a power supply terminal of the current mirror.
[0024] The gate of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the second PMOS transistor are connected to the drain of the first NMOS transistor,
[0025] The source of the first PMOS transistor serves as a current output terminal of the current mirror.
[0026] In a possible implementation manner, the currents of the first current source and the second current source are equal in magnitude.
[0027] In a possible implementation manner, the output current is:
[0028] IOUT=Ib*R2 / R1, wherein IOUT represents the output current, Ib represents the current of the first current source or the second current source, R2 represents the resistance of the second resistor, and R1 represents the resistance of the first resistor.
[0029] In a possible implementation manner, the first resistor or the second resistor is an adjustable resistor.
[0030] According to one aspect of the present disclosure, a driving chip is provided, wherein the chip includes the driving circuit.
[0031] According to one aspect of the present disclosure, an electronic device is provided. The electronic device includes the driving chip and a display panel.
[0032] In a possible implementation, the display panel includes any one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel and a micro light emitting diode display panel.
[0033] In a possible implementation, the electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.
[0034] The driving circuit proposed in the embodiment of the present disclosure realizes current-type driving through the above circuit structure, can generate a stable output current to efficiently drive the target transistor, can achieve consistency in a wide range of switching speed control, has high precision and fast response speed, can improve system performance, and does not require complex current detection and feedback circuits, and the output pins do not need to be increased or decreased, and has high compatibility.
[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only and do not limit the present disclosure. Other features and aspects of the present disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] The drawings herein are incorporated into the specification and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and are used to illustrate the technical solutions of the present disclosure together with the specification.
[0037] Figure 1 A schematic diagram of a driving circuit according to an embodiment of the present disclosure is shown.
[0038] Figure 2A schematic diagram showing a possible implementation of a driving circuit according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0039] Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise specified.
[0040] In the description of the present disclosure, it should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.
[0041] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.
[0042] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.
[0043] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
[0044] The term "and / or" herein is only a description of the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the term "at least one" herein represents any combination of at least two of any one or more of a plurality of. For example, including at least one of A, B, and C can represent including any one or more elements selected from the set consisting of A, B, and C.
[0045] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following specific embodiments. It should be understood by those skilled in the art that the present disclosure can also be implemented without certain specific details. In some examples, methods, means, components and circuits well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present disclosure.
[0046] See also Figure 1 , Figure 1 A schematic diagram of a driving circuit according to an embodiment of the present disclosure is shown.
[0047] For example, Figure 1 As shown, the circuit includes: a negative feedback module 10, a first current source Ib1, a second current source Ib2, a first resistor R1, a second resistor R2, a zeroth NMOS transistor NM0, a second NMOS transistor NM2, a pull-down NMOS transistor NMdn and a third PMOS transistor PM3, wherein,
[0048] The first end of the first current source Ib1, the first end of the second current source Ib2, the source of the third PMOS transistor PM3, and the first end Nod1 of the negative feedback module 10 are used to receive the power supply voltage VCC.
[0049] The second end of the first current source Ib1 is connected to the first end of the second resistor R2 and the second end Nod2 of the negative feedback module 10.
[0050] The second end of the second current source Ib2 is connected to the third end Nod3 of the negative feedback module 10.
[0051] The drain of the third PMOS transistor PM3 is connected to the fourth terminal Nod4 of the negative feedback module 10.
[0052] A common node of the fifth terminal Nod5 of the negative feedback module 10 and the first terminal of the first resistor R1 is used to generate an output current IOUT, and the output current IOUT is used to drive the target transistor.
[0053] The second end of the second resistor R2 is connected to the gate of the second NMOS transistor NM2 and the drain of the second NMOS transistor NM2.
[0054] The source of the second NMOS transistor NM2 is connected to the second end of the first resistor R1 and the drain of the pull-down NMOS transistor NMdn.
[0055] The sixth terminal Nod6 of the negative feedback module 10 is connected to the drain of the zeroth NMOS transistor NM0.
[0056] The source of the pull-down NMOS transistor NMdn and the source of the zeroth NMOS transistor NM0 are grounded,
[0057] The negative feedback module 10 is used to adjust the current on the first resistor R1.
[0058] The driving circuit proposed in the embodiment of the present disclosure realizes current-type driving through the above circuit structure, can generate a stable output current IOUT to efficiently drive the target transistor, can achieve consistency in a wide range of switching speed control, has high precision and fast response speed, can improve system performance, and does not require complex current detection and feedback circuits, and the output pins do not need to be increased or decreased, and has high compatibility.
[0059] The embodiment of the present disclosure does not limit the specific implementation of the negative feedback module 10, and those skilled in the art can use relevant technologies to implement it according to actual conditions and needs, as long as the negative feedback mechanism can be used to adjust the current on the first resistor R1. The preferred implementation is exemplarily introduced below.
[0060] See also Figure 2 , Figure 2 A schematic diagram showing a possible implementation of a driving circuit according to an embodiment of the present disclosure is shown.
[0061] In a possible implementation, Figure 2 As shown, the negative feedback module 10 includes a current mirror, a pull-up NMOS transistor NMup and a first NMOS transistor NM1, wherein:
[0062] The drain of the pull-up NMOS transistor NMup serves as the first terminal Nod1 of the negative feedback module 10.
[0063] The gate of the first NMOS transistor NM1 serves as the second terminal Nod2 of the negative feedback module 10.
[0064] The drain of the first NMOS transistor NM1 and the connection point of the current mirror serve as the third terminal Nod3 of the negative feedback module 10.
[0065] The connection point between the source of the first NMOS transistor NM1 and the source of the pull-up NMOS transistor NMup serves as the fifth terminal Nod5 of the negative feedback module 10.
[0066] The power supply end of the current mirror serves as the fourth end Nod4 of the negative feedback module 10.
[0067] The connection point of the current output end of the current mirror and the gate of the pull-up NMOS transistor NMup serves as the sixth end Nod6 of the negative feedback module 10 .
[0068] The embodiments of the present disclosure do not limit the specific implementation of the current mirror, and those skilled in the art can configure it according to actual conditions and needs. For example, in a possible implementation, Figure 2 As shown, the current mirror may include a first PMOS transistor PM1 and a second PMOS transistor PM2, wherein:
[0069] The source of the first PMOS transistor PM1 and the source of the second PMOS transistor PM2 are connected to serve as the power supply terminal of the current mirror.
[0070] The gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, and the drain of the second PMOS transistor PM2 are connected to the drain of the first NMOS transistor NM1.
[0071] The source of the first PMOS transistor PM1 serves as a current output terminal of the current mirror.
[0072] The embodiments of the present disclosure do not limit the specific implementation method and size of the first current source Ib1 and the second current source Ib2. For example, in one possible implementation, the first current source Ib1 and the second current source Ib2 can both be constant current sources, and the current sizes of the first current source Ib1 and the second current source Ib2 are equal, for example, both are Ib.
[0073] In a possible implementation, the output current IOUT is: IOUT=Ib*R2 / R1, wherein IOUT represents the output current, Ib represents the current of the first current source Ib1 or the second current source Ib2, R2 represents the resistance of the second resistor R2, and R1 represents the resistance of the first resistor R1.
[0074] In a possible implementation manner, the first resistor R1 or the second resistor R2 is an adjustable resistor, so that the embodiment of the present disclosure can conveniently adjust the output current IOUT.
[0075] Below Figure 2 The driving circuit shown is taken as an example to illustrate its working principle.
[0076] For example, Figure 2 As shown, the first NMOS transistor NM1, the second PMOS transistor PM2, the first PMOS transistor PM1 and the pull-up NMOS transistor NMup form a negative feedback loop (i.e., a negative feedback module 10), and the current on the first resistor R1 is adjusted by negative feedback. The first current source Ib1 and the second current source Ib2 are constant current sources, and their bias currents are equal, both Ib, i.e., Ib1=Ib2=Ib, wherein Ib1 and Ib2 represent the currents of the first current source Ib1 and the second current source Ib2, respectively.
[0077] For example, Figure 2 As shown, when the current Ib1 of the first current source Ib1 flows through the second resistor R2 and the second NMOS transistor NM2, a voltage drop is generated, so that the gate voltage Vg_NM1 of the first NMOS transistor NM1 is Vg_NM1=V_R2+Vgs_NM2+Vout, wherein V_R2 represents the voltage drop on the second resistor R2, Vgs_NM2 represents the voltage difference between the gate and the source of the second NMOS transistor NM2, and Vout represents the voltage of the port OUT. Figure 2 In FIG. 8 , Nod8 represents a common connection point of the second NMOS transistor NM2 , the first resistor R1 , and the pull-down NMOS transistor NMdn, wherein the common connection point Nod8 is connected to the port OUT.
[0078] For example, Figure 2 As shown, for example, Figure 2 As shown, Vg_NM1 turns on the first NMOS transistor NM1, thereby turning on the second PMOS transistor PM2 and the first PMOS transistor PM1, so that the gate voltage of the pull-up NMOS transistor NMup is pulled high, and the pull-up NMOS transistor NMup conducts current.
[0079] For example, Figure 2 As shown, the current turned on by the pull-up NMOS transistor NMup will flow through the first resistor R1, so that the voltage drop generated on the first resistor R1 will raise the source voltage of the first NMOS transistor NM1, so that the current of the first NMOS transistor NM1 will gradually decrease, which will cause the current of the second PMOS transistor PM2 and the first PMOS transistor PM1 to gradually decrease, which will gradually reduce the gate voltage of the pull-up NMOS transistor NMup, thereby reducing the current of the pull-up NMOS transistor NMup.
[0080] For example, Figure 2As shown, when the stable state is reached, the on-current of the first NMOS transistor NM1 is the current of the current source Ib2 plus the current of the second PMOS transistor PM2, that is, Id_NM1=Ib2+Id_PM2, where Id_NM1 represents the current of the first NMOS transistor NM1, and Id_PM2 represents the current of the second PMOS transistor PM2.
[0081] For example, Figure 2 As shown, since the second PMOS transistor PM2 and the first PMOS transistor PM1 form a current mirror, if the size of the first PMOS transistor PM1 is K times (K is a positive number) that of the second PMOS transistor PM2, then the current of the first PMOS transistor PM1 is also K times that of the second PMOS transistor PM2, that is, Id_PM1=K*Id_PM2, where Id_PM1 represents the current of the first PMOS transistor PM1.
[0082] Thus, Id_NM1=Ib2+(1 / K)*Id_PM1. When K is much larger than 1, Id_NM1≈Ib2. Since the current of the second NMOS transistor NM2 is Id_NM2=Ib1=Ib2=Ib, Id_NM2≈Id_NM1. In this way, the gate-source voltage of the second NMOS transistor NM2 and the first NMOS transistor NM1 are nearly equal, that is, Vgs_NM2=Vgs_NM1.
[0083] According to Kirchhoff's voltage law, in the loop formed by the second NMOS transistor NM2, the second resistor R2, the first NMOS transistor NM1 and the first resistor R1, the following relationship exists: Vgs_NM2+V_R2=Vgs_NM1+V_R1; therefore, the following relationship is established: V_R2=V_R1, where V_R2 and V_R1 represent the voltage drops across the second resistor R2 and the first resistor R1, respectively.
[0084] In the actual driving circuit, the main component (>99%) of the current flowing through the first resistor R1 is the current of the pull-up NMOS transistor NMup, which is the pull-up current IOUT of the driver, so V_R1 = IOUT*R1; and V_R2 = Ib1*R2 = Ib*R2, thus obtaining: IOUT = Ib*R2 / R1. It can be seen that the driving circuit can generate a constant driving current.
[0085] The disclosed embodiment does not limit the adjustment method of the adjustable resistor, and does not limit the control method of the zeroth NMOS transistor NM0, the pull-down NMOS transistor NMdn, and the third PMOS transistor PM3. Those skilled in the art can set them according to actual conditions and needs.
[0086] Exemplarily, the driving circuit can be connected to a control module, and the control module can generate a resistance adjustment signal to adjust the resistance of the first resistor R1 or the second resistor R2. The control module can also generate a switch control signal to perform switch control on the zeroth NMOS transistor NM0, the pull-down NMOS transistor NMdn, and the third PMOS transistor PM3. Of course, the embodiments of the present disclosure do not limit the specific generation method of the resistance adjustment signal and the switch control signal, and those skilled in the art can set them according to actual conditions and needs.
[0087] Exemplarily, the control module can also generate a switch control signal, which acts on the third PMOS transistor PM3, the zeroth NMOS transistor NM0 and the pull-down NMOS transistor NMdn to achieve switch control of the third PMOS transistor PM3, the zeroth NMOS transistor NM0 and the pull-down NMOS transistor NMdn. For example, the switch control signal can be a PWM control signal. When the PWM control signal is at a high level, the third PMOS transistor PM3 is disconnected, and the zeroth NMOS transistor NM0 and the pull-down NMOS transistor NMdn are turned on; when the PWM control signal is at a low level, the third PMOS transistor PM3 is turned on, and the zeroth NMOS transistor NM0 and the pull-down NMOS transistor NMdn are disconnected. Of course, the embodiments of the present disclosure do not limit the specific generation method and form of the switch control signal, and those skilled in the art can set it according to actual conditions and needs.
[0088] The embodiments of the present disclosure do not limit the specific implementation of the control module. Those skilled in the art can set it according to actual conditions and needs. For example, the control module may include a processing component. In one example, the processing component includes but is not limited to a separate processor, or a discrete component, or a combination of a processor and a discrete component. The processor may include a controller having an execution instruction function in an electronic device. The processor may be implemented in any appropriate manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components. Inside the processor, the executable instructions may be executed by hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.
[0089] The advantages and effects of this application compared to the prior art are as follows:
[0090] The current source output power tube drive circuit can achieve consistency in wide-range switching speed control and improve system performance;
[0091] The current source output solution proposed in the present invention does not require complex current detection and feedback circuits, and the output pins do not need to be increased or decreased. It is compatible with existing product definitions and is convenient for customers to import.
[0092] The current source output solution proposed in the present invention only requires one external resistor to set the output current IOUT, which is convenient for customers to adjust the output current IOUT according to system requirements.
[0093] According to one aspect of the present disclosure, a driving chip is provided, wherein the chip includes the driving circuit.
[0094] According to one aspect of the present disclosure, an electronic device is provided. The electronic device includes the driving chip and a display panel.
[0095] In a possible implementation, the display panel includes any one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel and a micro light emitting diode display panel.
[0096] In a possible implementation, the electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.
[0097] Of course, the electronic device can also be other terminal devices, wherein the terminal device can be a user equipment (UE), a mobile device, a user terminal, a terminal, a handheld device, a computing device or a vehicle-mounted device, etc. For example, some examples of terminals are: mobile phones, tablet computers, laptop computers, PDAs, mobile Internet devices (MID), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control (Industrial Control), wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids (Smart Grid), wireless terminals in transportation safety (Transportation Safety), wireless terminals in smart cities (Smart City), wireless terminals in smart homes (Smart Home), wireless terminals in Internet of Vehicles, etc. For example, the server can be a local server or a cloud server.
[0098] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.
Claims
1. A driving circuit, characterized in that: The circuit includes: a negative feedback module, a first current source, a second current source, a first resistor, a second resistor, a zeroth NMOS transistor, a second NMOS transistor, a pull-down NMOS transistor and a third PMOS transistor, wherein: The first end of the first current source, the first end of the second current source, the source of the third PMOS transistor, and the first end of the negative feedback module are used to receive a power supply voltage. The second end of the first current source is connected to the first end of the second resistor and the second end of the negative feedback module. The second end of the second current source is connected to the third end of the negative feedback module. The drain of the third PMOS transistor is connected to the fourth terminal of the negative feedback module. A common node between the fifth terminal of the negative feedback module and the first terminal of the first resistor is used to generate an output current, and the output current is used to drive the target transistor. The second end of the second resistor is connected to the gate of the second NMOS transistor and the drain of the second NMOS transistor. The source of the second NMOS transistor is connected to the second end of the first resistor and the drain of the pull-down NMOS transistor. The sixth terminal of the negative feedback module is connected to the drain of the zeroth NMOS transistor. The source of the pull-down NMOS transistor and the source of the zeroth NMOS transistor are grounded, The negative feedback module is used to adjust the current on the first resistor.
2. The driving circuit according to claim 1, characterized in that: The negative feedback module includes a current mirror, a pull-up NMOS transistor and a first NMOS transistor, wherein: The drain of the pull-up NMOS transistor serves as the first terminal of the negative feedback module. The gate of the first NMOS transistor serves as the second terminal of the negative feedback module. The drain of the first NMOS transistor and the connection point of the current mirror serve as the third terminal of the negative feedback module. The connection point between the source of the first NMOS transistor and the source of the pull-up NMOS transistor serves as the fifth terminal of the negative feedback module. The power supply terminal of the current mirror serves as the fourth terminal of the negative feedback module. The connection point of the current output terminal of the current mirror and the gate of the pull-up NMOS transistor serves as the sixth terminal of the negative feedback module.
3. The driving circuit according to claim 2, characterized in that: The current mirror comprises a first PMOS transistor and a second PMOS transistor, wherein: The source of the first PMOS transistor and the source of the second PMOS transistor are connected to serve as a power supply terminal of the current mirror. The gate of the first PMOS transistor, the gate of the second PMOS transistor, and the drain of the second PMOS transistor are connected to the drain of the first NMOS transistor, The source of the first PMOS transistor serves as a current output terminal of the current mirror.
4. The driving circuit according to claim 1, characterized in that: The currents of the first current source and the second current source are equal in magnitude.
5. The driving circuit according to claim 1, characterized in that: The output current is: IOUT=Ib*R2 / R1, wherein IOUT represents the output current, Ib represents the current of the first current source or the second current source, R2 represents the resistance of the second resistor, and R1 represents the resistance of the first resistor.
6. The driving circuit according to claim 1, characterized in that: The first resistor or the second resistor is an adjustable resistor.
7. A driver chip, characterized in that: The chip comprises the driving circuit according to any one of claims 1-6.
8. An electronic device, characterized in that: The electronic device comprises the driving chip and the display panel as claimed in claim 7.
9. The electronic device according to claim 8, characterized in that: The display panel includes any one of a liquid crystal display panel, an organic light emitting diode display panel, a quantum dot light emitting diode display panel, a mini light emitting diode display panel and a micro light emitting diode display panel.
10. The electronic device according to claim 9, characterized in that: The electronic device includes any one of a display, a smart phone, a smart watch, a smart bracelet, a tablet computer, a laptop computer, an all-in-one computer, an access control device, and an electronic door lock.