output driver

Abstract

The application discloses an output driver, comprising: a pull-up transistor having a first current path coupled between a power supply voltage and an output node; a pull-down transistor having a second current path coupled between the output node and a reference ground; a gate drive circuit for driving a control terminal of the pull-up transistor according to a first control signal and driving a control terminal of the pull-down transistor according to a second control signal; a logic control circuit for generating the first control signal and the second control signal according to an input signal and an enable control signal; and a current source circuit for providing a pull-down or pull-up current related to the power supply voltage to the control terminal of the pull-up transistor or the pull-down transistor respectively during a rising or falling edge of an output signal at the output node, so as to offset the influence of the power supply voltage on the transmission time of the output signal, thereby maintaining a stable transmission time under a wider power supply voltage range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to an output driver. Background Technology

[0002] In high-speed analog-to-digital converter (ADC) applications, as conversion rates continue to increase, the performance requirements for output drivers also become increasingly demanding. Output drivers need to provide sufficient current to meet the needs of high-speed data transmission, resulting in a large number of current fluctuations within a short period, thus generating significant switching noise on the power lines. Furthermore, in applications with large capacitive loads, the inductive effect of the package and circuit board can cause voltage bounce on the power lines. This noise not only causes data transmission delays and oscillations but can also cause crosstalk between adjacent signal lines, and in severe cases, even affect the normal operation and performance of the chip's internal circuitry.

[0003] To address the aforementioned issues, controlling the slew rate of the output driver has become an effective technique. By adjusting the slew rate of the output driver, the rate of current change can be reduced, thereby lowering noise levels. Currently, various methods exist for controlling the slew rate of the output driver, among which capacitive feedback structures are favored due to their high area efficiency.

[0004] like Figure 1 As shown, the prior art output driver 100 includes a pull-up transistor M1 connected between the power supply voltage VDD_IO and the output node N0, a pull-down transistor M2 connected between the output node N0 and ground, and transistors M3 to M6. Transistors M5 and M3 are connected in series between the power supply voltage VDD_IO and ground, with their intermediate node connected to the gate of the pull-up transistor M1. Transistors M3 and M5 provide a pull-up drive signal VGP to the pull-up transistor M1 based on the input signal Din, thereby charging the load capacitor CL at the output pad PAD connected to the output node N0 through the pull-up transistor M1. Transistors M4 and M6 are connected in series between the power supply voltage VDD_IO and ground, with their intermediate node connected to the gate of the pull-down transistor M2. Transistors M4 and M6 provide a pull-down drive signal VGN to the pull-down transistor M2 based on the input signal Din, thereby discharging the load capacitor CL at the output pad PAD through the pull-down transistor M2.

[0005] The prior art output driver 100 controls the gate voltages of the pull-up transistor M1 and the pull-down transistor M2 by introducing a capacitive feedback from the output pad PAD to the gates of the pull-up transistor M1 and the pull-down transistor M2, so as to match the output current with the load. In this structure, the transistors M3 and M4 act as constant current sources, and the feedback capacitors CFP and CFN are used to keep the gate voltage VGP of the pull-up transistor M1 and the gate voltage VGN of the pull-down transistor M2 at a relatively stable value during the rising or falling edge of the output pad PAD, so that the propagation time of the output driver mainly depends on the supply voltage, the feedback capacitors and the size of the current sources, and is not greatly related to the size of the output load in a wide range.

[0006] However, the propagation time of this conventional capacitive feedback structure is directly related to the supply voltage VDD IO, which limits its application in a wide range of supply voltages, resulting in a large variation of the propagation time under different supply voltages, thereby limiting the performance stability of the circuit under different supply voltages and load conditions. SUMMARY

[0007] Therefore, the purpose of the present application is to provide an output driver capable of maintaining stable propagation time in a wide range of supply voltage conditions to adapt to various application scenarios.

[0008] According to an aspect of the present application, an output driver is provided, comprising: a pull-up transistor having a first current path coupled between a supply voltage and an output node; a pull-down transistor having a second current path coupled between the output node and a reference ground; a gate drive circuit for generating a pull-up drive signal to drive a control terminal of the pull-up transistor according to a first control signal, and generating a pull-down drive signal to drive a control terminal of the pull-down transistor according to a second control signal; a feedback capacitor coupled between the gate drive circuit and the output node for maintaining stability of the pull-up drive signal or the pull-down drive signal; and a current source circuit for providing a pull-down current related to the supply voltage to the control terminal of the pull-up transistor during a rising edge of an output signal at the output node, or providing a pull-up current related to the supply voltage to the control terminal of the pull-down transistor during a falling edge of the output signal, so as to weaken the influence of the supply voltage on the propagation time of the output signal.

[0009] Optionally, the pull-up current and the pull-down current are both proportional to the supply voltage.

[0010] Optionally, the gate drive circuit comprises: a first sub-module configured to generate the pull-up drive signal according to the first control signal and an inverted signal of the first control signal; and a second sub-module configured to generate the pull-down drive signal according to the second control signal and an inverted signal of the second control signal, wherein the feedback capacitor is coupled between a first reference node between the first sub-module and the second sub-module and the output node.

[0011] Optionally, the first sub-module comprises: a first transistor coupled between the power voltage and a second reference node, the inverted signal of the first control signal being configured to drive a control terminal of the first transistor; and a second transistor coupled between the second reference node and the first reference node, the first control signal being configured to drive a control terminal of the second transistor, wherein the second reference node is connected to a control terminal of the pull-up transistor to provide the pull-up drive signal to the pull-up transistor, and the second sub-module comprises: a third transistor coupled between the first reference node and a third reference node, the second control signal being configured to drive a control terminal of the third transistor; and a fourth transistor coupled between the third reference node and a reference ground, an inverted signal of the second control signal being configured to drive a control terminal of the fourth transistor, wherein the third reference node is connected to a control terminal of the pull-down transistor to provide the pull-down drive signal to the pull-down transistor.

[0012] Optionally, the gate drive circuit further comprises a logic control circuit configured to generate the first control signal and the second control signal according to an input signal and an enable control signal, wherein the logic control circuit is configured to output the first control signal as a valid signal when both the input signal and the enable control signal are valid signals, and output the second control signal as a valid signal when the input signal is an invalid signal and the enable control signal is a valid signal.

[0013] Optionally, the logic control circuit comprises: a NAND gate having a first input terminal configured to receive the enable control signal, a second input terminal configured to receive the input signal, and an output terminal configured to output the first control signal; a first inverter having an input terminal connected to the output terminal of the NAND gate and an output terminal configured to output an inverted signal of the first control signal; or a NOR gate having a first input terminal configured to receive the input signal, a second input terminal configured to receive an inverted signal of the enable control signal, and an output terminal configured to output the second control signal; and a second inverter having an input terminal connected to the output terminal of the NOR gate and an output terminal configured to output an inverted signal of the second control signal.

[0014] Optionally, the current source circuit comprises: a first current source circuit connected to the control end of the pull-up transistor, configured to provide a pull-down current to the control end of the pull-up transistor during a rising edge of the output signal; and a second current source circuit connected to the control end of the pull-down transistor, configured to provide a pull-up current to the control end of the pull-down transistor during a falling edge of the output signal.

[0015] Optionally, the first current source circuit comprises: a first switch having a first end connected to the power supply voltage; a first resistor having a first end connected to a second end of the first switch; a fifth transistor having a first end connected to a second end of the first resistor and a second end connected to a reference ground; a sixth transistor having a first end connected to the control end of the pull-up transistor and a control end connected to the first end of the fifth transistor; a second resistor having a first end connected to the control end of the fifth transistor and a second end connected to the second end of the sixth transistor; a second switch having a first end connected to the second end of the second resistor and a second end connected to the reference ground; a third resistor having a first end connected to the control end of the pull-up transistor; a third switch having a first end connected to the second end of the third resistor and a second end connected to the reference ground; a fourth switch having a first end connected to the control end of the fifth transistor and a second end connected to the reference ground; and a fifth switch having a first end connected to the control end of the sixth transistor and a second end connected to the reference ground; and the second current source circuit comprises: a seventh transistor having a first end connected to the power supply voltage; a fourth resistor having a first end connected to a second end of the seventh transistor; a sixth switch having a first end connected to the second end of the fourth resistor and a second end connected to the reference ground; a seventh switch having a first end connected to the power supply voltage; a fifth resistor having a first end connected to a second end of the seventh switch; an eighth transistor having a first end connected to the second end of the fifth resistor and the control end of the seventh transistor, a control end connected to the second end of the seventh transistor, and a second end connected to the control end of the pull-down transistor; an eighth switch having a first end connected to the power supply voltage; a sixth resistor having a first end connected to a second end of the eighth switch and a second end connected to the control end of the pull-down transistor; a ninth switch having a first end connected to the power supply voltage and a second end connected to the control end of the seventh transistor; and a tenth switch having a first end connected to the power supply voltage and a second end connected to the control end of the eighth transistor.

[0016] Optionally, the turn-on and turn-off of the first switch to the fifth switch are controlled by the first control signal, and the turn-on and turn-off of the sixth switch to the tenth switch are controlled by the second control signal, wherein when the first control signal is a valid signal, the first switch to the third switch are turned on, and the fourth switch and the fifth switch are turned off; when the first control signal is an invalid signal, the first switch to the third switch are turned off, and the fourth switch and the fifth switch are turned on; when the second control signal is a valid signal, the sixth switch to the eighth switch are turned on, and the ninth switch and the tenth switch are turned off; when the second control signal is an invalid signal, the sixth switch to the eighth switch are turned off, and the ninth switch and the tenth switch are turned on.

[0017] Optionally, the pull-down transistor, the first transistor and the second transistor are N-channel field effect transistors, and the pull-up transistor, the third transistor and the fourth transistor are P-channel field effect transistors.

[0018] Optionally, the fifth transistor and the sixth transistor are N-channel field effect transistors, and the seventh transistor and the eighth transistor are P-channel field effect transistors.

[0019] In summary, the embodiment of the present application provides a swing rate control output driver based on capacitance feedback and wide power supply voltage working range. By using a current source circuit to provide pull-down or pull-up current related to the power supply voltage to the driving transistor, the correlation between the output driver transmission time and the power supply voltage and the output impedance is reduced, so that the output conversion time is relatively stable under a relatively wide power supply voltage and capacitance load, and then the output driver can maintain stable output conversion time under different power supply voltages and load conditions, enhancing the adaptability of the circuit to environmental changes and improving the robustness of the circuit. The output driver of the embodiment of the present application can maintain stable transmission time under a wide range of power supply voltages and different load capacitance conditions, has strong adaptability, and is suitable for various application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0020] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 A circuit schematic diagram of an output driver according to the prior art is shown.

[0022] Figure 2 A structure schematic diagram of an output driver according to an embodiment of the present application is shown.

[0023] Figure 3 A circuit schematic diagram of a driving circuit and a gate driving circuit according to an embodiment of the present application is shown.

[0024] Figure 4 A circuit schematic diagram of a logic control circuit according to an embodiment of the present application is shown.

[0025] Figure 5 A circuit schematic diagram of a first current source circuit according to an embodiment of the present application is shown.

[0026] Figure 6 A circuit schematic diagram of a second current source circuit according to an embodiment of the present application is shown.

[0027] Figure 7 A waveform comparison diagram of the transmission delay of an output driver according to an embodiment of the present application and an output driver of the prior art is shown. DETAILED DESCRIPTION

[0028] The present application will be described in more detail with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements throughout. For clarity, not all of the parts of the application have been shown to scale in the drawings. Furthermore, certain prior art can not be shown to scale in the drawings.

[0029] Many specific details of the application are described below in order to provide a thorough understanding of the present application. However, it will be understood by those skilled in the art that the present application can be practiced without employing these specific details.

[0030] It should be understood that, in the following description, "circuitry" can include a single or multiple components of hardware, programmable circuitry, state machine circuitry, and / or elements to store instructions for execution by a programmable circuitry. When an element or circuitry is referred to as being "connected to" another element, or "between" two elements, it can be directly coupled to the other element or be coupled to the other element with intervening elements between them that can perform one or more of the functions described in the specification. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that no intervening element is present.

[0031] In this application, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. In the on state of the MOSFET, current flows from the first terminal to the second terminal. The first current terminal, the second current terminal, and the control terminal of a P-channel MOSFET are the source, the drain, and the gate, respectively. The first current terminal, the second current terminal, and the control terminal of an N-channel MOSFET are the drain, the source, and the gate, respectively.

[0032] Figure 2A structural schematic diagram of an output driver according to an embodiment of the present application is shown. Referring to Figure 2 The output driver 200 comprises a driving circuit 210, a gate driving circuit 220, a current source circuit, and a logic control circuit 240.

[0033] The output pad PAD is connected to an output node of the driving circuit 210 through an output line, a capacitive load CL is connected between the output pad PAD and a reference ground GND, and the driving circuit 210 is configured to perform a pull-up operation or a pull-down operation on the output pad PAD according to a control signal to provide an output signal Dout to the output pad PAD.

[0034] Further, Figure 3 A circuit schematic diagram of the driving circuit 210 according to an embodiment of the present application is shown. Referring to Figure 3 The driving circuit 210 can comprise a pull-up transistor M1 (e.g., a P-channel MOSFET) and a pull-down transistor M2 (e.g., an N-channel MOSFET), the pull-up transistor M1 being connected between a supply voltage VDD IO and an output node N0, the pull-down transistor M2 being connected between the output node N0 and a reference ground GND, and the output node N0 being connected to the output pad PAD. The pull-up transistor M1 and the pull-down transistor M2 have a current path therethrough (in the case of a field-effect transistor such as a MOSFET, the current path is between the source and the drain of the MOSFET) to provide a current path from the supply voltage VDD IO and the reference ground GND to the output node N0 between the transistors M1 and M2.

[0035] As shown in Figure 3 the source of the pull-up transistor M1 is connected to the supply voltage VDD IO, the drain of the pull-up transistor M1 is connected to the output node N0, the drain of the pull-down transistor M2 is connected to the output node N0, and the source of the pull-down transistor M2 is connected to the reference ground GND.

[0036] As an example, the supply voltage VDD IO is provided, for example, as an IO power supply, which refers to the voltage level used when the chip interacts with external devices for data exchange, and it is directly related to the performance and stability of the chip.

[0037] The gate driving circuit 220 is configured to generate a pull-up driving signal VGP and a pull-down driving signal VGN to control the pull-up operation and the pull-down operation of the driving circuit 210, respectively. Further, the gate driving circuit 220 is configured to apply the pull-up driving signal VGP and the pull-down driving signal VGN to the control terminal (in the case of a field-effect transistor such as a MOSFET, the gate) of the pull-up transistor M1 and the pull-down transistor M2, respectively, to control the turn-on and turn-off of the pull-up transistor M1 and the pull-down transistor M2.

[0038] Further, the gate drive circuit 220 is configured to generate the pull-up drive signal VGP and the pull-down drive signal VGN according to the first control signal CTRL1 and the second control signal CTRL2 from the logic control circuit 240. For example, the gate drive circuit 220 can generate the pull-up drive signal VGP according to the first control signal CTRL1, and the gate drive circuit 220 can generate the pull-down drive signal VGN according to the second control signal CTRL2.

[0039] Further, the output driver 200 according to the embodiment of the present application further comprises a feedback capacitor CF connected between the gate drive circuit 220 and the output node N0, and the feedback capacitor CF is configured to feedback drive the gate drive circuit 220 according to the voltage at the output node N0, so that the pull-up drive signal VGP and the pull-down drive signal VGN are at a relatively stable value during the rising or falling of the voltage at the output pad PAD, so that the output current is matched with the load.

[0040] Further, Figure 3 The circuit schematic diagram of the gate drive circuit 220 according to the embodiment of the present application is shown. As shown in the figure, Figure 3 The gate drive circuit 220 can comprise two sub-modules 221 and 222. The sub-module 221 is configured to generate the pull-up drive signal VGP according to the first control signal CTRL1 and the inverted signal CTRL1B thereof, and the sub-module 222 is configured to generate the pull-down drive signal VGN according to the second control signal CTRL2 and the inverted signal CTRL2B thereof.

[0041] Further, the sub-module 221 comprises P-channel MOSFET transistors M5 and M3, which are connected in series between the power supply voltage VDD IO and the node A3, the middle node Al of the transistors M5 and M3 is connected to the control terminal of the pull-up transistor Ml, the control terminal of the transistor M3 is connected to the first control signal CTRL1, and the control terminal of the transistor M5 is connected to the inverted signal CTRL1B of the first control signal. The transistors M3 and M5 are used to control the logic state of the pull-up driving signal VGP according to the first control signal CTRL1. For example, the first control signal CTRL1 and its inverted signal CTRL1B are, for example, binary "0" (or logic low signal) and "1" (or logic high signal). When the first control signal CTRL1 is an effective signal (for example, "0" or logic low signal), at this time, the inverted signal CTRL1B of the first control signal is "1" or logic high signal, the transistor M3 is turned on and the transistor M5 is turned off, the pull-up driving signal VGP is pulled low by the pull-down current IBP, so that the pull-up transistor Ml is turned on, and the pull-up operation is performed on the output node N0. When the first control signal CTRL1 is an ineffective signal (for example, "1" or logic high signal), at this time, the inverted signal CTRL1B of the first control signal is "0" or logic low signal, the transistor M5 is turned on and the transistor M3 is turned off, the pull-up driving signal VGP is pulled high to a logic high signal through the transistor M5, so that the pull-up transistor Ml is turned off.

[0042] Further, the sub-module 222 includes N-channel MOSFET transistors M4 and M6 connected in series between the node A3 and the reference ground GND, with the middle node A2 of the transistors M4 and M6 connected to the control terminal of the pull-down transistor M2, the control terminal of the transistor M4 connected to the second control signal CTRL2, and the control terminal of the transistor M6 connected to the inverted signal CTRL2B of the second control signal. The transistors M4 and M6 are used to control the logic state of the pull-down drive signal VGN according to the second control signal CTRL2. For example, the second control signal CTRL2 and the inverted signal CTRL2B thereof are binary "0" (or logic low signal) and "1" (or logic high signal), when the second control signal CTRL2 is an effective signal (e.g., "1" or logic high signal), at this time the inverted signal CTRL2B of the second control signal is "0" or logic low signal, the transistor M4 is turned on and the transistor M6 is turned off, the pull-down drive signal VGN is pulled up by the pull-up current IBN, so that the pull-down transistor M2 is turned on, and a pull-down operation is performed on the output node N0. When the second control signal CTRL2 is an ineffective signal (e.g., "0" or logic low signal), at this time the inverted signal CTRL2B of the second control signal is "1" or logic high signal, the transistor M6 is turned on and the transistor M4 is turned off, the pull-down drive signal VGN is pulled down to a logic low signal by the transistor M6, so that the pull-down transistor M2 is turned off.

[0043] Further, the feedback capacitor CF is coupled between the node A3 and the output node N0, and drives the drain terminals of the transistors M3 and M4 according to the voltage at the output node N0, so that the pull-up drive signal VGP and the pull-down drive signal VGN can be at a relatively stable value during the rising or falling of the voltage at the output pad PAD, so as to match the output current with the load.

[0044] With reference to Figure 2 , the logic control circuit 240 is used to generate the first control signal CTRL1 and the second control signal CTRL2 according to the input signal Din and the enable control signal EN. For example, the input signal Din and the enable control signal EN are binary "0" (or logic low signal) and "1" (or logic high signal), when both the input signal Din and the enable control signal EN are effective signals (e.g., "1" or logic high signal), the first control signal CTRL1 is an ineffective signal (e.g., "0" or logic low signal); when the input signal Din is an ineffective signal (e.g., "0" or logic low signal) and the enable control signal EN is an effective signal (e.g., "1" or logic high signal), the second control signal CTRL2 is an effective signal (e.g., "1" or logic high signal).

[0045] Further, Figure 4A circuit diagram of a logic control circuit 240 according to an embodiment of the present invention is shown, as follows: Figure 4 As shown, the logic control circuit 240 includes a NAND gate (NAND1), a NOR gate (NOR1), an inverter (INV1), and an inverter (INV2). One input of the NAND gate (NAND1) receives the enable control signal EN, and the other input receives the input signal Din. The NAND gate (NAND1) performs a NAND operation on the input signal Din and the enable control signal EN to provide the first control signal CTRL1 at its output. The input of the inverter (INV1) is connected to the output of the NAND gate (NAND1), and its output provides the inverted signal CTRL1B of the first control signal. One input of the NOR gate (NOR1) receives the inverted signal ENB of the enable control signal, and the other input receives the input signal Din. The NOR gate (NOR1) performs a NOR operation on the input signal Din and the signal ENB to provide the second control signal CTRL2 at its output. The input of inverter INV2 is connected to the output of NOR gate NOR1, and the output of inverter INV2 is used to provide the inverted signal CTRL2B of the second control signal.

[0046] It should be noted that the circuit structure of the logic control circuit 240 in the above embodiments is only exemplary, and the present invention does not limit it. Those skilled in the art can also choose to implement the logic control circuit 240 by other logic or analog circuits.

[0047] Continue to refer to Figure 2 and Figure 3 The current source circuit is used to connect to reference nodes A1 and A2 (or the gate terminals of pull-up transistor M1 and pull-down transistor M2) in the gate drive circuit 220, and is used to provide pull-down current IBP or pull-up current IBN related to the power supply voltage VDD_IO to the gate drive circuit 220 during the rising or falling edge of the output pad PAD, so as to counteract the influence of the power supply voltage VDD_IO on the transmission time of the output signal Dout, and obtain a constant transmission time in the output driver 200.

[0048] Further, the current source circuit comprises a first current source circuit 231 and a second current source circuit 232. The first current source circuit 231 is connected to the reference node A1 or the gate of the pull-up transistor M1 in the gate drive circuit 220, and is configured to provide a pull-down current IBP related to the power supply voltage VDD IO to the gate drive circuit 220 during the rising edge of the output pad PAD or the output node N0, so as to control the transmission time of the output signal Dout from the logic low signal to the logic high signal. The second current source circuit 232 is connected to the reference node A2 or the gate of the pull-down transistor M2 in the gate drive circuit 220, and is configured to provide a pull-up current IBN related to the power supply voltage VDD IO to the gate drive circuit 220 during the falling edge of the output pad PAD or the output node N0, so as to control the transmission time of the output signal Dout from the logic high signal to the logic low signal. Therefore, by setting the first current source circuit 231 and the second current source circuit 232, the rising edge transmission time or the falling edge transmission time of the output driver is finally related to only the feedback capacitor CF and the internal resistance of the current source circuit, and is irrelevant to the power supply voltage VDD IO and the output impedance, so that a constant transmission time can be obtained in a wide power supply voltage range.

[0049] Figure 5 The circuit schematic diagram of the first current source circuit according to an embodiment of the present application is shown. For convenience of description, only the pull-up transistor M1, the transistor M3, the transistor M5 and the feedback capacitor CF are shown in Figure 5 The pull-down transistor M2 and the transistors M4 and M6 are not shown. As shown in Figure 5 The first current source circuit 231 comprises resistors R1 to R3, transistors M7 and M8, and switches S1 to S5. The transistors M7 and M8 are, for example, N-channel MOSFETs. The first end of the switch S5 is connected to the power supply voltage VDD IO, the second end of the switch S5 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the gate of the transistor M8 and the drain of the transistor M7, the gate of the transistor M7 is connected to the source of the transistor M8 and the first end of the resistor R1, and the source of the transistor M7 is connected to the reference ground GND. The drain of the transistor M8 is connected to the reference node A1 and the gate of the pull-up transistor M1, the second end of the resistor R1 is connected to one end of the switch S1, and the other end of the switch S1 is connected to the reference ground GND. The first end of the resistor R2 is connected to the reference node A1 and the gate of the pull-up transistor M1, the second end of the resistor R2 is connected to one end of the switch S2, and the other end of the switch S2 is connected to the reference ground GND. The switch S3 is connected between the gate of the transistor M8 and the reference ground GND, and the switch S4 is connected between the gate of the transistor M7 and the reference ground GND.

[0050] Further, the on and off of the switches S1 to S5 in the first current source circuit 231 are controlled by the first control signal CTRL1. In the preferred embodiment, the logic control circuit 240 can further comprise a switch control unit 241 for controlling the on and off of the switches S1 to S5 according to the first control signal CTRL1.

[0051] Further, when the enable control signal EN is a logic high signal, and in the process of the rising edge of the input signal Din from a logic low signal to a logic high signal, the first control signal CTRL1 is a logic low signal, the transistor M3 is turned on, and the transistor M5 is turned off. At this time, the gate voltage VGP of the pull-up transistor M1 starts to drop from the power supply voltage VDD IO, and the discharge current is equal to the pull-down current IBP provided by the first current source circuit 231. When the gate voltage VGP drops to VDD IO-VTP1 (VTP1 is the threshold voltage of the pull-up transistor M1), the pull-up transistor M1 is turned on and the voltage of the output pad PAD rises. At the same time, due to the action of the feedback capacitor CF, a compensation current Icp flowing through the feedback capacitor CF is generated, and the current size is:

[0052] (1)

[0053] where C F is the capacitance value of the compensation capacitor CF, and V PAD is the voltage at the output pad PAD. When the compensation current Icp is equal to the pull-down current IBP, the gate voltage VGP of the pull-up transistor M1 is stabilized around a certain value, so that the output current of the output driver is kept stable, and the rising rate of the voltage at the output pad PAD is stable. When the gate voltage VGP of the pull-up transistor M1 is pulled down to ground potential, the rising process of the voltage at the output pad PAD is completed. Therefore, the slew rate SR+ of the rising edge of the output signal Dout can be calculated by the following formula:

[0054] (2)

[0055] Generally, the rising edge transmission time of the output driver is defined as the time when the output signal Dout rises from 10% to 90%, so the rising edge transmission time of the output driver 200 can be obtained as:

[0056] (3)

[0057] According to the formula (3), it can be concluded that, without considering the gate end parasitic capacitance of the output driving transistor, the rising edge transmission time of the output driver 200 is related to the pull-down current IBP, the size of the feedback capacitance CF and the power supply voltage VDD IO. Further, by introducing the correlation coefficient of the power supply voltage VDD IO in the pull-down current IBP, the correlation between the transmission time and the power supply voltage VDD IO can be weakened, and a constant transmission time can be obtained in a wide power supply voltage range.

[0058] Further, when the enable control signal EN is a logic high signal and the input signal Din is changed from a logic low signal to a logic high signal, the first control signal CTRL1 is a logic low signal, the switches S1, S2 and S5 are turned on, the switches S3 and S4 are turned off, and the current flows from the power supply voltage VDD IO through the resistor R3, so that the working voltage of the transistors M7 and M8 is established, and thus the current flowing through the resistor R1 can be obtained as:

[0059] (4)

[0060] wherein V GS7 is the gate-source voltage of the transistor M7. In addition, when the pull-up transistor M1 is turned on, the voltage of the pull-up driving signal VGP is stabilized at VDD IO- |V GS1 |, wherein V GS1 is the gate-source voltage of the pull-up transistor M1, and thus the current flowing through the resistor R2 can be obtained as:

[0061] (5)

[0062] Since the pull-down current IBP is equal to the sum of the current flowing through the resistor R1 and the current flowing through the resistor R2, the pull-down current IBP can be obtained as:

[0063] (6)

[0064] According to the formula (6), by adjusting the resistance values of the resistors R1 and R2, the second term in the formula (6) can be equal to zero, and thus the following formula (7) can be obtained:

[0065] (7)

[0066] In another embodiment, the resistors R1 and R2 can be set as variable resistors. Further, by substituting the obtained pull-down current IBP into the formula (3), the following formula (8) can be obtained:

[0067] (8)

[0068] Therefore, in this embodiment, the pull-down current IBP related to the power supply voltage VDD IO is generated by the first current source circuit 231, so that the rising time of the output driver is only related to the feedback capacitance CF and the resistance R2 of the current source circuit, and is independent of the power supply voltage VDD IO and the output impedance, thereby controlling the transmission time of the output driver, and obtaining a constant transmission time in a wide power supply voltage range.

[0069] Figure 6 The circuit schematic diagram of the second current source circuit according to an embodiment of the present application is shown. Similarly, for the convenience of description, only the pull-down transistor M2, the transistor M4, the transistor M6 and the feedback capacitance CF are shown in Figure 6 The pull-up transistor M1 and the transistors M3 and M5 are not shown. As shown in Figure 6 The second current source circuit 232 includes resistors R4 to R6, a transistor M9, a transistor M10 and switches S6 to S10. The transistors M9 and M10 are, for example, P-channel MOSFETs. The source of the transistor M9 is connected to the power supply voltage VDD IO, the drain of the transistor M9 is connected to the first end of the resistor R4, the second end of the resistor R4 is connected to the first end of the switch S6, the second end of the switch S6 is connected to the reference ground GND. The first end of the switch S7 is connected to the power supply voltage VDD IO, the second end of the switch S7 is connected to the first end of the resistor R5, the second end of the resistor R5 is connected to the gate of the transistor M9 and the source of the transistor M10, the gate of the transistor M10 is connected to the drain of the transistor M9, the drain of the transistor M10 is connected to the reference node A2 and the gate of the pull-down transistor M2. The first end of the switch S8 is connected to the power supply voltage VDD IO, the second end of the switch S8 is connected to the first end of the resistor R6, the second end of the resistor R6 is connected to the reference node A2 and the gate of the pull-down transistor M2. The switch S9 is connected between the power supply voltage VDD IO and the gate of the transistor M10, and the switch S10 is connected between the power supply voltage VDD IO and the gate of the transistor M9.

[0070] Further, the on and off of the switches S6 to S10 in the second current source circuit 232 are controlled by the second control signal CTRL2. In a preferred embodiment, the logic control circuit 240 can further include a switch control unit 242 for controlling the switching of the switches S6 to S10 according to the second control signal CTRL2.

[0071] Further, when the enable control signal EN is a logic high signal, and during the falling edge of the input signal Din from a logic high signal to a logic low signal, the second control signal CTRL2 is a logic high signal, the transistor M4 is turned on, and the transistor M6 is turned off. At this time, the gate voltage VGN of the pull-down transistor M2 starts to rise from the reference ground GND, and the charging current is equal to the pull-up current IBN provided by the second current source circuit 232. When the gate voltage VGN rises to VTP2 (VTP2 is the threshold voltage of the pull-down transistor M2), the pull-down transistor M2 is turned on and the voltage of the output pad PAD is lowered. At the same time, due to the effect of the feedback capacitor CF, a compensation current Icp flowing through the feedback capacitor CF is generated, and the current value of the compensation current Icp can be calculated according to formula (1). When the compensation current Icp is equal to the pull-up current IBN, the gate voltage VGN of the pull-down transistor M2 is stabilized at a certain value, so that the output current of the output driver is kept stable, and the voltage falling rate of the output pad PAD is stable. Finally, the falling edge slew rate SR- of the output signal Dout can be obtained as:

[0072] (9)

[0073] Similarly, the falling edge transmission time of the output driver is generally defined as the time when the output signal Dout falls from 90% to 10%, so the falling edge transmission time of the output driver can be obtained as:

[0074] (10)

[0075] According to formula (10), in the case of not considering the gate parasitic capacitance of the output driving transistor, the falling edge transmission time of the output driver 200 is related to the pull-up current IBN, the size of the feedback capacitor CF, and the power supply voltage VDD IO. Further, by introducing a correlation coefficient related to the power supply voltage VDD IO in the pull-up current IBN, the correlation between the transmission time and the power supply voltage VDD IO can be weakened, and a constant transmission time can be obtained in a wide power supply voltage range.

[0076] Further, when the enable control signal EN is a logic high signal, and during the falling edge of the input signal Din from a logic high signal to a logic low signal, the second control signal CTRL2 is a logic high signal, the switch S6, S7 and S8 are turned on, and the switch S9 and S10 are turned off. The current flows from the power supply voltage VDD IO through the resistor R4 to establish the operating voltage of the transistors M9 and M10, so that the current flowing through the resistor R5 can be obtained as:

[0077] (11)

[0078] where V GS9This is the gate-source voltage of transistor M9. Furthermore, during the period when pull-down transistor M2 has just turned on and the output is still on its falling edge, the gate voltage VGN of pull-down transistor M2 stabilizes at VGS2. Therefore, the current flowing through resistor R6 can be obtained as:

[0079] (12)

[0080] Since the pull-up current IBN is equal to the sum of the current flowing through resistor R5 and the current flowing through resistor R6, the pull-up current IBN can be obtained as follows:

[0081] (13)

[0082] According to formula (13), by adjusting the resistance values ​​of resistors R5 and R6, the second term in formula (13) can be made equal to zero, and thus we can obtain:

[0083] (14)

[0084] In another embodiment, resistors R5 and R6 can be set as variable resistors. Further, substituting the obtained pull-up current IBN into formula (10), we can obtain:

[0085] (15)

[0086] Therefore, it can be seen that in this embodiment, the pull-up current IBN related to the power supply voltage VDD_IO is generated by the second current source circuit 232, so that the falling edge propagation time of the output driver is only related to the feedback capacitor CF and the internal resistance R5 of the current source circuit, and is independent of the power supply voltage VDD_IO and the output impedance. Thus, the falling edge propagation time of the output driver can be controlled, and a constant propagation time can be obtained over a wide power supply voltage range.

[0087] Figure 7 A waveform comparison diagram showing the rise edge propagation time of the output driver according to an embodiment of the present invention and that of the output driver in the prior art is presented. Figure 7 In the diagram, the horizontal axis represents the power supply voltage VDD_IO, and the vertical axis represents the transmission time of the output driver. Curve 1 represents the transmission time curve of the output driver 200 in this embodiment of the invention, and curve 2 represents the transmission time curve of the output driver in the prior art. Figure 7 As shown, within the power supply voltage VDD_IO range of 2.4V to 5.5V, the transmission time of the output driver in the prior art is positively correlated with the power supply voltage VDD_IO, while the transmission time of the output driver in the embodiment of the present invention can remain relatively constant.

[0088] In summary, the embodiment of the present application provides a slew rate control output driver based on capacitance feedback and wide power voltage working range. By using a current source circuit to provide pull-down or pull-up current related to the power voltage to the driving transistor, the correlation between the output driver transmission time and the power voltage and the output impedance is reduced, so that the output conversion time is relatively stable under a relatively wide power voltage and capacitance load, and then the output driver can maintain stable output conversion time under different power voltage and load conditions, enhancing the adaptability of the circuit to environmental changes and improving the robustness of the circuit. The output driver of the embodiment of the present application can maintain stable transmission time under a wide range of power voltages and different load capacitance conditions, has strong adaptability, and is suitable for various application scenarios.

[0089] It should be noted that although in this document a device is described as being a certain N-channel or P-channel device, or a certain N-type or P-type doped region, one of ordinary skill in the art will understand that complementary devices are also possible in accordance with the present application. One of ordinary skill in the art will understand that the conductivity type is the mechanism by which conduction occurs, e.g., by holes or electrons, and thus the conductivity type does not refer to the doping concentration but to the type of doping, e.g., P-type or N-type.

[0090] As those skilled in the art will appreciate, the terms "during," "when," and "while" used herein are not strictly temporal terms, but rather, are used to open up the possibility that other intervening events could occur between the start of the initiating action and the reaction action initiated by the initiating action, such as various transmission delays, etc. The use of the terms "about" or "substantially" herein means that the element has a parameter that is intended to be close to the stated value or position. However, as is well understood by those skilled in the art, there are always minor variations that make it difficult to be precise exactly to the stated value. It is well established in the art that a variation of at least ten percent (10%) (and at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable variation from the described accurate ideal target. When used in connection with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of a signal depends on whether positive logic or negative logic is used. For example, "logic high" and "logic low" are used to describe the logic level of a signal. A signal having a "logic high" is different from a signal having a "logic low." For example, when a signal having a first voltage corresponds to a "logic high," a signal having a second voltage can correspond to a "logic low." According to embodiments, the "logic high" can be set to a higher voltage than the "logic low." Furthermore, according to embodiments, the logic levels of signals can be set to other logic levels or reversed logic levels. For example, according to embodiments, a signal having a logic high can be set to have a logic low, and according to embodiments, a signal having a logic low can be set to have a logic high.

[0091] Also, it is to be appreciated that the terms "first," "second," etc. are used herein only to distinguish one from another thing, and do not necessarily have an actual relationship or order. Moreover, the terms "include," "have," or any variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements is not necessarily limited to those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0092] In accordance with the practices of the present invention, these embodiments have been described in relation to the above-described embodiments, which are intended to be illustrative only and not restrictive of the invention. Obviously, many modifications and variations of this invention can be effected without departing from the scope of the novel concept of the disclosure. No limitation with respect to the specific implementation techniques and applications presented thereby should be inferred into the scope of the invention, as understood by those skilled in the art. The specification and drawings should be regarded as illustrative only and in no way limiting of the scope of the invention as defined by the appended claims and equivalents thereof.

Claims

1. An output driver, comprising: a pull-up transistor having a first current path coupled between a supply voltage and an output node; a pull-down transistor having a second current path coupled between the output node and a reference ground; a gate drive circuit for generating a pull-up drive signal to drive a control terminal of the pull-up transistor according to a first control signal, and generating a pull-down drive signal to drive a control terminal of the pull-down transistor according to a second control signal; a feedback capacitor coupled between the gate drive circuit and the output node for holding a stability of the pull-up drive signal or the pull-down drive signal; and a current source circuit for providing a pull-down current related to the supply voltage to the control terminal of the pull-up transistor in a process of an output signal at the output node being in a rising edge, or providing a pull-up current related to the supply voltage to the control terminal of the pull-down transistor in a process of the output signal being in a falling edge, to weaken an effect of the supply voltage on a transmission time of the output signal, wherein the current source circuit comprises: a first current source circuit connected to the control terminal of the pull-up transistor for providing the pull-down current to the control terminal of the pull-up transistor in the process of the rising edge of the output signal, the first current source circuit comprising: a first switch having a first terminal connected to the supply voltage; a first resistor having a first terminal connected to a second terminal of the first switch; a fifth transistor having a first terminal connected to a second terminal of the first resistor, and a second terminal connected to the reference ground; a sixth transistor having a first terminal connected to the control terminal of the pull-up transistor, and a control terminal connected to the first terminal of the fifth transistor; a second resistor having a first terminal connected to the control terminal of the fifth transistor and a second terminal connected to the second terminal of the sixth transistor; a second switch having a first terminal connected to a second terminal of the second resistor, and a second terminal connected to the reference ground; a third resistor having a first terminal connected to the control terminal of the pull-up transistor; a third switch having a first terminal connected to a second terminal of the third resistor, and a second terminal connected to the reference ground; a fourth switch having a first terminal connected to the control terminal of the fifth transistor, and a second terminal connected to the reference ground; and a fifth switch having a first terminal connected to the control terminal of the sixth transistor, and a second terminal connected to the reference ground; and ​ A second current source circuit is connected to the control terminal of the pull-down transistor, and is configured to provide a pull-up current to the control terminal of the pull-down transistor during a falling edge of the output signal. The second current source circuit comprises: a seventh transistor having a first terminal connected to the power supply voltage; a fourth resistor having a first terminal connected to a second terminal of the seventh transistor; a sixth switch having a first terminal connected to a second terminal of the fourth resistor and a second terminal connected to the reference ground; a seventh switch having a first terminal connected to the power supply voltage; a fifth resistor having a first terminal connected to a second terminal of the seventh switch; an eighth transistor having a first terminal connected to a second terminal of the fifth resistor and a control terminal connected to the second terminal of the seventh transistor, and a second terminal connected to the control terminal of the pull-down transistor; an eighth switch having a first terminal connected to the power supply voltage; a sixth resistor having a first terminal connected to a second terminal of the eighth switch and a second terminal connected to the control terminal of the pull-down transistor; a ninth switch having a first terminal connected to the power supply voltage and a second terminal connected to the control terminal of the seventh transistor; and a tenth switch having a first terminal connected to the power supply voltage and a second terminal connected to the control terminal of the eighth transistor.

2. The output driver of claim 1, wherein, The pull-up current and the pull-down current are both proportional to the power supply voltage.

3. The output driver of claim 1, wherein, The gate drive circuit comprises: A first sub-module configured to generate the pull-up drive signal based on the first control signal and an inverted signal of the first control signal; and A second sub-module configured to generate the pull-down drive signal based on the second control signal and an inverted signal of the second control signal, wherein the feedback capacitor is coupled between a first reference node between the first sub-module and the second sub-module and the output node.

4. The output driver of claim 3, wherein, The first sub-module comprises: a first transistor coupled between the power supply voltage and a second reference node, and an inverted signal of the first control signal configured to drive a control terminal of the first transistor; and a second transistor coupled between the second reference node and the first reference node, and the first control signal configured to drive a control terminal of the second transistor, wherein the second reference node is connected to the control terminal of the pull-up transistor to provide the pull-up drive signal to the control terminal of the pull-up transistor, The second sub-module comprises: a third transistor coupled between the first reference node and a third reference node, and the second control signal configured to drive a control terminal of the third transistor; and a fourth transistor coupled between the third reference node and a reference ground, and an inverted signal of the second control signal configured to drive a control terminal of the fourth transistor, wherein the third reference node is connected to the control terminal of the pull-down transistor to provide the pull-down drive signal to the control terminal of the pull-down transistor.

5. The output driver of claim 1, wherein, Further comprising: a logic control circuit configured to generate the first control signal and the second control signal based on an input signal and an enable control signal, The logic control circuit is configured to output the first control signal as a valid signal when both the input signal and the enable control signal are valid signals, and output the second control signal as a valid signal when the input signal is an invalid signal and the enable control signal is a valid signal.

6. The output driver of claim 5, wherein, The logic control circuit comprises: a NAND gate, a first input end of the NAND gate configured to receive the enable control signal, a second input end of the NAND gate configured to receive the input signal, and an output end of the NAND gate configured to output the first control signal; a first inverter, an input end of the first inverter connected to the output end of the NAND gate, and an output end of the first inverter configured to output an inverted signal of the first control signal; a NOR gate, a first input end of the NOR gate configured to receive the input signal, a second input end of the NOR gate configured to receive an inverted signal of the enable control signal, and an output end of the NOR gate configured to output the second control signal; a second inverter, an input end of the second inverter connected to the output end of the NOR gate, and an output end of the second inverter configured to output an inverted signal of the second control signal.

7. The output driver of claim 1, wherein, Conduction and shutdown of the first switch to the fifth switch are controlled by the first control signal, and conduction and shutdown of the sixth switch to the tenth switch are controlled by the second control signal, wherein when the first control signal is a valid signal, the first switch to the third switch are turned on, and the fourth switch and the fifth switch are turned off, and when the first control signal is an invalid signal, the first switch to the third switch are turned off, and the fourth switch and the fifth switch are turned on, when the second control signal is a valid signal, the sixth switch to the eighth switch are turned on, and the ninth switch and the tenth switch are turned off, and when the second control signal is an invalid signal, the sixth switch to the eighth switch are turned off, and the ninth switch and the tenth switch are turned on.

8. The output driver of claim 4, wherein, The pull-down transistor, the first transistor, and the second transistor are N-channel field effect transistors, the pull-up transistor, the third transistor, and the fourth transistor are P-channel field effect transistors.

9. The output driver of claim 1, wherein, The fifth transistor and the sixth transistor are N-channel field effect transistors, the seventh transistor and the eighth transistor are P-channel field effect transistors.

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