FPGA code stream rapid compression method and system

Abstract

The invention relates to the technical field of FPGA code stream compression, in particular to an FPGA code stream rapid compression method and system, which comprises the following steps: traversing a line number in a target multi-layer index structure, identifying a data block group, a feature value group and the number of data blocks corresponding to the line number, judging whether the number of the data blocks is a preset number or not, if the number is the preset number, judging whether a subsequent single data block group set exists or not, and if the number is the preset number, sending the subsequent single data block group set to the target multi-layer index structure; if yes, merging the data block group with a subsequent single data block group to obtain a merged data block group, if not, taking the data block group as an original data block group, if not, judging whether the same feature value exists in the feature value group, if yes, compressing the data block group to obtain a compressed data block group, and if not, taking the data block group as the original data block group; and if not, taking the data block group as an original data block group, and performing code stream recombination on the merged data block group set, the compressed data block group set and the original data block group set. The problems that the overall compression effect of the FPGA code stream data is poor, and more computing resources are occupied can be solved.

Description

Technical Field

[0001] The present invention relates to the field of FPGA code stream compression technology, and in particular to a FPGA code stream fast compression method and system. Background Art

[0002] FPGA (Field Programmable Gate Array) is currently widely used in electronic system design. FPGA needs to rely on externally written bitstream data for configuration when working. By downloading the bitstream data to the corresponding FPGA chip, specific functions can be realized. As the amount of bitstream data written by FPGA continues to increase, the time consumed to transmit the bitstream data from the outside to the FPGA chip increases, which in turn leads to a longer configuration time for FPGA.

[0003] In order to shorten the configuration time of FPGA, the configuration code stream is usually compressed to shorten the code stream length and reduce the configuration time. However, the existing configuration code stream compression method is to reduce the compression granularity to bytes, that is, when compressing the code stream data, it is necessary to traverse the code stream byte by byte. This compression method can provide better compression effect for complex code stream data, but due to the decreasing boundary, the overall compression effect is not significantly improved and too many computing resources are occupied. Summary of the invention

[0004] The present invention provides a method and system for quickly compressing FPGA code streams, the main purpose of which is to solve the problem that the overall compression effect of FPGA code stream data is poor and more computing resources are occupied.

[0005] To achieve the above object, the present invention provides a method for fast compression of FPGA code stream, comprising: Parsing the pre-constructed original code stream to obtain data to be compressed, dividing the data to be compressed according to a preset unit bit number to obtain a data block set, wherein the unit bit number refers to the number of bits written to the storage RAM at one time; Extracting data blocks in the data block set in sequence, identifying the frame type, region type and row number of the data block, and calculating the hash value of the data block using a pre-built cryptographic hash algorithm; Filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure; Traversing the row numbers in the target multi-layer index structure, identifying the data block group, feature value group and number of data blocks corresponding to the row numbers; Determining whether the number of data blocks is a preset number; If the number of data blocks is a preset number, determining whether the data block group has a subsequent single data block group set, the subsequent single data block group set refers to a set of data block groups whose number of data blocks subsequent to the data block group is a preset number; If the data block group has a subsequent single data block group set, merging the data block group and the subsequent single data block group set to obtain a merged data block group; If there is no subsequent single data block group set for the data block group, the data block group is used as the original data block group; If the number of data blocks is not the preset number, determining whether there are identical eigenvalues ​​in the eigenvalue group; If the same eigenvalue exists in the eigenvalue group, compressing the data block group to obtain a compressed data block group; If the same eigenvalue does not exist in the eigenvalue group, the data block group is used as the original data block group; The merged data block groups, compressed data block groups and original data block groups are collected to obtain merged data block group sets, compressed data block group sets and original data block group sets, and the merged data block group sets, compressed data block group sets and original data block group sets are reorganized into code streams using the target multi-layer index structure to complete the FPGA code stream fast compression.

[0006] Optionally, the parsing of the pre-constructed original code stream to obtain the data to be compressed includes: Identifying a specification field in the original bitstream, and extracting a preamble bitstream from the original bitstream according to the specification field; Parsing the pre-stream to obtain pre-information, wherein the pre-information includes: whether the original stream has been compressed, the data specification of the original stream, and the stream length; The data to be compressed is extracted from the original code stream according to the code stream length in the preamble information.

[0007] Optionally, calculating the hash value of the data block by using a pre-built cryptographic hash algorithm includes: Using a pre-built cryptographic hash algorithm, the data blocks are concatenated into a binary string of a first preset number of bits; Filling the binary string of the first preset number of digits to obtain a filled string, wherein the length of the filled string is a minimum integer multiple of the second preset number of digits; The hash value of the padding string is calculated according to an encrypted hash algorithm to obtain the hash value of the data block.

[0008] Optionally, before filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure, the method further includes: Identifying a frame type sequence, a region type sequence, and a row number sequence of the data block set; Constructing a frame type hierarchy, a region type hierarchy and a row number hierarchy respectively according to the frame type sequence, the region type sequence and the row number sequence; Associatively indexing the frame type level, the region type level, and the line number level to obtain an index level; Constructing a data block feature value hierarchy and a data block data hierarchy; The initial multi-layer index structure is constructed according to the index level, the data block feature value level and the data block data level.

[0009] Optionally, the step of filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure includes: identifying a frame type level position of the frame type in the frame type level, identifying a region type level position of the region type in the region type level, and identifying a line number level position of the line number in the line number level; Determine an index path of the hash value according to the frame type level position, the region type level position and the line number level position; Identify, according to the index path, the feature value level position and the data level position of the hash value at the data block feature value level and the data block data level respectively; The hash value is filled into the characteristic value level position, and the data block is filled into the data level position until all the data blocks in the data block set are filled in, thereby obtaining a target multi-layer index structure.

[0010] Optionally, traversing the row numbers in the target multi-layer index structure to identify the data block group, the feature value group and the number of data blocks corresponding to the row numbers includes: Extracting the frame types to be traversed in sequence from the frame type sequence, and identifying the region type sequence to be traversed contained in the frame types to be traversed; Extracting the area types to be traversed in sequence from the area type sequence to be traversed, and identifying the row number sequence to be traversed contained in the area type to be traversed; The row numbers to be traversed are sequentially extracted from the sequence of row numbers to be traversed, and the characteristic value groups, data block groups and the number of data blocks corresponding to the row numbers to be traversed are identified.

[0011] Optionally, the determining whether the data block group has a subsequent single data block group set includes: Identify a subsequent row number of the row number, and obtain a data block group corresponding to the subsequent row number; Identify the number of data blocks in the data block group corresponding to the subsequent row number; Determine whether the number of data blocks in the data block group corresponding to the subsequent row number is 1; If the number of data blocks in the data block group corresponding to the subsequent row number is not 1, then there is no subsequent single data block group set in the data block group; If the number of data blocks in the data block group corresponding to the subsequent row number is 1, then the data block group has a subsequent single data block group set.

[0012] Optionally, compressing the data block group to obtain a compressed data block group includes: Among multiple specific data blocks having the same characteristic value, obtaining position information of remaining specific data blocks after the first specific data block; The compressed data block set is obtained by combining the content of the specific data block and the position information of the remaining specific data blocks. Optionally, the code stream reorganization of the merged data block set, the compressed data block set and the original data block set using the target multi-layer index structure includes: Identify the code stream sequence of the merged data block group, the compressed data block group and the original data block group in the merged data block group set, the compressed data block group set and the original data block group set according to the target multi-layer index structure; Combining the merged data block set, the compressed data block set and the original data block set according to the code stream sequence to obtain a data block group sequence; Obtaining code stream specification information of the data block group sequence; Identify the head bit position and the tail bit position of the data block group sequence, and add the code stream specification information to the head bit position and the tail bit position of the data block group sequence to obtain an initial recombined code stream; Calculate the cyclic redundancy check information of the data block group sequence, identify the tail position of the initial reorganized code stream, add the cyclic redundancy check information to the tail position of the initial reorganized code stream, and complete the code stream reorganization.

[0013] To achieve the above object, the present invention further provides an FPGA code stream fast compression system, comprising: A position information and hash value calculation module is used to parse the pre-constructed original code stream to obtain data to be compressed, divide the data to be compressed according to a preset unit bit number to obtain a data block set, wherein the unit bit number refers to the number of bits written to the storage RAM at one time, extract data blocks in the data block set in sequence, identify the frame type, region type and row number of the data block, and calculate the hash value of the data block using a pre-constructed encrypted hash algorithm; A target multi-layer index structure construction module is used to fill the frame type, region type, row number, hash value and data block of the data block into the pre-constructed initial multi-layer index structure to obtain a target multi-layer index structure; a data block group compression module, for traversing the row number in the target multi-layer index structure, identifying the data block group, the characteristic value group and the number of data blocks corresponding to the row number; judging whether the number of data blocks is a preset number; if the number of data blocks is a preset number, judging whether the data block group has a subsequent single data block group set, the subsequent single data block group set refers to a set of data block groups whose subsequent number of data blocks of the data block group is a preset number; if the data block group has a subsequent single data block group set, merging the data block group with the subsequent single data block group set to obtain a merged data block group; if the data block group does not have a subsequent single data block group set, taking the data block group as the original data block group; if the number of data blocks is not a preset number, judging whether the same characteristic value exists in the characteristic value group; if the same characteristic value exists in the characteristic value group, compressing the data block group to obtain a compressed data block group; if the same characteristic value does not exist in the characteristic value group, taking the data block group as the original data block group; The code stream reorganization module is used to collect the merged data block groups, the compressed data block groups and the original data block groups to obtain the merged data block group sets, the compressed data block group sets and the original data block group sets, and use the target multi-layer index structure to perform code stream reorganization on the merged data block group sets, the compressed data block group sets and the original data block group sets.

[0014] In order to solve the above problem, the present invention further provides an electronic device, the electronic device comprising: A memory storing at least one instruction; and a processor executing the instruction stored in the memory to implement the above-mentioned FPGA code stream fast compression method.

[0015] In order to solve the above problem, the present invention also provides a computer-readable storage medium, in which at least one instruction is stored. The at least one instruction is executed by a processor in an electronic device to implement the above-mentioned FPGA code stream fast compression method.

[0016] The present invention is to solve the problem described in the background technology. The present invention first needs to parse the original code stream to obtain the data to be compressed, and then divide the data to be compressed according to the number of unit bits to obtain a data block set. At this time, the frame type, region type and row number of each data block can be identified, and the hash value of the data block is calculated using a pre-built encrypted hash algorithm. After obtaining the location information and hash value of the data block, it is necessary to traverse each data block in the data block set. Therefore, the frame type, region type, row number, hash value and data block of the data block can be filled into the initial multi-layer index structure to obtain the target multi-layer index structure, thereby traversing the data block. At this time, the row number can be traversed in the target multi-layer index structure, and the data block group, feature value group and data block number corresponding to the row number can be identified. When compressing the data block group, there are three types of data block group, and different data block group types correspond to different compression methods. First, it is determined whether the number of data blocks is A preset number, if the number of data blocks is the preset number, then determine whether the data block group has a subsequent single data block group set, if the data block group has a subsequent single data block group set, then merge the data block group and the subsequent single data block group set to obtain a merged data block group, if the number of data blocks is not the preset number, then determine whether the same feature value exists in the feature value group, if the same feature value exists in the feature value group, then compress the data block group to obtain a compressed data block group, if the same feature value does not exist in the feature value group, then use the data block group as the original data block group, finally, collect the merged data block group, compressed data block group and original data block group to obtain a merged data block group set, compressed data block group set and original data block group set, and then use the target multi-layer index structure to reorganize the merged data block group set, compressed data block group set and original data block group set to complete the FPGA code stream fast compression. Therefore, the present invention can solve the problem that the overall compression effect of FPGA code stream data is poor and occupies more computing resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of a flow chart of a method for fast compression of FPGA bitstreams provided by an embodiment of the present invention; Figure 2 A target multi-layer index structure provided by an embodiment of the present invention; Figure 3 A schematic diagram of data block group compression provided by an embodiment of the present invention; Figure 4 A functional module diagram of an FPGA code stream fast compression system provided by an embodiment of the present invention; Figure 5 A schematic diagram of the structure of an electronic device for implementing the FPGA code stream fast compression method provided by an embodiment of the present invention.

[0018] Description of reference numerals: 1. Electronic device; 10. Processor; 11. Memory; 12. Bus; 100. FPGA code stream fast compression system; 101. Position information and hash value calculation module; 102. Target multi-layer index structure construction module; 103. Data block group compression module; 104. Code stream reorganization module.

[0019] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0020] It should be understood that the specific embodiments described herein are only used to explain the present invention, and are not used to limit the present invention.

[0021] The embodiment of the present application provides a method for fast compression of FPGA code streams. The execution subject of the method for fast compression of FPGA code streams includes but is not limited to at least one of the electronic devices such as a server and a terminal that can be configured to execute the method provided in the embodiment of the present application. In other words, the method for fast compression of FPGA code streams can be executed by software or hardware installed in a terminal device or a server device, and the software can be a blockchain platform. The server includes but is not limited to: a single server, a server cluster, a cloud server or a cloud server cluster, etc.

[0022] Reference Figure 1 FIG. 1 is a flow chart of a method for rapidly compressing an FPGA bitstream provided by an embodiment of the present invention. In this embodiment, the method for rapidly compressing an FPGA bitstream includes: S1. Parse the pre-constructed original code stream to obtain data to be compressed, and divide the data to be compressed according to a preset number of unit bits to obtain a data block set.

[0023] Furthermore, the unit bit quantity refers to the number of bits written to the storage RAM at one time.

[0024] It is understandable that the original code stream refers to the code stream data of the FPGA, which is designed by the user, and is generated according to the FPGA code stream configuration library after processes such as synthesis, layout, and routing. FPGA chips need to rely on externally written code stream data for configuration. By downloading the original code stream to the corresponding FPGA chip, specific functions can be achieved. FPGA (Field Programmable Gate Array) is widely used in electronic system design.

[0025] It is understandable that the data to be compressed refers to the data to be compressed in the original code stream. The data block set refers to the set of data blocks to be compressed obtained after the data to be compressed is divided according to the number of unit bits. Different from other methods that compress the original code stream using bytes as the basic compression unit, the number of bits of the data block used as the basic compression unit in the embodiment of the present invention is consistent with the number of bits written to the storage RAM at one time, which will greatly simplify the decompression process and improve the efficiency of the entire process.

[0026] In the embodiment of the present invention, the step of parsing the pre-constructed original code stream to obtain the data to be compressed includes: Identifying a specification field in the original bitstream, and extracting a preamble bitstream from the original bitstream according to the specification field; Parsing the pre-stream to obtain pre-information, wherein the pre-information includes: whether the original stream has been compressed, the data specification of the original stream, and the stream length; The data to be compressed is extracted from the original code stream according to the code stream length in the preamble information.

[0027] It can be understood that the specification field refers to a field in the original code stream that records the code stream data specifications. The pre-code stream refers to a code stream that records the pre-information of the original code stream.

[0028] Furthermore, after the extraction of the pre-information is completed, the post-code stream needs to be extracted and stored in the original code stream using the specification field, so as to be combined with the compressed data into a complete code stream.

[0029] S2. Extract data blocks in the data block set in sequence, identify the frame type, region type and row number of the data block, and calculate the hash value of the data block using a pre-built encrypted hash algorithm.

[0030] It is understandable that the frame type (frame_type) refers to the data frame type of the data block, such as: synchronization frame, data packet frame and control frame. The region type (region_type) refers to the logical region or physical region where the data block is stored in the FPGA. The row number (row_num) refers to the position number used to identify the data block in a specific region, reflecting the relative sequential position of the data block in the logical region or physical region. The cryptographic hash algorithm refers to the irreversible cryptographic hash algorithm SHA-256.

[0031] In the embodiment of the present invention, the step of calculating the hash value of the data block by using a pre-built encrypted hash algorithm includes: Using a pre-built cryptographic hash algorithm, the data blocks are concatenated into a binary string of a first preset number of bits; Filling the binary string of the first preset number of digits to obtain a filled string, wherein the length of the filled string is a minimum integer multiple of the second preset number of digits; The hash value of the padding string is calculated according to an encrypted hash algorithm to obtain the hash value of the data block.

[0032] It can be understood that the internal data of each data block is spliced ​​into a binary string of a first preset number of bits through the irreversible encryption hash algorithm SHA-256, and the bits are padded to the minimum integer multiple length of a second preset number of bits, and then the hash value of the padded string is calculated according to the SHA-256 compression function, and the hash value is used as the characteristic value of the data block. The number of bits of the characteristic value is much smaller than the number of bits of the data block, and the characteristic value (hash value) corresponds one-to-one to the data block. Therefore, the characteristic value can reflect the differences and similarities between different data blocks. By comparing the characteristic values, the amount of calculation can be greatly reduced, and the efficiency of comparing the differences and similarities between different data blocks can be improved.

[0033] Preferably, the first preset number of bits is 3232 bits, and the second preset number of bits is 512 bits. The encrypted hash algorithm is a SHA-256 algorithm.

[0034] S3. Fill the frame type, region type, row number, hash value and data block of the data block into the pre-built initial multi-layer index structure to obtain a target multi-layer index structure.

[0035] It can be understood that the initial multi-layer index structure refers to a multi-layer index structure constructed according to the frame type, region type, row number, data block feature value and data block data contained in the data block set. The target multi-layer index structure refers to a multi-layer index structure obtained by storing the hash values ​​and data blocks of all data blocks in the data block set according to the frame type, region type and row number.

[0036] In the embodiment of the present invention, before filling the frame type, region type, row number, hash value and data block of the data block into the pre-built initial multi-layer index structure to obtain the target multi-layer index structure, the method further includes: Identifying a frame type sequence, a region type sequence, and a row number sequence of the data block set; Constructing a frame type hierarchy, a region type hierarchy and a row number hierarchy respectively according to the frame type sequence, the region type sequence and the row number sequence; Associatively indexing the frame type level, the region type level, and the line number level to obtain an index level; Constructing a data block feature value hierarchy and a data block data hierarchy; The initial multi-layer index structure is constructed according to the index level, the data block feature value level and the data block data level.

[0037] It can be understood that the frame type sequence, region type sequence and row number sequence refer to the sequence of frame types, region types and row numbers corresponding to each data block in the data block set, respectively. The frame type hierarchy refers to the hierarchy where the index item is the frame type, the region type hierarchy refers to the hierarchy where the index item is the region type, and the row number hierarchy refers to the hierarchy where the index item is the row number. The associated index refers to the inclusive pointing association of the frame type, region type and row number in the frame type hierarchy, region type hierarchy and row number hierarchy. For example, when the frame type type0 contains region types Top and bottom, the region type Top contains row numbers row1, row2, row3, and the region type bottom contains row numbers row1, row2, row3, row4 and row5, the associated index can be frame type type0 pointing to region type Top, and region type Top pointing to row numbers row1, row2 and row3 respectively; frame type type0 pointing to region type bottom, and region type bottom pointing to row numbers row1, row2, row3, row4 and row5 respectively. Please refer to Figure 2 As shown, according to the actual storage location distribution rule of the original code stream in the storage RAM, the location information of each data block can be calculated and recorded as the index values ​​of the first three layers, the first layer is the frame type, the second layer is the area type, and the third layer is the row number.

[0038] Furthermore, the index level refers to a three-layer index structure obtained after the frame type level, the region type level and the line number level complete the inclusive pointing association. The data block feature value level refers to the level where the index item is the data block feature value, and the data block data level refers to the level where the index item is the data block data.

[0039] It can be explained that the embodiment of the present invention constructs an initial multi-layer index structure of multi-dimensional data to index data blocks, and the multi-layer index of the data block is stored in a dictionary form, wherein the first three layers of indexes are the corresponding position information of the data block in the FPGA memory, the fourth layer of indexes are the data block feature values, and the fifth layer of indexes are the data block data.

[0040] In the embodiment of the present invention, the step of filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure includes: identifying a frame type level position of the frame type in the frame type level, identifying a region type level position of the region type in the region type level, and identifying a line number level position of the line number in the line number level; Determine an index path of the hash value according to the frame type level position, the region type level position and the line number level position; Identify, according to the index path, the feature value level position and the data level position of the hash value at the data block feature value level and the data block data level respectively; The hash value is filled into the characteristic value level position, and the data block is filled into the data level position until all the data blocks in the data block set are filled in, thereby obtaining a target multi-layer index structure.

[0041] It can be understood that the frame type level position refers to the position of the frame type in the frame type level, the region type level position refers to the position of the region type in the region type level, and the row number level position refers to the position of the row number in the row number level. The index path refers to an index route formed by connecting the frame type level position, the region type level position and the row number level position, which is used to determine the hash value and data block data. For example, when the frame type of the data block is type0, the region type is Top, and the row number is row1, the index path is type0Toprow1 hash value (data block feature value) data block data, which can be referred to Figure 2 The characteristic value level position refers to the position of the data block characteristic value in the data block characteristic value level, and the data level position refers to the position of the data block data in the data block data level.

[0042] S4. Traverse the row numbers in the target multi-layer index structure to identify the data block group, feature value group and data block quantity corresponding to the row number.

[0043] It can be understood that the data block group refers to all data block combinations contained under the row number, the feature value group refers to the feature value combination corresponding to the data block group, and the number of data blocks refers to the number of data blocks in the data block group.

[0044] In the embodiment of the present invention, traversing the row numbers in the target multi-layer index structure to identify the data block group, the feature value group and the number of data blocks corresponding to the row numbers includes: Extracting the frame types to be traversed in sequence from the frame type sequence, and identifying the region type sequence to be traversed contained in the frame types to be traversed; Extracting the area types to be traversed in sequence from the area type sequence to be traversed, and identifying the row number sequence to be traversed contained in the area type to be traversed; The row numbers to be traversed are sequentially extracted from the sequence of row numbers to be traversed, and the characteristic value groups, data block groups and the number of data blocks corresponding to the row numbers to be traversed are identified.

[0045] It can be understood that the row numbers in the multi-layer index structure can be traversed from top to bottom. For example, first fix frame type 1, region type 1, and row number 1, and then traverse the feature values ​​of each data block included in frame type 1, region type 1 and row number 1. After that, change to another row number 2 under region type 1 to traverse until all row numbers under region type 1 are traversed, change to region type 2, and fix row number 1 under region type 2, traverse each data block feature value of row number 1 under region type 2, until all data block feature values ​​contained in all region types under all frame type 1 are traversed, then change frame type 2 to continue traversing until all data block feature values ​​contained in all frame type sequences are traversed.

[0046] S5. Determine whether the number of data blocks is a preset number.

[0047] Preferably, the preset number is 1.

[0048] If the number of the data blocks is the preset number, then S6 is executed to determine whether there is a subsequent single data block group set in the data block group.

[0049] In detail, the subsequent single data block group set refers to a set of data block groups whose number of data blocks subsequent to the data block group is a preset number.

[0050] For example, when the frame type of the data block is type0, the area type is Top, the row number is row1, and the index path corresponding to type0, Top, and row1 contains only one data block feature value a, it means that the number of data blocks is a preset number; when the index path corresponding to type0, Top, and row2 contains only one data block feature value b; the index path corresponding to type0, Top, and row3 contains only one data block feature value c; the index path corresponding to type0, Top, and row4 contains only one data block feature value d; and the index path corresponding to type0, Top, and row5 contains two data block feature values ​​e and f, the subsequent single data block group is a set of data blocks corresponding to b, c, and d.

[0051] In the embodiment of the present invention, the determining whether the data block group has a subsequent single data block group set includes: Identify a subsequent row number of the row number, and obtain a data block group corresponding to the subsequent row number; Identify the number of data blocks in the data block group corresponding to the subsequent row number; Determine whether the number of data blocks in the data block group corresponding to the subsequent row number is 1; If the number of data blocks in the data block group corresponding to the subsequent row number is not 1, then there is no subsequent single data block group set in the data block group; If the number of data blocks in the data block group corresponding to the subsequent row number is 1, then the data block group has a subsequent single data block group set.

[0052] It is understandable that the subsequent row number refers to the next adjacent row number of the row number. For example, when the index path of the row number is type0, Top, row1, the index path of the subsequent row number may be type0, Top, row2.

[0053] If the data block group has a subsequent single data block group set, then S7 is executed to merge the data block group and the subsequent single data block group set to obtain a merged data block group.

[0054] In the embodiment of the present invention, the merged data block group refers to a combination of the data block group and its subsequent single data block group set.

[0055] If the data block group does not have a subsequent single data block group set, then S8 is executed to use the data block group as the original data block group.

[0056] It can be explained that when the number of data blocks is the preset number and there is no subsequent single data block group set in the data block group, the data block group is not compressed.

[0057] If the number of data blocks is not the preset number, executing S9, determining whether there is an identical eigenvalue in the eigenvalue group.

[0058] If the same eigenvalue exists in the eigenvalue group, S10 is executed to compress the data block group to obtain a compressed data block group.

[0059] It can be understood that the compressed data block group refers to a data block group obtained after compressing data blocks corresponding to the same characteristic value.

[0060] In the embodiment of the present invention, compressing the data block group to obtain the compressed data block group includes: Among multiple specific data blocks having the same characteristic value, obtaining position information of remaining specific data blocks after the first specific data block; A compressed data block group is obtained according to the content of the specific data block and the position information of the remaining specific data blocks.

[0061] Furthermore, when the number of data blocks with the same characteristic value in the data block group is greater than 1, the first data block data and the position information of each data block can be selected from the data block group, and then the two items can be recombined to obtain a new data block group, and the new data block group can be used to replace the old data block group, thereby obtaining a compressed code stream. The first data block data (not compressed) is retained according to the order of the data blocks in the data block group, and the remaining repeated data blocks are used as compressed data blocks, and replaced with characters reflecting their position information. For details, see Figure 3 shown.

[0062] For example, when the data block group is ABAAB, the 1st, 3rd, and 4th data blocks have the same characteristic value and can be classified as the 1st compression group. The 2nd and 5th data blocks have the same characteristic value and can be classified as the 2nd compression group. The code stream obtained after compressing the 1st compression group is A+addr3,4, and the code stream obtained after compressing the 2nd compression group is B+addr5, thereby achieving the purpose of replacing repeated data blocks with short position information and completing the compression of the data block group.

[0063] If the same eigenvalue does not exist in the eigenvalue group, S11 is executed to use the data block group as the original data block group.

[0064] It is understandable that when the same characteristic value does not exist in the characteristic value group and the number of data blocks is not a preset number, the data block group is not compressed.

[0065] S12, collecting the merged data block groups, compressed data block groups and original data block groups to obtain merged data block group sets, compressed data block group sets and original data block group sets, and using the target multi-layer index structure to reorganize the code stream of the merged data block group sets, compressed data block group sets and original data block group sets to complete FPGA code stream fast compression.

[0066] In the embodiment of the present invention, the step of reorganizing the code streams of the merged data block set, the compressed data block set and the original data block set by using the target multi-layer index structure includes: Identify the code stream sequence of the merged data block group, the compressed data block group and the original data block group in the merged data block group set, the compressed data block group set and the original data block group set according to the target multi-layer index structure; Combining the merged data block set, the compressed data block set and the original data block set according to the code stream sequence to obtain a data block group sequence; Obtaining code stream specification information of the data block group sequence; Identify the head bit position and the tail bit position of the data block group sequence, and add the code stream specification information to the head bit position and the tail bit position of the data block group sequence to obtain an initial recombined code stream; Calculate the cyclic redundancy check information of the data block group sequence, identify the tail position of the initial reorganized code stream, add the cyclic redundancy check information to the tail position of the initial reorganized code stream, and complete the code stream reorganization.

[0067] It can be understood that the code stream order refers to the order of the merged data block group, compressed data block group and original data block group from top to bottom in the target multi-layer index structure. For example: when the row numbers of the merged data block group corresponding to the frame type type0 and the region type Top are row3, row4, row5, the row numbers of the compressed data block group 1 and the compressed data block group 2 are row1, row2, and the row number of the original data block group is row6, then the code stream order is compressed data block group 1, compressed data block group 2, merged data block group, original data block group, and the data block group sequence is compressed data block group 1, compressed data block group 2, merged data block group, original data block group. The head bit refers to the head bit of the new code stream composed of the data block group sequence, and the tail bit refers to the tail bit of the new code stream composed of the data block group sequence. The cyclic redundancy check information can be calculated based on the information of the newly generated initial reorganized code stream. After all data frames are configured, the code stream specification information is added to the head and tail of the new code stream, and the cyclic redundancy check information is added after the code stream specification information at the tail, thus completing the compression of the entire original code stream.

[0068] The present invention is to solve the problem described in the background technology. The present invention first needs to parse the original code stream to obtain the data to be compressed, and then divide the data to be compressed according to the number of unit bits to obtain a data block set. At this time, the frame type, region type and row number of each data block can be identified, and the hash value of the data block is calculated using a pre-built encrypted hash algorithm. After obtaining the location information and hash value of the data block, it is necessary to traverse each data block in the data block set. Therefore, the frame type, region type, row number, hash value and data block of the data block can be filled into the initial multi-layer index structure to obtain the target multi-layer index structure, thereby traversing the data block. At this time, the row number can be traversed in the target multi-layer index structure, and the data block group, feature value group and data block number corresponding to the row number can be identified. When compressing the data block group, there are three types of data block group, and different data block group types correspond to different compression methods. First, it is determined whether the number of data blocks is A preset number, if the number of data blocks is the preset number, then determine whether the data block group has a subsequent single data block group set, if the data block group has a subsequent single data block group set, then merge the data block group and the subsequent single data block group set to obtain a merged data block group, if the number of data blocks is not the preset number, then determine whether the same feature value exists in the feature value group, if the same feature value exists in the feature value group, then compress the data block group to obtain a compressed data block group, if the same feature value does not exist in the feature value group, then use the data block group as the original data block group, finally, collect the merged data block group, compressed data block group and original data block group to obtain a merged data block group set, compressed data block group set and original data block group set, and then use the target multi-layer index structure to reorganize the merged data block group set, compressed data block group set and original data block group set to complete the FPGA code stream fast compression. Therefore, the present invention can solve the problem that the overall compression effect of FPGA code stream data is poor and occupies more computing resources.

[0069] like Figure 4 , which is a functional module diagram of an FPGA code stream fast compression system provided by an embodiment of the present invention.

[0070] The FPGA code stream fast compression system 100 of the present invention can be installed in an electronic device. According to the functions to be implemented, the FPGA code stream fast compression system 100 can include a position information and hash value calculation module 101, a target multi-layer index structure construction module 102, a data block group compression module 103 and a code stream reorganization module 104. The module of the present invention can also be called a unit, which refers to a series of computer program segments that can be executed by an electronic device processor and can complete fixed functions, which are stored in the memory of the electronic device.

[0071] The position information and hash value calculation module 101 is used to parse the pre-constructed original code stream to obtain the data to be compressed, divide the data to be compressed according to a preset unit bit number to obtain a data block set, wherein the unit bit number refers to the number of bits written to the storage RAM at one time, extract data blocks in the data block set in sequence, identify the frame type, region type and row number of the data block, and calculate the hash value of the data block using the pre-constructed encrypted hash algorithm; The target multi-layer index structure construction module 102 is used to fill the frame type, region type, row number, hash value and data block of the data block into the pre-constructed initial multi-layer index structure to obtain a target multi-layer index structure; The data block group compression module 103 is used to traverse the row number in the target multi-layer index structure, identify the data block group, feature value group and data block number corresponding to the row number; determine whether the data block number is a preset number; if the data block number is a preset number, determine whether the data block group has a subsequent single data block group set, and the subsequent single data block group set refers to a set of data block groups whose subsequent data block number is a preset number; if the data block group has a subsequent single data block group set, merge the data block group and the subsequent single data block group set to obtain a merged data block group; if the data block group does not have a subsequent single data block group set, use the data block group as the original data block group; if the data block number is not the preset number, determine whether the feature value group has the same feature value; if the feature value group has the same feature value, compress the data block group to obtain a compressed data block group; if the feature value group does not have the same feature value, use the data block group as the original data block group; The code stream reassembly module 104 is used to collect the merged data block groups, compressed data block groups and original data block groups to obtain merged data block group sets, compressed data block group sets and original data block group sets, and use the target multi-layer index structure to perform code stream reassembly on the merged data block group sets, compressed data block group sets and original data block group sets.

[0072] In detail, each module in the FPGA code stream fast compression system 100 in the embodiment of the present invention is used in the same manner as described above. Figure 1 The FPGA code stream fast compression method described in the previous section has the same technical means and can produce the same technical effects, so I will not go into details here.

[0073] like Figure 5 FIG. 1 is a schematic diagram of the structure of an electronic device for implementing a method for fast compression of FPGA code streams provided by an embodiment of the present invention.

[0074] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as an FPGA code stream fast compression method program.

[0075] The memory 11 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a mobile hard disk, a multimedia card, a card-type memory (e.g., SD or DX memory, etc.), a magnetic memory, a disk, an optical disk, etc. In some embodiments, the memory 11 may be an internal storage unit of the electronic device 1, such as a mobile hard disk of the electronic device 1. In other embodiments, the memory 11 may also be an external storage device of the electronic device 1, such as a plug-in mobile hard disk, a smart memory card (Smart Media Card, SMC), a secure digital (SecureDigital, SD) card, a flash card (Flash Card), etc. equipped on the electronic device 1. Further, the memory 11 also includes an internal storage unit of the electronic device 1 and an external storage device. The memory 11 can not only be used to store application software and various types of data installed in the electronic device 1, such as the code of the FPGA code stream fast compression method program, etc., but also can be used to temporarily store data that has been output or is to be output.

[0076] The processor 10 may be composed of an integrated circuit in some embodiments, for example, a single packaged integrated circuit, or a plurality of packaged integrated circuits with the same or different functions, including one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and combinations of various control chips, etc. The processor 10 is the control core (Control Unit) of the electronic device, and uses various interfaces and lines to connect various components of the entire electronic device, and executes or executes programs or modules (such as FPGA code stream fast compression method programs, etc.) stored in the memory 11, and calls data stored in the memory 11 to execute various functions of the electronic device 1 and process data.

[0077] The bus 12 may be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 may be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize connection and communication between the memory 11 and at least one processor 10, etc.

[0078] Figure 5 Only an electronic device with components is shown, and those skilled in the art will understand that Figure 5 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown in the figure, or combine certain components, or arrange the components differently.

[0079] For example, although not shown, the electronic device 1 may also include a power source (such as a battery) for supplying power to various components. Preferably, the power source may be logically connected to the at least one processor 10 through a power management device, so that the power management device can realize functions such as charging management, discharging management, and power consumption management. The power source may also include one or more DC or AC power sources, recharging devices, power failure detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include a variety of sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be repeated here.

[0080] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a WI-FI interface, a Bluetooth interface, etc.), which is generally used to establish a communication connection between the electronic device 1 and other electronic devices.

[0081] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), or a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, and an OLED (Organic Light-Emitting Diode) touch device. The display may also be appropriately referred to as a display screen or a display unit, which is used to display information processed in the electronic device 1 and to display a visual user interface.

[0082] The FPGA code stream fast compression method program stored in the memory 11 in the electronic device 1 is a combination of multiple instructions. When running in the processor 10, it can achieve: Parsing the pre-constructed original code stream to obtain data to be compressed, dividing the data to be compressed according to a preset unit bit number to obtain a data block set, wherein the unit bit number refers to the number of bits written to the storage RAM at one time; Extracting data blocks in the data block set in sequence, identifying the frame type, region type and row number of the data block, and calculating the hash value of the data block using a pre-built cryptographic hash algorithm; Filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure; Traversing the row numbers in the target multi-layer index structure, identifying the data block group, feature value group and number of data blocks corresponding to the row numbers; Determining whether the number of data blocks is a preset number; If the number of data blocks is a preset number, determining whether the data block group has a subsequent single data block group set, the subsequent single data block group set refers to a set of data block groups whose number of data blocks subsequent to the data block group is a preset number; If the data block group has a subsequent single data block group set, merging the data block group and the subsequent single data block group set to obtain a merged data block group; If there is no subsequent single data block group set for the data block group, the data block group is used as the original data block group; If the number of data blocks is not the preset number, determining whether there are identical eigenvalues ​​in the eigenvalue group; If the same eigenvalue exists in the eigenvalue group, compressing the data block group to obtain a compressed data block group; If the same eigenvalue does not exist in the eigenvalue group, the data block group is used as the original data block group; The merged data block groups, compressed data block groups and original data block groups are collected to obtain merged data block group sets, compressed data block group sets and original data block group sets, and the merged data block group sets, compressed data block group sets and original data block group sets are reorganized into code streams using the target multi-layer index structure to complete the FPGA code stream fast compression.

[0083] Specifically, the specific implementation method of the processor 10 for the above instructions can refer to Figures 1 to 5 The description of the relevant steps in the corresponding embodiments will not be repeated here.

[0084] Furthermore, if the module / unit integrated in the electronic device 1 is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium can include: any entity or device capable of carrying the computer program code, a recording medium, a USB flash drive, a mobile hard disk, a magnetic disk, an optical disk, a computer memory, and a read-only memory (ROM).

[0085] The present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor of an electronic device, the computer program can implement: Parsing the pre-constructed original code stream to obtain data to be compressed, dividing the data to be compressed according to a preset unit bit number to obtain a data block set, wherein the unit bit number refers to the number of bits written to the storage RAM at one time; Extracting data blocks in the data block set in sequence, identifying the frame type, region type and row number of the data block, and calculating the hash value of the data block using a pre-built cryptographic hash algorithm; Filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure; Traversing the row numbers in the target multi-layer index structure, identifying the data block group, feature value group and number of data blocks corresponding to the row numbers; Determining whether the number of data blocks is a preset number; If the number of data blocks is a preset number, determining whether the data block group has a subsequent single data block group set, the subsequent single data block group set refers to a set of data block groups whose number of data blocks subsequent to the data block group is a preset number; If the data block group has a subsequent single data block group set, merging the data block group and the subsequent single data block group set to obtain a merged data block group; If there is no subsequent single data block group set for the data block group, the data block group is used as the original data block group; If the number of data blocks is not the preset number, determining whether there are identical eigenvalues ​​in the eigenvalue group; If the same eigenvalue exists in the eigenvalue group, compressing the data block group to obtain a compressed data block group; If the same eigenvalue does not exist in the eigenvalue group, the data block group is used as the original data block group; The merged data block groups, compressed data block groups and original data block groups are collected to obtain merged data block group sets, compressed data block group sets and original data block group sets, and the merged data block group sets, compressed data block group sets and original data block group sets are reorganized into code streams using the target multi-layer index structure to complete the FPGA code stream fast compression.

[0086] In the several embodiments provided by the present invention, it should be understood that the disclosed devices, systems and methods can be implemented in other ways. For example, the system embodiments described above are only illustrative, and actual implementation may have other division methods.

[0087] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0088] In addition, each functional module in each embodiment of the present invention may be integrated into one processing unit, each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0089] It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention.

Claims

1. A method for fast compression of FPGA code stream, characterized in that: The method comprises: Parsing the pre-constructed original code stream to obtain data to be compressed, dividing the data to be compressed according to a preset unit bit number to obtain a data block set, wherein the unit bit number refers to the number of bits written to the storage RAM at one time; Extracting data blocks in the data block set in sequence, identifying the frame type, region type and row number of the data block, and calculating the hash value of the data block using a pre-built cryptographic hash algorithm; Filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure; Traversing the row numbers in the target multi-layer index structure, identifying the data block group, feature value group and number of data blocks corresponding to the row numbers; Determining whether the number of data blocks is a preset number; If the number of data blocks is a preset number, determining whether the data block group has a subsequent single data block group set, the subsequent single data block group set refers to a set of data block groups whose number of data blocks subsequent to the data block group is a preset number; If the data block group has a subsequent single data block group set, merging the data block group and the subsequent single data block group set to obtain a merged data block group; If there is no subsequent single data block group set for the data block group, the data block group is used as the original data block group; If the number of data blocks is not the preset number, determining whether there are identical eigenvalues ​​in the eigenvalue group; If the same eigenvalue exists in the eigenvalue group, compressing the data block group to obtain a compressed data block group; If the same eigenvalue does not exist in the eigenvalue group, the data block group is used as the original data block group; The merged data block groups, compressed data block groups and original data block groups are collected to obtain merged data block group sets, compressed data block group sets and original data block group sets, and the merged data block group sets, compressed data block group sets and original data block group sets are reorganized into code streams using the target multi-layer index structure to complete the FPGA code stream fast compression.

2. The FPGA code stream fast compression method according to claim 1, characterized in that: The parsing of the pre-constructed original code stream to obtain the data to be compressed includes: Identifying a specification field in the original bitstream, and extracting a preamble bitstream from the original bitstream according to the specification field; Parsing the pre-stream to obtain pre-information, wherein the pre-information includes: whether the original stream has been compressed, the data specification of the original stream, and the stream length; The data to be compressed is extracted from the original code stream according to the code stream length in the preamble information.

3. The FPGA code stream fast compression method according to claim 1, characterized in that: The calculating the hash value of the data block by using a pre-built cryptographic hash algorithm comprises: Using a pre-built cryptographic hash algorithm, the data blocks are concatenated into a binary string of a first preset number of bits; Filling the binary string of the first preset number of digits to obtain a filled string, wherein the length of the filled string is a minimum integer multiple of the second preset number of digits; The hash value of the padding string is calculated according to an encrypted hash algorithm to obtain the hash value of the data block.

4. The FPGA code stream fast compression method according to claim 1, characterized in that: Before filling the frame type, region type, row number, hash value and data block of the data block into the pre-built initial multi-layer index structure to obtain the target multi-layer index structure, the method further includes: Identifying a frame type sequence, a region type sequence, and a row number sequence of the data block set; Constructing a frame type hierarchy, a region type hierarchy and a row number hierarchy respectively according to the frame type sequence, the region type sequence and the row number sequence; Associatively indexing the frame type level, the region type level, and the line number level to obtain an index level; Constructing a data block feature value hierarchy and a data block data hierarchy; The initial multi-layer index structure is constructed according to the index level, the data block feature value level and the data block data level.

5. The FPGA code stream fast compression method as claimed in claim 4, characterized in that: The step of filling the frame type, region type, row number, hash value and data block of the data block into a pre-built initial multi-layer index structure to obtain a target multi-layer index structure includes: identifying a frame type level position of the frame type in the frame type level, identifying a region type level position of the region type in the region type level, and identifying a line number level position of the line number in the line number level; Determine an index path of the hash value according to the frame type level position, the region type level position and the line number level position; Identify the feature value level position and the data level position of the hash value at the data block feature value level and the data block data level respectively according to the index path; The hash value is filled into the characteristic value level position, and the data block is filled into the data level position until all the data blocks in the data block set are filled in, thereby obtaining a target multi-layer index structure.

6. The FPGA code stream fast compression method as claimed in claim 5, characterized in that: The traversing the row numbers in the target multi-layer index structure to identify the data block group, the feature value group and the number of data blocks corresponding to the row numbers includes: Extracting the frame types to be traversed in sequence from the frame type sequence, and identifying the region type sequence to be traversed contained in the frame types to be traversed; Extracting the area types to be traversed in sequence from the area type sequence to be traversed, and identifying the row number sequence to be traversed contained in the area type to be traversed; The row numbers to be traversed are sequentially extracted from the sequence of row numbers to be traversed, and the characteristic value groups, data block groups and the number of data blocks corresponding to the row numbers to be traversed are identified.

7. The FPGA code stream fast compression method according to claim 1, characterized in that: The determining whether the data block group has a subsequent single data block group set includes: Identify a subsequent row number of the row number, and obtain a data block group corresponding to the subsequent row number; Identify the number of data blocks in the data block group corresponding to the subsequent row number; Determine whether the number of data blocks in the data block group corresponding to the subsequent row number is 1; If the number of data blocks in the data block group corresponding to the subsequent row number is not 1, then there is no subsequent single data block group set in the data block group; If the number of data blocks in the data block group corresponding to the subsequent row number is 1, then the data block group has a subsequent single data block group set.

8. The FPGA code stream fast compression method according to claim 1, characterized in that: The step of compressing the data block group to obtain a compressed data block group includes: Among multiple specific data blocks having the same characteristic value, obtaining position information of remaining specific data blocks after the first specific data block; A compressed data block group is obtained according to the content of the specific data block and the position information of the remaining specific data blocks.

9. The FPGA code stream fast compression method according to claim 8, characterized in that: The step of using the target multi-layer index structure to reorganize the merged data block set, the compressed data block set and the original data block set into a code stream comprises: Identify the code stream sequence of the merged data block group, the compressed data block group and the original data block group in the merged data block group set, the compressed data block group set and the original data block group set according to the target multi-layer index structure; Combining the merged data block set, the compressed data block set and the original data block set according to the code stream sequence to obtain a data block group sequence; Obtaining code stream specification information of the data block group sequence; Identify the head bit position and the tail bit position of the data block group sequence, and add the code stream specification information to the head bit position and the tail bit position of the data block group sequence to obtain an initial recombined code stream; Calculate the cyclic redundancy check information of the data block group sequence, identify the tail position of the initial reorganized code stream, add the cyclic redundancy check information to the tail position of the initial reorganized code stream, and complete the code stream reorganization.

10. An FPGA code stream fast compression system, characterized in that: The system comprises: A position information and hash value calculation module is used to parse the pre-constructed original code stream to obtain data to be compressed, divide the data to be compressed according to a preset unit bit number to obtain a data block set, wherein the unit bit number refers to the number of bits written to the storage RAM at one time, extract data blocks in the data block set in sequence, identify the frame type, region type and row number of the data block, and calculate the hash value of the data block using a pre-constructed encrypted hash algorithm; A target multi-layer index structure construction module is used to fill the frame type, region type, row number, hash value and data block of the data block into the pre-constructed initial multi-layer index structure to obtain a target multi-layer index structure; a data block group compression module, for traversing the row number in the target multi-layer index structure, identifying the data block group, the characteristic value group and the number of data blocks corresponding to the row number; judging whether the number of data blocks is a preset number; if the number of data blocks is a preset number, judging whether the data block group has a subsequent single data block group set, the subsequent single data block group set refers to a set of data block groups whose subsequent number of data blocks of the data block group is a preset number; if the data block group has a subsequent single data block group set, merging the data block group with the subsequent single data block group set to obtain a merged data block group; if the data block group does not have a subsequent single data block group set, taking the data block group as the original data block group; if the number of data blocks is not a preset number, judging whether the same characteristic value exists in the characteristic value group; if the same characteristic value exists in the characteristic value group, compressing the data block group to obtain a compressed data block group; if the same characteristic value does not exist in the characteristic value group, taking the data block group as the original data block group; The code stream reorganization module is used to collect the merged data block groups, the compressed data block groups and the original data block groups to obtain the merged data block group sets, the compressed data block group sets and the original data block group sets, and use the target multi-layer index structure to perform code stream reorganization on the merged data block group sets, the compressed data block group sets and the original data block group sets.

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