Data encoding and decoding method and device

Abstract

The invention relates to the field of data coding and decoding, in particular to a data coding and decoding method and device. The method comprises the following steps: acquiring to-be-coded first data; the first data is an N-bit binary number; calculating a first code of M bits corresponding to the first data according to a first preset coding rule; the first preset coding rule is a coding rule used for generating an error correction code; obtaining a second code according to the first code; the second code is a result obtained by performing XOR operation on the first code and a first preset value; the first preset numerical value is a result obtained by carrying out XOR operation on a second preset numerical value and an M-bit 1 binary number; the second preset numerical value is an M-bit code corresponding to an N-bit 1 binary number calculated according to the first preset coding rule; and determining coded data corresponding to the first data, wherein the coded data comprises the first data and the second code.

Description

Technical Field

[0001] The present application relates to the field of data encoding and decoding, and in particular to a data encoding and decoding method and device. Background Art

[0002] At present, with the increasing demand for high-reliability memory chips in consumer electronic products, the requirements for data storage time and erase and write cycles of memory chips are also increasing. In addition, with the increasing integration of chip processes, the design requirements for memory chips in terms of process size and low power consumption are also increasing. Under the premise of continuously optimizing chip area and power consumption, improving the reliability of chip storage has become a challenge in the design and manufacture of non-volatile memory chips.

[0003] At present, more and more non-volatile memory chips on the market use error correction code encoding and decoding to ensure storage reliability. The error correction codes for correcting 1-bit errors include Hamming code, Hsiao code, and cyclic redundancy check code. The error correction codes for correcting multi-bit errors include BCH code, RS code, and LDPC code.

[0004] Among them, the erasing process of non-volatile storage is to uniformly erase the data in the storage unit to data 1, which makes the data bits of the user data in the storage unit and the data bits of the encoding corresponding to the user data both 1, while the data bits of the user data and the data bits of the encoding are both 1, which usually does not comply with the encoding rules.

[0005] Taking 128 bits of user data as an example, the Hamming code corresponding to the 128-bit binary number of all 1s is 01110111. It can be seen that if the data bits of the user data and the encoded data bits are both 1, it does not comply with the encoding rules of the Hamming code.

[0006] Therefore, in the prior art, the erased stored data cannot be corrected by Hamming code, and even erroneous correction may occur. Summary of the invention

[0007] In order to solve the above technical problems, the present application provides a data encoding and decoding method and device.

[0008] In a first aspect, a data encoding method is provided, the method comprising: obtaining first data to be encoded; the first data is an N-bit binary number; according to a first preset encoding rule, calculating an M-bit first code corresponding to the first data; the first preset encoding rule is a coding rule for generating an error correction code; according to the first code, a second code is obtained; the second code is a result of an XOR operation of the first code and a first preset value; the first preset value is a result of an XOR operation of a second preset value and an M-bit 1 binary number; the second preset value is an M-bit code corresponding to an N-bit 1 binary number calculated according to the first preset encoding rule; and determining the encoded data corresponding to the first data, the encoded data comprising: the first data and the second code.

[0009] In some implementations, the method also includes: determining whether all data bits in the first storage space used to write the encoded data are 1; if there is 0 in each data bit in the first storage space, generating the M-bit first code corresponding to the first data according to the second preset coding rule; wherein the second preset coding rule includes: setting the preset data bit set in the first code to a third preset value; the preset data bit set includes: data bits at multiple preset positions in the first code; calculating the M-bit first code corresponding to the first data according to the first preset coding rule includes: if all data bits in the first storage space are 1, calculating the M-bit first code corresponding to the first data according to the first preset coding rule.

[0010] In some implementations, the calculating of the M-bit first code corresponding to the first data according to the first preset coding rule includes: calculating the third code corresponding to the first data; the third code is a redundant bit value obtained by performing Hamming code encoding on the first data; judging whether the third code is equal to the third preset value; if the third code is equal to the third preset value, determining that the preset data bit set in the first code is a fourth preset value, and determining that the first data bit in the first code is an odd parity bit of the first data and the preset data bit set; the fourth preset value is a preset value greater than the decimal number N+M; the first data bit is a data bit at a preset position in the first code; if the third code is not equal to the third preset value, determining that the preset data bit set in the first code is the third code, and determining that the first data bit in the first code is an even parity bit of the first data and the preset data bit set.

[0011] In some implementations, the method further includes: determining a second data bit in the first encoding based on the first data bit and the preset data bit set; wherein the second data bit is an odd check bit or an even check bit of the first data bit and the preset data bit set.

[0012] In some implementations, the method further includes: programming the second encoding to write data bits other than the target data bit in the second encoding into the first storage space; wherein the target data bit is any data bit in the second encoding that is 0; encoding the first data to write the first data into the first storage space; programming the second encoding to write the target data bit into the first storage space.

[0013] In a second aspect, a data decoding method is provided, the method comprising: acquiring coded data; the coded data comprising first acquisition data and a first acquisition code; obtaining a second acquisition code according to the first acquisition code; the second acquisition code being the result of an XOR operation between the first acquisition code and a first preset value; the first preset value being the result of an XOR operation between the second preset value and an M-bit 1 binary number; the second preset value being the M-bit code corresponding to the N-bit 1 binary number calculated according to the first preset coding rule; determining a decoding result corresponding to the first acquisition data according to a preset decoding rule and the second acquisition code; the preset decoding rule being a decoding rule corresponding to the first preset coding rule.

[0014] In some implementations, the method also includes: determining whether a preset data bit set in the second acquisition code is a third preset value; the preset data bit set includes: data bits at multiple preset positions in the second acquisition code; if the preset data bit set in the second acquisition code is the third preset value, determining that the decoding result corresponding to the first acquisition data is the first acquisition data; determining the decoding result corresponding to the first acquisition data according to the preset decoding rule and the second acquisition code includes: if the preset data bit set in the second acquisition code is not the third preset value, determining the decoding result corresponding to the first acquisition data according to the preset decoding rule and the second acquisition code.

[0015] In some implementations, determining a decoding result corresponding to the first acquired data according to a preset decoding rule and the second acquired code includes: determining whether the preset data bit set is a fourth preset value, and performing a parity check on the preset data bit set, the first acquired data, and the first data bit; the first data bit is a data bit at a preset position in the second acquired code; if the preset data bit set is not the fourth preset value, and the preset data bit set, the first acquired data, and the first data bit satisfy an even check, determining that the decoding result corresponding to the first acquired data is the first acquired data; if the preset data bit set is not the fourth preset value, and the preset data bit set, the first acquired data, and the first data bit satisfy an odd check, performing 1-bit data error correction on the preset data bit set and the first acquired data according to the Hamming code decoding rule to obtain a decoding result corresponding to the first acquired data; if the preset data bit set is the fourth preset value, and the preset data bit set , if the first acquired data and the first data bit satisfy even parity, then determine whether the error correction decoded data is a binary number of all 0s; wherein the error correction decoded data is: error correction decoded data obtained by decoding the preset data bit set and the first acquired data according to the Hamming code decoding rule; if the error correction decoded data is a binary number of all 0s, then determine that the decoding result corresponding to the first acquired data is the first acquired data; if the error correction decoded data is not a binary number of all 0s, then use the Hamming code decoding rule and the third acquisition code to perform 1-bit data error correction on the first acquired data to obtain the decoding result corresponding to the first acquired data; the third acquisition code is the result of an exclusive OR operation between the error correction decoded data and the fourth preset value; if the preset data bit set is the fourth preset value, and the preset data bit set, the first acquired data and the first data bit satisfy odd parity, then decode the preset data bit set and the first acquired data according to the Hamming code decoding rule to obtain the decoding result corresponding to the first acquired data.

[0016] In some implementations, the method further includes: determining whether the preset data bit set, the first data bit, and the second data bit in the second acquisition code comply with a preset parity check rule; the preset parity check rule is odd check or even check; if the preset data bit set, the first data bit, and the second data bit in the second acquisition code do not comply with the preset parity check rule, determining that the decoding result corresponding to the first acquisition data is the first acquisition data; determining whether the preset data bit set in the second acquisition code is a fourth preset value, and performing a parity check on the preset data bit set, the first acquisition data, and the first data bit in the second acquisition code, includes: if the preset data bit set, the first data bit, and the second data bit in the second acquisition code comply with the preset parity check rule, determining whether the preset data bit set in the second acquisition code is a fourth preset value, and performing a parity check on the preset data bit set, the first acquisition data, and the first data bit in the second acquisition code.

[0017] In a third aspect, a data processing device is provided, including: an acquisition unit, used to acquire first data to be encoded; the first data is an N-bit binary number; a processing unit, used to calculate the M-bit first code corresponding to the first data according to a first preset coding rule; the first preset coding rule is a coding rule for generating an error correction code; a processing unit, used to obtain a second code according to the first code; the second code is the result of an XOR operation of the first code and a first preset value; the first preset value is the result of an XOR operation of a second preset value and an M-bit 1 binary number; the second preset value is the M-bit code corresponding to the N-bit 1 binary number calculated according to the first preset coding rule; the processing unit is used to determine the coded data corresponding to the first data, the coded data including: the first data and the second code.

[0018] In some implementations, the processing unit is also used to determine whether all data bits in the first storage space used to write the encoded data are 1; the processing unit is used to generate the M-bit first code corresponding to the first data according to the second preset coding rule if there is 0 in each data bit in the first storage space; wherein the second preset coding rule includes: setting the preset data bit set in the first code to a third preset value; the preset data bit set includes: data bits at multiple preset positions in the first code; the processing unit is used to calculate the M-bit first code corresponding to the first data according to the first preset coding rule, including: the processing unit is used to calculate the M-bit first code corresponding to the first data according to the first preset coding rule if all data bits in the first storage space are 1.

[0019] In some implementations, a processing unit is used to calculate the first code of M bits corresponding to the first data according to a first preset coding rule, including: a processing unit is used to calculate a third code corresponding to the first data; the third code is a redundant bit value obtained by performing Hamming code encoding on the first data; a processing unit is used to determine whether the third code is equal to the third preset value; a processing unit is used to determine that the preset data bit set in the first code is a fourth preset value if the third code is equal to the third preset value, and determine that the first data bit in the first code is an odd parity bit of the first data and the preset data bit set; the fourth preset value is a preset value greater than the decimal number N+M; the first data bit is a data bit at a preset position in the first code; a processing unit is used to determine that the preset data bit set in the first code is the third code if the third code is not equal to the third preset value, and determine that the first data bit in the first code is an even parity bit of the first data and the preset data bit set.

[0020] In some implementations, the processing unit is further used to determine a second data bit in the first encoding based on the first data bit and the preset data bit set; wherein the second data bit is an odd check bit or an even check bit of the first data bit and the preset data bit set.

[0021] In some implementations, the processing unit is further used to program the second encoding to write other data bits in the second encoding except the target data bit into the first storage space; wherein the target data bit is any data bit in the second encoding that is 0; the processing unit is further used to encode the first data to write the first data into the first storage space; the processing unit is further used to program the second encoding to write the target data bit into the first storage space.

[0022] In a fourth aspect, a data processing device is provided, comprising: an acquisition unit, configured to acquire coded data; the coded data comprising first acquisition data and a first acquisition code; a processing unit, configured to obtain a second acquisition code according to the first acquisition code; the second acquisition code being the result of an XOR operation between the first acquisition code and a first preset value; the first preset value being the result of an XOR operation between the second preset value and an M-bit binary number; the second preset value being the M-bit code corresponding to the N-bit binary number calculated according to the first preset coding rule; the processing unit being further configured to determine a decoding result corresponding to the first acquisition data according to a preset decoding rule and the second acquisition code; the preset decoding rule being a decoding rule corresponding to the first preset coding rule.

[0023] In some implementations, the processing unit is further used to determine whether the preset data bit set in the second acquisition code is a third preset value; the preset data bit set includes: data bits at multiple preset positions in the second acquisition code; the processing unit is further used to determine that the decoding result corresponding to the first acquisition data is the first acquisition data if the preset data bit set in the second acquisition code is the third preset value; the processing unit is further used to determine the decoding result corresponding to the first acquisition data according to the preset decoding rule and the second acquisition code, including: the processing unit is further used to determine the decoding result corresponding to the first acquisition data according to the preset decoding rule and the second acquisition code if the preset data bit set in the second acquisition code is not the third preset value.The processing unit is also used to determine the decoding result corresponding to the first acquired data according to the preset decoding rule and the second acquired code, including: the processing unit is also used to determine whether the preset data bit set is a fourth preset value, and perform parity check on the preset data bit set, the first acquired data and the first data bit; the first data bit is a data bit at a preset position in the second acquired code; the processing unit is also used to determine that the decoding result corresponding to the first acquired data is the first acquired data if the preset data bit set is not the fourth preset value, and the preset data bit set, the first acquired data and the first data bit satisfy even parity check; the processing unit is also used to perform 1-bit data error correction on the preset data bit set and the first acquired data according to the Hamming code decoding rule to obtain the decoding result corresponding to the first acquired data if the preset data bit set is not the fourth preset value, and the preset data bit set, the first acquired data and the first data bit satisfy odd parity check. The processing unit is also used to determine that the decoding result corresponding to the first acquired data is the first acquired data if the preset data bit set is not the fourth preset value, and the preset data bit set, the first acquired data and the first data bit satisfy odd parity check. If the bit set, the first acquired data and the first data bit satisfy even parity, it is determined whether the error correction decoded data is a binary number of all 0s; wherein the error correction decoded data is: error correction decoded data obtained by decoding the preset data bit set and the first acquired data according to the Hamming code decoding rule; the processing unit is further used to determine that the decoding result corresponding to the first acquired data is the first acquired data if the error correction decoded data is a binary number of all 0s; the processing unit is further used to perform 1-bit data error correction on the first acquired data using the Hamming code decoding rule and the third acquisition code if the error correction decoded data is not a binary number of all 0s, and obtain the decoding result corresponding to the first acquired data; the third acquisition code is the result of an exclusive OR operation between the error correction decoded data and the fourth preset value; the processing unit is further used to decode the preset data bit set and the first acquired data according to the Hamming code decoding rule to obtain the decoding result corresponding to the first acquired data if the preset data bit set is the fourth preset value and the preset data bit set, the first acquired data and the first data bit satisfy odd parity.

[0024] In some implementations, the processing unit is further used to determine whether the preset data bit set, the first data bit, and the second data bit in the second acquisition code meet the preset parity check rule; the preset parity check rule is odd check or even check. The processing unit is further used to determine that the decoding result corresponding to the first acquisition data is the first acquisition data if the preset data bit set, the first data bit, and the second data bit in the second acquisition code do not meet the preset parity check rule; the processing unit is further used to determine whether the preset data bit set in the second acquisition code is a fourth preset value, and perform a parity check on the preset data bit set, the first acquisition data, and the first data bit in the second acquisition code, including: the processing unit is further used to determine whether the preset data bit set in the second acquisition code is a fourth preset value if the preset data bit set, the first data bit, and the second data bit in the second acquisition code meet the preset parity check rule, and perform a parity check on the preset data bit set, the first acquisition data, and the first data bit in the second acquisition code.

[0025] In a fifth aspect, an embodiment of the present application provides a data processing device, comprising: a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to enable the data processing device to implement the method described in any of the above implementation methods when executing the computer program.

[0026] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, which, when the computer program is executed by a computing device, enables the computing device to implement the method described in any of the above implementation methods.

[0027] In a seventh aspect, an embodiment of the present application provides a computer program product, which, when executed on a computer, enables the computer to implement the method described in any one of the above implementation modes.

[0028] Through the method provided in the embodiment of the present application, the situation where the data bits of the user data and the encoded data bits are both 1 can satisfy the first preset encoding rule, thereby avoiding the situation where the stored data after erasure cannot be corrected or even erroneous correction may occur. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0030] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0031] Figure 1 A schematic diagram of the structure of a non-volatile memory chip provided in an embodiment of the present application;

[0032] Figure 2 One of the flowcharts of a data encoding method provided in an embodiment of the present application;

[0033] Figure 3 One of the flowcharts of a data decoding method provided in an embodiment of the present application;

[0034] Figure 4 A second flow chart of a data encoding method provided in an embodiment of the present application;

[0035] Figure 5 A second flowchart of a data decoding method provided in an embodiment of the present application;

[0036] Figure 6 A third flow chart of a data encoding method provided in an embodiment of the present application;

[0037] Figure 7 A third flowchart of a data decoding method provided in an embodiment of the present application;

[0038] Figure 8 A fourth flowchart of a data encoding method provided in an embodiment of the present application;

[0039] Fig. 9 A fourth flowchart of a data decoding method provided in an embodiment of the present application;

[0040] Fig.10 A fifth flow chart of a data encoding method provided in an embodiment of the present application;

[0041] Fig.11 A fifth flow chart of a data decoding method provided in an embodiment of the present application;

[0042] Fig.12 One of the flowcharts of data programming provided in the embodiment of the present application;

[0043] Fig.13 A second schematic diagram of a data programming process provided in an embodiment of the present application;

[0044] Fig.14One of the structural schematic diagrams of a data processing device provided in an embodiment of the present application;

[0045] Fig.15 The second structural diagram of a data processing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.

[0047] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.

[0048] First, the application scenarios of the technical solutions provided in the embodiments of the present application are introduced:

[0049] like Figure 1 , which is a schematic diagram of the structure of a non-volatile memory chip provided in an embodiment of the present application.

[0050] On the one hand, during the process of writing data, when the encoding circuit 102 receives the write enable of the write instruction decoding circuit (referred to as write instruction decoding in the figure) 1011 in the interface and instruction decoding circuit 101, it can simultaneously obtain the data to be written and the write address.

[0051] After obtaining the data to be written and the write address, the encoding circuit 102 can encode the data according to the data encoding method provided in the embodiment of the present application. In the encoding process, the encoding circuit 102 can also send a read enable and a read address to the read circuit 103 to obtain the original data content in the storage space corresponding to the write address.

[0052] After the encoding circuit 102 obtains the encoding data corresponding to the data according to the data encoding method provided in the embodiment of the present application, the programming circuit sends the encoding data to the data buffer 104. Then, the data buffer encodes the programming data into the non-volatile storage 105 under the control of the encoding control circuit.

[0053] On the other hand, in the process of reading data, the read instruction decoding circuit (abbreviated as read instruction decoding in the figure) 1012 sends a read enable and a read address to the read circuit 103. Afterwards, the read circuit 103 controls the non-volatile storage 105 to read out the encoded data in the storage space corresponding to the read address and transmit it to the decoding circuit 106.

[0054] After obtaining the encoded data, the decoding circuit 106 can decode the data according to the data decoding method provided in the embodiment of the present application to obtain a decoding result. After the decoding operation is completed, the decoding circuit 106 transmits the decoding result to the reading circuit 103, and finally the reading circuit 103 sends the read data (i.e., the decoding result) to the chip interface.

[0055] The following examples are combined with Figure 1 Taking the process in which the encoding circuit encodes data and the decoding circuit decodes data as an example, the technical solution provided in the embodiment of the present application is introduced.

[0056] Specifically, Figure 2 As shown, the data encoding process in the method may include:

[0057] S201: The encoding circuit obtains first data to be encoded.

[0058] The first data is an N-bit binary number.

[0059] For example, Figure 1 In the example, the first data may be write data obtained by the encoding circuit 102 through the write instruction decoding 1011 .

[0060] S202: The encoding circuit calculates a first code of M bits corresponding to the first data according to a first preset encoding rule.

[0061] The first preset coding rule is a coding rule for generating an error correction code.

[0062] For example, the first preset coding rule may be an extended Hamming code rule, etc. The specific implementation process of calculating the first code according to the first preset coding rule will be described in detail below, which will not be expanded here.

[0063] S203: The encoding circuit obtains a second code according to the first code.

[0064] The second code is the result of an XOR operation between the first code and the first preset value. The first preset value is the result of an XOR operation between the second preset data and the binary number of M bits 1. The second preset value is the M-bit code corresponding to the binary number of N bits 1 calculated according to the first preset coding rule.

[0065] Exemplarily, taking the first preset coding rule as Hamming code as an example (it should be noted that in actual applications, the first preset coding rule may be an extended Hamming code or other types of coding rules), if the first data is a 128-bit binary number, then:

[0066] On the one hand, according to the Hamming code encoding of the related art, when the first data is 128 bits all 1, the corresponding Hamming code is "0111 0111". At this time, the data bits of the user data (i.e., the first data) and the data bits of the code (i.e., the Hamming code) are both 1, which does not comply with the Hamming code encoding rules.

[0067] On the other hand, if the process of S202-S203 described above in the embodiment of the present application is followed, when the first data is 128 bits of all 1, the corresponding second code is also all 1. Specifically, when the first data is 128 bits of all 1, the second preset value is "01110111" (i.e., the Hamming code corresponding to the binary number of 128 bits), and the first preset value is "1000 1000" (i.e., the result of the XOR operation of the second preset data and the binary number of M bits 1), so the second code is the result of the XOR operation of the first code (in this case, the Hamming code corresponding to the first data: "0111 0111") and the first preset value (in this case, "1000 1000"), i.e., "1111 1111". In other words, through the method of the embodiment of the present application, the situation where the data bits of the user data and the data bits of the code are all 1 can satisfy the first preset coding rule, thereby avoiding the situation where the stored data after erasure cannot be corrected or even erroneous correction may occur.

[0068] S204: The encoding circuit determines the encoding data corresponding to the first data.

[0069] The coded data includes: first data and second code.

[0070] by Figure 1 Taking the illustrated scenario as an example, after the encoding circuit 102 determines the encoded data corresponding to the first data, the encoded data may be transmitted to the data buffer 104 so that the data buffer 104 writes the encoded data into the non-volatile storage 105 .

[0071] and Figure 2 The data encoding process corresponds to Figure 3 As shown, the data decoding process in the method may include:

[0072] S401: The decoding circuit obtains encoded data.

[0073] The coded data includes first acquired data and first acquired code.

[0074] For example, Figure 1 In the process, the decoding circuit 106 can read the encoded data from the non-volatile storage 105.

[0075] The coded data acquired by the decoding circuit can be understood as: the coded data determined by the coding circuit in the above S204. Specifically, the first acquired data can be understood as: the first data read by the decoding circuit 106, and the first acquired code can be understood as: the second code read by the decoding circuit 106. Considering that the data read by the decoding circuit may be erroneous, in order to distinguish them, the data read by the decoding circuit are named "first acquired data" and "first acquired code" respectively.

[0076] S402: The decoding circuit obtains a second acquisition code according to the first acquisition code.

[0077] The second acquisition code is the result of an XOR operation between the first acquisition code and the first preset value. The first preset value is the result of an XOR operation between the second preset value and the binary number of M bits 1. The second preset value is the M-bit code corresponding to the binary number of N bits 1 calculated according to the first preset coding rule.

[0078] It is understandable that S402 can be understood as a decoding process corresponding to the above S203, so the implementation process of S402 can refer to the process of S203. The repeated contents will not be repeated here.

[0079] S403: The decoding circuit determines a decoding result corresponding to the first acquired data according to a preset decoding rule and the second acquired code.

[0080] The preset decoding rule is a decoding rule corresponding to the first preset encoding rule.

[0081] It is understandable that S403 can be understood as a decoding process corresponding to the above S202, so the implementation process of S403 can refer to the process of S202. The repeated contents will not be repeated here.

[0082] In one implementation, Figure 4 As shown, the data encoding process in the method may also include:

[0083] S205: The encoding circuit determines whether all data bits in the first storage space used to write the encoded data are 1.

[0084] For example, in Figure 1 The encoding circuit 102 can also obtain the write address when obtaining the write data (ie, the first data), and can then read each data bit in the storage space corresponding to the write address (ie, the first storage space) to determine whether each data bit is 1.

[0085] S206: If there is 0 in each data bit in the first storage space, the encoding circuit generates a first code of M bits corresponding to the first data according to a second preset encoding rule.

[0086] The second preset coding rule includes: setting the preset data bit set in the first coding to a third preset value.

[0087] The preset data bit set includes: data bits at multiple preset positions in the first code. For example, the preset data bit set may be data bits at positions 1 to x in the first code, where x is a positive integer.

[0088] In addition, if Figure 2 As shown, the above S202 may specifically include: if each data bit in the first storage space is 1, then calculating the M-bit first code corresponding to the first data according to the first preset coding rule.

[0089] Specifically, in the above implementation, it is taken into consideration that: in the related art, since the programming process of non-volatile storage can only program the data in the storage unit from data 1 to data 0, when programming the same storage address for the second or multiple times, data 1 cannot be written to the position of data 0 in the latter programming, resulting in the data bit possibly not corresponding to the coding bit, not complying with the corresponding coding rules, and even causing erroneous correction.

[0090] In view of the above problem, in the present implementation, it can be determined whether all data bits in the first storage space to which data is to be written are originally 1 (i.e., S205). If there are 0s in each data bit in the first storage space, it means that this writing process is multiple writings to the first storage space, so the preset data bit set in the first code can be set to the third preset value through S206. In this way, during the decoding process, when the preset data bit set is read as the third preset value (for example, the data bit read from the 1-xth position is the third preset value), it can be determined that the read data has not undergone the encoding process of the first preset encoding rule, and the read data is directly output as the decoding result. In this way, it is possible to avoid the situation where the error correction occurs when programming the same storage address twice and multiple times.

[0091] In a possible design, the third preset value is a binary number of all 0s.

[0092] and Figure 4 The data encoding process corresponds to Figure 5 As shown, the data decoding process in the method may also include:

[0093] S404: The decoding circuit determines whether the preset data bit set in the second acquired code is third preset data.

[0094] The preset data bit set includes: data bits at multiple preset positions in the second acquisition code.

[0095] In a possible design, the third preset value is a binary number of all 0s.

[0096] S405: If the preset data bit set in the second acquired code is a third preset value, the decoding circuit determines that the decoding result corresponding to the first acquired data is the first acquired data.

[0097] With reference to the content of S206, it can be understood that in S405: if the preset data bit set is the third preset data, it means that the current data is written into the storage space multiple times when being written into the storage space, and the first acquired data read can be output as the decoding result.

[0098] In addition, the above S403 may specifically include: if the preset data bit set in the second acquisition code is not the third preset value, determining a decoding result corresponding to the first acquisition data according to a preset decoding rule and the second acquisition code.

[0099] In one implementation, it is considered that: when using the content of S206 (i.e., setting the preset data bit set to the third preset value) to distinguish whether data is written multiple times when writing to the storage space, conflicts may occur. For example, if the preset data bit set in the first code obtained by S202 also happens to be the third preset value, it may be impossible to distinguish during the decoding process whether the read first code (for the convenience of distinction, it is called "second acquired code" on the decoding side) is obtained by S202 or S206 encoding, making it difficult to decode.

[0100] In response to the above problems, Figure 6 As shown, in the data encoding process of the method, S202 calculates the M-bit first code corresponding to the first data according to the first preset encoding rule, which may specifically include:

[0101] S202a1. The encoding circuit calculates a third code corresponding to the first data.

[0102] The third code is a redundant bit value obtained by performing Hamming code encoding on the first data.

[0103] For example, if the first data is all 1s of 128 bits, the third code is 01110111.

[0104] S202a2: The encoding circuit determines whether the third code is equal to a third preset value.

[0105] S202a3: If the third code is equal to the third preset value, the encoding circuit determines that the preset data bit set in the first code is a fourth preset value, and determines that the first data bit in the first code is an odd parity bit of the first data and the preset data bit set.

[0106] The fourth preset value is a preset value greater than the decimal number N+M.

[0107] The first data bit is a data bit at a preset position in the first code.

[0108] S202a4: If the third code is not equal to the third preset value, the encoding circuit determines that the preset data bit set in the first code is the third code, and determines that the first data bit in the first code is the even parity bit of the first data and the preset data bit set.

[0109] In the above implementation, when the data is encoded by using the Hamming code, it can be determined whether the Hamming code of the first data (i.e., the third code) is the third preset value. If not, the Hamming code of the first data (i.e., the third code) is used as the preset data bit set in the first code so as to be written into the non-volatile storage; if so, in order to avoid conflict with the coding content of S206, the preset data bit set in the first code is filled with the fourth preset value. In addition, even parity and odd parity are used to distinguish the two situations for subsequent decoding. In addition, in the above implementation, by setting the first data bit in the first code, an alarm can also be issued for abnormal flipping of the 2-bit storage unit data in the non-volatile storage.

[0110] and Figure 6 The data encoding process corresponds to Figure 7 As shown, in the data decoding process of the method, S403 (determining the decoding result corresponding to the first acquired data according to the preset decoding rule and the second acquired code) may specifically include:

[0111] S403a1-3, the decoding circuit determines whether the preset data bit set is a fourth preset value, and performs a parity check on the preset data bit set, the first acquired data and the first data bit.

[0112] The first data bit is a data bit at a preset position in the second acquisition code.

[0113] For example, S403a1-3 may specifically include Figure 7 S403a1, S403a2 and S403a3 in.

[0114] S403a1. Determine whether the preset data bit set is a fourth preset value.

[0115] If not, execute S403a2; if so, execute S403a3.

[0116] Specifically, if the preset data bit set is not the fourth preset value, it means that the preset data bit set carries the Hamming code obtained through S202a4; if the preset data bit set is the fourth preset value, it means that the preset data bit set may carry the fourth preset value in S202a3, or may carry the Hamming code obtained through S202a4, and further judgment is needed.

[0117] S402a2: After determining that the preset data bit set is not the fourth preset value, perform an even check on the preset data bit set, the first acquired data, and the first data bit.

[0118] If yes, execute S403a4; if no, execute S403a5.

[0119] Specifically, on one hand, if the preset data bit set, the first acquired data and the first data bit meet the even check (i.e., the result of the parity check is 0), it means that there is no 1-bit error in the data, so the Hamming code decoding function is not enabled, and the first acquired data can be used as the decoding result (i.e., S403a4 below). On the other hand, if the preset data bit set, the first acquired data and the first data bit meet the odd check (i.e., they do not meet the even check, or the result of the parity check is 1), it means that there is a 1-bit error in the data, and the Hamming code decoding function can be used to determine the decoding result (i.e., S403a5 below).

[0120] S402a3: After determining that the preset data bit set is the fourth preset value, perform an even check on the preset data bit set, the first acquired data and the first data bit.

[0121] If yes, execute S403a6; if no, execute S403a9.

[0122] Specifically, on one hand, if the preset data bit set, the first acquired data and the first data bit meet even parity, it means that there may be two situations: in the first situation, the preset data bit set carries the fourth preset value in S202a3, and there is a 1-bit error in the first acquired data, which requires error correction. In the second situation, the preset data bit set carries the Hamming code obtained by S202a4 (the Hamming code itself is equal to the fourth preset value), and there is no error in the first acquired data, which requires error correction. Therefore, S403a6 is needed to distinguish the above two situations.

[0123] On the other hand, if the preset data bit set, the first acquired data and the first data bit meet the odd parity check, it means that there may be two situations: In the first situation, the preset data bit set carries the Hamming code obtained by S202a4 (the Hamming code itself is equal to the fourth preset value), and there is a 1-bit error in the first acquired data, which requires error correction. In the second situation, the preset data bit set carries the fourth preset value in S202a3, and there is no error in the first acquired data, which requires error correction. Both of the above situations can be solved by performing Hamming code decoding (i.e., S403a9 below).

[0124] S403a4: If the preset data bit set is not the fourth preset value, and the preset data bit set, the first acquired data and the first data bit satisfy even parity, determine that the decoding result corresponding to the first acquired data is the first acquired data.

[0125] S403a5. If the preset data bit set is not the fourth preset value, and the preset data bit set, the first acquired data and the first data bit satisfy odd parity, then the preset data bit set and the first acquired data are subjected to 1-bit data error correction according to the Hamming code decoding rule to obtain a decoding result corresponding to the first acquired data.

[0126] S403a6: Determine whether the error correction decoding data is a binary number of all 0s.

[0127] The error correction decoding data is error correction decoding data obtained by decoding the preset data bit set and the first acquired data according to the Hamming code decoding rule.

[0128] The calculation process of the error correction decoding data may refer to the Hamming code decoding process, which will not be described in detail here.

[0129] If yes, execute S403a7; if no, execute S403a8.

[0130] S403a7: If the error correction decoded data is a binary number of all 0s, determine that the decoding result corresponding to the first acquired data is the first acquired data.

[0131] If the error correction decoding data is all 0, it means that there is no error in the first acquired data, so the decoding result corresponding to the first acquired data is determined to be the first acquired data.

[0132] S403a8: If the error correction decoded data is not a binary number of all 0s, use the Hamming code decoding rule and the third acquisition code to perform 1-bit data error correction on the first acquired data to obtain a decoding result corresponding to the first acquired data.

[0133] The third acquisition code is the result of an XOR operation between the error correction decoding data and a fourth preset value.

[0134] If the error correction decoded data is not all 0, it means that there is an error in the first acquired data, and the preset data bit set carries the fourth preset value in S202a3. That is to say, at this time, the calculated error correction decoded data and the fourth preset value need to be XORed to obtain the correct error correction decoded data (i.e., the third acquired code) that complies with the Hamming code decoding rule. Then, by using the Hamming code decoding rule and the third acquired code to perform 1-bit data error correction on the first acquired data, the decoding result corresponding to the first acquired data can be obtained.

[0135] S403a9: If the preset data bit set is a fourth preset value, and the preset data bit set, the first acquired data and the first data bit satisfy odd parity, the preset data bit set and the first acquired data are decoded according to the Hamming code decoding rule to obtain a decoding result corresponding to the first acquired data.

[0136] Specifically, on one hand, if the preset data bit set carries the Hamming code obtained by S202a4 (the Hamming code itself is equal to the fourth preset value), and there is a 1-bit error in the first acquired data that needs to be corrected, then the decoding can be performed directly according to the Hamming code decoding rule. On the other hand, if the preset data bit set carries the fourth preset value in S202a3, and there is no error in the first acquired data that does not need to be corrected, then because the fourth preset value (greater than N+M) exceeds the data bit length, the first acquired data will be used as the decoding result according to the Hamming code decoding rule, which still meets the expected operation.

[0137] It is understandable that the above Figure 6 and Figure 7 In the encoding and decoding process shown, when the redundant bit value (i.e., the third code) obtained by encoding the first data by Hamming code is equal to the third preset value, the first data bit is set to an odd parity bit (i.e., S202a3); when the third code is not equal to the third preset value, the first data bit is set to an even parity bit (i.e., S202a4). It can be understood that in actual application, when the third code is equal to the third preset value, the first data bit can also be set to an even parity bit, and when the third code is not equal to the third preset value, the first data bit can be set to an odd parity bit.

[0138] In one implementation, Figure 8 As shown, the data encoding process in the method may also include:

[0139] S207: Determine a second data bit in the first code according to the first data bit and a preset data bit set.

[0140] The second data bit is an odd parity bit or an even parity bit of the first data bit and a preset data bit set.

[0141] In the above implementation, by setting the second data bit for performing parity check on the first data bit and the preset data bit set in the first encoding, in this way, during the decoding process, it can be first determined whether there is an error in the first data bit and the preset data bit set according to the second data bit, so as to ensure the correctness of the subsequent decoding process using the first data bit and the preset data bit set.

[0142] and Figure 8 The data encoding process corresponds to Fig. 9 As shown, the data decoding process in the method may also include:

[0143] S406: Determine whether the preset data bit set, the first data bit, and the second data bit in the second acquired code comply with a preset parity check rule.

[0144] The preset parity check rule is odd check or even check. Specifically, the preset parity check rule only needs to be the same as the parity check rule used for the second data bit in the encoding process.

[0145] If not, S405 is executed, i.e., the decoding result corresponding to the first acquired data is determined to be the first acquired data. It can be understood that if the preset data bit set, the first data bit, and the second data bit in the second acquired code do not meet the preset parity check rule, it means that there are errors in the preset data bit set and the first data bit, so the first acquired data is directly used as the decoding result.

[0146] If yes, then execute S403a1. At this time, S403a1 specifically includes:

[0147] If the preset data bit set, the first data bit and the second data bit in the second acquisition code meet the preset parity check rule, then determine whether the preset data bit set in the second acquisition code is a fourth preset value, and perform a parity check on the preset data bit set, the first acquisition data and the first data bit in the second acquisition code.

[0148] Below, taking the encoding and decoding of 128-bit data as an example, the actual application process of the method provided in the embodiment of the present application is introduced.

[0149] First, the terminology in this application process is introduced:

[0150] "xtECC[9:0]" indicates the final code in the coded data corresponding to the 128-bit data (ie, the second code in the above text). "[9:0]" indicates that the generated code has a total of 10 bits, from bit 0 to bit 9.

[0151] The term "ECC[9:0]" represents an intermediate code (i.e., a first code) calculated based on 128 bits of data. Among them, ECC[7:0] is equivalent to the above-mentioned preset data bit set, which can be generated using the calculation rule of the Hamming code, or it can be a fourth preset value. ECC[8] is equivalent to the first data bit in the above text, and ECC[9] is equivalent to the second data bit in the above text. ECC[9:0] will be bit-wise XORed with a specific number (i.e., the first preset value) to generate the final code "xtECC[9:0]" (i.e., the second code).

[0152] The term "ECC[9]" represents bit 9 of the intermediate code generated by this specific embodiment. Similarly, the term ECC[8] represents bit 8 of the intermediate code generated by this specific embodiment.

[0153] The term "cal_index[7:0]" represents the decoding method implemented in this embodiment, in which the read xtECC[9:0] is calculated to obtain the intermediate code ECC[9:0], and then the intermediate code ECC[7:0] and 128-bit data are decoded according to the Hamming code rule to obtain error correction decoding data.

[0154] like Fig.10 The following is the process of encoding 128-bit data.

[0155] S501: The chip encoding circuit receives 128 bits of programming data (equivalent to the first data) and the address in the non-volatile storage to which the 128 bits need to be written (equivalent to the address of the first storage space).

[0156] The implementation process of S501 may refer to the content of S201.

[0157] S502: The chip encoding circuit reads the original data in the non-volatile storage address to be written.

[0158] S503: Determine whether the original data is all 1s. If it is all 1s, it means that this programming is the first programming of the address after the chip is erased. If it is not all 1s, it means that the address has been programmed once or multiple times. This programming needs to set all ECC[9:0] to 0 to prevent the ECC[9:0] and 128-bit data read out when the chip performs a read operation after multiple programming from being judged by the decoding rules proposed in this embodiment, resulting in an erroneous result, which leads to incorrect data correction.

[0159] The implementation process of S502 and S503 may refer to the content of S205.

[0160] S504: It is determined that the original data is not all 1s, and this programming is a multiple programming process of the programming address, and ECC[9:0] is assigned a value of 10'h0. 10'h0 means: 10 bits of 0.

[0161] The implementation process of S504 may refer to the content of S206.

[0162] S505: Determine that the original data is all 1s, and this programming is the first programming process of the programming address. Calculate ECC[7:0] according to the 128-bit data written and the Hamming code rule.

[0163] The implementation process of S505 may refer to the content of S202a1.

[0164] S506: Determine whether the ECC[7:0] calculated according to the write data in S505 is 8'h0. If it is 8'h0, it is necessary to distinguish the data of ECC[7:0] from the ECC[7:0] in step S504 during the multiple programming process, so it is necessary to replace ECC[7:0] with other values; if it is not 8'h0, proceed to step S508 normally.

[0165] The implementation process of S506 may refer to the content of S202a2. 8'h0 is equivalent to the third preset value. 8'h0 means: 8 bits of 0.

[0166] S507: The calculated ECC[7:0] is 8'h0, indicating that the data needs to be replaced at this time, and the data is replaced with 8'hC0.

[0167] The replacement data is not limited to 8'hC0, but can also be replaced by other data as long as the data is larger than the data bit length plus the required Hamming code length. In this specific embodiment, the data should be larger than the decimal data 136 (128 plus 8).

[0168] The implementation process of S507 may refer to the content of S202a3. 8'hC0 is equivalent to the fourth preset value. 8'hC0 represents: 8-bit 1100 0000.

[0169] S508: Generate an even-parity bit ECC[9] according to the ECC[7:0] data and the 128-bit data to be written and the parity check rule.

[0170] The implementation process of S508 may refer to the content of S202a4.

[0171] S509: Generate odd check bit ECC[9] according to the ECC[7:0] data and the 128-bit data to be written and the parity check rule.

[0172] It should be noted that the difference between step S509 and step S508 is that data replacement is performed on ECC[7:0] before S509, and the data replacement performed in step S507 is marked by using ECC[9] being an odd parity bit.

[0173] The implementation process of S509 may refer to the content of S202a3.

[0174] S510: Generate an even parity bit ECC[8] according to the calculated ECC[7:0] and ECC[9] and the parity check rule.

[0175] The implementation process of S510 may refer to the content of S207.

[0176] S511: Perform bitwise XOR on ECC[9:0] and data 10'h388 to obtain xtECC[9:0].

[0177] The purpose of this step is to match the situation where xtECC[9:0]=10'h3FF, that is, xtECC[9:0] is all 1, with the situation where 128 bits of data are all 1, to ensure that after the data is erased, data correction can still be performed according to the decoding rules, thereby improving the reliability of the chip erase operation.

[0178] The implementation process of S511 may refer to the content of S203. 10'h388 is equivalent to the first preset value.

[0179] S512: The final xtECC[9:0] code and 128-bit data are written into the non-volatile storage unit in steps through the chip high voltage programming operation.

[0180] Among them, the xtECC[9:0] code and the 128-bit data constitute the coded data in S204.

[0181] like Fig.11 As shown in FIG. 1 , the process of decoding 128-bit data includes:

[0182] S601: Read 128 bits of data in the non-volatile storage and the code xtECC[9:0] written according to the encoding process of this embodiment according to the read address.

[0183] The implementation process of S601 may refer to the content of S401.

[0184] S602: Perform bitwise XOR decoding on xtECC[9:0] and the fixed number 10'h388.

[0185] The fixed number used in this step should be consistent with the data used by S511. The purpose is to correspond the situation where xtECC[9:0] is all 1 and the 128-bit data bits are all 1. When reading the data after the chip is erased, 1-bit error correction can also be performed. After the calculation in this step is completed, the result obtained is ECC[9:0].

[0186] The implementation process of S602 may refer to the content of S402. 10'h388 is equivalent to the first preset value.

[0187] S603: Determine whether ECC[7:0] is 8'h0.

[0188] If the result is yes, it means that the non-volatile storage space corresponding to the read address has been programmed multiple times, and the ECC[9:0] corresponding to the address is unreliable, so the error correction decoding function is turned off and 128 bits of data are directly output. That is, S612 is executed.

[0189] If the result is no, it means that the non-volatile storage space corresponding to the read address has not been programmed or has only been programmed once, and the judgment continues, that is, S604 is executed.

[0190] The implementation process of S603 may refer to the content of S404. 8'h0 is equivalent to the third preset value.

[0191] S604: Perform parity check on ECC[9:0].

[0192] If the result is 1, it means that ECC[8], ECC[9], and ECC[7:0] no longer meet the even parity check rule, and one or more odd bits in ECC[9:0] are wrong, ECC[9:0] is unreliable, and the error correction decoding function is disabled. Then, S612 is executed.

[0193] If the result is 0, it is determined that there is no data error in ECC[9:0], and the determination is continued, that is, S605 is executed.

[0194] The implementation process of S604 may refer to the content of S406. ECC[8] is equivalent to the second data bit, ECC[9] is equivalent to the first data bit, and ECC[7:0] is equivalent to the preset data bit set.

[0195] S605: Determine whether ECC[7:0] is a fixed number 8'hC0.

[0196] The fixed number 8'hC0 is consistent with the data replaced in S507. This step is used to determine whether ECC[7:0] is the special data 8'hC0.

[0197] If the result is yes, then ECC[7:0] is likely to be the result of data replacement, and ECC[9:0] needs to be specially processed, that is, S606 is executed.

[0198] If the result is no, then the data error correction judgment is performed according to the general extended Hamming code rule, that is, S611 is executed.

[0199] The implementation process of S605 may refer to the content of S403a1.

[0200] S606: The premise of this step is that ECC[7:0] is 8'hC0. Under this premise, a parity check is performed on ECC[9], ECC[7:0] and 128-bit data.

[0201] If the result is 1, execute S611.

[0202] Specifically, if the result is 1, it may be one of the following two situations:

[0203] 1) ECC[7:0] data has not been replaced and is 8'C0, but one bit of the 128-bit data is wrong and needs to be corrected.

[0204] 2) ECC[7:0] data is replaced from 8'h0 to 8'hC0, and the 128-bit data is correct and does not require error correction.

[0205] In either case, ECC[7:0] and 128-bit data bits are decoded using Hamming code. If it is case 1), the cal_index[7:0] obtained corresponds to the data bit number, and the data bit can be corrected; if it is case 2), the cal_index[7:0] obtained is 8'hC0, which exceeds the data bit length and cannot be corrected. Therefore, in either case, normal decoding using the Hamming code rule is in line with the expected operation.

[0206] If the result is 0, execute S607.

[0207] Specifically, if the result is 0, it may be one of the following two situations:

[0208] 1) ECC[7:0] data has not been replaced, it is 8'hC0, and the 128-bit data is correct, so no error correction is required;

[0209] 2) ECC[7:0] data is replaced from 8'h0 to 8'hC0, and 1 bit of 128-bit data has an error, which needs to be corrected;

[0210] The above two situations need to be further judged and processed by entering S607.

[0211] The implementation process of S606 may refer to the content of S403a3.

[0212] S607: According to ECC[7:0] and 128-bit data, calculate the error correction coding data cal_index[7:0] according to the Hamming code decoding rule.

[0213] This step is used to determine whether ECC[7:0] has performed data replacement.

[0214] If cal_index[7:0] is 8'h0, it means that according to the Hamming code decoding rule, the 128-bit data is correct, and the ECC[7:0] data has not been replaced and is 8'hC0. Then, S408 is executed.

[0215] If cal_index[7:0] is not 8'h0, it means that according to the Hamming code decoding rule, 128 bits of data are wrong, and the ECC[7:0] data has been replaced and is 8'h0, then ECC[7:0] is replaced back to 8'h0 for error correction, that is, S409 is executed.

[0216] The implementation process of S607 may refer to the content of S403a6.

[0217] S608: The premise of this step is that S607 determines that ECC[7:0] has not been replaced with data, is 8'hC0, and the 128-bit data is correct. At this time, no error correction is required, the extended Hamming code decoding function is not enabled, and the data bits are directly output.

[0218] The implementation process of S608 may refer to the content of S403a7.

[0219] S609: The premise of this step is that S607 determines that ECC[7:0] has been replaced with data, is 8'h0, and has 1 bit error in the 128-bit data. Perform bitwise XOR of ECC[7:0] and data 8'hC0, replace the data back to 8'h0, and then perform data error correction according to the Hamming code decoding rules.

[0220] The implementation process of S609 may refer to the content of S403a8.

[0221] S610: Calculate ECC[9], ECC[7:0] and 128-bit data bits according to the parity check rule.

[0222] If the result is 0, it means that ECC[9], ECC[7:0] and 128 bits of data comply with the even parity check rule and the data bits are correct, and S612 is executed.

[0223] If the result bit is 1, it means that ECC[9], ECC[7:0] and the 128-bit data bits do not conform to the even parity rule, and there is one bit error in the data bits. Then, S611 is executed.

[0224] The implementation process of S610 may refer to the content of S403a2.

[0225] S611: Perform 1-bit data error correction on ECC[7:0] and 128-bit data according to the Hamming code decoding rule, and output the corrected data.

[0226] The implementation process of S611 may refer to the contents of S403a5, S403a8 or S403a9.

[0227] S612: The extended Hamming code function is not enabled, and the data bits are output directly.

[0228] The implementation process of S612 may refer to the content of S405 or S403a4.

[0229] In addition, in some implementations, Figure 8 After the process shown in the figure obtains the encoded data of the first data, the method writes the encoded data into the non-volatile storage, such as Fig.12 As shown, the method may also include:

[0230] S301, programming the second code, and writing other data bits in the second code except the target data bit into the first storage space.

[0231] The target data bit is any data bit that is 0 in the second code.

[0232] Among them, programming is to write the corresponding data 0 to the non-volatile storage unit

[0233] For example, Fig.10 Taking the 128-bit data in as an example, S301 may specifically include: programming xtECC[9:0] data (ie, the second encoding). Fig.13 As shown, in this programming process, it is necessary to control the judgment to write 1 less bit 0 in the storage unit. For example, xtECC[9:0] is 10'b11_1100_0011, and the original storage data of the corresponding address in the non-volatile storage is 10'b11_1111_1111. Then, it is only necessary to write data 0 to bit 5 to bit 3 in the non-volatile storage space, and bit 2 is temporarily not written with data 0, and data 1 is maintained.

[0234] S302: Encode the first data to write the first data into a first storage space.

[0235] Still Fig.10Taking the 128-bit data in as an example, S302 may specifically include: programming the 128 bits according to the word length. Fig.13 As shown, in this example, the length of 1word data is 16 bits.

[0236] S303 , programming the second code to write the target data bit into the first storage space.

[0237] Still Fig.10 Taking the 128-bit data in as an example, S303 may specifically include: programming the xtECC[9:0] data again after the data bit programming is completed, and programming and writing all data 0s of xtECC[9:0] in this programming process.

[0238] In the above implementation, the second code is programmed in two steps, S301 and S303, in order to prevent the chip from terminating abnormally during the programming process (such as abnormal power failure), which may cause the data bits and the code bits to not correspond, and may cause the problem of incorrect correction of normally written data.

[0239] Specifically, in the above implementation, since the second code lacks 1 bit of data 0 after S301 is executed, the parity check result of the second code does not meet the preset parity check calculation rules of the first data bit, the second data bit and the preset data bit set (i.e., the content of S207). At this time, if the chip abnormally terminates, after reading the encoded data that the above data bit does not correspond to the encoding bit, it will enter S405 through S406, thereby turning off the error correction function and directly outputting the data bit to prevent the data bit from being erroneously corrected during decoding.

[0240] Only when the programming process completes step S303, the parity check result of the written second code will meet the preset parity check calculation rule, ensuring that the data can be decoded after normal programming.

[0241] Based on the same inventive concept, as an implementation of the above method, an embodiment of the present application also provides a data processing device, which corresponds to the above method embodiment. For ease of reading, this embodiment will no longer repeat the details of the above method embodiment one by one, but it should be clear that the fault handling device in this embodiment can correspond to all the contents in the above method embodiment.

[0242] Specifically, Fig.14 As shown, the data processing device 70 may include: an acquisition unit 701 and a processing unit 702 .

[0243] In some implementations, the data processing device 70 may be used to perform the above Figure 2 , Figure 4 , Figure 6 , Figure 8 , Fig.10 as well as Fig.12 Steps in the data encoding process. At this point:

[0244] The acquisition unit 701 is used to acquire first data to be encoded; the first data is an N-bit binary number;

[0245] The processing unit 702 is used to calculate the first M-bit first code corresponding to the first data according to a first preset coding rule; the first preset coding rule is a coding rule for generating an error correction code;

[0246] The processing unit 702 is configured to obtain a second code according to the first code; the second code is a result of an XOR operation between the first code and a first preset value; the first preset value is a result of an XOR operation between the second preset value and a binary number with M bits 1; the second preset value is an M-bit code corresponding to the binary number with N bits 1 calculated according to the first preset coding rule;

[0247] The processing unit 702 is configured to determine coded data corresponding to the first data, where the coded data includes: the first data and the second code.

[0248] In some implementations, the processing unit 702 is further configured to determine whether all data bits in the first storage space used to write the encoded data are 1;

[0249] The processing unit 702 is configured to generate, according to a second preset coding rule, a first code of M bits corresponding to the first data if there is 0 in each data bit in the first storage space; wherein the second preset coding rule includes: setting a preset data bit set in the first code to a third preset value; the preset data bit set includes: data bits at multiple preset positions in the first code;

[0250] The processing unit 702 is configured to calculate, according to a first preset coding rule, a first code of M bits corresponding to the first data, including:

[0251] The processing unit 702 is configured to calculate a first code of M bits corresponding to the first data according to a first preset coding rule if all data bits in the first storage space are 1.

[0252] In some implementations, the processing unit 702 is configured to calculate, according to a first preset coding rule, a first code of M bits corresponding to the first data, including:

[0253] A processing unit 702 is configured to calculate a third code corresponding to the first data; the third code is a redundant bit value obtained by performing Hamming code encoding on the first data;

[0254] The processing unit 702 is used to determine whether the third code is equal to the third preset value;

[0255] The processing unit 702 is configured to determine, if the third code is equal to the third preset value, that the preset data bit set in the first code is a fourth preset value, and determine that the first data bit in the first code is an odd parity bit of the first data and the preset data bit set; the fourth preset value is a preset value greater than the decimal number N+M; and the first data bit is a data bit at a preset position in the first code;

[0256] The processing unit 702 is configured to determine that the preset data bit set in the first code is the third code if the third code is not equal to the third preset value, and to determine that the first data bit in the first code is an even parity bit of the first data and the preset data bit set.

[0257] In some implementations, the processing unit 702 is further used to determine a second data bit in the first encoding based on the first data bit and the preset data bit set; wherein the second data bit is an odd check bit or an even check bit of the first data bit and the preset data bit set.

[0258] In some implementations, the processing unit 702 is further configured to program the second code to write other data bits in the second code except the target data bit into the first storage space; wherein the target data bit is any data bit in the second code that is 0;

[0259] The processing unit 702 is further configured to encode the first data to write the first data into the first storage space;

[0260] The processing unit 702 is further configured to program the second code to write the target data bit into the first storage space.

[0261] In other implementations, the data processing device 70 may be used to execute the above Figure 3 , Figure 5 , Figure 7 , Fig. 9 as well as Fig.11 The steps in the data decoding process. At this point:

[0262] The acquisition unit 701 is used to acquire coded data; the coded data includes first acquired data and a first acquired code;

[0263] The processing unit 702 is configured to obtain a second acquisition code according to the first acquisition code; the second acquisition code is a result of an XOR operation between the first acquisition code and a first preset value; the first preset value is a result of an XOR operation between the second preset value and a binary number with M bits 1; the second preset value is an M-bit code corresponding to the binary number with N bits 1 calculated according to the first preset coding rule;

[0264] The processing unit 702 is further configured to determine a decoding result corresponding to the first acquired data according to a preset decoding rule and the second acquired code; the preset decoding rule is a decoding rule corresponding to the first preset coding rule.

[0265] In some implementations, the processing unit 702 is further configured to determine whether the preset data bit set in the second acquisition code is a third preset value; the preset data bit set includes: data bits at multiple preset positions in the second acquisition code;

[0266] The processing unit 702 is further configured to determine that a decoding result corresponding to the first acquired data is the first acquired data if the preset data bit set in the second acquired code is a third preset value;

[0267] The processing unit 702 is further configured to determine a decoding result corresponding to the first acquired data according to a preset decoding rule and the second acquired code, including:

[0268] The processing unit 702 is further configured to determine a decoding result corresponding to the first acquired data according to a preset decoding rule and the second acquired code if the preset data bit set in the second acquired code is not a third preset value.

[0269] The processing unit 702 is further configured to determine a decoding result corresponding to the first acquired data according to a preset decoding rule and the second acquired code, including:

[0270] The processing unit 702 is further configured to determine whether the preset data bit set is a fourth preset value, and perform a parity check on the preset data bit set, the first acquired data, and a first data bit; the first data bit is a data bit at a preset position in the second acquired code;

[0271] The processing unit 702 is further configured to determine that a decoding result corresponding to the first acquired data is the first acquired data if the preset data bit set is not a fourth preset value and the preset data bit set, the first acquired data and the first data bit satisfy an even parity check;

[0272] The processing unit 702 is further configured to, if the preset data bit set is not a fourth preset value, and the preset data bit set, the first acquired data, and the first data bit satisfy odd parity, perform 1-bit data error correction on the preset data bit set and the first acquired data according to a Hamming code decoding rule to obtain a decoding result corresponding to the first acquired data;

[0273] The processing unit 702 is further configured to determine whether the error correction decoded data is a binary number of all 0s if the preset data bit set is a fourth preset value and the preset data bit set, the first acquired data and the first data bit satisfy even parity; wherein the error correction decoded data is: error correction decoded data obtained by decoding the preset data bit set and the first acquired data according to a Hamming code decoding rule;

[0274] The processing unit 702 is further configured to determine, if the error correction decoded data is a binary number of all 0s, that a decoding result corresponding to the first acquired data is the first acquired data;

[0275] The processing unit 702 is further configured to, if the error correction decoded data is not a binary number of all 0s, perform 1-bit data error correction on the first acquired data using a Hamming code decoding rule and the third acquisition code to obtain a decoding result corresponding to the first acquired data; the third acquisition code is a result of an XOR operation between the error correction decoded data and the fourth preset value;

[0276] The processing unit 702 is also used to decode the preset data bit set and the first acquired data according to the Hamming code decoding rule to obtain a decoding result corresponding to the first acquired data if the preset data bit set is a fourth preset value and the preset data bit set, the first acquired data and the first data bit satisfy odd parity.

[0277] In some implementations, the processing unit 702 is further used to determine whether the preset data bit set, the first data bit, and the second data bit in the second acquisition code comply with a preset parity check rule; the preset parity check rule is odd check or even check.

[0278] The processing unit 702 is further configured to determine that a decoding result corresponding to the first acquired data is the first acquired data if the preset data bit set, the first data bit, and the second data bit in the second acquired code do not meet the preset parity check rule;

[0279] The processing unit 702 is further configured to determine whether the preset data bit set in the second acquisition code is a fourth preset value, and perform a parity check on the preset data bit set in the second acquisition code, the first acquisition data, and the first data bit, including:

[0280] The processing unit 702 is also used to determine whether the preset data bit set in the second acquisition code is a fourth preset value if the preset data bit set, the first data bit and the second data bit in the second acquisition code meet the preset parity check rule, and perform a parity check on the preset data bit set, the first acquisition data and the first data bit in the second acquisition code.

[0281] The data processing device 70 provided in the embodiment of the present application can execute the method provided in any of the above embodiments. Its implementation principle and technical effect are similar and will not be repeated here.

[0282] Based on the same inventive concept, an embodiment of the present application also provides a data processing device. Fig.15 A schematic diagram of the structure of a data processing device provided in an embodiment of the present application is shown in FIG. Fig.15 As shown, the data processing device provided in this embodiment includes: a memory 801 and a processor 802, wherein the memory 801 is used to store a computer program, and the processor 802 is used to execute any one of the methods provided in the above embodiments when executing the computer program.

[0283] Based on the same inventive concept, an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the computing device implements any distributed key-value storage system fault handling method provided in the above embodiments.

[0284] Based on the same inventive concept, an embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computing device implements any of the distributed key-value storage system fault handling methods provided in the above embodiments.

[0285] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media that include computer-usable program code.

[0286] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0287] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0288] Computer readable media include permanent and non-permanent, removable and non-removable storage media. Storage media can be implemented by any method or technology to store information, and the information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0289] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein, and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A data encoding method, characterized in that: The method comprises: Acquire first data to be encoded; the first data is an N-bit binary number; Calculate the M-bit first code corresponding to the first data according to a first preset coding rule; the first preset coding rule is a coding rule for generating an error correction code; According to the first code, a second code is obtained; the second code is the result of an XOR operation between the first code and a first preset value; the first preset value is the result of an XOR operation between the second preset value and a binary number with M bits 1; the second preset value is the M-bit code corresponding to the binary number with N bits 1 calculated according to the first preset coding rule; Determine coded data corresponding to the first data, where the coded data includes: the first data and the second code.

2. The method according to claim 1, characterized in that The method further includes: determining whether all data bits in a first storage space used to write the encoded data are 1; If there is 0 in each data bit in the first storage space, generate a first code of M bits corresponding to the first data according to a second preset coding rule; wherein the second preset coding rule includes: setting a preset data bit set in the first code to a third preset value; the preset data bit set includes: data bits at multiple preset positions in the first code; The calculating, according to the first preset coding rule, a first code of M bits corresponding to the first data includes: If all data bits in the first storage space are 1, a first code of M bits corresponding to the first data is calculated according to a first preset coding rule.

3. The method according to claim 2, characterized in that The calculating, according to the first preset coding rule, a first code of M bits corresponding to the first data includes: Calculate a third code corresponding to the first data; the third code is a redundant bit value obtained by performing Hamming code encoding on the first data; Determining whether the third code is equal to the third preset value; If the third code is equal to the third preset value, the preset data bit set in the first code is determined to be a fourth preset value, and the first data bit in the first code is determined to be an odd parity bit of the first data and the preset data bit set; the fourth preset value is a preset value greater than the decimal number N+M; the first data bit is a data bit at a preset position in the first code; If the third code is not equal to the third preset value, the preset data bit set in the first code is determined to be the third code, and the first data bit in the first code is determined to be an even parity bit of the first data and the preset data bit set.

4. The method according to claim 3, characterized in that The method further comprises: A second data bit in the first encoding is determined according to the first data bit and the preset data bit set; wherein the second data bit is an odd parity bit or an even parity bit of the first data bit and the preset data bit set.

5. The method according to claim 4, characterized in that The method further comprises: Programming the second code to write other data bits in the second code except the target data bit into the first storage space; wherein the target data bit is any data bit in the second code that is 0; encoding the first data to write the first data into the first storage space; The second code is programmed to write the target data bit into the first storage space.

6. A data decoding method, characterized in that: The method comprises: Acquire coded data; the coded data includes first acquired data and a first acquired code; According to the first acquisition code, a second acquisition code is obtained; the second acquisition code is the result of an XOR operation between the first acquisition code and a first preset value; the first preset value is the result of an XOR operation between the second preset value and a binary number with M bits 1; the second preset value is the M-bit code corresponding to the binary number with N bits 1 calculated according to the first preset coding rule; According to a preset decoding rule and the second acquisition code, a decoding result corresponding to the first acquisition data is determined; the preset decoding rule is a decoding rule corresponding to the first preset coding rule.

7. The method according to claim 6, characterized in that The method further includes: determining whether a preset data bit set in the second acquisition code is a third preset value; the preset data bit set includes: data bits at multiple preset positions in the second acquisition code; If the preset data bit set in the second acquired code is a third preset value, determining that the decoding result corresponding to the first acquired data is the first acquired data; The determining, according to a preset decoding rule and the second acquired code, a decoding result corresponding to the first acquired data includes: If the preset data bit set in the second acquisition code is not the third preset value, a decoding result corresponding to the first acquisition data is determined according to a preset decoding rule and the second acquisition code.

8. The method according to claim 7, characterized in that The determining, according to a preset decoding rule and the second acquired code, a decoding result corresponding to the first acquired data includes: Determine whether the preset data bit set is a fourth preset value, and perform a parity check on the preset data bit set, the first acquired data, and a first data bit; the first data bit is a data bit at a preset position in the second acquired code; If the preset data bit set is not a fourth preset value, and the preset data bit set, the first acquired data, and the first data bit satisfy even parity, determining that the decoding result corresponding to the first acquired data is the first acquired data; If the preset data bit set is not a fourth preset value, and the preset data bit set, the first acquired data, and the first data bit satisfy odd parity, performing 1-bit data error correction on the preset data bit set and the first acquired data according to a Hamming code decoding rule to obtain a decoding result corresponding to the first acquired data; If the preset data bit set is a fourth preset value, and the preset data bit set, the first acquired data, and the first data bit satisfy even parity, then determining whether the error correction decoded data is a binary number of all 0s; wherein the error correction decoded data is: error correction decoded data obtained by decoding the preset data bit set and the first acquired data according to a Hamming code decoding rule; If the error correction decoding data is a binary number of all 0s, determining that the decoding result corresponding to the first acquired data is the first acquired data; If the error correction decoded data is not a binary number of all 0s, a 1-bit data error correction is performed on the first acquired data using a Hamming code decoding rule and the third acquisition code to obtain a decoding result corresponding to the first acquired data; the third acquisition code is a result of an XOR operation between the error correction decoded data and the fourth preset value; If the preset data bit set is a fourth preset value, and the preset data bit set, the first acquired data and the first data bit satisfy odd parity, the preset data bit set and the first acquired data are decoded according to the Hamming code decoding rule to obtain a decoding result corresponding to the first acquired data.

9. The method according to claim 8, characterized in that The method further comprises: Determine whether the preset data bit set, the first data bit, and the second data bit in the second acquisition code meet a preset parity check rule; the preset parity check rule is odd check or even check; If the preset data bit set, the first data bit, and the second data bit in the second acquired code do not conform to the preset parity check rule, determining that the decoding result corresponding to the first acquired data is the first acquired data; The determining whether the preset data bit set in the second acquisition code is a fourth preset value, and performing a parity check on the preset data bit set in the second acquisition code, the first acquisition data, and the first data bit, comprises: If the preset data bit set, the first data bit and the second data bit in the second acquisition code meet the preset parity check rule, then determine whether the preset data bit set in the second acquisition code is a fourth preset value, and perform a parity check on the preset data bit set, the first acquisition data and the first data bit in the second acquisition code.

10. A data processing device, characterized in that: include: A memory and a processor, wherein the memory is used to store a computer program and the processor is used to enable the data processing device to implement the method according to any one of claims 1 to 9 when executing the computer program.

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