Data processing method and related device

Abstract

The embodiment of the invention discloses a data processing method and a related device, which are used for realizing inner code coding with higher gain, improving the performance of cascade coding and being beneficial to being applied to a 1.6 T ZR scene. Specifically, a coded data frame subjected to outer code coding is obtained, the coded data frame comprises v bits, and v is an integer greater than 1. Afterwards, a first bit set is obtained according to the coded data frame and the added dpad filling bits, the number of bits in the first bit set is v + dpad, and dpad is an integer greater than or equal to 1; next, performing convolutional interleaving on the first bit set to obtain a second bit set; and further, performing inner code coding on the second bit set to obtain a third bit set. The third bit set comprises R code words coded by the second FEC, each code word comprises N bits including K information bits and N-K check bits, R, N and K are all integers greater than 1, v + dpad = R * K, and dpad cannot be exactly divided by K.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of optical communications, and in particular to a data processing method and related devices. Background Art

[0002] Driven by 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTNs) are developing toward high capacity and ultra-high speeds. Forward error correction (FEC) is used to correct errors in transmitted data, resolving transmission errors and recovering the original data from the received data.

[0003] In 400G ZR scenarios, optical modules use CFEC as the error correction coding scheme, with staircase codes as the outer code and two-bit extended Hamming codes as the inner code. In the future 1.6T ZR scenario, due to the significant increase in transmission rates, the performance of existing CFEC solutions will not be able to meet the link budget for this scenario. Summary of the Invention

[0004] The embodiments of the present application provide a data processing method and related devices, which achieve higher-gain inner code encoding, improve the performance of cascade coding, and are conducive to application in 1.6T ZR scenarios.

[0005] In a first aspect, an embodiment of the present application provides a data processing method. First, a coded data frame that has been coded by a first forward error correction (FEC) coding is obtained. The first FEC coding can be regarded as an outer code coding. The coded data frame includes v bits, where v is an integer greater than 1. Then, according to the coded data frame and the added d pad The number of bits in the first bit set is v+d. pad , d pad is an integer greater than or equal to 1. Next, convolution interleaving is performed on the first bit set to obtain a second bit set. Further, the second bit set is subjected to a second FEC encoding to obtain a third bit set. The second FEC encoding can be regarded as an inner code. The third bit set includes R codewords that have undergone the second FEC encoding. Each codeword includes K information bits and NK check bits, a total of N bits. R, N, and K are all integers greater than 1. v+d pad =R×K,d pad Not divisible by K.

[0006] In this embodiment, for the coded data frame encoded by the outer code, by adding d padThe first bit set is obtained by convolution interleaving the first bit set, and the second bit set is further inner-coded to obtain a third bit set including R inner-code codewords. Each codeword includes K information bits and NK check bits, a total of N bits, d pad cannot be divided by K. In other words, this scheme provides a higher gain inner code encoding method by design, which can replace the Hamming code with a 1-bit error correction capability with the BCH code or its extended code with a 2-bit error correction capability, thereby improving the performance of the concatenated coding. In addition, by adding d pad The padding bits help the receiving end to better synchronize the inner code, outer code and convolutional interleaving.

[0007] In some possible implementations, performing convolution interleaving on the first bit set to obtain the second bit set includes: delaying the bits from the first bit set according to P delay lines. P is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units, and the difference in the number of storage units between each two adjacent delay lines is Q. Each storage unit is used to store d bits, and the input bits are input into the P delay lines in sequence according to the sequence of the P delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. The continuous P×d bits output after convolution interleaving include d bits output by each delay line, and Q and d are both integers greater than or equal to 1. This implementation provides a specific implementation method of convolution interleaving, which has good practical effects.

[0008] In some possible implementations, K is divisible by d, P×d is divisible by K, It is divisible by P, so that the P×d bits output by a polling of the convolution interleaver can be mapped to an integer number of information bits of the inner code word, which is convenient for hardware implementation; and after convolution interleaving a first bit set, the switch of the interleaver returns to the initial position, which is convenient for rapid synchronization of the convolution interleaver after inner code synchronization.

[0009] In some possible implementations, the second bit set includes R rows and K columns of bits, and the K bits in each row of the second bit set are K bits are output from the delay line. Performing the second FEC encoding on the second bit set to obtain the third bit set includes: performing the second FEC encoding on the K bits in each row of the second bit set to obtain N bits of each codeword in the third bit set. In this embodiment, the bits in the second bit set are distributed into R rows and K columns, facilitating the inner code encoding of the K bits in each row of the second bit set.

[0010] In some possible implementations, after performing a second FEC encoding on the second bit set to obtain a third bit set, the method further includes: performing symbol mapping and polarization division on every 8 bits in the third bit set to obtain a dual-polarization (DP)-16QAM symbol. Any of the X-polarization direction I component, the X-polarization direction Q component, the Y-polarization direction I component, and the Y-polarization direction Q component of the DP-16QAM symbol is obtained by mapping two consecutive bits in a codeword, and the X polarization direction and the Y polarization direction are mutually orthogonal. In other words, any component of the DP-16QAM symbol is obtained by mapping two consecutive bits in the same codeword. In this way, the two bits with different error probabilities in any component are evenly distributed in each inner codeword, which is beneficial to improving the performance of inner code encoding.

[0011] In some possible implementations, at least bits are mapped to On the same component of a DP-16QAM symbol, the maximum number of bits are mapped to On the same component of a DP-16QAM symbol, Indicates rounding a down. = t(a) = t(a) t(a) = t(a) t(a) = t(a) t(b) t(c) t(d ...

[0012] In some possible implementations, a total of 8 consecutive bits from the 8ith bit to the 8i+7th bit in the codeword are mapped to 4 different components of 4 DP-16QAM symbols. The f consecutive bits from the first bit to the N-1th bit are mapped to f / 2 different components of f / 2 DP-16QAM symbols. Furthermore, two adjacent bits from each of the four consecutive codewords, totaling eight bits, are mapped to one DP-16QAM symbol. This mapping method allows each inner codeword to be evenly mapped to the four components of DP-16QAM, preventing component-related errors from converging on certain inner codewords, thereby improving error tolerance.

[0013] In some possible implementations, N is divisible by 8, and eight consecutive bits in a codeword are mapped to one DP-16QAM symbol. This mapping method not only allows each inner codeword to be evenly mapped to the four components of DP-16QAM, but also prevents component-related errors from converging in certain inner codewords, improving error tolerance and facilitating hardware implementation.

[0014] In some possible implementations, before obtaining the encoded data frame after the first FEC encoding, the method further includes: distributing the first data stream to obtain four second data streams; and performing the first FEC encoding on each second data stream to obtain the encoded data frame. This data method facilitates compatibility with throughput scenarios such as 1.6T, 800G, and 400G.

[0015] In some possible implementations, before performing convolution interleaving on the first bit set to obtain the second bit set, the method further includes: scrambling the first bit set, which can improve the balance between 0 bits and 1 bits in the first bit set.

[0016] In some possible implementations, the second FEC code uses a finite field GF(2 m ) 2-bit BCH coding or extended BCH coding improves the performance of cascade coding.

[0017] In some possible implementations, the encoded data frame includes r rows and w columns of bits, where r=119 and w=10970; or r=595 and w=2194.

[0018] In some possible implementations, K = 110, N = 126, or K = 112, N = 128, or K = 113, N = 128. That is, while maintaining the inner codeword length at 128 bits or slightly reducing the inner codeword length, the decoding complexity is effectively controlled, and the error correction capability of the inner codeword is increased from correcting 1-bit errors to correcting 2-bit errors, effectively improving the performance of concatenated coding.

[0019] In some possible implementations, K=110, N=126, P=16, d=110, d pad =490; or, K=112, N=128, P=16, d=112, d pad =938; or, K=113, N=128, P=16, d=113, d pad =1754; or, K=112, N=128, P=62, d=56, d pad =42; or, K=110, N=126, P=24, d=55, d pad = 50. This allows bit filling and convolutional interleaving to better adapt to the inner code encoding scheme with better performance provided by this scheme.

[0020] In a second aspect, an embodiment of the present application provides a data processing device, the data processing device comprising: an acquisition unit, a padding unit, a convolution interleaving unit, and an encoding unit. The acquisition unit is used to: acquire a coded data frame that has been coded by a first forward error correction (FEC), the coded data frame comprising v bits, where v is an integer greater than 1. The padding unit is used to: pad The number of bits in the first bit set is v+d. pad , d pad is an integer greater than or equal to 1. The convolution interleaving unit is configured to perform convolution interleaving on the first bit set to obtain a second bit set. The encoding unit is configured to perform a second FEC encoding on the second bit set to obtain a third bit set, the third bit set including R codewords encoded by the second FEC, each codeword including K information bits and NK check bits, a total of N bits, where R, N, and K are all integers greater than 1, and v+d pad =R×K,d pad Not divisible by K.

[0021] In some possible implementations, the convolution interleaving unit is specifically used to: delay bits from the first bit set according to P delay lines, where P is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between each two adjacent delay lines is Q, each storage unit is used to store d bits, the input bits are input into the P delay lines in sequence according to the sequence numbers of the P delay lines, each delay line inputs d bits at a time and outputs d bits at a time, and the continuous P×d bits output after convolution interleaving include d bits output by each delay line, and Q and d are both integers greater than or equal to 1.

[0022] In some possible implementations, K is divisible by d, P×d is divisible by K, Divisible by P.

[0023] In some possible implementations, the second bit set includes R rows and K columns of bits, and the K bits in each row of the second bit set are The encoding unit is specifically configured to perform a second FEC encoding on the K bits in each row of the second bit set to obtain N bits of each codeword in the third bit set.

[0024] In some possible embodiments, the data processing device further includes a mapping unit, which is configured to perform symbol mapping and polarization division on every 8 bits in the third bit set to obtain a dual-polarization DP-16QAM symbol, wherein any one of the X-polarization direction I component, the X-polarization direction Q component, the Y-polarization direction I component, and the Y-polarization direction Q component of the DP-16QAM symbol is obtained by mapping two consecutive bits in a codeword, and the X-polarization direction and the Y-polarization direction are orthogonal to each other.

[0025] In some possible implementations, at least bits are mapped to On the same component of a DP-16QAM symbol, the maximum number of bits are mapped to On the same component of a DP-16QAM symbol, Indicates rounding a down. Indicates rounding a upwards.

[0026] In some possible implementations, a total of 8 consecutive bits from the 8ith bit to the 8i+7th bit in the codeword are mapped to 4 different components of 4 DP-16QAM symbols. The f consecutive bits from the first bit to the N-1th bit are mapped to f / 2 different components of f / 2 DP-16QAM symbols. Furthermore, two adjacent bits from each codeword in the four consecutive codewords, a total of eight bits, are mapped to one DP-16QAM symbol.

[0027] In some possible implementations, N is divisible by 8, and 8 consecutive bits in the codeword are mapped to 1 DP-16QAM symbol.

[0028] In some possible implementations, the data processing device further includes a processing unit, which, before obtaining the encoded data frame encoded by the first FEC, is used to: distribute data on the first data stream to obtain four second data streams; and perform the first FEC encoding on each second data stream to obtain an encoded data frame.

[0029] In some possible implementations, the data processing apparatus further includes a scrambling unit, and before performing convolution interleaving on the first bit set to obtain the second bit set, the scrambling unit is configured to: scramble the first bit set.

[0030] In some possible implementations, the second FEC code uses a finite field GF(2 m ) BCH coding or extended BCH coding with 2 bits of error correction.

[0031] In some possible implementations, the encoded data frame includes r rows and w columns of bits, where r=119 and w=10970; or r=595 and w=2194.

[0032] In some possible implementations, K=110, N=126, or K=112, N=128, or K=113, N=128.

[0033] In some possible implementations, K=110, N=126, P=16, d=110, d pad =490; or, K=112, N=128, P=16, d=112, d pad =938; or, K=113, N=128, P=16, d=113, d pad =1754; or, K=112, N=128, P=62, d=56, d pad =42; or, K=110, N=126, P=24, d=55, d pad =50.

[0034] In a third aspect, an embodiment of the present application provides a chip comprising a processor and a memory, the memory and the processor being interconnected via lines, instructions being stored in the memory, and the processor being used to execute the method described in any embodiment of the first aspect.

[0035] In a fourth aspect, an embodiment of the present application provides a data transmission system, which includes a data sending device and a data receiving device, wherein the data sending device is used to execute the method described in any embodiment of the first aspect and send data to the data receiving device, and the data receiving device is used to perform operations such as decoding on the received data.

[0036] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a computer, the method described in any embodiment of the first aspect is implemented.

[0037] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0038] In this embodiment, for the coded data frame encoded by the outer code, by adding d pad The first bit set is obtained by convolution interleaving the first bit set, and the second bit set is further inner-coded to obtain a third bit set including R inner-code codewords. Each codeword includes K information bits and NK check bits, a total of N bits, d padcannot be divided by K. In other words, this scheme provides a higher gain inner code encoding method by design, which can replace the Hamming code with a 1-bit error correction capability with the BCH code or its extended code with a 2-bit error correction capability, thereby improving the performance of the concatenated coding. In addition, by adding d pad The padding bits help the receiving end to better synchronize the inner code, outer code and convolutional interleaving. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 A schematic diagram of a communication system used in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of another communication system used in an embodiment of the present application;

[0041] Figure 3 This is a schematic diagram of an implementation of a data processor at the originating end in an embodiment of the present application;

[0042] Figure 4 A flowchart of a data processing method provided in an embodiment of the present application;

[0043] Figure 5 It is a structural diagram of a data frame;

[0044] Figure 6 Schematic diagram of the structure of a coded data frame;

[0045] Figure 7 A schematic diagram of a structure of the first bit set after adding padding bits to the coded data frame;

[0046] Figure 8 Another structural diagram of the first bit set after adding padding bits to the encoded data frame;

[0047] FIG9( a ) is a schematic diagram of a first implementation method of convolutional interleaving in an embodiment of the present application;

[0048] FIG9( b ) is a schematic diagram of a second implementation method of convolutional interleaving in an embodiment of the present application;

[0049] Figure 10 Schematic diagram of an implementation method of performing a second FEC encoding on a second bit set in an embodiment of the present application;

[0050] Figure 11 This is a schematic diagram of an implementation of a multi-channel parallel transmitting end data processor in an embodiment of the present application;

[0051] Figure 12 This is a schematic diagram of an implementation method of data distribution in an embodiment of the present application;

[0052] Figure 13This is a schematic diagram of an application scenario of internal code encoding in an embodiment of the present application;

[0053] Figure 14 A schematic diagram of the structure of a data processing device in an embodiment of the present application;

[0054] Figure 15 This is another structural diagram of the data processing device in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The embodiments of the present application provide a data processing method and related devices, which achieve higher-gain inner code encoding, improve the performance of cascade coding, and are beneficial for application in 1.6T ZR scenarios. It should be noted that the terms "first", "second", etc. in the description and claims of this application and the above-mentioned drawings are used to distinguish similar objects, rather than to limit a specific order or sequence. It should be understood that the above terms can be interchangeable where appropriate, so that the embodiments described in this application can be implemented in an order other than that described in this application. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0056] Figure 1 This is a schematic diagram of a communication system used in the embodiment of the present application. Figure 1As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking the communication system as a data center network as an example, transmitting device 01 and receiving device 05 can be devices such as switches or routers. Transmitting device 01 is also called a host chip at the transmitting end, while receiving device 05 is also called a host chip at the receiving end. Channel transmission medium 03 can be an optical fiber. The host chip is sometimes also called a host device. Transmitting device 01 and transmitting processing module 02 can be connected via an attachment unit interface (AUI), and receiving device 05 and receiving processing module 04 can be connected via an AUI. Transmitting processing module 02 and receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during transmission. For example, the processing module can be an 800G ZR module (a type of coherent optical module). Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04 and receiving device 05 in the communication system can support bidirectional transmission or unidirectional transmission, which is not specifically limited here.

[0057] Figure 2 This is another communication system diagram used in the embodiment of the present application. Figure 2 As shown, at the transmitting end, the information source provides the data stream to be sent; the transmitting end data processor receives the data stream and performs data processing including coding, interleaving, and modulation on it to obtain a symbol data stream, which is sent to the transmitting end signal processor for framing, transmitted through the channel, and reaches the receiving device. After the receiving device receives the distorted signal caused by noise or other damage in the channel, it is sent to the receiving end signal processor for dispersion compensation, synchronization, phase recovery and other operations, and then sent to the receiving end data processor for demodulation, deinterleaving, decoding, and recovery of the original data, which is sent to the destination. Among them, Figure 2 The transmitting end data processing and transmitting end signal processing shown in can be applied to Figure 1 In the sending end processing module 02 shown, Figure 2 The receiving end data processing and receiving end signal processing shown in can be applied to Figure 1 In the receiving end processing module 04 shown.

[0058] Figure 3 This is a schematic diagram of an implementation of the data processor at the originating end in the embodiment of the present application. Figure 3As shown, the data processor at the transmitting end sequentially performs outer code encoding, padding bit insertion, convolution interleaving, inner code encoding, symbol mapping, and polarization division on the input data stream. It should be understood that the operations performed by the data processor at the transmitting end in actual applications include but are not limited to Figure 3 The operation embodied in, for example, before performing convolution interleaving, the coded data frame obtained by outer code encoding can also be scrambled.

[0059] It should be understood that the "inner" in the inner code and the "outer" in the outer code are distinguished only based on the distance between the execution subject of the data operation and the channel transmission medium. The execution subject of the inner code operation is closer to the channel transmission medium, and the execution subject of the outer code operation is farther away from the channel transmission medium. Figure 1 For example, because the transmitting processing module 02 encodes data twice before sending it to the channel transmission medium, the data encoded first by the transmitting processing module 02 is farther away from the channel transmission medium, while the data encoded later by the transmitting processing module 02 is closer to the channel transmission medium. Therefore, the data encoded first by the transmitting processing module 02 is called outer-coded data, and the data encoded later by the transmitting processing module 02 is called inner-coded data. Correspondingly, the data decoded first by the receiving processing module 04 is called inner-coded data, and the data decoded later by the receiving processing module 04 is called outer-coded data. In one possible embodiment, both the inner and outer coding described above utilize FEC encoding, thereby forming a cascaded FEC transmission scheme. For example, the transmitting data processing module 02 may use staircase codes for outer coding and Hamming codes for inner coding, or Bose-Chaudhuri-Hocquenghem (BCH) codes for inner coding.

[0060] It should be noted that the above content is an exemplary description of the application scenario of the data processing method provided in the embodiment of the present application, and does not constitute a limitation on the application scenario of the data processing method. It is known to those skilled in the art that as business needs change, its application scenario can be adjusted according to application needs, and the embodiment of the present application does not list them one by one. The following mainly introduces the data processing method applied to the data sending end. The data processing method applied to the receiving end can be understood as the inverse operation of the data processing method of the sending end. On the basis of the determination of the data processing method of the sending end, the data processing method of the receiving end is also clear, and this application no longer introduces the data processing method of the receiving end in detail.

[0061] Figure 4This is a flow chart of a data processing method provided in an embodiment of the present application. The data processing method includes the following steps, which are described in detail below. It should be understood that, for ease of explanation, the first FEC encoding described below can be considered the outer code encoding described above, and the second FEC encoding described below can be considered the inner code encoding described above, and the following description can be understood based on this.

[0062] 101. Obtain a coded data frame that has undergone first FEC coding.

[0063] Figure 5 This is a structural diagram of a data frame. Figure 5 As shown, the payload of the data frame includes multiple rows and columns of bits, and each row may specifically include H = 2056 bits or 10280 bits. For example, the payload of a 400G ZR frame contains 256 rows, each row contains 10280 bits. For another example, the payload of an 800G ZR frame contains 512 rows, each row contains 10280 bits, or the payload of an 800G ZR frame contains 2560 rows, each row contains 2056 bits. From the payloads of multiple data frames, r consecutive rows totaling r×H bits are obtained for outer code encoding to obtain a coded data frame.

[0064] Figure 6 This is a schematic diagram of the structure of a coded data frame. Figure 6 As shown, the coded data frame includes r rows and w columns of bits, for example, r = 119, w = 10970. Among them, 119 rows and 10280 columns of bits are the information bits of the coded data frame, and 119 rows and 690 columns of bits are the check bits of the coded data frame. Alternatively, r = 595, w = 2194; among them, 595 rows and 2056 columns of bits are the information bits of the coded data frame, and 595 rows and 138 columns of bits are the check bits of the coded data frame. It should be understood that the outer code encoding can specifically adopt staircase code, for example, the outer code encoding can specifically adopt staircase (512, 510) encoding. In some possible scenarios, the coded data frame can also be called a coded data stream, that is, the bits in the coded data stream obtained by outer code encoding can also be arranged continuously, without row and column division.

[0065] 102. Obtain a first bit set according to the encoded data frame and the added padding bits.

[0066] Figure 7 A structural diagram of the first bit set after adding padding bits to the coded data frame. Figure 7 As shown, taking the coded data frame including v=119×10970 bits as an example, the first bit set includes 119×10970+d padbits, d pad is the number of padding bits, d pad is an integer greater than or equal to 1. Figure 8 Another structural diagram of the first bit set after adding padding bits to the coded data frame. Figure 8 As shown, in some possible scenarios, the first bit set is distributed in rows and columns. For example, the first bit set includes R rows and K columns of bits, that is, 119×10970+d pad =R×K. It should be understood that K can be understood as the length of the information sequence of each inner code word obtained by inner code encoding.

[0067] 103. Perform convolution interleaving on the first bit set to obtain a second bit set.

[0068] Specifically, performing convolution interleaving on the first bit set can obtain a second bit set with disrupted data order. The following introduces possible implementation methods of convolution interleaving.

[0069] FIG9(a) is a schematic diagram of the first implementation of convolution interleaving in an embodiment of the present application. FIG9(b) is a schematic diagram of the second implementation of convolution interleaving in an embodiment of the present application. As shown in FIG9(a) and FIG9(b), the convolution interleaver includes P delay lines. The convolution interleaver delays the data in the input first bit set according to the p delay lines to obtain a second bit set. Wherein, P is an integer greater than 1. Each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between two adjacent delay lines is Q. Each storage unit is used to store d bits. The bits in the first bit set are input to the P delay lines in sequence according to the sequence of the P delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. After convolution interleaving, the continuous P×d bits output include the d bits output by each delay line. Wherein, Q is an integer greater than or equal to 1, and d is an integer greater than or equal to 1. For example, P delay lines respectively include 0 storage units, Q storage units, 2Q storage units, ..., (P-1)Q storage units, and each storage unit is used to store d bits. Then, the P delay lines respectively correspond to P delay values, and the delay values ​​include 0 bits, Q×d bits, 2Q×d bits, ..., (P-1)Q×d bits. It can also be understood that the interleaving depth of the convolution interleaver is P. It should be noted that the delay values ​​in this application are counted in bits. The more bits the delay value of the delay line includes, the longer the delay (also called time delay) of this delay line to the data. It should be understood that when the delay line does not include a storage unit, the delay of the delay line is 0 bit, that is, there is no delay in transmission.

[0070] As shown in Figure 9(a), the number of storage cells in the P delay lines decreases sequentially according to the sequence of the P delay lines. That is, delay line 0 has (P-1)Q storage cells, and each delay line decreases by Q storage cells, and delay line P-1 has 0 storage cells. As shown in Figure 9(b), the number of storage cells in the P delay lines increases sequentially according to the sequence of the P delay lines. That is, delay line 0 has 0 storage cells, and each delay line increases by Q storage cells, and delay line P-1 has (P-1)Q storage cells.

[0071] It should be noted that at the same time, the switches for the input and output of the convolution interleaver are located on the same delay line. After the current delay line inputs d bits and outputs d bits at a time, the switch is switched to the next delay line to ensure that the bits in the first bit set are input to the P delay lines in sequence according to the sequence of the P delay lines. The continuous P×d bits output after convolution interleaving include the d bits output by each delay line. The specific data read and write operations are as follows: d bits are read from the storage unit closest to the output port of the current delay line. The d bits stored in each storage unit in the current delay line are transferred to the next storage unit. Then, d bits are written to the storage unit closest to the input port in the current delay line. After that, switch to the next delay line and repeat the above operations, and so on.

[0072] It should be understood that when the same parameters P, Q, and d are used, the convolutional interleaving process in Figure 9(a) and the convolutional interleaving process in Figure 9(b) are inverse operations of each other. That is, when the transmitting processing module adopts the convolutional interleaving structure shown in Figure 9(a), the corresponding convolutional deinterleaving process in the receiving processing module adopts the structure shown in Figure 9(b). Similarly, when the transmitting processing module adopts the convolutional interleaving structure shown in Figure 9(b), the corresponding convolutional deinterleaving process in the receiving processing module adopts the structure shown in Figure 9(a).

[0073] The first bit set is as follows Figure 8 As shown in the figure, the second bit set also includes R rows and K columns of bits. The K bits in each row of the second bit set are K bits are output from the delay line. In one possible scenario, K is divisible by d, P×d is divisible by K, It is divisible by P. In this way, before performing convolution interleaving on the data in the first bit set, the input and output switches of the convolution interleaver are initialized to delay line 0. After all the data in the first bit set is input into the convolution interleaver, the input and output switches of the convolution interleaver are returned to delay line 0. This facilitates synchronization of the deconvolution interleaver at the receiving end.

[0074] 104. Perform a second FEC encoding on the second bit set to obtain a third bit set.

[0075] Figure 10 Schematic diagram of the implementation method of performing the second FEC encoding on the second bit set in the embodiment of the present application. Figure 10 As shown, the third bit set includes R code words encoded by the inner code, and each code word includes K information bits and NK check bits, totaling N bits. Taking the second bit set including R rows and K columns of bits as an example, the third bit set obtained by performing inner code encoding on the second bit set includes R rows and N columns of bits. Among them, the N bits in each row of the third bit set can be regarded as an inner code code word. It should be understood that in the embodiment of the present application, the number of padding bits d pad Cannot be divided by K. In order to use a BCH codeword with lower complexity and capable of correcting 2 bits as the inner codeword after filling bits, a codeword whose number of bits v of the coded data frame cannot be divided by the number of information bits K can be selected. pad bits, so that the number of bits contained in the first data set is an integer number K of information bits, which facilitates rapid outer code synchronization after inner code synchronization.

[0076] In a possible implementation manner, the inner code encoding of the embodiment of the present application may specifically adopt GF(2 m ) BCH coding or extended BCH coding with 2-bit error correction, while the length of the inner code word remains unchanged or slightly reduced, increases the error correction capability of the inner code word to 2 bits, thereby improving the performance of concatenated coding. GF refers to a finite field, also known as a Galois field, 2 m represents the order of a finite field.

[0077] Table 1 below provides several possible inner code encoding schemes, where N represents the length of the inner code codeword, K represents the length of the information bits in the inner code codeword, t represents the error correction capability of the inner code codeword as t bits, and OH represents the overhead of the outer code encoding + inner code encoding. It should be noted that in order to make the bits of each inner code codeword evenly mapped to the most significant bit (MSB) and the least significant bit (LSB) of the 4-way component of the DP-16QAM symbol, the length N of the inner code codeword should be an even number. In order to effectively improve the performance of cascade coding, one solution is to effectively control the decoding complexity while keeping the inner code codeword length unchanged at 128 bits or slightly reducing the inner code codeword length, and to increase the error correction capability of the inner code codeword from correcting 1-bit errors to correcting 2-bit errors. The corresponding codeword is a BCH code with t=2 or an extended BCH code.

[0078] Table 1

[0079] plan N K t OH 1 126 110 2 22.2％ 2 128 112 2 21.9％ 3 128 113 2 20.8％

[0080] 105. Perform symbol mapping and polarization division on the third bit set.

[0081] Specifically, symbol mapping and polarization division are performed on every 8 bits in the third bit set to obtain one DP-16QAM symbol. For example, M consecutive inner codewords are obtained from the third bit set, that is, M consecutive rows are obtained from the third bit set. Then, these M inner codewords with a total of N×M bits are mapped to L DP-16QAM symbols, where L=N×M / 8, that is, N×M is divisible by 8. Indicates that M inner codewords are mapped to the lth DP-16QAM symbol among L DP-16QAM symbols, where Respectively represent the X-polarization direction I-path (in-phase) component, X-polarization direction Q-path (quadrature-phase) component, Y-polarization direction I-path (in-phase) component, and Y-polarization direction Q-path (quadrature-phase) component of the l-th DP-16QAM symbol. Considering that any component of the DP-16QAM symbol is obtained by mapping the 2 bits of the inner codeword, and since the binary bit DP-16QAM symbol adopts Gray mapping, the probability of error of the 2 bits mapped to any component of the DP-16QAM symbol is inconsistent. In order to improve the performance of concatenated coding, Any component in the mth inner codeword is obtained by mapping two consecutive bits in the mth inner codeword. In other words, any component of the DP-16QAM symbol is obtained by mapping two consecutive bits in the same codeword. In this way, the two bits with different error probabilities in any component are evenly distributed to each inner codeword.

[0082] Furthermore, a mapping scheme is to map the N bits of the inner codeword to the same components of N / 2 DP-16QAM. For example, the 4 components of the 1st DP-16QAM symbol The mapping relationship corresponding to the M inner code words is:

[0083] from code words No. Bit and Bitmap is obtained;

[0084] from code words No. Bit and Bitmap is obtained;

[0085] from code words No. Bit and Bitmap is obtained;

[0086] from code words No. Bit and Bitmap obtained.

[0087] Among them, a%b means a modulo b, Indicates rounding down. Indicates rounding up.

[0088] Furthermore, considering that the error probabilities on the four components are inconsistent, each inner codeword can be evenly mapped to the four components, with at least bits are mapped to On the same component of a DP-16QAM symbol, the maximum number of inner code words is bits are mapped to On the same component of a DP-16QAM symbol, Indicates rounding a down. Indicates rounding a upwards.

[0089] In one possible implementation, every 8 consecutive bits in the inner codeword are mapped to 4 different components of 4 DP-16QAM symbols. In another possible implementation, when N is a multiple of 8, every 8 consecutive bits in the inner codeword are mapped to 1 DP-16QAM symbol.

[0090] The above introduces the data processing method provided in the embodiments of the present application. It should be understood that in some possible scenarios, considering the potential need for the FEC solution to be compatible with throughput rates such as 1.6T, 800G, 400G, and the problem of hardware implementation at ultra-high throughput rates, a multi-channel parallel data processing solution can also be proposed based on the aforementioned embodiments. Figure 11 This is a schematic diagram of an implementation of a multi-channel parallel transmitting end data processor in the embodiment of the present application. Figure 11 As shown, first distribute the input data stream to obtain 4 data streams, and then follow Figure 3 The data processing method shown performs data processing on each data stream after distribution.

[0091] Figure 12 This is a schematic diagram of an implementation method of data distribution in the embodiment of this application. Figure 12 As shown in the figure, first obtain continuous 4×119×10280 bits of data, then poll and distribute them according to the granularity of h bits to obtain 4 data frames. The bits in each data frame are arranged as 119 rows and 10280 columns. The 4 data frames are encoded by outer code to obtain 4 encoded data frames, and then according to Figure 3 The following data processing is performed on each coded data frame in the manner shown. It should be understood that 10280% (4×h) = 0, for example, h = 1, 257, 514 or 1285. This solution can be well compatible with 1.6T, 800G, 400G and other throughput rates. As an example, when the input data frame is a 1.6T service, the data frame can be processed according to Figure 11 As another example, when the input data frame is an 800G service, the data frame can be distributed to 2 channels for processing, and the other 2 channels can be turned off to save power. As another example, when the input data frame is a 400G service, the data frame distribution can be omitted and the data frame can be directly processed as shown in the following example. Figure 3 The data processing shown is as follows, and the other 3 channels are turned off to save power.

[0092] Several specific embodiments are provided below in combination with several different implementations of inner code encoding.

[0093] Embodiment 1: The inner code adopts (126, 110) coding, that is, the length of the inner code codeword is 126 bits, and the inner code codeword includes 110 information bits.

[0094] As a first example, the number of padding bits d pad =490, such as Figure 8 The first bit set shown includes 11872 rows and 110 columns of bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = 110 bits. As a second example, the number of padding bits d pad =50, such as Figure 8 The first bit set shown includes 11,868 rows and 110 columns of bits. The convolutional interleaver includes P = 24 delay lines, with two adjacent delay lines differing by Q = 4 storage units. Each storage unit contains d = 55 bits. In this case, the 110 bits output by two consecutive delay lines in the convolutional interleaver are mapped to the information data of an inner code. It should be understood that compared to the first example, the second example reduces the number of padding bits, reduces system redundancy, and increases the depth of the convolutional interleaver, thereby improving the performance of cascaded coding.

[0095] The inner code of this embodiment 1 can use the double-extended BCH code (126,110), which is denoted as DE-BCH (126,110). DE-BCH (126,110) is constructed on the finite field GF (2 7) is a 2-bit CRC extended BCH code with 2-bit error correction. The 16 parity bits in the inner codeword include a 2-bit cyclic redundancy check (CRC) extended parity bit. The generating polynomial of DE-BCH (126, 110) can be expressed as:

[0096] g1(x)=M1(x)M3(x)(x 2 +1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x 2 +1)

[0097] =x 16 +x 14 +x 11 +x 10 +x 9 +x 7 +x 5 +x 3 +x+1

[0098] Among them, M1(x) and M3(x) correspond to GF(2 7 ) element α 1 With α 3 The minimum polynomial of α is a finite field GF(2 7 ) primitive element. The 110-bit information sequence to be encoded is represented as A[0:109]=[a0,a1,…,a 109 ], each bit of which is used as the coefficient of the information polynomial with the highest degree of 109. For example, a0 is the first bit received in the information sequence to be encoded, and is the coefficient of the highest degree 109 of the information polynomial. 109 is the last received bit in the information sequence to be encoded, corresponding to the coefficient of the 0th order term of the information polynomial. The information polynomial m(x) = a0x can be obtained 109 +a1x 108 +a2x 107 +…+a 107 x 2 ++a 108 x+a 109 .x 16 m(x) is divided by g1(x) using modulo 2 division to obtain the remainder polynomial r(x) = p0x 15 +p1x 14 +p2x 13 +…+p 13 x 2 +p 14 x+p 15, that is, r(x)=x 16 m(x)(modulo g1(x)). Then by c(x)=x 16 m(x)+r(x) ​​obtains the code polynomial c(x) with the highest degree of 125. The coefficients of each term in c(x) are the encoded codewords. The codeword constructed in this way is the system codeword, that is, codeword C[0:109]=[c0,c1,…,c 125 ] bits c0 to c 109 and bits a0 to a of the information sequence to be encoded respectively 109 One-to-one correspondence, bit c in C[0:125] 110 to Bit C 125 and check sequence bits p0 to p respectively 15 One to one correspondence.

[0099] In one possible implementation, M=4 consecutive inner code words are taken from the third bit set after inner code encoding, and mapped into 63 consecutive DP-16QAM symbols. The four components of the first DP-16QAM symbol are: The mapping relationship corresponding to the four inner code words is:

[0100] from code words The 2×1+1%2 bits and the 2×1+(1+1)%2 bits are mapped to obtain;

[0101] from code words The 2×1+1%2 bits and the 2×1+(1+1)%2 bits are mapped to obtain; By self-coded words The 2×1+1%2 bits and the 2×1+(1+1)%2 bits are mapped to obtain;

[0102] By self-coded words The 2×1+1%2 bits and the 2×1+(1+1)%2 bits are mapped to obtain;

[0103] Among them, 0≤l<63.

[0104] In another possible implementation, M=8 or 16 consecutive inner code words are taken from the third bit set after inner code encoding and mapped to 126 or 252 consecutive DP-16QAM symbols. In order to make each inner code word evenly mapped to each component of the DP-16QAM symbol, 8 consecutive bits from the 8ith bit to the 8i+7th bit of the mth inner code word are mapped to 4 different components of 4 DP-16QAM symbols, and 6 bits from the 120th bit to the 125th bit of the mth inner code word are mapped to 3 different components of 3 DP-16QAM symbols. In addition, in the 4 consecutive inner code words from the 4jth inner code word to the 4j+3th inner code word, 8 bits from the 2kth bit to the 2k+1th bit in each code word are mapped to 1 DP-16QAM symbol. Where 0≤m <M,0≤i<15, 0≤k<63. One possible implementation is the 4 components of the first DP-16QAM symbol The mapping relationship corresponding to the M inner code words is:

[0105] from code words No. Bit and Bitmap is obtained;

[0106] from code words No. Bit and

[0107] Bitmap is obtained;

[0108] from code words No. Bit and Bitmap is obtained;

[0109] from code words No. Bit and Bitmap is obtained;

[0110] Among them, 0≤l<63×M / 4.

[0111] Figure 13 This is a schematic diagram of an application scenario of internal code encoding in the embodiment of this application. Figure 13As shown, first, the adjacent two bits in the information sequence to be encoded A[0:109] are divided into a group, and the two bits in each group are XORed to obtain a 55-bit sequence B[0:54]=[b0,b1,…,b 54 Then, the sequence B is encoded with DE-BCH (71,55) to generate 16 check bits [p0, p1, ..., p 15 ]. Among them, DE-FEC (71,55) is constructed on the finite field GF (2 7 ) on the extended BCH codeword of t = 2. The generating polynomial of DE-FEC (71, 55) can be expressed as:

[0112] g1(x)=M1(x)M3(x)(x 2 +1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x 2 +1)

[0113] =x 16 +x 14 +x 11 +x 10 +x 9 +x 7 +x 5 +x 3 +x+1

[0114] The information sequence to be encoded is B[0:54]=[b0,b1,…,b 54 ] A total of 55 bits are used as coefficients of the information polynomial with the highest degree of 54. For example, b0 is the coefficient of the highest degree 54 of the information polynomial, b 54 Corresponding to the coefficient of the 0th order term of the information polynomial, we can get the information polynomial m(x)=b0x 54 +b1x 53 +b2x 52 +…+b 52 x 2 +b 53 x+b 54 .x 16 m(x) is divided by g1(x) by modulo 2 division to obtain the remainder polynomial r(x), that is, r(x) = x 16 m(x)(modulo g1(x)), 16 check bits [p0,p1,…,p 15] are the coefficients of the remainder polynomial r(x) from the highest to the lowest order. Finally, the information sequence A and the check sequence P form a complete codeword sequence of the inner code (126,110), which is recorded as C[0:125]=[c0,c1,…,c 125 ], which can be expressed as: It can be seen that the inner code encoding method transfers the encoding operation to a shorter codeword through the group XOR method, thereby reducing the decoding complexity.

[0115] Embodiment 2: The inner code adopts (128, 112) coding, that is, the length of the inner code codeword is 128 bits, and the inner code codeword includes 112 information bits.

[0116] As a first example, the number of padding bits d pad =938, such as Figure 8 The first bit set shown includes 11664 rows and 112 columns of bits, the convolution interleaver includes P = 16 delay lines, the difference between two adjacent delay lines is Q = 2 storage units, and each storage unit includes d = 112 bits. As a second example, the number of padding bits d pad =42, such as Figure 8 The first bit set shown includes 11656 rows and 112 columns of bits, the convolution interleaver includes P=62 delay lines, the difference between two adjacent delay lines is Q=4 storage units, and each storage unit includes d=56 bits.

[0117] The inner code of this embodiment 1 can use the double-extended BCH code (128,112), which is denoted as DE-BCH (128,112). DE-BCH (128,112) is constructed on the finite field GF (2 7 ) is an extended BCH code with 2 bits of error correction on the inner codeword. The 16 check bits in the inner codeword include 2 bits of CRC extended check bits. The generating polynomial of DE-BCH(128,112) can be expressed as:

[0118] g1(x)=M1(x)M3(x)(x 2 +1)=(x 7 +x 3 +1)(x 7 +x 3 +x 2 +x+1)(x 2 +1)

[0119] =x 16 +x 14 +x 11 +x 10 +x 9 +x7 +x 5 +x 3 +x+1

[0120] Among them, M1(x) and M3(x) correspond to GF(2 7 ) element α 1 With α 3 The minimum polynomial of α is a finite field GF(2 7 ) primitive element. The 112-bit information sequence to be encoded is represented as A[0:111]=[a0,a1,…,a 111 ], each bit of which is used as the coefficient of the information polynomial with the highest degree of 111. For example, a0 is the first bit received in the information sequence to be encoded, and is the coefficient of the highest degree 111 of the information polynomial. 111 is the last received bit in the information sequence to be encoded, corresponding to the coefficient of the 0th order term of the information polynomial. The information polynomial m(x) = a0x can be obtained 111 +a1x 110 +a2x 109 +…+a 109 x 2 ++a 110 x+a 111 .x 16 m(x) is divided by g1(x) using modulo 2 division to obtain the remainder polynomial r(x) = p0x 15 +p1x 14 +p2x 13 +…+p 13 x 2 +p 14 x+p 15 , that is, r(x)=x 16 m(x)(modulo g1(x)). Then by c(x)=x 16 m(x)+r(x) ​​obtains the code polynomial c(x) with the highest degree of 125. The coefficients of each term in c(x) are the encoded codewords. The codeword constructed in this way is the system codeword, that is, codeword C[0:127]=[c0,c1,…,c 127 ] bits c0 to c 111 and bits a0 to a of the information sequence to be encoded respectively 111 One-to-one correspondence, bit c in C[0:127] 112 to Bit C 127 and check sequence bits p0 to p respectively 15 One to one correspondence.

[0121] In one possible implementation, M=4 or 8 or 16 consecutive inner code words are taken from the third bit set after inner code encoding and mapped to 16×M64 or 128 consecutive DP-16QAM symbols. In order to make each inner code word evenly mapped to each component of the DP-16QAM symbol, the 8i-th bit to the 8i+7-th bit of the m-th inner code is mapped to 4 different components of 4 DP-16QAM symbols. Moreover, in the 4 consecutive inner code words from the 4j-th inner code word to the 4j+3 inner code word, a total of 8 bits, namely the 2k-th bit and the 2k+1-th bit in each code word, are mapped to 1 DP-16QAM symbol. Wherein, 0≤m <M,0≤i<16, 0≤k<64. Two specific implementations are given below. One possible implementation is the 4 components of the first DP-16QAM symbol. The mapping relationship corresponding to the M inner code words is:

[0122] from code words No. Bit and Bitmap is obtained;

[0123] from code words No. Bit and Bitmap is obtained;

[0124] By self-coded words No. Bit and Bitmap is obtained;

[0125] By self-coded words No. Bit and Bitmap is obtained;

[0126] Among them, 0≤l<16×M.

[0127] In another possible implementation, the four components of the first DP-16QAM symbol The mapping relationship corresponding to the M inner code words is:

[0128] from code words No. Bit and Bitmap is obtained;

[0129] from code words No. Bit and Bitmap is obtained;

[0130] from code words No. Bit and Bitmap is obtained;

[0131] from code words No. Bit and Bitmap is obtained;

[0132] Where, 0≤l<16×M, and ^ represents a bitwise exclusive OR operation.

[0133] It should be understood that since the length of the inner code word is 128, which is an integer multiple of 8, a simpler mapping method is to map the 8*i bit to the 8*i+7 bit of the m-th code word in the M=4 or 8 or 16 inner codes to the M×i+m-th DP-16PAM symbol in the 16×M DP-16PAM symbols, where 0≤m <M,0≤i<15。

[0134] Embodiment 3: The inner code adopts (128, 113) coding, that is, the length of the inner code codeword is 128 bits, and the inner code codeword includes 113 information bits.

[0135] Example 3 changes the inner code to a single-bit extended error correction 2-bit BCH code based on Example 2, which can reduce the redundancy of the system without reducing the performance. In Example 3, the number of padding bits d pad =1754, such as Figure 8 The first bit set shown includes 11568 rows and 113 columns of bits, the convolution interleaver includes P=16 delay lines, the difference between two adjacent delay lines is Q=2 storage units, and each storage unit includes d=113 bits.

[0136] The inner code of this embodiment 3 can use the (128,113) single-bit extended BCH code, which is denoted as E-BCH (128,113). E-BCH (128,113) is constructed on the finite field GF (2 7 ) is a 1-bit CRC extended BCH code with 2-bit error correction. The 15 check bits in the inner codeword include a 1-bit CRC extended check bit. The generating polynomial of E-BCH (128, 113) can be expressed as:

[0137] g2(x)=M1(x)M3(x)(x+1)=(x 7 +x3 +1)(x 7 +x 3 +x 2 +x+1)(x+1)

[0138] =x 16 +x 14 +x 10 +x 8 +x 7 +x 4 +x 3 +1

[0139] Among them, M1(x) and M3(x) correspond to GF(2 7 ) element α 1 With α 3 The minimum polynomial of α is a finite field GF(2 7 ) primitive element. The 112-bit information sequence to be encoded is represented as A[0:112]=[a0,a1,…,a 112 ], each bit of which is used as the coefficient of the information polynomial with the highest degree of 112. For example, a0 is the first bit received in the information sequence to be encoded, and is the coefficient of the highest degree 112 of the information polynomial. 112 is the last received bit in the information sequence to be encoded, corresponding to the coefficient of the 0th order term of the information polynomial. The information polynomial m(x) = a0x can be obtained 112 +a1x 111 +a2x 110 +…+a 110 x 2 ++a 111 x+a 112 .x 15 m(x) is divided by g2(x) using modulo 2 division to obtain the remainder polynomial r(x) = p0x 14 +p1x 13 +p2x 12 +…+p 12 x 2 +p 13 x+p 14 , that is, r(x)=x 15 m(x)(modulo g2(x)). Then by c(x)=x 15 m(x)+r(x) ​​obtains the code polynomial c(x) with the highest degree of 128. The coefficients of each term in c(x) are the encoded codewords. The codeword constructed in this way is the system codeword, that is, codeword C[0:127]=[c0,c1,…,c 127 ] bits c0 to c 112 and bits a0 to a of the information sequence to be encoded respectively 112One-to-one correspondence, bit c in C[0:127] 113 to Bit C 127 and check sequence bits p0 to p respectively 14 The third bit set after inner code encoding can be mapped into DP-16QAM symbols using any of the methods in Example 2.

[0140] Figure 14 FIG. 1 is a structural diagram of a data processing device in an embodiment of the present application. Figure 14 As shown, the data processing device includes an acquisition unit 201, a padding unit 202, a convolutional interleaving unit 203, an encoding unit 204, and a mapping unit 205. Optionally, the data processing device also includes a scrambling unit 206. The acquisition unit 201 is used to perform the operations of step 101 above, the padding unit 202 is used to perform the operations of step 102 above, the convolutional interleaving unit 203 is used to perform the operations of step 103 above, the encoding unit 204 is used to perform the operations of step 104 above, and the mapping unit 205 is used to perform the operations of step 105 above. It should be understood that the data processing device provided in this application can also be implemented in other ways. For example, the unit division in the above device is merely a logical functional division. In actual implementation, there may be other division methods, for example, multiple units or components can be combined or integrated into another system. In addition, the functional units in various embodiments of the present application can be integrated into a single processing unit, or can be independent physical units, or two or more functional units can be integrated into a single processing unit. The above integrated units can be implemented in the form of hardware or software functional units.

[0141] Figure 15 FIG. 1 is another structural diagram of the data processing device in the embodiment of the present application. Figure 15 As shown, the data processing device includes a processor 301 and a transceiver 302. The processor 301 and the transceiver 302 are connected to each other via a line. Specifically, the transceiver 302 is used to perform data transmission and reception operations, and the processor 301 is used to perform other operations except data transmission and reception. In a possible embodiment, the processor 301 may include the above Figure 14 The filling unit 202, the convolution interleaving unit 203, the encoding unit 204 and the mapping unit 205 shown in the figure, the transceiver 302 includes the above Figure 14 The obtaining unit 201 is shown. Optionally, the data processing device may further include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0142] The present application also provides a chip. This chip integrates circuitry and one or more interfaces for implementing the functions of the processor 301 described above. When the chip integrates memory, it can perform the method steps of any one or more of the aforementioned embodiments. When the chip does not integrate memory, it can be connected to an external memory via an interface. The chip implements the actions performed by the transmitting device or receiving device in the aforementioned embodiments based on program code stored in the external memory.

[0143] Finally, it should be noted that the above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A data processing method, characterized in that: include: Obtaining a coded data frame after first forward error correction FEC encoding, wherein the coded data frame includes v bits, where v is an integer greater than 1; According to the encoded data frame and the added d pad The number of bits in the first bit set is v+d. pad , d pad is an integer greater than or equal to 1; Performing convolution interleaving on the first bit set to obtain a second bit set; Perform a second FEC encoding on the second bit set to obtain a third bit set, wherein the third bit set includes R codewords encoded by the second FEC, each of the codewords includes K information bits and NK check bits, a total of N bits, R, N and K are all integers greater than 1, v+d pad =R×K,d pad Not divisible by K.

2. The method according to claim 1, characterized in that Performing convolution interleaving on the first bit set to obtain a second bit set includes: The bits from the first bit set are delayed according to P delay lines, where P is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between every two adjacent delay lines is Q. Each storage unit is used to store d bits. The input bits are input into the P delay lines in sequence according to the sequence numbers of the P delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. The continuous P×d bits output after convolution interleaving include d bits output by each delay line, and Q and d are both integers greater than or equal to 1.

3. The method according to claim 2, characterized in that K is divisible by d, P×d is divisible by K, Divisible by P.

4. The method according to claim 2 or 3, characterized in that: The second bit set includes R rows and K columns of bits, and the K bits in each row of the second bit set are The K bits output by the delay line, performing the second FEC encoding on the second bit set to obtain a third bit set comprises: The second FEC encoding is performed on the K bits in each row of the second bit set to obtain N bits of each codeword in the third bit set.

5. The method according to any one of claims 1 to 4, characterized in that After performing a second FEC encoding on the second bit set to obtain a third bit set, the method further includes: Symbol mapping and polarization division are performed on every 8 bits in the third bit set to obtain one dual-polarization DP-16QAM symbol, wherein any one of the I component in the X polarization direction, the Q component in the X polarization direction, the I component in the Y polarization direction, and the Q component in the Y polarization direction of the DP-16QAM symbol is obtained by mapping two consecutive bits in one codeword, and the X polarization direction is orthogonal to the Y polarization direction.

6. The method according to claim 5, characterized in that At least one of the code words bits are mapped to On the same component of a DP-16QAM symbol, the codeword has a maximum of bits are mapped to On the same component of a DP-16QAM symbol, It means to round down a. Indicates rounding a upwards.

7. The method according to claim 6, characterized in that The 8 consecutive bits from the 8ith bit to the 8i+7th bit in the codeword are mapped to 4 different components of 4 DP-16QAM symbols. The f consecutive bits from the first bit to the N-1th bit are mapped to f / 2 different components of f / 2 DP-16QAM symbols. A total of 8 bits, including 2 adjacent bits from each codeword in the 4 consecutive codewords, are mapped to 1 DP-16QAM symbol.

8. The method according to claim 6, characterized in that The N is divisible by 8, and 8 consecutive bits in the codeword are mapped to 1 DP-16QAM symbol.

9. The method according to any one of claims 1 to 8, characterized in that Before obtaining the encoded data frame after the first FEC encoding, the method further includes: Distribute the first data stream to obtain four second data streams; The first FEC encoding is performed on each of the second data streams to obtain the encoded data frame.

10. The method according to any one of claims 1 to 9, characterized in that Before performing convolution interleaving on the first bit set to obtain a second bit set, the method further includes: The first set of bits is scrambled.

11. The method according to any one of claims 1 to 10, characterized in that The second FEC code uses a finite field GF(2 m ) BCH coding or extended BCH coding with 2 bits of error correction.

12. The method according to any one of claims 1 to 11, characterized in that The coded data frame includes r rows and w columns of bits, where r=119, w=10970; or r=595, w=2194.

13. The method according to any one of claims 1 to 12, characterized in that K=110, N=126, or K=112, N=128, or K=113, N=128.

14. The method according to any one of claims 2 to 13, characterized in that K=110, N=126, P=16, d=110, d pad =490; or, K = 112, N = 128, P = 16, d = 112, d pad =938; or, K = 113, N = 128, P = 16, d = 113, d pad =1754; or, K = 112, N = 128, P = 62, d = 56, d pad =42; or, K = 110, N = 126, P = 24, d = 55, d pad =50.

15. A data processing device, characterized in that: The data processing device comprises: an acquisition unit, a filling unit, a convolution interleaving unit and an encoding unit; The acquisition unit is used to: acquire a coded data frame that has been coded by a first forward error correction (FEC) method, wherein the coded data frame includes v bits, where v is an integer greater than 1; The filling unit is used to: according to the coded data frame and the added d pad The number of bits in the first bit set is v+d. pad , d pad is an integer greater than or equal to 1; The convolution interleaving unit is used to: perform convolution interleaving on the first bit set to obtain a second bit set; The encoding unit is used to: perform a second FEC encoding on the second bit set to obtain a third bit set, wherein the third bit set includes R code words encoded by the second FEC, each of the code words includes K information bits and NK check bits, a total of N bits, R, N and K are all integers greater than 1, v+d pad =R×K,d pad Not divisible by K.

16. The data processing device according to claim 15, characterized in that: The convolution interleaving unit is specifically used for: The bits from the first bit set are delayed according to P delay lines, where P is an integer greater than 1, and each delay line includes a different number of storage units. The delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between every two adjacent delay lines is Q. Each storage unit is used to store d bits. The input bits are input into the P delay lines in sequence according to the sequence numbers of the P delay lines. Each delay line inputs d bits at a time and outputs d bits at a time. The continuous P×d bits output after convolution interleaving include d bits output by each delay line, and Q and d are both integers greater than or equal to 1.

17. The data processing device according to claim 16, characterized in that: K is divisible by d, P×d is divisible by K, Divisible by P.

18. The data processing device according to claim 16 or 17, characterized in that: The second bit set includes R rows and K columns of bits, and the K bits in each row of the second bit set are The coding unit is specifically used for: The second FEC encoding is performed on the K bits in each row of the second bit set to obtain N bits of each codeword in the third bit set.

19. The data processing device according to any one of claims 15 to 18, characterized in that: The data processing device further comprises a mapping unit, wherein the mapping unit is configured to: Symbol mapping and polarization division are performed on every 8 bits in the third bit set to obtain one dual-polarization DP-16QAM symbol, wherein any one of the I component in the X polarization direction, the Q component in the X polarization direction, the I component in the Y polarization direction, and the Q component in the Y polarization direction of the DP-16QAM symbol is obtained by mapping two consecutive bits in one codeword, and the X polarization direction is orthogonal to the Y polarization direction.

20. The data processing device according to claim 19, characterized in that At least one of the code words bits are mapped to On the same component of a DP-16QAM symbol, the codeword has a maximum of bits are mapped to On the same component of a DP-16QAM symbol, It means to round down a. Indicates rounding a upwards.

21. The data processing device according to claim 20, characterized in that: The 8 consecutive bits from the 8ith bit to the 8i+7th bit in the codeword are mapped to 4 different components of 4 DP-16QAM symbols. The f consecutive bits from the first bit to the N-1th bit are mapped to f / 2 different components of f / 2 DP-16QAM symbols. A total of 8 bits, including 2 adjacent bits from each codeword in the 4 consecutive codewords, are mapped to 1 DP-16QAM symbol.

22. The data processing device according to claim 20, characterized in that: The N is divisible by 8, and 8 consecutive bits in the codeword are mapped to 1 DP-16QAM symbol.

23. The data processing device according to any one of claims 15 to 22, characterized in that: The data processing device further includes a processing unit, which is used to: Distribute the first data stream to obtain four second data streams; The first FEC encoding is performed on each of the second data streams to obtain the encoded data frame.

24. The data processing device according to any one of claims 15 to 23, characterized in that: The data processing device further includes a scrambling unit, which is used to: The first set of bits is scrambled.

25. The data processing device according to any one of claims 15 to 24, characterized in that: The second FEC code uses a finite field GF(2 m ) BCH coding or extended BCH coding with 2 bits of error correction.

26. The data processing device according to any one of claims 15 to 25, characterized in that: The coded data frame includes r rows and w columns of bits, where r=119, w=10970; or r=595, w=2194.

27. The data processing device according to any one of claims 15 to 26, characterized in that: K=110, N=126, or K=112, N=128, or K=113, N=128.

28. The data processing device according to any one of claims 15 to 27, characterized in that: K=110, N=126, P=16, d=110, d pad =490; or, K = 112, N = 128, P = 16, d = 112, d pad =938; or, K = 113, N = 128, P = 16, d = 113, d pad =1754; or, K = 112, N = 128, P = 62, d = 56, d pad =42; or, K = 110, N = 126, P = 24, d = 55, d pad =50.

29. A chip, characterized in that: The chip includes a processor and a memory, wherein the memory and the processor are connected to each other via a line, instructions are stored in the memory, and the processor is used to execute the method according to any one of claims 1 to 14.

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