Modular multiplication mask circuit applied to post quantum cryptography algorithm and capable of resisting side channel attack

Abstract

The invention discloses an anti-side channel attack modular multiplication mask circuit applied to a post quantum cryptography algorithm, which is characterized by comprising a random number generation unit, a modular multiplication unit and a control logic unit, the random number generation module is used for generating a pseudo-random number; the modular multiplication unit is used for performing modular multiplication operation on the first input data and the pseudo-random number to obtain first primary processing data, and performing modular multiplication operation on the second input data and an inverse element of the pseudo-random number to obtain second primary processing data; performing modular multiplication operation on the first primary processing data and the second primary processing data to obtain final output data; the control logic unit is used for controlling the random number generation unit and the modular multiplication unit to operate. According to the embodiment of the invention, the randomness of the calculation process is increased by introducing the pseudo-random number, the resistance to side channel attacks such as template attacks is improved, the security and anti-attack performance of the system are greatly improved, and the system is effectively protected from the side channel attacks.

Description

Technical Field

[0001] The present invention belongs to the field of post-quantum information security algorithms, digital signal processing and circuit implementation, and in particular relates to a modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms. Background Art

[0002] Side-Channel Attack is a cryptanalysis technique that cracks an encryption system by monitoring the "side channel" information generated by the physical implementation of the encryption system (such as current, voltage, processing time, etc.). This attack exploits the information leaked by the encryption device when performing encryption operations, rather than directly attacking the algorithm itself.

[0003] Instead of mathematically analyzing encryption algorithms to crack passwords, side channel attacks analyze the behavior of actual devices to obtain encryption keys or other sensitive information. These "side channels" may include electromagnetic radiation, power consumption analysis, timing analysis, etc. An important feature of side channel attacks is that they do not usually rely on knowledge of the specific implementation details of the encryption algorithm or the key. Instead, the attacker can analyze and infer the key or other sensitive information simply by monitoring the operation of the actual device.

[0004] Since side channel attacks are a very effective attack method, when designing a secure cryptographic system, in addition to considering the security of the encryption algorithm itself, it is also necessary to consider and resist side channel attacks. This may involve protecting the physical implementation, using anti-side channel technology, or considering the potential impact of side channel attacks when designing encryption algorithms. In this regard, the present invention provides a modular multiplication mask circuit that resists side channel attacks by introducing random numbers and is applied to post-quantum cryptographic algorithms, which can provide protection against side channel attacks when the encryption algorithm is operated. Summary of the invention

[0005] The technical problem to be solved by the present invention is that, in order to enable the post-quantum cryptographic algorithm to be protected against side channel attacks during operation, the present invention provides a modular multiplication mask circuit for resisting side channel attacks applied to the post-quantum cryptographic algorithm, comprising: a random number generation unit, a modular multiplication unit and a control logic unit;

[0006] The random number generation module is used to generate pseudo-random numbers;

[0007] The modular multiplication unit is used to perform modular multiplication operation on the first input data and the pseudo-random number to obtain the first preliminary processed data, and perform modular multiplication operation on the second input data and the inverse element of the pseudo-random number to obtain the second preliminary processed data; and then perform modular multiplication operation on the first preliminary processed data and the second preliminary processed data to obtain the final output data;

[0008] The control logic unit is used to control the operation of the random number generation unit and the modular multiplication unit;

[0009] Among them, the output end of the random number generation module is connected to the output end of the analog multiplication unit; the output end of the control logic unit is connected to the analog multiplication unit and the input end of the random number generation module; the input end of the analog multiplication unit is also connected to the first input data and the second input data.

[0010] Preferably, the modular multiplication unit includes a first modular multiplier, a second modular multiplier, a third modular multiplier and a first register;

[0011] Among them, the first modular multiplier is used to perform modular multiplication operation on the first input data and the pseudo-random number; the second modular multiplier is used to perform modular multiplication operation on the second input data and the inverse element of the pseudo-random number; the third modular multiplier is used to perform modular multiplication operation on the first pre-processed data and the second pre-processed data; the first register is used to output the inverse element of the pseudo-random number according to the input pseudo-random number.

[0012] Preferably, the first modular multiplier input terminal is connected to the pseudo-random number and the first input data respectively; the first register input terminal is connected to the random number generation unit output terminal and the control logic unit output terminal; the first register output terminal is connected to the second modular multiplier input terminal; the third modular multiplier input terminal is connected to the first modular multiplier output terminal and the second modular multiplier output terminal; the third modular multiplier is used to output the final output data.

[0013] Preferably, the modular multiplication unit further includes a second register; the second register is connected to the first register and is used to transmit the inverse element of the pseudo-random number to the second modular multiplier.

[0014] Preferably, the first modular multiplier includes a first multiplier, a first adder, a second adder, a third adder, a third register, a fourth register, a fifth register, a sixth register, a seventh register, a first subtractor, a first selector, a second selector and a first modular adder;

[0015] The first multiplier input end is connected to the pseudo-random number and the first input data, and the output end is connected to the third register input end; the third register output end is respectively connected to the fourth register, the fifth register, the sixth register, and the second adder input end; the fourth register and the fifth register output ends are connected to the first adder input end; the sixth register output end is connected to the second adder input end; the first adder and the second adder output ends are connected to the third adder input end; the third adder output end is connected to the seventh register input end; the seventh register output end is respectively connected to the first selector selection end, the second selector input end, and the first subtractor minuend end; the first selector output end and the second selector output end are connected to the first modulo adder input end; the first subtractor subtrahend end is connected to the first reference number, the output end is connected to the second selector input end, and the borrow end is connected to the second selector selection end; the first modulo adder output end outputs the first preliminary processed data.

[0016] Preferably, the fourth register stores all 4 bits*2 20 Modulo q = 3329 result; the fifth register stores all 4 bits * 2 16 Modulo q = 3329 result; the sixth register stores all 4 bits * 2 12 The result of modulo q=3329; the first selector input is all 2bits*2 12 Modulo the result of q=3329; the first reference number is the number 3329.

[0017] Preferably, the third register is used to store the 24 bits of data output by the first multiplier, and transmit the 1st to 12th bits of the 24 bits of data to the second adder, the 13th to 16th bits of the 24 bits of data to the sixth register, the 17th to 20th bits of the 24 bits of data to the fifth register, and the 21st to 24th bits of the 24 bits of data to the fourth register.

[0018] Preferably, the seventh register is used to store the 14 bits of data output by the third adder, and transmit the 1st to 12th bits of the 14 bits of data to the second selector input terminal and the minuend terminal of the first subtractor, and transmit the 13th to 14th bits of the 14 bits of data to the selection terminal of the first selector; the first modular multiplier, the second modular multiplier and the third modular multiplier have the same structure.

[0019] Preferably, the random number generation unit includes an eighth register, a ninth register, a first Keccak core and a second Keccak core;

[0020] Among them, the eighth register input end is connected to external data and a control logic unit, and the output end is connected to the ninth register input end; the ninth register output end is connected to the first Keccak core input end; the second Keccak core input end is connected to the first Keccak core output end, and the output ends are respectively connected to the ninth register input end and the modular multiplication unit input end; the ninth register input end is also connected to the control logic unit.

[0021] Preferably, the eighth register is used to roll the externally input 64 bits of data 25 times according to the control logic unit instruction to generate 1600 bits of data;

[0022] The ninth register is used to input the 1600 bits of data into the first Keccak core and the second Keccak core for circulation according to the control logic unit instruction;

[0023] The first Keccak core and the second Keccak core are used to generate a 1600-bit pseudo-random number based on the 1600-bit data, and transmit the 1589th to 1600th pseudo-random numbers to the modular multiplication unit.

[0024] The implementation of the embodiments of the present invention has the following beneficial effects:

[0025] (1) The embodiment of the present invention introduces a pseudo-random number through a random number generation module, and then performs a modular multiplication operation on the first input data and the pseudo-random number through a modular multiplication unit to obtain the first preliminary processed data, and performs a modular multiplication operation on the second input data and the inverse element of the pseudo-random number to obtain the second preliminary processed data, and then performs a modular multiplication operation on the first preliminary processed data and the second preliminary processed data to replace the original modular multiplication operation of the first input data and the second input data. The randomness of the pseudo-random number is used to interfere with the behavior of the actual device, thereby improving the resistance to side channel attacks such as template attacks. This effectively protects the system from side channel attacks, improves the security and anti-attack performance of the system, and reduces the risk of the system being attacked.

[0026] (2) In the embodiment of the present invention, the fourth register, the fifth register, and the sixth register are set in the modular multiplier to store all 4 bits*2 in advance. 20 Modulo q = 3329 result, all 4 bits * 2 16 Modulo q = 3329 result, 4 bits * 2 12The result of q=3329 on the module. The third register transmits different data to the fourth register, the fifth register, and the sixth register, which output corresponding data, thereby avoiding the processing of the data transmitted by the third register, improving the efficiency of modular multiplication in the modular multiplier, and thus achieving overall computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 This is a schematic diagram of a modular multiplication mask circuit architecture for resisting side channel attacks in a post-quantum cryptographic algorithm according to the present invention;

[0029] Figure 2 It is a diagram of the modular multiplier architecture in the modular multiplication mask circuit for resisting side channel attacks applied to the post-quantum cryptographic algorithm in the present invention;

[0030] Figure 3 This is an attack result diagram of the modular multiplication mask circuit for resisting side channel attacks applied to the post-quantum cryptographic algorithm in the present invention under 1200 energy trajectories of correlated power attacks. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0032] like Figure 1 As shown, the embodiment discloses a modular multiplication mask circuit for resisting side channel attacks applied to a post-quantum cryptographic algorithm, and the modular multiplication mask circuit for resisting side channel attacks applied to a post-quantum cryptographic algorithm includes: a random number generation unit 10, a modular multiplication unit 20, and a control logic unit 30. Among them, the output end of the random number generation module 10 is connected to the output end of the modular multiplication unit 20. The output end of the control logic unit 30 is connected to the input end of the modular multiplication unit 20 and the random number generation module 10. The input end of the modular multiplication unit 20 is also connected to the first input data and the second input data.

[0033] The random number generation module 10 is used to generate a pseudo-random number. The modular multiplication unit 20 is used to convert the first input data (s * ) is subjected to modular multiplication operation with a pseudo-random number to obtain first preliminary processed data, and the second input data (u) is subjected to modular multiplication operation with an inverse element of the pseudo-random number to obtain second preliminary processed data, wherein the inverse element of the pseudo-random number is the result of multiplying the pseudo-random number with the inverse element of the pseudo-random number and then taking the modulus modulo 1. The first preliminary processed data and the second preliminary processed data are then subjected to modular multiplication operation to obtain final output data. The control logic unit is used to control the operation of the random number generation unit and the modular multiplication unit.

[0034] The modular multiplication mask circuit for resisting side channel attacks applied to the post-quantum cryptographic algorithm increases the pseudo-random number by converting the original s * ×u is changed to (r×s * )×(rinv×u). * is the first input data, u is the second input data, r is a pseudo-random number, and rinv is the inverse element of the pseudo-random number. The randomness of the pseudo-random number r is used to interfere with the behavior of the actual device, thereby improving the resistance to side channel attacks such as template attacks. This effectively protects the system from side channel attacks, improves the security and anti-attack performance of the system, and reduces the risk of the system being attacked.

[0035] The modular multiplication unit 20 includes a first modular multiplier 210, a second modular multiplier 220, a third modular multiplier 230 and a first register 240. The input end of the first modular multiplier 210 is respectively connected to the pseudo-random number r, the first input data s * connected to the first input data s * Perform modular multiplication operation with the pseudo-random number r and output the first preliminary processed data (r×s * ). The input end of the first register 240 is connected to the output end of the random number generation unit 10 and the output end of the control logic unit 30, and is used to output the corresponding inverse element rinv of the pseudo-random number according to the input pseudo-random number r and the control signal output by the control logic unit 30. Among them, the first register 240 stores the results of the inverse elements rinv of all pseudo-random numbers. The output end of the first register 240 is connected to the input end of the second modular multiplier 220, and is used to perform modular multiplication operation on the second input data u and the inverse element rinv of the pseudo-random number, and output the second preliminary processed data (rinv×u). The input end of the third modular multiplier 230 is connected to the output end of the first modular multiplier 210 and the output end of the second modular multiplier 220, and is used to perform modular multiplication operation on the first preliminary processed data 9r×s * ) performs modular multiplication operation with the second preliminary processed data (rinv×u) and outputs the final output data.

[0036] In some embodiments, the modular multiplication unit 20 further includes a second register 250. The second register 250 is located between the first register 240 and the second modular multiplier 220, with an input end connected to an output end of the first register 240, and an output end connected to an input end of the second modular multiplier 220. The second register 250 is used to transmit the inverse element rinv of the pseudo-random number to the second modular multiplier 220, so as to speed up the transmission speed of the first register 240 and improve the overall efficiency.

[0037] The random number generation unit 10 includes an eighth register 110, a ninth register 120 and a pair of Keccak cores 130. The input end of the eighth register 110 is connected to the external data (Din) and the control logic unit 30, and the output end is connected to the input end of the ninth register 120. The eighth register 110 is used to roll 64 bits of external data 25 rounds according to the instruction of the control logic unit 30, fill and generate 1600 bits of data, and transmit the 1600 bits of data to the ninth register 120. The output end of the ninth register 120 is connected to the input end of a pair of Keccak cores 130, and the input end is also connected to the control logic unit 30. The ninth register 120 is used to input the 1600 bits of data into a pair of Keccak cores 130 for circulation according to the instruction (round) of the control logic unit 30. The instruction (round) can control the number of circulation rounds of the pair of Keccak cores 130, ranging from 1 to 8. The pair of Keccak cores 130 are connected in series. The second Keccak core input terminal is connected to the first Keccak core output terminal. The pair of Keccak core 130 output terminals are respectively connected to the ninth register input terminal and the modular multiplication unit 20 input terminal. The pair of Keccak cores 130 are used to generate a 1600-bit pseudo-random number using the Keccak algorithm according to the 1600-bit data, and transmit the 1589th to 1600th pseudo-random numbers to the modular multiplication unit 20, i.e., the pseudo-random number r.

[0038] In some embodiments, the random number generation unit 10 further includes a tenth register 140. The tenth register 140 is located between the pair of Keccak cores 130 and the modular multiplication unit 20, with an input end connected to an output end of the pair of Keccak cores 130, and an output end connected to the modular multiplication unit 20, for accelerating the transmission speed of the first register 240 and improving the overall efficiency.

[0039] See also Figure 2, the first modular multiplier 210, the second modular multiplier 220, and the third modular multiplier 230 have the same structure. The modular multiplier includes: a first multiplier 201, a first adder 202, a second adder 203, a third adder 204, a third register 205, a fourth register 206, a fifth register 207, a sixth register 208, a seventh register 209, a first subtractor 211, a first selector 212, a second selector 213, and a first modular adder 214. The multiplier is used for multiplication. The adder is used for addition. The subtractor is used for subtraction. The selector is used to selectively output the input end data according to the selected end. The modular adder is used for modular addition operation, that is, the data of the input end is added and then modulo taken.

[0040] In the first modular multiplier 210, the first multiplier 201 input terminal is connected to the pseudo-random number r and the first input data s * In the second modular multiplier 220 and the third modular multiplier 230, the input terminal is connected to the second input data u and the inverse element rinv of the pseudo-random number, the first preliminary processed data (r×s * ) is connected to the second preliminary processed data (rinv×u). The output end of the first multiplier 201 is connected to the input end of the third register 205. The output end of the third register 205 is respectively connected to the fourth register 206, the fifth register 207, the sixth register 208, and the input end of the second adder 203. Among them, the fourth register 206, the fifth register 207, and the sixth register 208 all output corresponding data according to the output data of the third register 205. The output ends of the fourth register 206 and the fifth register 207 are connected to the input end of the first adder 202. The output end of the sixth register 208 is connected to the input end of the second adder 203. The output ends of the first adder 202 and the second adder 203 are connected to the input end of the third adder 204. The output end of the third adder 204 is connected to the input end of the seventh register 209. The output end of the seventh register 209 is connected to the selection end of the first selector 212, the input end of the second selector 213, and the subtrahend end of the first subtractor 211 respectively. The output end of the first selector 212 and the output end of the second selector 213 are connected to the input end of the first modular adder 214. The subtrahend end of the first subtractor 211 is connected to the first reference number, the output end is connected to the input end of the second selector 213, and the borrow end is connected to the selection end of the second selector 213. The first reference number is 3329. In the first modular multiplier 210, the output end of the first modular adder 214 outputs the first pre-processed data.

[0041] The fourth register stores all 4 bits*2 20 The result of q=3329 modulo is the number 0-15 multiplied by 220 The result of modulo q=3329 is 16 data in total. The fifth register stores all 4 bits*2 16 The result of modulo q=3329. The sixth register stores all 4 bits*2 12 Result modulo q=3329.

[0042] The third register 205 is used to store the 24 bits of data output by the first multiplier 201, and transmits the 1st to 12th bits of the 24 bits of data to the second adder 203, i.e., the lowest 12 bits of data (referred to as the low 12 bits of data). The third register 205 transmits the 13th to 16th bits of the 24 bits of data to the sixth register 208, i.e., the middle 4 bits of data (referred to as the middle 4 bits of data). The third register 205 transmits the 17th to 20th bits of the 24 bits of data to the fifth register 207, i.e., the middle and high 4 bits of data (referred to as the middle and high 4 bits of data). The third register 205 transmits the 21st to 24th bits of the 24 bits of data to the fourth register 206, i.e., the highest 4 bits of data (referred to as the high 4 bits of data).

[0043] The seventh register 209 is used to store the 14-bit data output by the third adder 204, and transmit the 14-bit data from the 1st to the 12th bit to the input end of the second selector 213 and the minuend end of the first subtractor 211, and transmit the 13th to the 14th bit to the selection end of the first selector 212. The first selector input end is all 2 bits*2 12 The result of modulo q=3329 is the number 0-3 multiplied by 2 12 The result of modulo q=3329 is a total of 4 data.

[0044] When the modular multiplier is running, the input 12-bit data a and b are passed through the first multiplier 201 to obtain 24-bit data, which are stored in the third register 205. The third register 205 divides the obtained 24-bit data into four parts, namely, low 12-bit data, middle 4-bit data, middle and high 4-bit data and high 4-bit data. The high 4-bit data has 16 possibilities, namely, numbers 0-15. The fourth register 206 stores all 4 bits*2 20 The result of modulo q=3329. When the upper 4 bits of data are input to the fourth register 206, the fourth register 206 will output the corresponding number multiplied by 2 20The result of q=3329 on the module. The fifth register 207 and the sixth register 208 are similar, and output the corresponding data. By storing the data that needs to be calculated in advance to replace the modular multiplication operation, the modular multiplication efficiency of the modular multiplier is significantly improved, thereby improving the overall efficiency of the system. The output data (h) of the fourth register 206 and the output data m of the fifth register 207 will enter the first adder 202 for addition. The output data (l) of the sixth register 208 and the lower 12 bits of data will enter the second adder 203 for addition. The output results of the first adder 202 and the second adder 203 will enter the third adder 204 for addition, and output 14 bits of data (s) to the seventh register 209. The seventh register 209 divides the 14 bits of data into two parts, namely 12 bits of data and 2 bits of data. There are 4 cases for the 2 bits of data, namely the numbers 0-3. The input end of the first selector 212 is all 2 bits*2 12 When the seventh register 209 transmits the 2 bits of data to the selection terminal of the first selector 212, the first selector 212 outputs the corresponding number multiplied by 2. 12 The result of q=3329 on the module. By storing the data that needs to be calculated in advance to replace the modular multiplication operation, the modular multiplication efficiency of the modular multiplier is significantly improved. The 12 bits of data are transmitted to the second selector 213 and the first subtractor 211 respectively, serving as the input and minuend data. The subtrahend end of the first subtractor 211 is the first reference number of q=3329. The output data of the first subtractor 211 will be transmitted to the second selector 213 as the input end. The borrow end of the first subtractor 211 is connected to the selection end of the second selector 213, and the 12 bits of data or the 12 bits of data minus the first reference number is selected by whether to borrow. When borrowing is required, the 12 bits of data are selected, otherwise the 12 bits of data minus the first reference number are selected. The output data (j) of the first selector 212 and the output data (k) of the second selector 213 are input to the first modular adder 214 for modular addition operation to output final data a·b mod q.

[0045] See also Figure 3 , the attack result of the modular multiplication mask circuit for resisting side channel attacks applied to the post-quantum cryptographic algorithm under 1200 energy trajectories of related power attacks is shown in the figure. The figure shows the minimum exposure trajectory measurement diagram of the modular multiplier related power consumption attack after adopting the above structure. The attacker cannot predict the correct result. It can be seen that the modular multiplication mask circuit for resisting side channel attacks applied to the post-quantum cryptographic algorithm can effectively protect the Kyber modular multiplication process from side channel attacks and improve the security and reliability of the system.

[0046] In summary, the embodiment of the present invention adopts the modular multiplication mask circuit for resisting side channel attacks applied to the post-quantum cryptographic algorithm to make the original s * ×u is changed to (r×s * )×(rinv×u), after adding the pseudo-random number, the randomness of the pseudo-random number r is used to interfere with the behavior of the actual device, thereby improving the resistance to side channel attacks such as template attacks. And the modular multiplier in the modular multiplication mask circuit for resisting side channel attacks applied to the post-quantum cryptographic algorithm is changed, and all results are stored in registers, thereby avoiding the calculation process, and finally significantly improving the modular multiplication efficiency of the modular multiplier, thereby improving the overall efficiency of the system. Finally, the modular multiplication mask circuit for resisting side channel attacks applied to the post-quantum cryptographic algorithm is not only resistant to side channel attacks, but also highly efficient.

[0047] What is disclosed above is only a preferred embodiment of the present invention, and it certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope of the invention.

Claims

1. A modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms, characterized in that: include: Random number generation unit, modular multiplication unit and control logic unit; The random number generation module is used to generate pseudo-random numbers; The modular multiplication unit is used to perform modular multiplication operation on the first input data and the pseudo-random number to obtain the first preliminary processed data, and perform modular multiplication operation on the second input data and the inverse element of the pseudo-random number to obtain the second preliminary processed data; and then perform modular multiplication operation on the first preliminary processed data and the second preliminary processed data to obtain the final output data; The control logic unit is used to control the operation of the random number generation unit and the modular multiplication unit; Among them, the output end of the random number generation module is connected to the output end of the analog multiplication unit; the output end of the control logic unit is connected to the analog multiplication unit and the input end of the random number generation module; the input end of the analog multiplication unit is also connected to the first input data and the second input data.

2. The modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms according to claim 1, characterized in that: The modular multiplication unit includes a first modular multiplier, a second modular multiplier, a third modular multiplier and a first register; Among them, the first modular multiplier is used to perform modular multiplication operation on the first input data and the pseudo-random number; the second modular multiplier is used to perform modular multiplication operation on the second input data and the inverse element of the pseudo-random number; the third modular multiplier is used to perform modular multiplication operation on the first pre-processed data and the second pre-processed data; the first register is used to output the inverse element of the pseudo-random number according to the input pseudo-random number.

3. The modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms according to claim 2, characterized in that: The first modular multiplier input end is connected to the pseudo-random number and the first input data respectively; the first register input end is connected to the random number generation unit output end and the control logic unit output end; the first register output end is connected to the second modular multiplier input end; the third modular multiplier input end is connected to the first modular multiplier output end and the second modular multiplier output end; the third modular multiplier is used to output the final output data.

4. The modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms according to claim 2, characterized in that: The modular multiplication unit also includes a second register; the second register is connected to the first register and is used to transmit the inverse element of the pseudo-random number to the second modular multiplier.

5. The modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms according to claim 2, characterized in that: The first modular multiplier includes a first multiplier, a first adder, a second adder, a third adder, a third register, a fourth register, a fifth register, a sixth register, a seventh register, a first subtractor, a first selector, a second selector and a first modular adder; The first multiplier input end is connected to the pseudo-random number and the first input data, and the output end is connected to the third register input end; the third register output end is respectively connected to the fourth register, the fifth register, the sixth register, and the second adder input end; the fourth register and the fifth register output ends are connected to the first adder input end; the sixth register output end is connected to the second adder input end; the first adder and the second adder output ends are connected to the third adder input end; the third adder output end is connected to the seventh register input end; the seventh register output end is respectively connected to the first selector selection end, the second selector input end, and the first subtractor minuend end; the first selector output end and the second selector output end are connected to the first modulo adder input end; The subtrahend terminal of the first subtractor is connected to the first reference number, the output terminal is connected to the input terminal of the second selector, and the borrow terminal is connected to the selection terminal of the second selector; the output terminal of the first analog adder outputs the first preliminary processed data.

6. The modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms according to claim 5, characterized in that: The fourth register stores all 4 bits*2 20 Modulo q = 3329 result; the fifth register stores all 4 bits * 2 16 Modulo q = 3329 result; the sixth register stores all 4 bits * 2 12 The result of modulo q=3329; the first selector input is all 2bits*2 12 Modulo the result of q=3329; the first reference number is the number 3329.

7. The modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms according to claim 5, characterized in that: The third register is used to store the 24 bits of data output by the first multiplier, and transmit the 1st to 12th bits of the 24 bits of data to the second adder, the 13th to 16th bits of the 24 bits of data to the sixth register, the 17th to 20th bits of the 24 bits of data to the fifth register, and the 21st to 24th bits of the 24 bits of data to the fourth register.

8. The modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms according to claim 5, characterized in that: The seventh register is used to store the 14 bits of data output by the third adder, and transmit the 1st to 12th bits of the 14 bits of data to the second selector input terminal and the minuend terminal of the first subtractor, and transmit the 13th to 14th bits of the 14 bits of data to the selection terminal of the first selector; the first modular multiplier, the second modular multiplier, and the third modular multiplier have the same structure.

9. The modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms according to claim 1, characterized in that: The random number generation unit includes an eighth register, a ninth register, a first Keccak core and a second Keccak core; Among them, the eighth register input end is connected to external data and a control logic unit, and the output end is connected to the ninth register input end; the ninth register output end is connected to the first Keccak core input end; the second Keccak core input end is connected to the first Keccak core output end, and the output ends are respectively connected to the ninth register input end and the modular multiplication unit input end; the ninth register input end is also connected to the control logic unit.

10. The modular multiplication mask circuit for resisting side channel attacks applied to post-quantum cryptographic algorithms according to claim 9, characterized in that: The eighth register is used to roll the externally input 64 bits of data 25 times according to the control logic unit instruction to generate 1600 bits of data; The ninth register is used to input the 1600 bits of data into the first Keccak core and the second Keccak core for circulation according to the control logic unit instruction; The first Keccak core and the second Keccak core are used to generate a 1600-bit pseudo-random number based on the 1600-bit data, and transmit the 1589th to 1600th pseudo-random numbers to the modular multiplication unit.

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