Quarter-rate 8-phase sampling and decision feedback equalizer circuit and method

Abstract

The present invention discloses a quarter-rate 8-phase sampling and decision feedback equalizer circuit and method, relating to the field of circuit design and digital information transmission technology. Four groups of data signals and four groups of edge signals are sampled using eight quarter-rate clock phases. Only two adder circuits, switched by a multiplexer (MUX) switch, are required to implement a multi-tap time-interleaved decision feedback equalizer circuit. Furthermore, the outputs of the two time-interleaved samplers are directly fed back to the adder inputs, eliminating the need for a MUX switch in the first-stage tap feedback path. This effectively shortens feedback delay and increases the operating rate of the decision feedback equalizer. By using a quarter-rate low-speed clock, the area and power consumption of the receiver circuit can be effectively reduced, the delay time of the feedback path can be reduced, and a higher transmission rate can be achieved under limited power consumption conditions.

Description

Technical Field

[0001] The present invention relates to the field of circuit design and digital information transmission technology, and in particular to a quarter-rate 8-phase sampling and decision feedback equalizer circuit and method. Background Art

[0002] With the advancement of information technology, signal transmission rates continue to increase. However, the limited channel bandwidth can lead to significant loss of high-frequency signals, causing severe intersymbol interference (ISI), which affects signal quality at the receiving end and poses a challenge to large-bandwidth data transmission. In channels where frequency-dependent signal attenuation occurs, serializer / deserializer (SerDes) links are typically used to transmit data. One method to compensate for signal distortion caused by limited bandwidth is to add equalization to the SerDes link. Different equalization techniques can be used to compensate for this ISI in both the transmitter and receiver. Common equalization techniques used in high-speed SerDes links can be divided into linear equalizers and decision feedback equalizers (DFE).

[0003] Linear equalizers utilize the frequency characteristics of variable-gain amplifiers to compensate for channel loss. However, for high-speed signals, signal jitter can exceed one symbol interval (UI), making linear equalizers in isolation unsuitable. Furthermore, linear equalizers amplify both noise and signal, which does not improve the bit error rate (BER) performance of communication systems. Therefore, a DFE (Directional Feedback Element) (DFE) equalizer circuit is required to eliminate residual ISI in conjunction with the linear equalizer. As a nonlinear equalizer, DFE can compensate for ISI and flatten the channel response without amplifying noise or crosstalk, effectively improving the signal-to-noise ratio.

[0004] Existing DFE circuit structures typically use full-rate, half-rate, or quarter-rate clock signals to drive a sampler to sample the input signal, and then use latches and multiplexers (MUXes) to implement delay and multi-stage feedback equalization compensation for the sampled signal.

[0005] In the prior art, when the latch transmission rate is extremely high, the clock generation circuit and driver circuit consume very high power. The DFE circuit structure causes the number of adder circuits and sampler circuits to double, resulting in an increase in chip area and power consumption. While reducing the clock rate can reduce the power consumption of the clock generation circuit and driver circuit, it also doubles the number of samplers compared to the half-rate structure, resulting in an increase in chip area and power consumption. When the sampling results of the four-phase clocks are directly fed back to the adders at the input ends of adjacent branches through time interleaving for equalization compensation, there is a problem of a large number of adders and increased power consumption.

[0006] Due to the shortcomings of existing SerDes receiver sampling and DFE technical solutions, it is necessary to design a technical solution with a smaller circuit area, lower power consumption, and higher transmission rate under limited power consumption conditions. This technical solution must also be able to simultaneously output data intermediate sampling signals and edge sampling signals to be suitable for the clock and data recovery (CDR) loop of the SerDes receiver system. Summary of the Invention

[0007] The technical problem to be solved by the present invention is that under limited power consumption conditions, the power consumption of the sampling and decision feedback equalizer circuit in a SerDes receiver is inversely proportional to the transmission rate, resulting in poor coordination capability. The purpose of the present invention is to provide a quarter-rate 8-phase sampling and decision feedback equalizer circuit and method. By sampling signals separately at multiple quarter-rate clock phases, only two adder circuits need to be switched through a MUX switch to implement a multi-tap time-interleaved decision feedback equalizer circuit. At the same time, the connection mode in which the two time-interleaved sampler outputs are directly fed back to the adder input end avoids the use of a MUX switch on the first-stage tap feedback path, effectively shortens the feedback delay time, improves the operating rate of the DFE (Decision Feedback Equalizer), can simultaneously reduce the number of samplers and adders, and effectively reduce the area and power consumption of the SerDes receiver circuit.

[0008] The present invention is achieved through the following technical solutions:

[0009] A first aspect of the present invention provides a quarter rate 8-phase sampling and decision feedback equalizer circuit, comprising:

[0010] MUX switches, multiple adders, and multiple sampling and delay branches;

[0011] Each sampling and delay branch includes: a return-to-zero sampler, an SR latch and a clock-driven latch, the output of the return-to-zero sampler is connected to the SR latch, and the output of the SR latch is connected to the clock-driven latch;

[0012] The outputs of the return-to-zero sampler, SR latch, and clock-driven latch are selected by MUX switches and then interleaved as feedback signals of each order of the decision feedback equalizer and input into different adders to form a multi-tap time-interleaved decision feedback equalizer circuit.

[0013] Furthermore, the sampling clock of the return-to-zero sampler includes at least 8 sampling clock signals, namely 0 degree phase clock CK0, 45 degree phase clock CK45, 90 degree phase clock CK90, 135 degree phase clock CK135, 180 degree phase clock CK180, 225 degree phase clock CK225, 270 degree phase clock CK270, and 315 degree phase clock CK315.

[0014] Furthermore, the output data signal of the return-to-zero sampler is S<0-3>, the data signal S<0-3> outputs the data signal L<0-3> after passing through the SR latch, and the data signal L<0-3> outputs the final data signal D<0-3> after passing through the clock-driven latch.

[0015] Furthermore, the signals outputted by the sampling and delay branches connected to the sampling clocks CK0, CK90, CK180, and CK270 are respectively the data signals D <0> , D <1> , D <2> , D <3> ;

[0016] The final output signals of the sampling and delay branches connected to the sampling clocks CK45, CK135, CK225, and CK315 are edge signals E <0> , E <1> , E <2> , E <3> ;

[0017] Among them, the data signal D <0> , D <1> , D <2> , D <3> The delay time of the corresponding branch is half a clock cycle; the edge signal E <0> , E <1> , E <2> , E <3> The delay time of the corresponding branch is 3 / 8 clock cycle.

[0018] Furthermore, the sampling and delay branches connected to the sampling clock CK0 are connected to the data signal D <0> sampling;

[0019] The sampling clock CK45 corresponds to the sampling and delay branch connected to the edge signal E <0> sampling;

[0020] The sampling clock CK180 corresponds to the sampling and delay branches connected to the data signal D <2> sampling;

[0021] The sampling clock CK225 corresponds to the sampling and delay branches connected to the edge signal E <2> sampling;

[0022] The sampling clock CK90 corresponds to the sampling and delay branches connected to the data signal D <1> sampling;

[0023] The sampling clock CK135 corresponds to the sampling and delay branches connected to the edge signal E <1> sampling;

[0024] The sampling clock CK270 corresponds to the sampling and delay branches connected to the data signal D <3> sampling;

[0025] The sampling clock CK315 corresponds to the sampling and delay branches connected to the edge signal E <3> sampling.

[0026] A second aspect of the present invention provides a decision feedback equalization method, which is applied to a quarter-rate 8-phase sampling and decision feedback equalizer circuit, comprising the following specific steps:

[0027] The output signal of the return-to-zero sampler is fed back to the adder of the complementary branch to form a first-order feedback path;

[0028] The output signal of the SR latch is fed back to the adder of this branch after being selected by the MUX switch, forming a second-order feedback path;

[0029] The output signal of the SR latch is fed back to the adder of the complementary branch after being selected by the MUX switch, forming a third-order feedback path;

[0030] The output signal of the clock-driven latch is fed back to the adder of this branch after being selected by the MUX switch, forming a 4th-order feedback path;

[0031] The sampling and delay branch includes an even branch and an odd branch. The even branch is connected to the adder SUM1, and the odd branch is connected to the adder SUM2. The even branch and the odd branch are complementary to each other.

[0032] Furthermore, the signal feedback process of the first-order feedback path specifically includes:

[0033] The output signal S of the return-to-zero sampler of the even branch <0> and S <2> At the same time, it is directly fed back to the adder SUM2 of the odd-numbered branches to form the feedback path of the first-order tap DFE, and the feedback coefficient is H1;

[0034] The output signal S of the return-to-zero sampler of the odd branch <1> and S <3> At the same time, it is directly fed back to the adder SUM1 of the even-numbered branches to form a complementary first-order tap DFE feedback path with a feedback coefficient of H1;

[0035] Among them, the even-numbered branch output signal S <0> and S <2> The return-to-zero sampler driving clocks are CK0 and CK180 respectively, and the odd-numbered branch output signal S <1> and S <3> The return-to-zero sampler driving clocks are CK90 and CK270 respectively.

[0036] Furthermore, the signal feedback process of the second-order feedback path specifically includes:

[0037] The output signal L of the SR latch of the even branch <0> and L <2> The MUX switch driven by the CK270 clock signal is selected and then fed back to the SUM1 adder, with a feedback coefficient of H2;

[0038] The output signal L of the SR latch of the odd branch <1> and L <3> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, with a feedback coefficient of H2.

[0039] Furthermore, the signal feedback process of the third-order feedback path specifically includes:

[0040] The output signal L of the SR latch of the even branch <0> and L <2> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, with a feedback coefficient of H3;

[0041] The output signal L of the SR latch of the odd branch <1> and L <3> The MUX switch driven by the CK270 clock signal is selected and then fed back to the SUM1 adder, with a feedback coefficient of H3.

[0042] Furthermore, the signal feedback process of the 4th-order feedback path specifically includes:

[0043] The output signal D of the latch of the even branch <0> and D <2> The MUX switch driven by the CK270 clock signal is selected and then fed back to the SUM1 adder, with a feedback coefficient of H4;

[0044] The output signal D of the latch of the odd branch <1> and D <3> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, with a feedback coefficient of H4.

[0045] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0046] By sampling signals separately at multiple clock phases of a quarter rate, only two adder circuits need to be switched through a MUX switch to implement a multi-tap time-interleaved decision feedback equalizer circuit. At the same time, the outputs of the two time-interleaved samplers are directly fed back to the adder input, avoiding the use of a MUX switch on the first-stage tap feedback path, effectively shortening the feedback delay time and improving the operating rate of the DFE (Decision Feedback Equalizer). It can also reduce the number of samplers and adders, effectively reducing the area and power consumption of the SerDes receiver circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for use in the examples. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be considered as limiting the scope. A person of ordinary skill in the art can also derive other relevant drawings based on these drawings without inventive effort. In the drawings:

[0048] Figure 1 FIG1 is a structural diagram of an existing full-rate DFE in an embodiment of the present invention;

[0049] Figure 2 FIG1 is a structural diagram of an existing half-rate sampling DFE based on inference results in an embodiment of the present invention;

[0050] Figure 3 FIG1 is a structural diagram of a conventional quarter-rate sampling DFE based on inference results in an embodiment of the present invention;

[0051] Figure 4 A diagram of a conventional quarter-rate sampling time-interleaved feedback DFE structure in an embodiment of the present invention;

[0052] Figure 5 This is a circuit structure of a quarter rate 8-phase sampling and decision feedback equalizer in an embodiment of the present invention;

[0053] Figure 6 8-phase sampling and decision feedback equalizer circuit timing waveform diagram in an embodiment of the present invention;

[0054] Figure 7 A SUM adder circuit that can be used in an embodiment of the present invention;

[0055] Figure 8 is an RZ sampler circuit that can be used in an embodiment of the present invention;

[0056] Figure 9 It is an SR latch circuit that can be used in the embodiment of the present invention. DETAILED DESCRIPTION

[0057] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with examples and drawings. The exemplary embodiments of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0058] like Figure 1Figure 2 shows an existing full-rate DFE architecture. Latches implement multi-stage clock delays, and adders at the input add feedback signals of varying weights to offset ISI before sampling. This architecture's clock frequency is equal to the system's transmission bit rate. At extremely high transmission rates, the clock generation and drive circuits consume significant power, and the maximum operating frequency of the chip's internal transistors limits further increases in transmission rates.

[0059] like Figure 2 As shown in FIG, it is a half-rate sampling DFE circuit structure based on the predictive result (Predictive), as shown in FIG. Figure 2 As shown, by inferring that the result of the previous bit output by the other branch is '1' or '0', two adder circuits (adder) are used to perform operations with weights of +C1 and -C1, respectively. Then, two independent samplers (samplers) are used to sample the two output signals. After sampling, the two output signals are selected by the MUX selector based on the result of the other branch output. This method can reduce the impact of circuit delay, allowing the signal output by a branch sample to have a delay of up to 2 symbol intervals (UI), thereby increasing the maximum operating rate of the receiving circuit. The patent also uses a three-level delay feedback compensation DFE structure with C2 and C3 weights. This DFE circuit structure based on the inference result will double the number of adder circuits and sampler circuits, resulting in an increase in chip area and power consumption.

[0060] like Figure 3 The figure shows a predictive-based quarter-rate sampling DFE circuit structure. This result also uses a predictive-based DFE circuit structure, with the main difference being the use of a quarter-rate four-phase clock for sampling, with adjacent phase clock sampling outputs controlling the MUX selector for a two-or-one selection operation. This structure reduces the power consumption of the clock generation and drive circuits due to the reduced clock rate, but it also doubles the number of samplers compared to the half-rate structure, resulting in increased chip area and power consumption.

[0061] like Figure 4 The figure shows an existing quarter-rate sampling time-interleaved feedback DFE structure. This structure uses time interleaving to directly feed back the sampling results of the four phase clocks to the adders at the input ends of adjacent branches for equalization compensation. Since each branch requires an adder, the number of adders is large and the power consumption increases. This interleaved feedback DFE structure has very high requirements for the delay of the signal feedback path between adjacent branches, such as Figure 4In the figure marked (a), the feedback path runs from the sampler output point A to point B and then to point C. The figure marked (b) shows that the total delay from the sampler output point A to point B and then to point C must be less than one symbol interval (UI). Therefore, the delay of the feedback path determines the maximum operating rate of the DFE circuit, and appropriate technical solutions must be used to minimize this delay.

[0062] To address the aforementioned issues, this example provides a quarter-rate 8-phase sampling and decision feedback equalizer circuit to address the aforementioned technical challenges. This implementation samples four data signals (D<0-3>) and four edge signals (E<0-3>) using eight quarter-rate clock phases. Only two adder circuits, switched via a multiplexer (MUX) switch, are required to implement a multi-tap time-interleaved decision feedback equalizer circuit. Furthermore, the outputs of the two time-interleaved samplers are directly fed back to the adder inputs, eliminating the need for a MUX switch in the first-stage tap feedback path. This effectively shortens feedback delay and increases the DFE operating rate. By utilizing a quarter-rate low-speed clock and reducing the number of samplers and adders, the technical solution provided by this implementation can effectively reduce the area and power consumption of the SerDes receiver circuit.

[0063] Specifically, such as Figure 5As shown, the receiving circuit sends the signal from the linear equalizer (CTLE) output to two adders SUM1 and SUM2 at the same time. The output of each adder is connected to 4 return-to-zero type samplers (RZ Sampler). Each sampler uses a clock signal with a different phase to sample the input data. The frequency of the sampling clock is one-fourth of the SerDes data transmission rate. The 8 sampling clock signals are 0-degree phase clock CK0, 45-degree phase clock CK45, 90-degree phase clock CK90, 135-degree phase clock CK135, 180-degree phase clock CK180, 225-degree phase clock CK225, 270-degree phase clock CK270, and 315-degree phase clock CK315. The 8 sampling clock signals include 4 even branches and 4 odd branches. Among them, the even branches use CK0, CK180, CK45, and CK225 clocks to sample the D <0> 、D <2> The corresponding data signal sampling, E <0> 、E <2> The corresponding edge signal sampling; odd branches use CK90, CK270, CK135, CK315 clocks to sample D <1> 、D <3> The corresponding data signal sampling, E <1> 、E <3> The corresponding edge signal is sampled. The output data signal of the RZ sampler is S<0-3>, which is output after passing through the SR latch and the data signal L<0-3>. Finally, after passing through the ordinary latch (Latch), the final data signal D<0-3> is output. The SR latch and ordinary latch (Latch) realize the latching and delay control of the signal. The 4-tap decision feedback equalizer (DFE) circuit feeds back the S<0-3>, L<0-3>, and D<0-3> signals to the input SUM1 and SUM2 adders through the MUX switch for equalization compensation. The 1st-order feedback path feeds back the S<0-3> signal directly to the adder of the complementary branch with a feedback coefficient of H1. The 2nd-order feedback path feeds back the L<0-3> signal to the adder of the current branch after selection by the MUX switch with a feedback coefficient of H2. The 3rd-order feedback path feeds back the L<0-3> signal to the adder of the complementary branch after selection by the MUX switch with a feedback coefficient of H3. The 4th-order feedback path feeds back the D<0-3> signal to the adder of the current branch after selection by the MUX switch with a feedback coefficient of H4.

[0064] In some possible implementations, the SUM1 adder is connected to the even branch (even), and its output is connected to four samplers, with sampling clocks CK0, CK45, CK180 and CK225 respectively; the SUM2 adder is connected to the odd branch (odd), and its output is connected to four samplers, with sampling clocks CK90, CK135, CK270 and CK315 respectively.

[0065] In some possible implementations, the output of each sampler is connected to an SR latch (set-reset latch, SR Latch), and the output of the SR latch is connected to a clock-driven latch (Latch). These three stages of circuits connected in series form a sampling and delay branch, where the output of each stage of the circuit is selected by a MUX switch and then used as the feedback signal of each order of the decision feedback equalizer (DFE). The final output signal of the sampling and delay branch connected to the sampling clocks CK0, CK90, CK180, and CK270 is the data signal D <0> , D <1> , D <2> , D <3> The final output signal of the sampling and delay branches connected to the sampling clocks CK45, CK135, CK225, and CK315 is the edge signal E <0> , E <1> , E <2> , E <3> The data signals D<0-3> and edge signals E<0-3> are multiplexed through latches and multiplexers (DMUX) and then used for subsequent data processing in the SerDes receiver, including data serial-to-parallel conversion and clock data recovery (CDR).

[0066] In some possible implementations, due to the different phase differences between the sampler clock and the final latch clock, the sampling and delay branches corresponding to the data signal D<0-3> and the edge signal E<0-3> have different delay times: the data signal branch has a delay of half a clock cycle, while the edge signal branch has a delay of 3 / 8 of a clock cycle. Selecting the phase difference between the different clocks in the sampling and delay branches is critical. Incorrect clock selection can reduce the maximum operating rate of the SerDes and cause errors in the decision feedback equalizer (DFE).

[0067] In some possible implementations, Figure 5 The circuit structure shown shows a 4-tap DFE structure, where the tap coefficients of each order are H1, H2, H3, and H4. Depending on the embodiment, the DFE structure can be expanded to any tap coefficient by adding multiple stages of serial latches. Similar expanded structures are within the scope of protection of this embodiment.

[0068] The provided DFE structure is implemented through a time-interleaved feedback control structure between the even branch and the odd branch. The even branch and the odd branch are complementary to each other, and a MUX switch is used to switch and select delayed data signals with different sampling clocks to be fed back to the adder at the input end.

[0069] In some possible implementations, the feedback equalization process of the quarter-rate 8-phase sampling and decision feedback equalizer circuit includes:

[0070] The output signal S of the reset-to-zero sampler (RZ sampler) of the even branch <0> and S <2> At the same time, it is directly fed back to the adder SUM2 of the odd branch to form the feedback path of the first-order tap DFE, and the feedback coefficient is H1; similarly, the sampler output signal S of the odd branch <1> and S <3> At the same time, it is directly fed back to the adder SUM1 of the even branch to form a complementary first-order tap DFE feedback path. The return-to-zero type sampler (RZ Sampler) outputs a valid sampling result when the driving clock signal is high, and resets the output sampling result to zero when the driving clock signal is low. In the quarter-rate 8-phase sampling technical solution provided in this embodiment, the driving clocks of the data signal samplers (RZ Samplers) of the same even branch or odd branch are in opposite phases. For example, the output signal S of the even branch is <0> and S <2> The sampler driving clocks are CK0 and CK180 respectively, the clock phases are just opposite, and the odd-numbered branches output signal S <1> and S <3> The sampler driving clocks are CK90 and CK270 respectively, and the clock phases are also inverted. Therefore, the signals output by the data samplers in the same branch are not valid at the same time. When the output signal of one sampler is valid, the output signal of the other sampler is in a reset-to-zero state. Based on this phase-inverted characteristic of the data signal samplers (RZ Samplers), the technical solution provided in this embodiment simultaneously feeds back the outputs of the two data signal samplers (RZ Samplers) to the adder of the complementary branch for first-order tap DFE compensation, so that the first-order DFE feedback path no longer requires a latch or a MUX selector. The sampler output is directly connected to the adder, effectively shortening the delay time of the feedback path and improving the maximum operating rate of the DFE circuit.

[0071] The second-order feedback path of the DFE does not adopt the interleaved feedback structure between the even branch and the odd branch. Instead, the output signal of the SR latch (SR Latch) corresponding to the branch is selected by the MUX switch and fed back to the input adder of the branch. Specifically, the output signal L of the SR latch of the even branch is <0> 、L <2> The MUX switch driven by the CK270 clock signal is selected and fed back to the SUM1 adder, and the feedback coefficient is H2; the output signal L of the SR latch of the odd branch <1> 、L <3> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, with a feedback coefficient of H2.

[0072] The third-order feedback path of the DFE adopts an interwoven feedback structure between the even branch and the odd branch. The output signal of the SR latch (SR Latch) corresponding to the branch is selected by the MUX switch and fed back to the input adder of the complementary branch. Specifically, the output signal L of the SR latch of the even branch is <0> 、L <2> The MUX switch driven by the CK180 clock signal is selected and fed back to the SUM2 adder, and the feedback coefficient is H3; the output signal L of the SR latch of the odd branch <1> 、L <3> The MUX switch driven by the CK270 clock signal is selected and then fed back to the SUM1 adder, with a feedback coefficient of H3.

[0073] The fourth-order feedback path of the DFE does not use the interleaved feedback structure between the even and odd branches. Instead, it selects the latch output signal corresponding to the branch through the MUX switch and feeds it back to the input adder of the branch. Specifically, the output signal D of the latch of the even branch is <0> 、D <2> The MUX switch driven by the CK270 clock signal is selected and fed back to the SUM1 adder, with a feedback coefficient of H4; the output signal D of the latch of the odd branch <1> 、D <3> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, with a feedback coefficient of H4.

[0074] The DFE circuit structure provided in this embodiment is not limited to a DFE structure with a 4-tap coefficient. The number of taps can be reduced, and the structure can be expanded to a DFE structure with a 5-tap coefficient, a 6-tap coefficient, or any other tap coefficient by adding multiple stages of serial latches. Similar expanded structures are within the scope of protection of this embodiment.

[0075] In some possible implementations, the present embodiment provides Figure 5 The common latch used in the circuit structure diagram can be any type of latch structure, such as a D flip-flop, a CML logic latch, and the like.

[0076] Figure 6 A timing waveform diagram of the 8-phase sampling and decision feedback equalizer circuit provided by this embodiment is given, and the figure shows the data sampling D during the second cycle of the even branch. <4> and edge sampling E <4> The DFE timing and adder input signal waveform at the moment. The figure marks the process in which all 4-order feedback signals are equalized and compensated by the SUM1 adder during the high-level pulse stage of CK270. The input data D <3> ,correspond Figure 5 The sampler output of CK270 is S <3> The signal is fed back directly to the SUM1 adder through the first-order DFE feedback channel using the H1 feedback coefficient, and the input data D <2> ,correspond Figure 5The L of the SR latch output <2> The signal is connected to the SUM1 adder by the second-order DFE feedback channel using the H2 feedback coefficient after passing through the MUX selector driven by CK270. The input data D <1> ,correspond Figure 5 The L of the SR latch output <1> The signal is connected to the SUM1 adder through the third-order DFE feedback channel using the H3 feedback coefficient after passing through the MUX selector driven by CK270. The input data D <0> ,correspond Figure 5 D of the latch output <0> The signal passes through the MUX selector driven by CK270 and is connected to the SUM1 adder by the fourth-order DFE feedback channel using the H4 feedback coefficient. All DFE feedback signals of each order are added and compensated in the SUM1 adder with the signal input from the linear equalizer (CTLE) during the high-level pulse duration of the CK270 clock. Then, the sampler (RZ Sampler) driven by CK0 samples the data at the rising edge of the clock to obtain S <4> The data signal is then delayed by the SR latch and the latch to obtain the final data signal D. <4> Output; The sampler (RZ Sampler) driven by CK45 performs edge sampling at the rising edge of the clock to obtain the output edge signal, and then obtains the final edge signal E after the delay of the SR latch and the latch (Latch). <4> Output.

[0077] The sampling and DFE feedback timing waveforms on all clock phases are the same as Figure 6 Similarly, the eight clock phases and the even branches and the odd branches are cyclically fed back in sequence to form a time-continuous DFE equalization compensation structure, thereby achieving the effect described in this embodiment.

[0078] Figure 7 A schematic diagram of a SUM adder circuit that can be used in the technical solution of this embodiment is provided. The adder adopts a fully differential circuit structure and includes a 4th-order tap feedback coefficient branch. Figure 7 The differential pair composed of the M0 transistors is the main amplifying branch of the adder, which amplifies the input differential signals Inp and Inn. The output load resistance is R, and the amplification factor of the adder is controlled by the current size of the tail current source H0; the two groups of differential pairs composed of the M1 transistors are the first-order feedback branches, and the first-order feedback coefficient is controlled by the tail current source H1. The input signals Tap0p, Tap0n and Tap1p, Tap1n of the two groups of differential pairs are connected to Figure 5 The S in the DFE structure shown <0> 、S <2> or S <1> 、S <3> It should be noted that S<0-3> must also be in differential signal form to accommodate Figure 7In the differential circuit structure shown, since the sampling clocks of the two groups of signals in the first-order feedback path are in anti-phase, the two groups of differential signals Tap0p, Tap0n and Tap1p, Tap1n will not be valid at the same time. When one group of signals is valid, the other group of signals is in the reset state, that is, the positive and negative ends of the other group of differential signals are all 0; the differential pair composed of the M2 transistor is a second-order feedback branch, and the second-order feedback coefficient is controlled by the tail current source H2. The differential input signals Tap2p and Tap2n are connected Figure 5 The L<0-3> in the DFE structure shown is the second-order feedback path signal output after being selected by the MUX switch; the differential pair composed of the M3 transistor is the third-order feedback branch, and the third-order feedback coefficient is controlled by the tail current source H3. The differential input signals Tap3p and Tap3n are connected Figure 5 The L<0-3> in the DFE structure shown is the output of the 3rd order feedback path signal after being selected by the MUX switch; the differential pair composed of the M4 transistor is the 4th order feedback branch, and the 4th order feedback coefficient is controlled by the tail current source H4. The differential input signals Tap4p and Tap4n are connected Figure 5 The DFE structure shown in the figure shows the output of the 4th order feedback path signal after D<0-3> is selected by the MUX switch. It is particularly important to note that the decision feedback equalizer circuit (DFE) is a negative feedback control circuit, so the feedback signals of the tap coefficients of each order need to form a negative feedback compensation effect when connected. Figure 7 The connection relationship between the differential pair transistor output terminals of each order feedback branch and the output signals Outp and Outn is exactly opposite to the connection mode of the differential pair transistors of the main amplifier circuit.

[0079] Figure 8 A circuit schematic diagram of a return-to-zero sampler (RZ Sampler) that can be used in the technical solution of this embodiment is provided. The circuit is a dynamic comparator circuit driven by the CK clock signal. The input signals Inp and Inn are compared at the rising edge of the CK clock, and the output comparison result is maintained during the duration of the CK signal being at a high level. The comparison result signal of the sampler is generated by Figure 8 The inverter drives the output; when the CK signal becomes low, the RZ sampler resets the comparison result. Figure 8 The middle transistors M3 and M4 are turned on when the CK signal is at a low level, pulling up the output differential signals A and An to the power supply voltage VDD, and resetting the output differential signals Outp and Outn to a low level '0' after being driven by the inverter.

[0080] Figure 9A circuit diagram of an SR latch (SR Latch) that can be used in the technical solution of this embodiment is provided. The SR latch consists of two cross-coupled NOR gates. The R and S terminals are signal input ports, and the Q and Qn terminals are signal output ports. When the R and S signals are '0' or '1' respectively, the SR latch will latch the input signal to the output Q and Qn terminals. When the R and S signals are both '0', the SR latch will maintain the previous output result unchanged. Figure 9 The SR latch provided in the Figure 8 The return-to-zero type sampler (RZ Sampler) provided in the cascade is connected. When the CK signal is high, the return-to-zero type sampler outputs the comparison result, and the SR latch latches the result to the Q and Qn outputs. When the CK signal is low, the output result of the return-to-zero type sampler is reset, and all the differential output ends become '0' signals. At this time, the SR latch will keep the previous output result unchanged.

[0081] In order to better understand this embodiment, the following is given Figures 1-9 Specific instructions:

[0082] Figure 1 In the figure, Ain represents the input signal; Dout represents the output signal; F represents the filter in the feedback path; L represents the filter in the feedforward path; C1, C2, C3,…, Cn represent delay elements, which usually represent registers or storage units used to store the signal value at the previous moment; CK represents the clock signal, which is used to synchronize the operations of various parts of the system.

[0083] Figure 2 In the figure, From CTLE indicates that the input signal comes from a continuous time linear equalizer; +c1 and -c1 indicate that adders and subtractors with coefficients +c1 and -c1 are used in the circuit to adjust the gain or phase of the signal; MUX indicates a multiplexer, which is used to select the path of the input signal; DFF indicates a D-type flip-flop, which is a digital storage element that can store one bit of data under the control of a clock signal (CK); CK and CK′ indicate the clock signal and its inverted signal; c2 and c3 indicate circuit coefficients; and OUT indicates the output signal of the circuit.

[0084] Figure 3In the circuit diagram, INPUT DATA SIGNAL: Input data signal, representing the original data signal entering the circuit; 1ST INPUT SIGNAL, 2ND INPUT SIGNAL: The first input signal and the second input signal, representing different input data streams or signal channels; CLK1, CLK2, CLK3, CLK4: These usually represent clock signals, used to synchronize operations in the circuit. The numbers may represent different clock sources or phases of the clock signal; LATCH: Latch, used to store data until the next clock signal arrives; FTFS: Circuit module abbreviation; 1ST, 2ND, 3RD, 4TH: represent first, second, third and fourth, used to distinguish different outputs or processing stages; OUTPUT: Output signal, representing the processed data signal;

[0085] Figure 4 In the part marked as (a):

[0086] IN: represents input signal; β1: represents gain, which is used to adjust the strength of the input signal; FF: represents flip-flop, which is a storage unit that can store one bit of binary information; Φ 1 / 4,j : Indicates the phase or clock signal, which is used to synchronize the operation of the trigger; OUT0, OUT1, OUT2, OUT3: Indicates the output signal of the trigger;

[0087] Part marked (b):

[0088] T bit : represents the time period of a bit, that is, the duration of each bit signal; D0, D1, D2, D3: represent data input signals, which may be the input data of the trigger; A, B, C: represent output signals, which may correspond to the output of the trigger.

[0089] Figure 5In the diagram, VCC / VDD represent the power supply voltage, VCC refers to the positive power supply, and VDD refers to the power supply voltage. GND represents ground, a reference voltage point in the circuit. R represents a resistor. C represents a capacitor. Q represents a transistor, and in some cases, it may also represent a flip-flop. RZ Sampler represents a data signal sampler. IN represents an input signal. OUT represents an output signal. CLK represents a clock signal, used to synchronize circuit operations. EN typically represents an enable signal, used to control the activation state of a circuit. RST represents a reset signal, used to restore a circuit to its initial state. I / O represents input / output, referring to a data input or output port. MUX represents a multiplexer, used to select an output from multiple inputs. DE represents data enable. SR Latch represents an SR latch. Latch represents a latch.

[0090] Figure 6 In the data bus, Data refers to the data bus, which is used to transmit data signals. <0> ,D <1> ,...,D <9> : Indicates different bits on the data bus, usually used to indicate a 10-bit wide data bus. <0> ,E <1> , ...,E <9> : Indicates the signal (Enable), which is used to control the enable status of each bit on the data bus. <1> ,L <2> ,S <3> : Signals used to indicate different operations or states. CK0, CK45, CK90, ..., CK315: represent different clock signals. H0, H1, H2, H3, H4: represent tap feedback coefficients. SUM: represents the output of the adder (Sum), which may be the part of the circuit that performs addition operations.

[0091] Figure 7In the figure, VDD: represents the positive pole of the power supply voltage. GND: represents ground (Ground), the reference voltage point of the circuit. R: represents resistor (Resistor). M0, M1, M2, M3, M4: represent transistors (MOSFET), usually used for amplification or switching. Inp: represents input signal (Input). Outp, Outn: represent output signal (Output), where Outp may be a positive output and Outn is a negative output. Inn: may represent an internal node or signal. Tap0p, Tap0n, Tap1p, Tap1n,..., Tap4n: represent different taps (Tap) or nodes, used to connect different circuit parts to achieve specific filtering or amplification functions. H0, H1, H2, H3, H4: represent tap feedback coefficients.

[0092] Figure 8 In the diagram, VDD: represents the positive pole of the power supply voltage. GND: represents the ground, the reference voltage point of the circuit, that is, the zero potential point. CK: represents the clock signal (Clock), which is used to synchronize circuit operations or control switching elements. Inp: represents the positive end of the input signal (Positive Input). Inn: represents the negative end of the input signal (Negative Input), which together with Inp constitutes a differential input. Outp: represents the positive end of the output signal (Positive Output). Outn: represents the negative end of the output signal (Negative Output), which together with Outp constitutes a differential output. M0, M1, M2, M3, M4, M5: represent MOSFET transistors, which are usually used to build amplifiers, switches or other functional modules in analog circuits. A, An: represent nodes or signal points, which are used to connect different components in the circuit or represent specific voltage points.

[0093] Figure 9 In the figure, R is the abbreviation for Reset, indicating the reset input. When the R input is an active signal, the flip-flop is reset and the output is forced to 0. S is the abbreviation for Set, indicating the set input. When the S input is an active signal, the flip-flop is set and the output is forced to 1. Q is the output state of the flip-flop. When the flip-flop is set, the Q output is 1. Qn is the inverted output of Q (Not Q). When Q is 1, Qn is 0, and vice versa.

[0094] The specific implementation methods described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific implementation method of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A quarter rate 8-phase sampling and decision feedback equalizer circuit, characterized in that: include: MUX switches, multiple adders, and multiple sampling and delay branches; Each sampling and delay branch includes: a return-to-zero sampler, an SR latch and a clock-driven latch, the output of the return-to-zero sampler is connected to the SR latch, and the output of the SR latch is connected to the clock-driven latch; The outputs of the return-to-zero sampler, SR latch, and clock-driven latch are respectively selected by the MUX switch and then interleaved as feedback signals of each order of the decision feedback equalizer and input into different adders to form a multi-tap time-interleaved decision feedback equalizer circuit; The sampling clock of the return-to-zero sampler includes at least 8 sampling clock signals, which are 0-degree phase clock CK0, 45-degree phase clock CK45, 90-degree phase clock CK90, 135-degree phase clock CK135, 180-degree phase clock CK180, 225-degree phase clock CK225, 270-degree phase clock CK270, and 315-degree phase clock CK315; The output data signal of the return-to-zero sampler is S<0-3>, the data signal S<0-3> outputs the data signal L<0-3> after passing through the SR latch, and the data signal L<0-3> outputs the final data signal D<0-3> after passing through the clock-driven latch; The final output signals of the sampling and delay branches connected to the sampling clocks CK0, CK90, CK180, and CK270 are data signals D <0> , D <1> , D <2> , D <3> ; The final output signals of the sampling and delay branches connected to the sampling clocks CK45, CK135, CK225, and CK315 are edge signals E <0> , E <1> , E <2> , E <3> ; The decision feedback equalization method of the circuit specifically includes: The output signal of the return-to-zero sampler is fed back to the adder of the complementary branch to form a first-order feedback path; The output signal of the SR latch is fed back to the adder of this branch after being selected by the MUX switch, forming a second-order feedback path; The output signal of the SR latch is fed back to the adder of the complementary branch after being selected by the MUX switch, forming a third-order feedback path; The output signal of the clock-driven latch is fed back to the adder of this branch after being selected by the MUX switch, forming a 4th-order feedback path; The sampling and delay branch includes an even branch and an odd branch, the even branch is connected to the adder SUM1, the odd branch is connected to the adder SUM2, and the even branch and the odd branch are complementary branches to each other; The signal feedback process of the first-order feedback path specifically includes: The output signal S of the return-to-zero sampler of the even branch <0> and S <2> At the same time, it is directly fed back to the adder SUM2 of the odd-numbered branches to form the feedback path of the first-order tap DFE, and the feedback coefficient is H1; The output signal S of the return-to-zero sampler of the odd branch <1> and S <3> At the same time, it is directly fed back to the adder SUM1 of the even-numbered branches to form a complementary first-order tap DFE feedback path with a feedback coefficient of H1; Among them, the even-numbered branch output signal S <0> and S <2> The return-to-zero sampler driving clocks are CK0 and CK180 respectively, and the odd-numbered branch output signal S <1> and S <3> The return-to-zero sampler driving clocks are CK90 and CK270 respectively; The signal feedback process of the second-order feedback path specifically includes: The output signal L of the SR latch of the even branch <0> and L <2> The MUX switch driven by the CK270 clock signal is selected and then fed back to the SUM1 adder, with a feedback coefficient of H2; The output signal L of the SR latch of the odd branch <1> and L <3> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, with a feedback coefficient of H2; The signal feedback process of the third-order feedback path specifically includes: The output signal L of the SR latch of the even branch <0> and L <2> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, with a feedback coefficient of H3; The output signal L of the SR latch of the odd branch <1> and L <3> The MUX switch driven by the CK270 clock signal is selected and then fed back to the SUM1 adder, with a feedback coefficient of H3; The signal feedback process of the 4th-order feedback path specifically includes: The output signal D of the latch of the even branch <0> and D <2> The MUX switch driven by the CK270 clock signal is selected and then fed back to the SUM1 adder, with a feedback coefficient of H4; The output signal D of the latch of the odd branch <1> and D <3> The MUX switch driven by the CK180 clock signal is selected and then fed back to the SUM2 adder, with a feedback coefficient of H4.

2. The quarter rate 8 phase sampling and decision feedback equalizer circuit according to claim 1, characterized in that The sampling clock CK0 corresponds to the sampling and delay branches connected to the data signal D <0> sampling; The sampling clock CK45 corresponds to the sampling and delay branch connected to the edge signal E <0> sampling; The sampling clock CK180 corresponds to the sampling and delay branches connected to the data signal D <2> sampling; The sampling clock CK225 corresponds to the sampling and delay branch connected to the edge signal E <2> sampling; The sampling clock CK90 corresponds to the sampling and delay branches connected to the data signal D <1> sampling; The sampling clock CK135 corresponds to the sampling and delay branches connected to the edge signal E <1> sampling; The sampling clock CK270 corresponds to the sampling and delay branches connected to the data signal D <3> sampling; The sampling clock CK315 corresponds to the sampling and delay branches connected to the edge signal E <3> sampling.

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