Data packet analyzer and method based on FPGA (Field Programmable Gate Array)

Abstract

The invention provides a data packet analyzer and method based on an FPGA (Field Programmable Gate Array). The analyzer comprises a first-stage configurable packet analysis module and a secondary configurable packet analysis module which are connected in sequence, wherein the first-stage configurable packet analysis module is used for extracting a protocol field at the bottommost layer of a message, and outputting a matching field, a header, a packet header vector and an initial offset to the second-stage configurable packet analysis module; the plurality of secondary configurable packet analysis modules are connected in sequence; and the secondary configurable packet analysis module is used for analyzing the message according to the analysis action configured by the dynamic configuration message. The method has the advantages that processing requirements of different protocols can be met, the bit width of an interface between extraction units is reduced, and resource consumption is reduced; the matching rule and the field set of each stage are allowed to be flexibly adjusted according to requirements; free combination of a plurality of parallel protocol field extraction units is supported, and the analysis performance is greatly improved; different message analysis requirements can be met, and higher customization and adaptability are provided.

Description

Technical Field

[0001] The invention belongs to the field of network data packet processing, and in particular relates to a data packet parser and method based on FPGA. Background Art

[0002] In modern network communications, a large number of data packets need to be processed and forwarded in network devices. Packet parsing is one of the key functions in network devices, which involves identifying and extracting key information in data packets, such as protocol type, source address, destination address, etc., in order to perform corresponding forwarding and processing operations. Traditional packet parsing solutions are often based on fixed hardware logic or software implementation, and their performance and flexibility are limited.

[0003] With the rapid development of network communications and the emergence of new protocols, traditional analysis technology solutions can no longer meet the growing data processing needs. Traditional analysis technology solutions have the following defects:

[0004] 1. Insufficient scalability and flexibility: Traditional packet parsing solutions usually use hard-coded rules to match various fields of a packet. This approach requires writing a large number of rules when processing packets of different protocols and formats, and lacks scalability and flexibility.

[0005] 2. Low parsing efficiency: Traditional data packet parsing solutions usually use a linear scanning method to match rules field by field. This method will cause a large performance overhead when processing large-scale data packets and the parsing efficiency is low.

[0006] 3. Insufficient reliability: Traditional data packet parsing solutions are usually based on text matching methods such as regular expressions. This method is prone to mismatches and missed matches when processing complex data packets, resulting in inaccurate parsing results.

[0007] 4. Poor maintainability: Traditional data packet parsing solutions usually require rules to be embedded in the code. This approach requires code modification and recompilation and deployment when the rules change, which makes maintenance more complicated. Summary of the invention

[0008] The purpose of the present invention is to overcome the defects of the existing data packet parser, such as insufficient scalability and flexibility, and low parsing efficiency.

[0009] In order to achieve the above object, the present invention proposes a data packet parser based on FPGA, the parser comprises a first-level configurable packet parsing module and a secondary configurable packet parsing module connected in sequence; wherein,

[0010] The first-level configurable packet parsing module is used to extract the bottom-level protocol fields of the message and output the matching domain, header, packet header vector and starting offset to the secondary-level configurable packet parsing module;

[0011] A plurality of the secondary configurable packet parsing modules are connected in sequence; the secondary configurable packet parsing modules are used to parse the message according to the parsing action configured by the dynamic configuration message.

[0012] As an improvement of the above-mentioned parser, when the protocol contained in the message is of fixed length, one of the secondary configurable packet parsing modules parses one protocol; when the protocol contained in the message is of variable length, the parsing of the protocol is divided into multiple stages, one of the secondary configurable packet parsing modules parses part of the fields in the protocol, and multiple of the secondary configurable packet parsing modules work in sequence to complete the parsing of the entire protocol.

[0013] As an improvement of the above-mentioned parser, when multiple secondary configurable packet parsing modules parse the protocol in sequence, the most critical field in the protocol is parsed first, and then other fields in the protocol are processed; the most critical field is a part of the set field in the protocol. If the set field is not matched when being processed, there is no need to continue processing other fields of the protocol.

[0014] As an improvement of the above-mentioned parser, the secondary configurable packet parsing module includes a TCAM-RAM unit, a matching domain extraction unit, an offset calculation unit and a message segmentation processing unit; wherein,

[0015] The TCAM-RAM unit is a storage unit that combines TCAM and RAM and is used to match and store rules of the secondary configurable packet parsing module;

[0016] The matching domain extraction unit is used to extract the matching domain of the next layer protocol;

[0017] The offset calculation unit is used to calculate the starting offset of the next layer protocol in the message;

[0018] The message segmentation processing unit is used to segment the message in a prescribed manner, extract different fields of the message, and then merge them into a final parsing result.

[0019] As an improvement of the above-mentioned parser, the first-level configurable packet parsing module includes the matching domain extraction unit, the offset calculation unit and the message segmentation processing unit.

[0020] As an improvement of the above parser, the matching domain extraction unit, the offset calculation unit and the message segmentation processing unit process data in parallel.

[0021] As an improvement of the above parser, the message segmentation processing unit includes a message segmentation subunit, a plurality of field extraction subunits and a field combination subunit, wherein:

[0022] The message segmentation subunit is used to segment the message in a specified manner and output the segmented message to the field extraction subunit;

[0023] The field extraction subunit is used to extract different fields of the message and output the extraction results to the field combination subunit;

[0024] The field combination subunit is used to merge the output results of each of the field extraction subunits to obtain a final parsing result.

[0025] As an improvement of the above-mentioned parser, the message segmentation subunit evenly divides the header into multiple Cell units, and outputs a single Cell unit or a combination of multiple Cell units to the field extraction subunit according to the needs of the field extraction subunit; several of the field extraction subunits process data in parallel.

[0026] As an improvement of the above-mentioned parser, the parser configures the table items in the TCAM-RAM unit through FlowMod messages, and dynamically configures different protocol parsing rules.

[0027] The present invention also provides a data packet parsing method based on FPGA, which is implemented based on the above parser, and the method includes:

[0028] The first-level configurable packet parsing module extracts the lowest-level protocol fields of the message and provides matching domains, headers, packet header vectors and starting offsets for subsequent protocol parsing;

[0029] The plurality of secondary configurable packet parsing modules parse the message in sequence according to the parsing actions configured in the dynamic configuration message.

[0030] Compared with the prior art, the advantages of the present invention are:

[0031] 1. Flexible data packet segmentation: Through protocol field segmentation extraction, data packets can be segmented according to predefined rules, which can not only adapt to the processing requirements of different protocols, but also reduce the interface width between extraction units and reduce resource consumption.

[0032] 2. Dynamic configuration and adaptability: The packet parsing unit can be dynamically configured according to different configuration messages. This flexibility enables the packet parsing unit to adapt to different parsing requirements and protocol changes, improving the adaptability and scalability of the system.

[0033] 3. Efficient phased matching tasks: The hierarchical execution method of matching tasks for multiple protocol fields allows matching tasks to be divided into stages and executed step by step, and matching operations are performed on specific field sets. This phased matching task can improve matching efficiency and allow flexible adjustment of matching rules and field sets for each stage according to needs.

[0034] 4. Parallel parsing capability: supports free combination of multiple parallel protocol field extraction units, greatly improving parsing performance.

[0035] 5. Dynamic protocol field length configuration: The method of determining the protocol field length according to the type of the output message header vector enables the protocol field length to be dynamically configured according to the header vector type. This flexibility can meet different message parsing requirements and provide higher customization and adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The diagram shows the structure of the configurable packet parsing module;

[0037] Figure 2 Shown is the first level configurable packet parsing module structure diagram;

[0038] Figure 3 Shown is a flow chart of a data packet parsing method;

[0039] Figure 4 Shown is a schematic diagram of the data packet parsing method process;

[0040] Figure 5 The figure shows a schematic diagram of dynamically configuring parsing rules. DETAILED DESCRIPTION

[0041] As a configurable hardware platform, FPGA has flexibility and parallel processing capabilities, and can implement customized hardware logic and algorithms. By offloading the packet parsing function to FPGA, its highly parallel characteristics can be fully utilized to improve parsing performance and throughput. At the same time, FPGA is also programmable and can be dynamically configured and updated according to different protocol requirements, thereby supporting the parsing and processing of new protocols, making network equipment more adaptable and scalable.

[0042] The design of FPGA-based packet parser also has the advantages of flexibility and customizability. Due to the programmability of FPGA, customized design and optimization can be performed according to specific application requirements and protocol requirements. Not only can it adapt to different protocol types and message formats, but it can also flexibly adjust the parsing algorithm and logic to provide more efficient and accurate parsing capabilities.

[0043] Therefore, designing an FPGA-based packet parsing method is crucial to achieving high-performance, high-flexibility, and programmable network packet processing. It can meet the ever-changing network communication needs, support the parsing and processing of new protocols, and provide customized parsing capabilities, providing an important technical foundation for the development and innovation of network equipment.

[0044] In view of the problems existing in the current pipeline architecture packet parsing technology, such as poor flexibility of static configuration and large interface bit width between parsing units, the present invention proposes a FPGA-based data packet parser and method. The parser and parsing method make packet parsing flexible, efficient and configurable by adopting key technologies such as dynamic configuration, protocol segmentation and parallel processing, so as to be applied to high-speed network data packet processing scenarios.

[0045] The FPGA-based data packet parser provided by the present invention comprises a first-level configurable packet parsing module and a plurality of configurable packet parsing modules.

[0046] The technical solution of the present invention is described in detail below with reference to the accompanying drawings.

[0047] like Figure 1 As shown, the configurable packet parsing module includes a TCAM-RAM unit (Ternary Content Addressable Memory-Random Access Memory), a matching domain extraction unit, an offset calculation unit, a message segmentation unit, a field extraction unit, a field combination unit and a delay unit.

[0048] Figure 1In the header, Header indicates header; PHV (Packet Header Vector) indicates packet header vector; starting offset indicates starting offset; Delay indicates delay module; key indicates matching domain; Mask indicates mask; Action indicates action information; Pro len indicates protocol length information; Extra info indicates field extraction information; keyfield indicates matching domain information; calculate offset indicates offset calculation unit; Extract from header indicates extracting fields from header; select key from header indicates extracting matching domain from header; Gen key indicates matching domain extraction unit; split indicates message segmentation unit; cell_A, cell_B, cell_C, cell_D indicate field extraction units; Accumulate indicates field combination unit; Offset indicates offset; length indicates length; Con_type indicates container type; Con_index indicates container sequence number;

[0049] The TCAM-RAM unit is a storage unit that combines TCAM and RAM; TCAM is used for high-speed packet matching operations, while RAM is used to store and access data. The TCAM-RAM unit is used to match and store the rules of the packet parsing module.

[0050] The matching domain extraction unit is used to extract the matching domain of the next layer protocol.

[0051] The offset calculation unit is used to calculate the starting offset of the next layer protocol in the message.

[0052] The message segmentation unit is used to segment the message in a specified manner and output the segmented message to the field extraction unit.

[0053] The field extraction unit is used to extract different fields in the message header and output the extraction results to the field combination unit. The field extraction unit includes a narrow bit width cross bar, and the field extraction work is completed by the narrow bit width cross bar.

[0054] The field combination unit is used to merge the output results of each field extraction unit to obtain the final parsing result.

[0055] The delay unit is used to delay the input header, packet header vector and starting offset to ensure that the output result after searching the matching domain signal is aligned and input to the subsequent module.

[0056] like Figure 2As shown, the first-level configurable packet parsing module is similar to the configurable packet parsing module, except that since the input has no matching domain, starting offset and packet header vector, the first-level configurable packet parsing module has no TCAM match and has one less TCAM-RAM module in structure.

[0057] like Figure 3 , Figure 4 As shown, a method for parsing a data packet using an FPGA-based data packet parser is used to extract the required fields from a high-speed network data packet for subsequent search and forwarding operations, including configuring the parsing action through a dynamic configuration message. The configuration message may contain information such as protocol field extraction rules, protocol type location, and protocol length. The dynamic configuration message will be parsed and written into the corresponding table entry in the TCAM-RAM unit to update the parsing logic. After caching the original message header, the input data stream extracts the Ethernet layer protocol type in the header through the first-level configurable packet parsing module. Then, the configurable packet parsing unit parses the remaining protocols of the data packet layer by layer. Finally, these key fields are combined into a packet header vector output.

[0058] Figure 4 In the figure, Extract_header represents the message cache module; header represents the header; Eth_parser represents the first-level configurable packet parsing module; PHV (Packet Header Vector) represents the packet header vector; startingoffset represents the starting offset; Key represents the matching domain; TCAM-RAM: (Ternary Content Addressable Memory-Random Access Memory) represents content address addressable memory-random access memory; Insert / Delete flowrule represents insert / delete FlowMod message; Action_data represents action information; Action unit represents action unit; Parser_unit represents the configurable packet parsing module.

[0059] The method for parsing a data packet using a data packet parser based on FPGA specifically includes:

[0060] First, cache the input data stream and extract the required header length. Next, the first-level configurable packet parsing module extracts the protocol fields at the bottom layer of the message to provide basic information for subsequent parsing. The basic information includes the protocol fields and the starting offset of the subsequent configurable packet parsing module. Then, the configurable packet parsing module cooperates with multiple parallel processing units through the TCAM-RAM unit to independently and parallelly process various parts of the message, and perform corresponding actions based on the matching results, such as extracting the protocol type and key fields. Multiple parallel processing units specifically refer to three parts of parallel processing. The first part is the offset calculation unit, the second part consists of a message segmentation unit, a field extraction unit and a field combination unit, and the third part is a matching domain extraction unit.

[0061] In the second part of the parallel processing unit, the message segmentation unit segments the input message according to the protocol header information, so that each field extraction unit only processes part of the message to achieve parallel processing. The field extraction units remain independent and do not involve data interaction. After all field extraction units complete the parsing, the field combination unit merges the results of each field extraction unit to obtain the final parsing result.

[0062] like Figure 5 As shown, the data packet parser of the present invention has the characteristic of dynamic configuration. By sending a FlowMod (a message used to dynamically configure the table entries of the TCAM-RAM unit) message to the table entries of the TCAM-RAM unit, the configuration of the table entries in the TCAM-RAM unit is realized, so that the data packet parser can flexibly adapt to different protocols and business requirements.

[0063] Figure 5 In the figure, Packet represents a message; Extract_header represents a message buffer module; header represents a message header; Configuration represents dynamic configuration information, that is, a FlowMod message is sent to the TCAM-RAM in each configurable packet parsing module.

[0064] Take the packet parsing process of Ethernet protocol as an example to explain in detail:

[0065] The parsing method includes a message cache stage and several configurable packet parsing stages. First, the message cache module is used to extract the required header length from the cache. Then the first-level configurable packet parsing module is used to parse the Ethernet layer protocol type. The subsequent configurable packet parsing modules at each level first perform TCAM-RAM matching (the field value to be matched is stored in the table entry of the TCAM-RAM, and the matching domain is compared with the field value in the TCAM in parallel. If a match is found in the TCAM match, the corresponding information stored in the RAM will be output according to the result of the match). If the match is hit, parallel processing operations such as the protocol field extraction unit, the matching domain extraction unit and the offset calculation unit are executed. The message segmentation unit segments the message and assigns it to the corresponding field extraction unit for processing to extract the protocol field. The matching domain extraction unit extracts the next layer of protocol matching domain, and the offset calculation module calculates the corresponding offset. If a match miss occurs (a match miss means that no match is found during TCAM-RAM matching in the current configurable packet parsing stage. This does not mean that there is a problem with the data packet itself, but that the matching rule in the current stage is not applicable to the data packet. Data packets in the network can contain multiple protocol layers, each of which has its own header information and fields that need to be parsed. Even if no suitable rules are matched in the current stage, it is still necessary to continue parsing subsequent protocol layers to ensure that all protocol headers and fields of the entire data packet are fully parsed), then the next level of configurable packet parsing stage is directly entered to continue processing the next level of configurable packet parsing tasks.

[0066] The message buffer includes a data path and control logic. The control logic part gradually parses the header according to predefined rules and stores the parsing results in internal registers. The control logic ensures the accuracy and integrity of the data through state transitions and data transmission control. It determines whether the end of the header has been reached and sets the output signal to valid at the appropriate time, indicating that the header has been completely extracted. The control logic also handles the error condition of premature termination of header extraction.

[0067] The protocol field segmented extraction method (i.e., multiple field extraction units work in parallel to extract different fields of the message header respectively) divides the input message header according to predefined rules and assigns the header to the corresponding extraction unit for processing. To illustrate with an example, assuming that the bit width of the input header is 1024 bits, according to one implementation, the header can be evenly divided into 4 Cell units: Cell_A, Cell_B, Cell_C, and Cell_D. The bit width of each unit corresponds to a different part of the header, for example, Cell_A represents the lower 256 bits of the header, Cell_B represents 256 to 511 bits of the header, Cell_C represents 512 to 767 bits of the header, and Cell_D represents 768 to 1023 bits of the header. In practical applications, the Cell units within each layer of parsing can have different combinations. For example, when the first layer needs to configure protocol parsing, it may only be necessary to use Cell_A or a combination of Cell_A+Cell_B to meet the required extracted protocol fields. The specific combination to be used depends on the actual data packets to be parsed and the hardware resources occupied by each layer of parsing. Therefore, when designing, it is necessary to determine the optimal combination based on specific requirements and hardware resource limitations.

[0068] For fixed-length protocols, one configurable packet parsing module can complete the parsing of a protocol. For variable-length protocols, multiple configurable packet parsing modules can be used to parse using a phased matching method, matching the protocol fields of the data packet in sequence through multiple stages to achieve phased processing of the protocol. The phased matching method means a matching strategy for processing complex protocols such as variable-length protocols. Taking the IPv4 protocol as an example, using the phased matching method, first match whether the protocol type is IPv4, and then further match key fields such as the header length. Such a design can reduce unnecessary consumption of table resources, improve parsing efficiency, and ensure that only the corresponding processing logic is executed for packets that meet the conditions.

[0069] The staged matching method specifically includes: first, in the first stage, protocol type matching is performed, and judgment is made according to the protocol type field of the data packet. If the match is successful, that is, the data packet belongs to the target protocol type, it enters the next stage; otherwise, the default processing logic can be executed or the data packet is passed to the next layer ("next layer" refers to the next protocol layer in the protocol stack. In network communication, the data packet enters the bottom layer of the protocol stack from the network interface layer, and then is processed and parsed through different protocol layers in sequence until it reaches the application layer. The next layer is the upper layer protocol in the protocol stack, which is determined according to the specific protocol stack structure and design. Here it means passing the data packet to the higher layer protocol for processing) for processing. Then, in the second stage, for data packets of specific protocol types, matching is performed according to other protocol fields. These fields can be various attributes related to the protocol, such as header length, protocol field length, and optional items. For each field, a corresponding table entry can be designed to store the field value and the corresponding processing logic. If all protocol fields match successfully, that is, all conditions are met, the corresponding processing logic is executed; otherwise, the default processing logic can be executed or the data packet is passed to the next layer for processing. By matching in stages, the overall matching task can be broken down into multiple stages, matching is performed first based on the most critical fields, and then further matching is performed based on the results. This method effectively reduces the number of table entries and storage overhead, while providing flexibility to adapt to the parsing needs of different protocols and field combinations. For example, for the processing of the IPv4 protocol, the protocol type is first matched as IPv4, and then key fields such as the header length are further matched, thereby reducing unnecessary matching operations.

[0070] During the protocol parsing process, some fields may have higher importance and can more accurately determine the protocol type or structure of the data packet. Therefore, matching these key fields first can significantly improve the parsing efficiency. By matching the most critical fields first, you can quickly make a preliminary judgment to determine which protocol type or structure the data packet may belong to. If the most critical field matches successfully, that is, the data packet meets the expected protocol type or structure, then you can enter the next stage for further matching operations. In subsequent stages, based on the matching results and the values ​​of other fields, you can further refine the length or other properties of the protocol for more accurate processing and parsing.

[0071] Dynamic protocol field length configuration method (dynamic protocol field length configuration method refers to configuring the table entry in the TCAM-RAM unit through the FlowMod message. In the table entry in the TCAM-RAM unit, the protocol field length is represented by the type of the packet header vector. For example, Figure 1As shown, Con_type 0 represents a protocol field length of 1B, Con_type 1 represents a protocol field length of 2B, and Con_type 2 represents a protocol field length of 4B. The value of Con_type is dynamically configured through the FlowMod message to indicate different protocol field lengths) allowing the length of the protocol field to be dynamically configured according to the type of the header vector. This dynamic configuration enables the protocol field length to flexibly adapt to different types of packet header vectors. For example, if the output packet header vector has three types of 1B, 2B and 4B, a 2-bit bit width can be used to represent the configuration of the protocol field length. In this way, in the RAM storing the protocol field length, only 2 bits are needed to represent the protocol field length corresponding to different header vector types. If the protocol field length of a particular header vector exceeds the maximum bit width (for example, more than 4B), a splicing method of multiple sets of extraction rules can be used. By splicing multiple extraction rules in a predetermined order, the extraction and processing of super-long protocol fields can be achieved. This method has strong scalability, can handle protocol fields of various lengths, and can flexibly respond to changes in different header vector types.

[0072] The design steps of FPGA-based packet parser are as follows:

[0073] S01: Determine the protocol set supported by the parser, divide the protocol layers, and add layers for tasks with multiple protocol field matching.

[0074] S02: Design the parsing unit level according to the hierarchical structure. Each level of the tree is a parsing level. Determine the number of levels of the parsing unit.

[0075] S03: Determine the bit width of the interface and packet header vector, and design the header segmentation method according to the characteristics of each layer protocol, as well as the free combination of the Cell units inside the configurable packet parsing module.

[0076] S04: Designing the table entry content of the TCAM-RAM unit according to the protocol field bit width and the protocol format, including the matching rule of the protocol field, the matching bit width and the action of the matching result.

[0077] S05: Design a field extraction unit inside the configurable packet parsing module to extract corresponding protocol fields according to the data packet parts after header segmentation, and pass them to subsequent processing units.

[0078] S06: Design parallel processing units inside the configurable packet parsing module, such as Cell_A, Cell_B, Cell_C, and Cell_D, and assign different data packet parts to corresponding field extraction units for processing according to the designed packet header vector.

[0079] S07: Design the control logic between configurable packet parsing modules to ensure the independence and collaborative work of the configurable packet parsing modules, including data transmission, result merging, etc.

[0080] S08: configuring the table items and parameters inside the configurable packet parsing module, including protocol field rules, table item contents of the TCAM-RAM unit, configuration of the packet header vector, etc.

[0081] S09: Perform synthesis, place-and-route, and timing analysis to optimize the performance and resource usage of the configurable packet parsing module.

[0082] S10: Perform simulation and verification to verify whether the function and performance of the configurable packet parsing module meet the requirements.

[0083] S11: Integrate the configurable packet parsing module into the entire data packet parser and perform system-level verification and testing.

[0084] S12: Perform performance tuning and optimization based on actual application scenarios to meet the requirements of high-speed network packet processing.

[0085] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit the present invention. Although the present invention is described in detail with reference to the embodiments, it should be understood by those skilled in the art that any modification or equivalent replacement of the technical solutions of the present invention does not depart from the spirit and scope of the technical solutions of the present invention and should be included in the scope of the claims of the present invention.

Claims

1. A data packet parser based on FPGA, characterized in that: The parser includes a first-level configurable packet parsing module and a secondary-level configurable packet parsing module connected in sequence; wherein, The first-level configurable packet parsing module is used to extract the bottom-level protocol fields of the message and output the matching domain, header, packet header vector and starting offset to the secondary-level configurable packet parsing module; A plurality of the secondary configurable packet parsing modules are connected in sequence; the secondary configurable packet parsing modules are used to parse the message according to the parsing action configured by the dynamic configuration message.

2. The FPGA-based data packet parser according to claim 1, characterized in that: When the protocol contained in the message is of fixed length, one of the secondary configurable packet parsing modules parses one protocol; when the protocol contained in the message is of variable length, the parsing of the protocol is divided into multiple stages, one of the secondary configurable packet parsing modules parses part of the fields in the protocol, and multiple of the secondary configurable packet parsing modules work in sequence to complete the parsing of the entire protocol.

3. The FPGA-based data packet parser according to claim 2, characterized in that: When multiple secondary configurable packet parsing modules parse the protocol in sequence, the most critical field in the protocol is parsed first, and then other fields in the protocol are processed; the most critical field is a part of the set field in the protocol. If the set field is not matched when being processed, there is no need to continue processing other fields of the protocol.

4. The FPGA-based data packet parser according to claim 1, characterized in that: The secondary configurable packet parsing module includes a TCAM-RAM unit, a matching domain extraction unit, an offset calculation unit and a message segmentation processing unit; wherein, The TCAM-RAM unit is a storage unit that combines TCAM and RAM and is used to match and store rules of the secondary configurable packet parsing module; The matching domain extraction unit is used to extract the matching domain of the next layer protocol; The offset calculation unit is used to calculate the starting offset of the next layer protocol in the message; The message segmentation processing unit is used to segment the message in a prescribed manner, extract different fields of the message, and then merge them into a final parsing result.

5. The FPGA-based data packet parser according to claim 4, characterized in that: The first-level configurable packet parsing module includes the matching domain extraction unit, the offset calculation unit and the message segmentation processing unit.

6. The FPGA-based data packet parser according to claim 4, characterized in that: The matching domain extraction unit, the offset calculation unit and the message segmentation processing unit process data in parallel.

7. The FPGA-based data packet parser according to claim 5 or 6, characterized in that: The message segmentation processing unit includes a message segmentation subunit, a plurality of field extraction subunits and a field combination subunit, wherein: The message segmentation subunit is used to segment the message in a specified manner and output the segmented message to the field extraction subunit; The field extraction subunit is used to extract different fields of the message and output the extraction results to the field combination subunit; The field combination subunit is used to merge the output results of each of the field extraction subunits to obtain a final parsing result.

8. The FPGA-based data packet parser according to claim 7, characterized in that: The message segmentation subunit evenly divides the header into multiple Cell units, and outputs a single Cell unit or a combination of multiple Cell units to the field extraction subunit according to the needs of the field extraction subunit; several of the field extraction subunits process data in parallel.

9. The FPGA-based data packet parser according to claim 4, characterized in that: The parser configures the table entries in the TCAM-RAM unit through FlowMod messages, and dynamically configures different protocol parsing rules.

10. A data packet parsing method based on FPGA, implemented based on any parser described in claims 1-9, characterized in that: The method comprises: The first-level configurable packet parsing module extracts the lowest-level protocol fields of the message and provides matching domains, headers, packet header vectors and starting offsets for subsequent protocol parsing; The plurality of secondary configurable packet parsing modules parse the message in sequence according to the parsing actions configured in the dynamic configuration message.

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