Video encoding method and apparatus therefor

Abstract

A video encoding method, comprising: obtaining a plurality of video frames; processing the plurality of video frames through an encoder to obtain an encoding result; wherein the encoder comprises a first network layer; the first network layer comprises an inter-frame compression module; the plurality of video frames comprise M first video frames and N second video frames; the inter-frame compression module is configured to fuse feature representations of the M first video frames into feature representations of the N second video frames to obtain N feature representations; and performing a video-related task according to the encoding result to obtain a processing result. The inter-frame compression module can aggregate feature representations of similar video frames, thereby reducing the number of feature representations that the model needs to process, and further reducing the computational power consumption of the model.

Description

Technical Field

[0001] This application relates to the field of artificial intelligence, and more particularly to a video coding method and apparatus thereof. Background Technology

[0002] Artificial intelligence (AI) is the theory, methods, technology, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a branch of computer science that attempts to understand the essence of intelligence and produce a new kind of intelligent machine that can react in a way similar to human intelligence. AI studies the design principles and implementation methods of various intelligent machines, enabling them to possess the functions of perception, reasoning, and decision-making.

[0003] The Video Transformer model applies the original Transformer model to the video domain, encoding video features by modeling temporal and spatial information, which can then be used for downstream video understanding tasks such as video-text retrieval, video description generation, and video question answering. The Video Transformer model effectively adapts to large-scale pre-training and has become a fundamental model architecture for video understanding.

[0004] Long videos are segmented into a large number of visual tokens when input into the Video Transformer model, resulting in excessively long and redundant input token sequences. This impairs the efficiency of video encoding and hinders the model's learning of key semantic information. For example, for a 96-frame video with a resolution of 224x224 per frame, the commonly used Video Transformer model segments each frame into 16x16 patches, resulting in as many as (224 / 16)x(224 / 16)x96 = 19K visual tokens, placing a significant computational burden on subsequent feature encoding.

[0005] Therefore, there is an urgent need for a video coding method with lower computational overhead. Summary of the Invention

[0006] In a first aspect, this application provides a video encoding method, the method comprising: acquiring multiple video frames; processing the multiple video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the multiple video frames include M first video frames and N second video frames, the inter-frame compression module is used to fuse the feature representations of the M first video frames into the feature representations of the N second video frames to obtain N feature representations; and performing video-related tasks according to the encoding result to obtain a processing result.

[0007] The inter-frame compression module can reduce the number of feature representations that the model needs to process by aggregating the feature representations of similar video frames, thereby reducing the computational overhead of the model.

[0008] In one possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0009] In one possible implementation, fusing the feature representations of the M first video frames into the feature representations of the N second video frames includes: fusing the feature representation of each of the M first video frames into the feature representation of the second video frame most similar to the N second video frames.

[0010] The inter-frame compression module reduces the number of feature representations the model needs to process by aggregating the feature representations of similar video frames. By aggregating similar video frames, this embodiment ensures that important temporal information in the video is fully preserved. Therefore, the method of this embodiment improves computational efficiency while still guaranteeing the quality and effect of video encoding.

[0011] In one possible implementation, the M first video frames are the M video frames among the plurality of video frames that have the lowest correlation with the other video frames.

[0012] For the selection of objects to be fused (e.g., M first video frames), this application proposes a selection algorithm based on the importance of visual tokens. By evaluating and ranking the importance of each token, tokens with higher importance are selected as representative tokens.

[0013] In one possible implementation, the first video frame and the second video frame are interleaved among the plurality of video frames.

[0014] This application proposes a selection algorithm based on visual token geometric information. By considering the position and distribution of tokens in space, it selects tokens with a reasonable spatial distribution as representative tokens. The introduction of these selection algorithms makes the aggregation process more accurate and efficient, ensuring the quality and accuracy of the aggregation results.

[0015] In one possible implementation, the fusion is average pooling.

[0016] In one possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the plurality of video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse the feature representations of the X first image blocks into the feature representations of the Y second image blocks to obtain Y feature representations.

[0017] The intra-frame compression module can reduce the number of feature representations that the model needs to process by aggregating the feature representations of similar image blocks, thereby reducing the computational overhead of the model.

[0018] In one possible implementation, fusing the feature representations of the X first image blocks into the feature representations of the Y second image blocks includes:

[0019] The feature representations of each of the X first image blocks are fused into the feature representation of the second image block that is most similar to the Y second image blocks.

[0020] The inter-frame compression module reduces the number of feature representations the model needs to process by aggregating the feature representations of similar video frames. By aggregating similar video frames, this embodiment ensures that important temporal information in the video is fully preserved. Therefore, the method of this embodiment improves computational efficiency while still guaranteeing the quality and effect of video encoding.

[0021] In one possible implementation, the X first image blocks are the X image blocks with the lowest correlation to other image blocks among the multiple image blocks included in the third video frame.

[0022] In one possible implementation, the first image block and the second image block are interleaved in the third video frame.

[0023] Secondly, this application provides a video encoding apparatus, the apparatus comprising:

[0024] The acquisition module is used to acquire multiple video frames;

[0025] A processing module is used to process the plurality of video frames through an encoder to obtain an encoding result; wherein, the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the plurality of video frames include M first video frames and N second video frames, and the inter-frame compression module is used to fuse the feature representations of the M first video frames into the feature representations of the N second video frames to obtain N feature representations;

[0026] Based on the encoding results, video-related tasks are performed to obtain the processing results.

[0027] In one possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0028] In one possible implementation, the processing module is specifically used for:

[0029] The feature representations of each of the M first video frames are fused into the feature representation of the second video frame that is most similar to the N second video frames.

[0030] In one possible implementation, the M first video frames are the M video frames among the plurality of video frames that have the lowest correlation with the other video frames.

[0031] In one possible implementation, the first video frame and the second video frame are interleaved among the plurality of video frames.

[0032] In one possible implementation, the fusion is average pooling.

[0033] In one possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the plurality of video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse the feature representations of the X first image blocks into the feature representations of the Y second image blocks to obtain Y feature representations.

[0034] In one possible implementation, the processing module is specifically used for:

[0035] The feature representations of each of the X first image blocks are fused into the feature representation of the second image block that is most similar to the Y second image blocks.

[0036] In one possible implementation, the X first image blocks are the X image blocks with the lowest correlation to other image blocks among the multiple image blocks included in the third video frame.

[0037] In one possible implementation, the first image block and the second image block are interleaved in the third video frame.

[0038] Thirdly, embodiments of this application provide a data processing apparatus, which may include a memory, a processor, and a bus system, wherein the memory is used to store a program, and the processor is used to execute the program in the memory to perform the methods described in the first aspect above and any of its optional methods.

[0039] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any of its optional methods.

[0040] Fifthly, embodiments of this application provide a computer program that, when run on a computer, causes the computer to perform the first aspect and any of its optional methods described above.

[0041] Sixthly, this application provides a chip system including a processor for supporting an execution data processing device in implementing the functions involved in the foregoing aspects, such as transmitting or processing data involved in the foregoing methods; or, information. In one possible design, the chip system further includes a memory for storing program instructions and data necessary for the execution device or training device. This chip system may be composed of chips or may include chips and other discrete devices. Attached Figure Description

[0042] Figure 1A A structural diagram illustrating the main framework of artificial intelligence;

[0043] Figure 1B Hezhi Figure 1C This is a schematic diagram of the application system framework of the present invention;

[0044] Figure 1D This is a schematic diagram of an optional hardware structure for a terminal.

[0045] Figure 2 This is a schematic diagram of the structure of a server;

[0046] Figure 3 This is a schematic diagram of a system architecture according to this application;

[0047] Figure 4 A process for providing a cloud service;

[0048] Figure 5 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0049] Figure 6 This is a schematic diagram of a network structure in this application;

[0050] Figure 7 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0051] Figure 8 This is a schematic diagram of one fusion method in this application;

[0052] Figure 9A This is a schematic diagram of a pre-training method in this application;

[0053] Figure 9B This is a schematic diagram illustrating a beneficial effect of this application;

[0054] Figure 10 A schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application;

[0055] Figure 11 A schematic diagram of the structure of the execution device provided in the embodiments of this application;

[0056] Figure 12 A schematic diagram of the structure of the training device provided in the embodiments of this application;

[0057] Figure 13 This is a schematic diagram of a chip structure provided in an embodiment of this application. Detailed Implementation

[0058] The embodiments of the present invention will now be described with reference to the accompanying drawings. The terminology used in the embodiments section is for illustrative purposes only and is not intended to limit the scope of the invention.

[0059] The embodiments of this application will now be described with reference to the accompanying drawings. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are equally applicable to similar technical problems.

[0060] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.

[0061] The terms “substantially,” “about,” and similar terms used herein are used as approximations rather than as terms of degree, and are intended to take into account the inherent biases of measurements or calculations known to those skilled in the art. Furthermore, the use of “may” in describing embodiments of the invention refers to “one or more possible embodiments.” The terms “use,” “using,” and “used” used herein are to be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Additionally, the term “exemplary” is intended to refer to an instance or illustration.

[0062] First, the overall workflow of the artificial intelligence system is described; please refer to [link / reference]. Figure 1A , Figure 1A The diagram illustrates a structural framework for artificial intelligence (AI). The framework is further elaborated below along two dimensions: the "Intelligent Information Chain" (horizontal axis) and the "IT Value Chain" (vertical axis). The "Intelligent Information Chain" reflects a series of processes from data acquisition to processing. For example, it could be the general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, and intelligent execution and output. In this process, data undergoes a condensation process of "data—information—knowledge—wisdom." The "IT Value Chain" reflects the value that AI brings to the information technology industry, from the underlying infrastructure of human intelligence and information (provided and processed through technological means) to the industrial ecosystem of the system.

[0063] (1) Infrastructure

[0064] Infrastructure provides computing power to support artificial intelligence systems, enabling communication with the external world and providing support through a basic platform. This communication occurs through sensors; computing power is provided by intelligent chips (hardware acceleration chips such as CPUs, NPUs, GPUs, ASICs, and FPGAs); and the basic platform includes distributed computing frameworks and related platform guarantees and support, which may include cloud storage and computing, interconnected networks, etc. For example, sensors communicate with the outside world to acquire data, and this data is provided to intelligent chips in the distributed computing system provided by the basic platform for computation.

[0065] (2) Data

[0066] The data at the next layer of infrastructure is used to represent the data sources in the field of artificial intelligence. The data involves graphics, images, voice, text, and IoT data from traditional devices, including business data from existing systems and sensor data such as force, displacement, liquid level, temperature, and humidity.

[0067] (3) Data processing

[0068] Data processing typically includes methods such as data training, machine learning, deep learning, search, reasoning, and decision-making.

[0069] Among them, machine learning and deep learning can perform intelligent information modeling, extraction, preprocessing, and training on data, including symbolization and formalization.

[0070] Reasoning refers to the process in which, in a computer or intelligent system, the machine thinks and solves problems by simulating human intelligent reasoning, based on reasoning control strategies and using formalized information. Typical functions include search and matching.

[0071] Decision-making refers to the process of making decisions based on intelligent information after reasoning, and it typically provides functions such as classification, sorting, and prediction.

[0072] (4) General ability

[0073] After the data processing mentioned above, the results of the data processing can be used to form some general capabilities, such as algorithms or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0074] (5) Smart Products and Industry Applications

[0075] Intelligent products and industry applications refer to products and applications of artificial intelligence systems in various fields. They are the encapsulation of overall artificial intelligence solutions, productizing intelligent information decision-making and realizing practical applications. Their application areas mainly include: intelligent terminals, intelligent transportation, intelligent healthcare, autonomous driving, smart cities, etc.

[0076] This application can be applied to the field of natural language processing in the field of artificial intelligence. The following will introduce several application scenarios that have been implemented in products, taking natural language processing as an example.

[0077] First, we will introduce the application scenarios of this application. This application can be applied, but is not limited to, to applications with video understanding capabilities (hereinafter referred to as video understanding applications) or cloud services provided by cloud-side servers. These will be introduced separately below:

[0078] I. Video Understanding Applications

[0079] The product form of this application embodiment can be a video understanding application. Video understanding applications can run on terminal devices or cloud-based servers.

[0080] In one possible implementation, video understanding applications can perform video-related processing tasks and obtain processing results.

[0081] For example, video understanding applications can perform video understanding tasks including at least video classification, video search, video recommendation, video location, and ad matching, but are not limited to these.

[0082] In one possible implementation, a user can open a video understanding application installed on a terminal device and input a video (the video may be triggered by a command, not necessarily actively input by the user). The video understanding application can process the video using the methods provided in the embodiments of this application and present the processing result to the user (the presentation method may include, but is not limited to, displaying, saving, uploading to the cloud, etc.).

[0083] In one possible implementation, a user can open a video understanding application installed on a terminal device and input a video. The video understanding application can then send the video to a cloud-based server. The cloud-based server processes the video using the method provided in this application embodiment and sends the processing result back to the terminal device. The terminal device can then present the processing result to the user (the presentation method may include, but is not limited to, displaying, saving, or uploading to the cloud).

[0084] The following sections will introduce the video understanding application in this application from the perspectives of functional architecture and product architecture that implements the functions.

[0085] Reference Figure 1B , Figure 1B This is a schematic diagram of the functional architecture of the video understanding application in the embodiments of this application:

[0086] In one possible implementation, such as Figure 1B As shown, the video understanding application 102 can receive input parameters 101 (e.g., including images) and generate processing results 103. The video understanding application 102 can be executed on at least one computer system (for example) and includes computer code that, when executed by one or more computers, causes the computers to perform methods provided by embodiments of this application.

[0087] Reference Figure 1C , Figure 1C This is a schematic diagram of the entity architecture for running a video understanding application in this embodiment of the application:

[0088] See Figure 1C , Figure 1C A schematic diagram of a system architecture is shown. The system may include a terminal 100 and a server 200. The server 200 may include one or more servers (…). Figure 1C(The example includes a server), where server 200 can provide video understanding functionality for one or more terminals.

[0089] The terminal 100 may have a video understanding application installed, or a webpage related to video understanding function opened. The application and webpage can provide an interface. The terminal 100 can receive relevant parameters input by the user on the video understanding function interface and send the parameters to the server 200. The server 200 can obtain the processing result based on the received parameters and return the processing result to the terminal 100.

[0090] It should be understood that in some optional implementations, the terminal 100 can also complete the action of obtaining the processing result based on the received parameters on its own, without the need for the server to cooperate. This application embodiment is not limited to this.

[0091] The following description Figure 1C The product form of the mid-terminal 100;

[0092] The terminal 100 in this application embodiment can be a mobile phone, tablet computer, wearable device, vehicle device, augmented reality (AR) / virtual reality (VR) device, laptop computer, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), etc., and this application embodiment does not impose any restrictions on it.

[0093] Figure 1D A schematic diagram of an optional hardware structure for terminal 100 is shown.

[0094] refer to Figure 1D As shown, the terminal 100 may include a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), a processor 170, an external interface 180, a power supply 190, and other components. Those skilled in the art will understand that... Figure 1D These are merely examples of terminals or multi-functional devices and do not constitute a limitation on terminals or multi-functional devices. They may include more or fewer components than shown in the illustration, or combine certain components, or use different components.

[0095] The input unit 130 can be used to receive input numerical or character information, and to generate key signal inputs related to user settings and function control of the portable multi-functional device. Specifically, the input unit 130 may include a touchscreen 131 (optional) and / or other input devices 132. The touchscreen 131 can collect touch operations performed by the user on or near it (such as operations performed by the user using fingers, knuckles, styluses, or any suitable object on or near the touchscreen), and drive the corresponding connection devices according to a pre-set program. The touchscreen can detect the user's touch actions, convert the touch actions into touch signals and send them to the processor 170, and can receive and execute commands sent by the processor 170; the touch signal includes at least touch point coordinate information. The touchscreen 131 can provide an input interface and an output interface between the terminal 100 and the user. In addition, various types of touchscreens, such as resistive, capacitive, infrared, and surface acoustic wave, can be used to implement the touchscreen. Besides the touchscreen 131, the input unit 130 may also include other input devices. Specifically, other input devices 132 may include, but are not limited to, one or more of the following: physical keyboard, function keys (such as volume control buttons 132, power buttons 133, etc.), trackball, mouse, joystick, etc.

[0096] The input device 132 can receive the input video.

[0097] The display unit 140 can be used to display information input by the user or information provided to the user, various menus of the terminal 100, interactive interfaces, file display, and / or playback of any multimedia file. In this embodiment, the display unit 140 can be used to display the interface and processing results of a video understanding application.

[0098] The memory 120 can be used to store instructions and data. The memory 120 may primarily include an instruction storage area and a data storage area. The data storage area can store various types of data, such as multimedia files and text. The instruction storage area can store software units such as operating systems, applications, and instructions required for at least one function, or subsets or extended sets thereof. It may also include non-volatile random access memory. It provides the processor 170 with hardware, software, and data resources for managing the computing device, supporting control software and applications. It is also used for storing multimedia files, as well as storing running programs and applications.

[0099] The processor 170 is the control center of the terminal 100. It connects various parts of the terminal 100 via various interfaces and lines. By running or executing instructions stored in the memory 120 and calling data stored in the memory 120, it performs various functions and processes data of the terminal 100, thereby controlling the terminal device as a whole. Optionally, the processor 170 may include one or more processing units; preferably, the processor 170 may integrate an application processor and a modem processor, wherein the application processor mainly handles the operating system, user interface, and applications, and the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 170. In some embodiments, the processor and memory can be implemented on a single chip; in some embodiments, they can also be implemented separately on independent chips. The processor 170 can also be used to generate corresponding operation control signals, send them to the corresponding components of the computing processing device, read and process data in the software, especially read and process data and programs in the memory 120, so that the various functional modules therein perform corresponding functions, thereby controlling the corresponding components to act according to the instructions.

[0100] The memory 120 can be used to store software code related to the data processing method, and the processor 170 can execute the steps of the chip's data processing method, and can also schedule other units (such as the above-mentioned input unit 130 and display unit 140) to achieve the corresponding functions.

[0101] The radio frequency unit 110 (optional) can be used for receiving and transmitting signals during information transmission or calls. For example, it can receive downlink information from the base station and process it for the processor 170; additionally, it can transmit uplink data to the base station. Typically, the RF circuit includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low-noise amplifier (LNA), a duplexer, etc. Furthermore, the radio frequency unit 110 can also communicate wirelessly with network devices and other devices. This wireless communication can use any communication standard or protocol, including but not limited to Global System for Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.

[0102] In this embodiment of the application, the radio frequency unit 110 can send video to the server 200 and receive the processing results sent by the server 200.

[0103] It should be understood that the radio frequency unit 110 is optional and can be replaced with other communication interfaces, such as a network port.

[0104] The terminal 100 also includes a power supply 190 (such as a battery) that supplies power to various components. Preferably, the power supply can be logically connected to the processor 170 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system.

[0105] Terminal 100 also includes an external interface 180, which can be a standard Micro USB interface or a multi-pin connector, which can be used to connect terminal 100 to other devices for communication or to connect a charger to charge terminal 100.

[0106] Although not shown, terminal 100 may also include a flash, a wireless fidelity (WiFi) module, a Bluetooth module, sensors with various functions, etc., which will not be described in detail here. Some or all of the methods described below can be applied to, for example... Figure 1D In the terminal 100 shown.

[0107] The following description Figure 1C The product form of the mid-range server 200;

[0108] Figure 2 A structural diagram of a server 200 is provided, as follows: Figure 2 As shown, server 200 includes bus 201, processor 202, communication interface 203, and memory 204. Processor 202, memory 204, and communication interface 203 communicate with each other via bus 201.

[0109] Bus 201 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 2 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0110] The processor 202 can be any one or more of the following processors: central processing unit (CPU), graphics processing unit (GPU), microprocessor (MP), or digital signal processor (DSP).

[0111] Memory 204 may include volatile memory, such as random access memory (RAM). Memory 204 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard disk drive (HDD), or solid state drive (SSD).

[0112] The memory 204 can be used to store software code related to the data processing method, and the processor 202 can execute the steps of the chip's data processing method, and can also schedule other units to achieve corresponding functions.

[0113] It should be understood that the aforementioned terminal 100 and server 200 can be centralized or distributed devices. The processors (e.g., processor 170 and processor 202) in the aforementioned terminal 100 and server 200 can be hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the processor can be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0114] It should be understood that the steps related to the model inference process in the embodiments of this application involve AI-related operations. When performing AI operations, the instruction execution architecture of the terminal device and server is not limited to the processor-memory architecture described above. The following section will further explain... Figure 3 The system architecture provided in the embodiments of this application will be described in detail.

[0115] Figure 3 This is a schematic diagram of the system architecture provided for an embodiment of this application. Figure 3 As shown, the system architecture 500 includes an execution device 510, a training device 520, a database 530, a client device 540, a data storage system 550, and a data acquisition system 560.

[0116] The execution device 510 includes a calculation module 511, an I / O interface 512, a preprocessing module 513, and a preprocessing module 514. The calculation module 511 may include a target model / rule 501, while the preprocessing modules 513 and 514 are optional.

[0117] The execution device 510 can be a terminal device or a server that runs the aforementioned video understanding application.

[0118] The data acquisition device 560 is used to collect training samples. Training samples can be videos, etc. After collecting the training samples, the data acquisition device 560 stores these training samples in the database 530.

[0119] The training device 520 can maintain training samples in the database 530 to obtain the target model / rule 501 from the neural network to be trained (e.g., the model in the embodiments of this application (e.g., including image encoder, text encoder, etc.)).

[0120] It should be understood that the training device 520 can perform a pre-training process on the neural network to be trained based on the training samples maintained in the database 530, or fine-tune the model based on the pre-training.

[0121] It should be noted that in practical applications, the training samples maintained in database 530 may not all come from the data acquisition device 560; they may also be received from other devices. Furthermore, it should be noted that training device 520 may not necessarily train the target model / rule 501 entirely based on the training samples maintained in database 530; it may also obtain training samples from the cloud or other sources for model training. The above description should not be construed as limiting the embodiments of this application.

[0122] The target model / rule 501 trained using training device 520 can be applied to different systems or devices, such as... Figure 3 The execution device 510 shown can be a terminal, such as a mobile phone terminal, tablet computer, laptop computer, augmented reality (AR) / virtual reality (VR) device, vehicle terminal, etc., or it can be a server, etc.

[0123] Specifically, the training device 520 can transfer the trained model to the execution device 510.

[0124] exist Figure 3 In the execution device 510, an input / output (I / O) interface 512 is configured for data interaction with external devices. Users can input data (such as video in the embodiments of this application) to the I / O interface 512 through the client device 540.

[0125] Preprocessing modules 513 and 514 are used to preprocess the input data received from the I / O interface 512. It should be understood that preprocessing modules 513 and 514 may be absent, or only one preprocessing module may be used. When preprocessing modules 513 and 514 are absent, the calculation module 511 can be used directly to process the input data.

[0126] During the preprocessing of input data by the execution device 510, or during the calculation module 511 of the execution device 510 performing calculations and other related processes, the execution device 510 can call data, code, etc. in the data storage system 550 for corresponding processing, or store the data, instructions, etc. obtained from the corresponding processing into the data storage system 550.

[0127] Finally, the I / O interface 512 provides the processing result to the client device 540, thereby providing it to the user.

[0128] exist Figure 3 In the illustrated scenario, the user can manually provide input data, which can be done through the interface provided by I / O interface 512. Alternatively, the client device 540 can automatically send input data to I / O interface 512. If user authorization is required for the client device 540 to automatically send input data, the user can set the corresponding permissions in the client device 540. The user can view the output results of the execution device 510 on the client device 540, which can be presented in various forms such as display, sound, or animation. The client device 540 can also act as a data acquisition terminal, collecting the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530. Alternatively, data can be collected directly from the I / O interface 512 without going through the client device 540, using the input data and output results of the input I / O interface 512 as shown in the figure, and storing them as new sample data in database 530.

[0129] It is worth noting that, Figure 3 This is merely a schematic diagram of a system architecture provided in an embodiment of this application. The positional relationships between the devices, components, modules, etc., shown in the diagram do not constitute any limitation. For example, in Figure 3 In this context, the data storage system 550 is an external storage device relative to the execution device 510. However, in other cases, the data storage system 550 may also be placed within the execution device 510. It should be understood that the aforementioned execution device 510 may be deployed within the client device 540.

[0130] From the inference side of the model:

[0131] In this embodiment, the computing module 511 of the execution device 520 can obtain the code stored in the data storage system 550 to implement the steps related to the model reasoning process in this embodiment.

[0132] In this embodiment of the application, the computing module 511 of the execution device 520 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0133] Specifically, the computing module 511 of the execution device 520 can be a hardware system with the function of executing instructions. The steps related to the model inference process provided in this application embodiment can be software code stored in the memory. The computing module 511 of the execution device 520 can obtain the software code from the memory and execute the obtained software code to implement the steps related to the model inference process provided in this application embodiment.

[0134] It should be understood that the computing module 511 of the execution device 520 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps related to the model reasoning process provided in the embodiments of this application can also be implemented by the hardware system in the computing module 511 of the execution device 520 without the function of executing instructions, which is not limited here.

[0135] From the training side of the model:

[0136] In this embodiment of the application, the training device 520 can access the memory ( Figure 3 (Not shown in the diagram, but can be integrated into the training device 520 or deployed separately from the training device 520) The code stored in the diagram can be used to implement the steps related to model training in the embodiments of this application.

[0137] In this embodiment of the application, the training device 520 may include hardware circuits (such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), general-purpose processors, digital signal processors (DSPs), microprocessors or microcontrollers, etc.) or combinations of these hardware circuits. For example, the training device 520 may be a hardware system with instruction execution capabilities, such as a CPU or DSP, or a hardware system without instruction execution capabilities, such as an ASIC or FPGA, or a combination of the aforementioned hardware systems without instruction execution capabilities and hardware systems with instruction execution capabilities.

[0138] It should be understood that the training device 520 can be a combination of a hardware system without the function of executing instructions and a hardware system with the function of executing instructions. Some steps related to the training of the neutralization model provided in the embodiments of this application can also be implemented by the hardware system in the training device 520 without the function of executing instructions, which is not limited here.

[0139] II. Cloud services providing video understanding functionality provided by the server:

[0140] In one possible implementation, the server can provide video understanding services to the client side through an application programming interface (API).

[0141] In this process, the terminal device can send relevant parameters (such as images, text, and other data) to the server through the API provided by the cloud. The server can then obtain the processing results based on the received parameters and return the processing results to the terminal.

[0142] The description of the terminal and server can be found in the above embodiments, and will not be repeated here.

[0143] like Figure 4 This demonstrates the process of using a cloud service that provides video understanding capabilities through a cloud platform.

[0144] 1. Activate and purchase content moderation services.

[0145] 2. Users can download the software development kit (SDK) corresponding to the content moderation service. Cloud platforms usually provide multiple development versions of the SDK for users to choose from according to their development environment needs, such as JAVA version SDK, Python version SDK, PHP version SDK, Android version SDK, etc.

[0146] 3. After downloading the corresponding version of the SDK to their local machine according to their needs, users can import the SDK project into their local development environment, configure and debug it in the local development environment, and develop other functions in the local development environment to form an application that integrates video understanding capabilities.

[0147] 4. When a video understanding application is used, it can trigger an API call for the video understanding function when video understanding is required. When the application triggers the video understanding function, it sends an API request to the running instance of the video understanding service in the cloud environment. The API request carries an image, which is then processed by the running instance in the cloud environment to obtain the processing result.

[0148] 5. The cloud environment returns the processing results to the application, thus completing a video understanding function call.

[0149] Since the embodiments of this application involve a large number of neural network applications, for ease of understanding, the relevant terms and concepts such as neural networks involved in the embodiments of this application will be introduced below.

[0150] (1) Neural Network

[0151] A neural network can be composed of neural units, which can be defined as a computational unit that takes xs (i.e., input data) and an intercept of 1 as input. The output of this computational unit can be:

[0152]

[0153] Where s = 1, 2, ..., n, where n is a natural number greater than 1, Ws is the weight of xs, and b is the bias of the neural unit. f is the activation function of the neural unit, used to introduce nonlinear characteristics into the neural network to convert the input signal in the neural unit into an output signal. The output signal of this activation function can be used as the input of the next convolutional layer, and the activation function can be the sigmoid function. A neural network is a network formed by connecting multiple of the above-mentioned individual neural units together, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field, which can be a region composed of several neural units.

[0154] (2) Transformer layer

[0155] The neural network includes an embedding layer and at least one transformer layer. The at least one transformer layer can be N transformer layers (N being an integer greater than 0). Each transformer layer includes sequentially adjacent attention layers, add and normalize layers, feed-forward layers, and add and normalize layers. In the embedding layer, the current input is embedded to obtain multiple embedding vectors. In the attention layer, P input vectors are obtained from the layer above the first transformer layer. Using any first input vector among the P input vectors as the center, intermediate vectors corresponding to the first input vector are obtained based on the correlation between each input vector within a preset attention window and the first input vector. This process determines P intermediate vectors corresponding to the P input vectors. In the pooling layer, the P intermediate vectors are merged into Q output vectors, where the multiple output vectors obtained from the last transformer layer are used as feature representations of the current input.

[0156] (3) Attention mechanism

[0157] Attention mechanisms mimic the internal processes of biological observation—aligning internal experience with external senses to increase the precision of observation in specific areas. They enable the rapid sifting of high-value information from a large volume of data using limited attentional resources. Attention mechanisms can quickly extract important features from sparse data and are therefore widely used in natural language processing tasks, particularly machine translation. Self-attention mechanisms, an improvement on attention mechanisms, reduce reliance on external information and are better at capturing the internal correlations of data or features. The core idea of ​​attention mechanisms can be rewritten as follows:

[0158] In this formula, Lx = ||Source|| represents the length of the Source. The meaning is that the elements in the Source are imagined as a series of data pairs. Given a Query element in the Target, the similarity or relevance between the Query and each Key is calculated to obtain the weight coefficient of the Value corresponding to each Key. Then, the Values ​​are weighted and summed to obtain the final Attention value. Therefore, the Attention mechanism essentially performs a weighted sum of the Values ​​of the elements in the Source, while the Query and Key are used to calculate the weight coefficients of their corresponding Values. Conceptually, Attention can be understood as selectively filtering a small amount of important information from a large amount of information and focusing on this important information, ignoring most of the unimportant information. The focusing process is reflected in the calculation of the weight coefficients; the larger the weight, the more focused it is on its corresponding Value. That is, the weight represents the importance of the information, and the Value is the corresponding information. Self-attention can be understood as intra attention. The attention mechanism occurs between the elements of the Target (Query) and all elements of the Source. Self-attention refers to the attention mechanism that occurs between elements within the Source or between elements within the Target. It can also be understood as the attention calculation mechanism in the special case where Target = Source. The specific calculation process is the same, only the calculation object changes.

[0159] (4) Natural Language Processing (NLP)

[0160] Natural language is human language, and Natural Language Processing (NLP) is the processing of human language. NLP is a systematic process of analyzing, understanding, and extracting information from text data in an intelligent and efficient manner. By using NLP and its components, we can manage very large amounts of text data, perform numerous automated tasks, and solve a wide variety of problems, such as automatic summarization, machine translation (MT), named entity recognition (NER), relation extraction (RE), information extraction (IE), sentiment analysis, speech recognition, question answering systems, and topic segmentation, among others.

[0161] (5) Backpropagation algorithm

[0162] Convolutional neural networks can employ backpropagation (BP) to correct the parameters in the initial super-resolution model during training, thereby reducing the reconstruction error loss. Specifically, forward propagation of the input signal to the output generates an error loss; this error loss information is then propagated back to update the parameters in the initial super-resolution model, leading to convergence of the error loss. The backpropagation algorithm is an error-loss-driven backpropagation process aimed at obtaining the optimal parameters of the super-resolution model, such as the weight matrix.

[0163] (6) Loss Function

[0164] In training a deep neural network, to ensure the output closely approximates the desired predicted value, we compare the network's prediction with the target value. Based on the difference, we update the weight vector of each layer (usually pre-configuring parameters before the initial update). For example, if the prediction is too high, the weight vector is adjusted to predict a lower value. This adjustment continues until the deep neural network predicts the target value or a value very close to it. Therefore, we need to predefine "how to compare the difference between the predicted and target values," which is the loss function or objective function. These are important equations used to measure the difference between the predicted and target values. Taking the loss function as an example, a higher output value (loss) indicates a greater difference, and training the deep neural network becomes a process of minimizing this loss.

[0165] (7) Transformer: A network based on multi-head attention mechanism, containing residual connections, layer normalization and fully connected layers that can process sequence data in parallel. It was originally used to encode text features.

[0166] (8) Video Transformer: A Transformer network modified for the video domain. It models temporal and spatial information through spatiotemporal attention and can be used to encode video features.

[0167] (9) Token: The smallest unit in the input sequence of the Video Transformer model. Similar to the Transformer, the Video Transformer accepts a sequence of Tokens as input. The video input is 3-dimensional, including the number of frames T, the width W, and the height H of each frame. To encode the video, the model typically divides the video into several smallest units (i.e., Tokens) and then uses them as the input sequence. These Tokens can be 3-dimensional (i.e., small cubes, obtained by directly segmenting the 3-dimensional video) or 2-dimensional (i.e., small patches, obtained by segmenting each frame). In this technique, the Token corresponds to a 2-dimensional patch.

[0168] (10) Patch: A 2D small square obtained by segmenting each frame of an image in Video Transformer. An image (e.g., 224x224, where 224 is the side length of the image) is cut into several small squares of the same size (e.g., 16x16, where 16 is the side length of the small square), which is called a patch.

[0169] The Video Transformer model applies the original Transformer model to the video domain, encoding video features by modeling temporal and spatial information, which can then be used for downstream video understanding tasks such as video-text retrieval, video description generation, and video question answering. The Video Transformer model effectively adapts to large-scale pre-training and has become a fundamental model architecture for video understanding.

[0170] Long videos are segmented into a large number of visual tokens when input into the Video Transformer model, resulting in excessively long and redundant input token sequences. This impairs the efficiency of video encoding and hinders the model's learning of key semantic information. For example, for a 96-frame video with a resolution of 224x224 per frame, the commonly used Video Transformer model segments each frame into 16x16 patches, resulting in as many as (224 / 16)x(224 / 16)x96 = 19K visual tokens, placing a significant computational burden on subsequent feature encoding.

[0171] Therefore, there is an urgent need for a video coding method with lower computational overhead.

[0172] To address the aforementioned problems, embodiments of this application provide a data processing method. The data processing method of this application embodiment will be described in detail below with reference to the accompanying drawings.

[0173] Reference Figure 5 , Figure 5 This is a flowchart illustrating a data processing method provided in an embodiment of this application, such as... Figure 5 As shown in the embodiment of this application, a data processing method may include steps 501 to 505, which are described in detail below.

[0174] 501. Obtain multiple video frames;

[0175] In one possible implementation, the video, which includes multiple video frames, can be pre-stored locally on the terminal, obtained by the terminal from the outside world (such as the Internet), or captured in real time by the terminal, for example, captured in real time through the terminal's camera.

[0176] The video can be long or short. Generally, a short video is defined as one less than 30 seconds long, while a long video is defined as one longer than 30 seconds. In many academic datasets, the average length of long videos is around 150 seconds, more than five times that of short videos. Given a fixed frame rate, long videos naturally contain more input frames than short videos.

[0177] 502. The multiple video frames are processed by an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the multiple video frames include M first video frames and N second video frames, and the inter-frame compression module is used to fuse the feature representations of the M first video frames into the feature representations of the N second video frames to obtain N feature representations.

[0178] In the current Video Transformer model, long videos are segmented into a large number of visual tokens (the number of visual tokens is equal to the number of frames multiplied by the number of patches per frame). This results in an excessively long input token sequence and significant redundancy. This situation negatively impacts the efficiency of video encoding and imposes a huge computational burden on subsequent feature encoding processes. Furthermore, due to redundancy, the input sequence may contain a large amount of similar or repetitive visual information, further increasing computational redundancy. These problems collectively lead to a decrease in video encoding efficiency, resulting in a significant computational burden and complexity for subsequent feature encoding processes. Therefore, the embodiments of this application aim to address these technical problems triggered by long video input, in order to improve the efficiency of video encoding and reduce the computational burden of feature encoding.

[0179] The encoder may include multiple network layers, each of which can receive the feature representation output by the adjacent previous network layer and extract features from the feature representation output by the adjacent previous network layer.

[0180] In one possible implementation, the encoder includes a first network layer, which may include an inter-frame compression module. Specifically, the plurality of video frames includes M first video frames and N second video frames. The inter-frame compression module is used to fuse the feature representations of the M first video frames into the feature representations of the N second video frames, resulting in N feature representations. That is, the inter-frame compression module can, during encoding, fuse the feature representations of some video frames into the feature representations of another set of video frames, thereby reducing the number of feature representations.

[0181] In this context, the feature representation can be represented as a token. That is, the inter-frame compression module is used to convert the M tokens corresponding to the M first video frames (each first video frame corresponds to one token) to the N tokens corresponding to the N second video frames, thus obtaining N tokens.

[0182] For example, you can refer to Figure 6 , Figure 6The video encoder block can be the first network layer. The temporal aggregation in the video encoder block is an inter-frame compression module. The input of the temporal aggregation is a feature of size T*L*D, where T is the number of video frames, L is the number of image blocks included in the video frame, and D is the dimension of the feature representation of each image block. Since the temporal aggregation fuses the feature representations of Rt video frames out of T video frames into the feature representations of (T-Rt) video frames, a feature representation of size (T-Rt)*L*D can be obtained.

[0183] Next, we will explain how to determine the video frames whose feature representations need to be fused into other video frames:

[0184] In one possible implementation, the M first video frames are the M video frames among the plurality of video frames that have the lowest correlation with the other video frames.

[0185] In this approach, the M least important first video frames can be selected from multiple video frames and assigned to Set A, while the remaining N second video frames can be assigned to Set B. The feature representations of the M least important first video frames can be fused into the feature representations of the N second video frames, which can reduce the information loss during fusion.

[0186] For the selection of objects to be fused (e.g., M first video frames), this application proposes a selection algorithm based on the importance of visual tokens. By evaluating and ranking the importance of each token, tokens with higher importance are selected as representative tokens.

[0187] In one possible implementation, a video frame with a lower correlation to other video frames can be considered a less important video frame.

[0188] Alternatively, the method for calculating the importance of video frames is as follows:

[0189]

[0190] Among them, A ji From token x j (that is, the feature representation of the j-th video frame) to token x i The attention score (which represents the feature representation of the i-th video frame) indicates the correlation between video frames. Q and K denote the Query and Key in the attention mechanism.

[0191] In one possible implementation, the first video frame and the second video frame are interleaved among the plurality of video frames.

[0192] Adjacent video frames often have higher similarity and should be grouped into different sets to encourage their fusion. Therefore, adjacent first and second video frames can be grouped into different sets; for example, odd-numbered first video frames can be assigned to Set A, and even-numbered second video frames to Set B. The feature representations of the first video frames in Set A are then fused to the feature representations of the second video frames in Set B.

[0193] This application proposes a selection algorithm based on visual token geometric information. By considering the position and distribution of tokens in space, it selects tokens with a reasonable spatial distribution as representative tokens. The introduction of these selection algorithms makes the aggregation process more accurate and efficient, ensuring the quality and accuracy of the aggregation results.

[0194] In one possible implementation, each of the M first video frames can be fused into the feature representation of the most similar second video frame among the N second video frames.

[0195] The inter-frame compression module reduces the number of feature representations the model needs to process by aggregating the feature representations of similar video frames. By aggregating similar video frames, this embodiment ensures that important temporal information in the video is fully preserved. Therefore, the method of this embodiment improves computational efficiency while still guaranteeing the quality and effect of video encoding.

[0196] In the time dimension, embodiments of this application can integrate multiple similar video frames into a single frame for processing. To this end, a pseudo-token (proxy token) called a frame token can be defined to represent a frame. Optionally, the frame token can be obtained by performing mean pooling on the features of all patches within the frame. The similarity (e.g., cosine similarity) between frame tokens is calculated to determine which frames to aggregate. When two frames are aggregated, their corresponding patches will be aggregated one by one; that is, the L patches in the first frame... L patches in the second frame They will be aggregated separately to obtain L aggregated patches. Among them, optional, Through the and The feature representation is obtained by average pooling.

[0197] like Figure 7On the left, the initial input video contains 96 frames. Each layer reduces the number of frames by 8 through aggregation, reducing it to 52 frames by the 6th layer and to 8 frames by the 12th layer.

[0198] Taking each video frame's feature representation as a token as an example, given L tokens, this embodiment reduces R tokens by aggregating them each time. Therefore, the basic strategy of the aggregation algorithm is: first select R tokens, and then merge them into the remaining L / LR tokens based on similarity. The algorithm's process may include:

[0199] Divide the tokens in the input sequence into two parts, denoted as Set A and Set B. For each token in Set A, find the token in Set B that is most similar to it and connect them with an edge. The similarity is calculated as follows: for two tokens x... i and x j The features K of their attention keys are obtained respectively. i and K j Then, cosine similarity is used to calculate norm(K). i norm(K) j The R edges with the highest similarity are retained, and the tokens at both ends of each edge are aggregated. The aggregation method is mean pooling of the features of the tokens at both ends. The remaining tokens from the two sets are concatenated into a single sequence, which is then used as the output sequence.

[0200] Reference Figure 8 , Figure 8 This is a schematic diagram of a fusion process, which may include 8 tokens, each token corresponding to a video frame, dividing adjacent frames into different sets (e.g., Figure 8 Tokens 1, 3, 5, and 7 are assigned to set A, and tokens 2, 4, 6, and 8 are assigned to set B. Based on similarity calculation, tokens 1 and 2, 3 and 6, 7 and 8 are the most similar. Therefore, tokens 1 and 3 can be merged into token 2 to obtain token 123, and token 5 can be merged into token 6 to obtain token 56.

[0201] The above describes the inter-frame fusion process; the next step is to describe the intra-frame fusion process.

[0202] The encoder may include multiple network layers, each of which can receive the feature representation output by the adjacent previous network layer and extract features from the feature representation output by the adjacent previous network layer.

[0203] In one possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the plurality of video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse the feature representations of the X first image blocks into the feature representations of the Y second image blocks to obtain Y feature representations.

[0204] The feature representation can be represented as a token. That is, the intra-frame compression module is used to convert the X tokens corresponding to the X first image blocks (each first image block corresponds to one token) to the Y tokens corresponding to the Y second image blocks to obtain Y tokens.

[0205] For example, you can refer to Figure 6 , Figure 6 The video encoder block can be the second network layer. The spatial aggregation in the video encoder block is an intra-frame compression module. The input of the spatial aggregation is a feature of size (T-Rt)*L*D, where T-Rt is the number of video frames, L is the number of image blocks included in the video frame, and D is the dimension of the feature representation of each image block. Since the spatial aggregation fuses the feature representations of Rs image blocks in each video frame into the feature representations of (L-Rs) video frames, a feature representation of size (T-Rt)*(L-Rs)*D can be obtained.

[0206] The following section describes how to determine the image patches whose feature representations need to be fused into other image patches:

[0207] In one possible implementation, the X first image blocks are the X image blocks among the plurality of image blocks that have the lowest correlation with other image blocks.

[0208] In this approach, the least important X first image blocks among multiple image blocks can be assigned to Set A, and the remaining Y second image blocks can be assigned to Set B. The feature representations of the least important X first image blocks can be fused into the feature representations of the Y second image blocks, which can reduce the information loss during fusion.

[0209] For the selection of objects to be fused (e.g., X first image blocks), this application proposes a selection algorithm based on the importance of visual tokens. By evaluating and ranking the importance of each token, tokens with higher importance are selected as representative tokens.

[0210] In one possible implementation, an image patch with lower correlation to other image patches can be considered a less important image patch.

[0211] Alternatively, the importance of an image patch can be calculated using the following method:

[0212]

[0213] Among them, A ji From tokeY x j (that is, the feature representation of the j-th image patch) to tokeY x i The attention score (which represents the feature representation of the i-th image patch) indicates the correlation between image patches. Q and K denote the Query and Key in the attention mechanism.

[0214] In one possible implementation, the first image block and the second image block are interleaved among the plurality of image blocks.

[0215] Adjacent image patches often have higher similarity and should be grouped into different sets to encourage their fusion. Therefore, adjacent first and second image patches can be grouped into different sets; for example, odd-numbered first image patches can be assigned to Set A, and even-numbered second image patches to Set B. The feature representations of the first image patches in Set A are then fused to the feature representations of the second image patches in Set B.

[0216] This application proposes a selection algorithm based on visual token geometric information. By considering the position and distribution of tokens in space, it selects tokens with a reasonable spatial distribution as representative tokens. The introduction of these selection algorithms makes the aggregation process more accurate and efficient, ensuring the quality and accuracy of the aggregation results.

[0217] In one possible implementation, the feature representation of each of the X first image blocks can be fused to the feature representation of the most similar second image block among the Y second image blocks.

[0218] In this embodiment of the application, semantically similar patches within each frame can be integrated into a single patch for processing. For example... Figure 7On the right, the initial video contains 196 patches per frame. Each layer reduces the number of patches by 16 through aggregation, decreasing to 101 patches by the 6th layer and to 11 patches by the 12th layer.

[0219] The intra-frame compression module automatically aggregates similar patches within each frame, merging them into a larger patch, thereby further reducing the number of visual tokens. This aggregation of similar patches within each frame also ensures that important visual features and details are not lost. Therefore, the method in this embodiment improves computational efficiency while still guaranteeing the quality and effect of video encoding.

[0220] Next Figure 6 An example is given to illustrate a specific implementation of an embodiment of this application:

[0221] Reference Figure 6 The video encoder is a Video Transformer. In this embodiment, a temporal aggregation module and a spatial aggregation module are introduced in each layer of the video encoder. The temporal aggregation module reduces RT frames in each aggregation, and the spatial aggregation module reduces RS patches in each aggregation. RT and RS are hyperparameters used to control the final speedup ratio. This layer-by-layer reduction of the video feature size lowers the computational overhead of subsequent layers. For example, for the Video Transformer in the figure, the input of its i-th layer is a video feature of size Ti*Li*D, where Ti is the number of frames, Li is the number of patches per frame, and D is the feature dimension of the token. After passing through the temporal aggregation module, RT frames can be reduced through frame aggregation, reducing the size of the video feature to (Ti-RT)*Li*D. After passing through the spatial aggregation module, RS patches can be reduced through patch aggregation within each frame, reducing the size of the video feature to (Ti-RT)*(Li-RS)*D. After passing through the M layer of the Video Transformer, the number of visual tokens will be reduced from T*L to (TM*RT)*(LM*RS). By setting appropriate hyperparameters RT and RS, a total reduction of 75% in visual tokens can be achieved, speeding up video encoding by 1.7 times.

[0222] During inference, the method provided in this application can perform aggregation and reduction layer by layer and quantitatively based on the number of frames and the number of patches per frame of the input video. Specifically, during the aggregation process at each layer, the number of visual tokens reduced by aggregation can be controlled according to the set hyperparameters. In this way, as the network progresses layer by layer, the number of visual tokens in the input sequence will gradually decrease, thereby realizing the aggregation and reduction operations in the video encoding process.

[0223] 503. Based on the encoding results, perform video-related tasks to obtain processing results.

[0224] In one possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0225] Based on the spatiotemporal aggregation algorithm of this visual token, refer to Figure 9A , Figure 9A A video-language pre-trained model is shown, consisting of one video encoder, one text encoder, one cross-modal encoder, and one text decoder. All three encoders and one decoder utilize the Transformer architecture.

[0226] The beneficial effects of the embodiments of this application will be described below with reference to experiments:

[0227] Figure 9B The left side shows the impact of reducing the number of frames on GFlops and Recall. It can be seen that reducing the number of frames by 5 per layer can lower GFlops by 800 with almost no performance loss.

[0228] Figure 9B The middle section demonstrates the impact of reducing the number of patches on GFlops and Recall. It shows that reducing the number of frames per layer by 10 can reduce GFlops by 800 with almost no performance loss.

[0229] Figure 9B The right side shows the relationship between reducing frame rate, patch count, and GFlops / Recall.

[0230] Table 1

[0231]

[0232] Referring to Table 1, the embodiment of this application (TESTA) achieves state-of-the-art results in Paragraph-to-Video Retrieval. Task description: Given a text query, find the top K videos in the video database that are semantically closest to it. Target datasets are: QuerYD and CondenseMovie; the automatic evaluation metric is: Recall@K.

[0233] As shown in Table 1, for 32-frame video input, TESTA achieved R@1 scores of 77.0 and 21.5 respectively, surpassing SOTA 7.3 and 3.1. Meanwhile, TESTA's computational overhead (GFLOPs) was only 420, significantly lower than Frozen and VINDLU. Using 96-frame video input, TESTA further improved R@1 to 83.4 and 24.9, demonstrating its excellent scalability.

[0234] Table 2

[0235]

[0236] As shown in Table 2, the results on the target datasets, DiDeMo and ActivityNet Caption, are similar to those described above. For a 32-frame video input, TESTA achieved an R@1 of 56.6 on DiDeMo with only 5M pre-trained data, surpassing methods using over 100M pre-trained data. With a 96-frame video input, TESTA improved the R@1 to 59.2 and 53.7, surpassing state-of-the-art (SOTA) scores of 2.7 and 2.6.

[0237] Table 3

[0238]

[0239] As shown in Table 3, the embodiments of this application achieved state-of-the-art results on Long-form VideoQA. Target dataset: ActivityNet-QA; Automatic evaluation metric: Accuracy. Conclusion: TESTA achieved an accuracy of 45.0%, which is 3.2% higher than the state-of-the-art (SOTA).

[0240] Table 4

[0241]

[0242] As shown in Table 4, the aggregation algorithm based on bipartite graph matching outperforms the pruning algorithm. Furthermore, geometry-based aggregation exhibits the best performance.

[0243] Reference Figure 10 , Figure 10 This is a schematic diagram of the structure of a data processing apparatus provided in an embodiment of this application, such as... Figure 10 As shown in the embodiment of this application, a data processing apparatus 1000 is provided, the apparatus comprising:

[0244] Acquisition module 1001 is used to acquire multiple video frames;

[0245] For a detailed description of the acquisition module 1001, please refer to the description of step 501 in the above embodiment, which will not be repeated here.

[0246] The processing module 1002 is used to process the plurality of video frames through an encoder to obtain an encoding result; wherein, the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the plurality of video frames include M first video frames and N second video frames, and the inter-frame compression module is used to fuse the feature representations of the M first video frames into the feature representations of the N second video frames to obtain N feature representations;

[0247] Based on the encoding results, video-related tasks are performed to obtain the processing results.

[0248] For a detailed description of the processing module 1002, please refer to the description of steps 502 to 503 in the above embodiments, which will not be repeated here.

[0249] In one possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0250] In one possible implementation, the processing module 1002 is specifically used for:

[0251] The feature representations of each of the M first video frames are fused into the feature representation of the second video frame that is most similar to the N second video frames.

[0252] In one possible implementation, the M first video frames are the M video frames among the plurality of video frames that have the lowest correlation with the other video frames.

[0253] In one possible implementation, the first video frame and the second video frame are interleaved among the plurality of video frames.

[0254] In one possible implementation, the fusion is average pooling.

[0255] In one possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the plurality of video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse the feature representations of the X first image blocks into the feature representations of the Y second image blocks to obtain Y feature representations.

[0256] In one possible implementation, the processing module 1002 is specifically used for:

[0257] The feature representations of each of the X first image blocks are fused into the feature representation of the second image block that is most similar to the Y second image blocks.

[0258] In one possible implementation, the X first image blocks are the X image blocks with the lowest correlation to other image blocks among the multiple image blocks included in the third video frame.

[0259] In one possible implementation, the first image block and the second image block are interleaved in the third video frame.

[0260] In one possible implementation, the task network is used to perform at least one of the following tasks: video retrieval task, video classification task, video localization task, and video generation task (such as video question answering and video title generation).

[0261] The following describes an execution device provided in an embodiment of this application. Please refer to [link / reference]. Figure 11 , Figure 11 This is a schematic diagram of an execution device provided in an embodiment of this application. The execution device 1100 can specifically be a virtual reality (VR) device, a mobile phone, a tablet, a laptop, a smart wearable device, a monitoring data processing device, or a server, etc., and is not limited thereto. Specifically, the execution device 1100 includes: a receiver 1101, a transmitter 1102, a processor 1103, and a memory 1104 (wherein the execution device 1100 may have one or more processors 1103). Figure 11 (Taking a processor as an example), processor 1103 may include application processor 11031 and communication processor 11032. In some embodiments of this application, receiver 1101, transmitter 1102, processor 1103 and memory 1104 may be connected via bus or other means.

[0262] Memory 1104 may include read-only memory and random access memory, and provides instructions and data to processor 1103. A portion of memory 1104 may also include non-volatile random access memory (NVRAM). Memory 1104 stores processor and operation instructions, executable modules, or data structures, or subsets thereof, or extended sets thereof, wherein the operation instructions may include various operation instructions for implementing various operations.

[0263] Processor 1103 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together through a bus system, which may include not only the data bus, but also power buses, control buses, and status signal buses. However, for clarity, all buses are referred to as the bus system in the diagram.

[0264] The methods disclosed in the embodiments of this application can be applied to or implemented by the processor 1103. The processor 1103 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 1103 or by instructions in software form. The processor 1103 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and may further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor 1103 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can reside in a mature storage medium in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 1104. Processor 1103 reads the information from memory 1104 and, in conjunction with its hardware, completes the steps involved in the model inference process described above.

[0265] Receiver 1101 can be used to receive input digital or character information, and to generate signal inputs related to the settings and function control of the execution device. Transmitter 1102 can be used to output digital or character information through the first interface; transmitter 1102 can also be used to send instructions to the disk group through the first interface to modify the data in the disk group; transmitter 1102 may also include a display device such as a display screen.

[0266] This application also provides a training device; please refer to [link / reference]. Figure 12 , Figure 12 This is a schematic diagram of a training device provided in an embodiment of this application. Specifically, the training device 1200 is implemented by one or more servers. The training device 1200 can vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 1212 (e.g., one or more processors) and memory 1232, and one or more storage media 1230 (e.g., one or more mass storage devices) for storing application programs 1242 or data 1244. The memory 1232 and storage media 1230 can be temporary or persistent storage. The program stored in the storage media 1230 may include one or more modules (not shown in the diagram), each module may include a series of instruction operations on the training device. Furthermore, the CPU 1212 may be configured to communicate with the storage media 1230 and execute the series of instruction operations in the storage media 1230 on the training device 1200.

[0267] The training device 1200 may also include one or more power supplies 1226, one or more wired or wireless network interfaces 1250, one or more input / output interfaces 1258; or, one or more operating systems 1241, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0268] In this embodiment, the central processing unit 1212 is used to perform actions related to model training in the above embodiments.

[0269] This application also provides a computer program product that, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0270] This application also provides a computer-readable storage medium storing a program for signal processing, which, when run on a computer, causes the computer to perform steps as performed by the aforementioned execution device, or causes the computer to perform steps as performed by the aforementioned training device.

[0271] The execution device, training device, or terminal device provided in this application embodiment can specifically be a chip. The chip includes a processing unit and a communication unit. The processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, pins, or circuits. The processing unit can execute computer execution instructions stored in the storage unit to cause the chip within the execution device to execute the data processing method described in the above embodiments, or to cause the chip within the training device to execute the data processing method described in the above embodiments. Optionally, the storage unit can be a storage unit within the chip, such as a register or cache. Alternatively, the storage unit can be a storage unit located outside the chip within the wireless access device, such as a read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0272] For details, please refer to Figure 13 , Figure 13 This is a schematic diagram of a chip provided in an embodiment of this application. The chip can be represented as a neural network processor (NPU) 1300. The NPU 1300 is mounted as a coprocessor on the host CPU, and tasks are assigned by the host CPU. The core part of the NPU is the arithmetic circuit 1303, which is controlled by the controller 1304 to extract matrix data from the memory and perform multiplication operations.

[0273] In some implementations, the arithmetic circuit 1303 internally includes multiple processing engines (PEs). In some implementations, the arithmetic circuit 1303 is a two-dimensional pulsating array. The arithmetic circuit 1303 can also be a one-dimensional pulsating array or other electronic circuits capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 1303 is a general-purpose matrix processor.

[0274] For example, suppose we have an input matrix A, a weight matrix B, and an output matrix C. The arithmetic circuit retrieves the corresponding data of matrix B from the weight memory 1302 and caches it in each PE of the arithmetic circuit. The arithmetic circuit retrieves the data of matrix A from the input memory 1301 and performs matrix operations with matrix B. The partial result or the final result of the obtained matrix is ​​stored in the accumulator 1308.

[0275] Unified memory 1306 is used to store input and output data. Weight data is directly transferred to weight memory 1302 via Direct Memory Access Controller (DMAC) 1305. Input data is also transferred to unified memory 1306 via DMAC.

[0276] BIU stands for Bus Interface Unit, which is used for interaction between the AXI bus and the DMAC and the Instruction Fetch Buffer (IFB) 1309.

[0277] The Bus Interface Unit (BIU) 1310 is used by the instruction fetch memory 1309 to fetch instructions from external memory, and also by the memory access controller 1305 to fetch the original data of the input matrix A or the weight matrix B from external memory.

[0278] The DMAC is mainly used to move input data from external memory DDR to unified memory 1306, or to weight data to weight memory 1302, or to input data to input memory 1301.

[0279] The vector computation unit 1307 includes multiple processing units that further process the output of the computation circuit 1303 when needed, such as vector multiplication, vector addition, exponential operations, logarithmic operations, size comparisons, etc. It is mainly used for computation in non-convolutional / fully connected layers of neural networks, such as Batch Normalization, pixel-level summation, and upsampling of feature planes.

[0280] In some implementations, the vector computation unit 1307 can store the processed output vector in the unified memory 1306. For example, the vector computation unit 1307 can apply a linear function, or a nonlinear function, to the output of the computation circuit 1303, such as performing linear interpolation on the feature planes extracted by the convolutional layer, or, for example, accumulating a vector of values ​​to generate activation values. In some implementations, the vector computation unit 1307 generates normalized values, pixel-level summed values, or both. In some implementations, the processed output vector can be used as an activation input to the computation circuit 1303, for example, for use in subsequent layers of the neural network.

[0281] The instruction fetch buffer 1309 connected to the controller 1304 is used to store the instructions used by the controller 1304;

[0282] Unified memory 1306, input memory 1301, weighted memory 1302, and instruction fetch memory 1309 are all on-chip memories. External memory is proprietary to this NPU hardware architecture.

[0283] The processor mentioned above can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits used to control the execution of the above program.

[0284] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.

[0285] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0286] In the above embodiments, the implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, in the form of a computer program product.

[0287] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).

Claims

1. A method of video coding, the method comprising: The method comprises: obtaining a plurality of video frames; processing the plurality of video frames by an encoder to obtain an encoding result; wherein the encoder comprises a first network layer; the first network layer comprises an inter-frame compression module; the plurality of video frames comprise M first video frames and N second video frames; the inter-frame compression module is configured to fuse feature representations of the M first video frames into feature representations of the N second video frames to obtain N feature representations; performing a video-related task according to the encoding result to obtain a processing result.

2. The method of claim 1, wherein, The video-related task is video retrieval, video question answering, or video description generation.

3. The method according to claim 1 or 2, characterized in that, The fusing of the feature representations of the M first video frames into the feature representations of the N second video frames comprises: fusing the feature representation of each of the M first video frames into the feature representation of the most similar second video frame among the N second video frames.

4. The method according to claim 1 or 2, characterized in that, The M first video frames are M video frames with the lowest relevance to other video frames among the plurality of video frames.

5. The method according to claim 1 or 2, characterized in that, The first video frames and the second video frames are interleaved with each other in the plurality of video frames.

6. The method of claim 1 or 2, wherein, The fusing is average pooling.

7. The method according to claim 1 or 2, characterized in that, The encoder comprises a second network layer; the first network layer and the second network layer are the same or different network layers; the second network layer comprises an intra-frame compression module; the plurality of video frames comprise a third video frame; the third video frame comprises X first image blocks and Y second image blocks; the intra-frame compression module is configured to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

8. The method of claim 7, wherein, The fusing of the feature representations of the X first image blocks into the feature representations of the Y second image blocks comprises: fusing the feature representation of each of the X first image blocks into the feature representation of the most similar second image block among the Y second image blocks.

9. The method of claim 7, wherein, The X first image blocks are X image blocks with the lowest relevance to other image blocks among a plurality of image blocks included in the third video frame.

10. The method of claim 7, wherein, The first image blocks and the second image blocks are interleaved with each other in the third video frame.

11. A video encoding apparatus, comprising: The apparatus comprises: an obtaining module configured to obtain a plurality of video frames; a processing module configured to process the plurality of video frames by an encoder to obtain an encoding result; wherein the encoder comprises a first network layer; the first network layer comprises an inter-frame compression module; the plurality of video frames comprise M first video frames and N second video frames; the inter-frame compression module is configured to fuse feature representations of the M first video frames into feature representations of the N second video frames to obtain N feature representations; performing a video-related task according to the encoding result to obtain a processing result.

12. The apparatus of claim 11, wherein, The video-related task is video retrieval, video question answering, or video description generation.

13. The apparatus of claim 11 or 12, wherein, The processing module is specifically configured to: fuse the feature representation of each of the M first video frames into the feature representation of the most similar second video frame among the N second video frames.

14. The apparatus of claim 11 or 12, wherein, The M first video frames are M video frames with the lowest relevance to other video frames among the plurality of video frames.

15. The apparatus of claim 11 or 12, wherein, The first video frame and the second video frame are interleaved with each other in the plurality of video frames.

16. The apparatus of claim 11 or 12, wherein, The fusion is average pooling.

17. The apparatus of claim 11 or 12, wherein, The encoder comprises a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer comprises an intra-frame compression module, the plurality of video frames comprises a third video frame, the third video frame comprises X first image blocks and Y second image blocks, and the intra-frame compression module is configured to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

18. The apparatus of claim 17, wherein, The processing module is further configured to: fuse the feature representation of each first image block in the X first image blocks into the feature representation of the most similar second image block in the Y second image blocks.

19. The apparatus of claim 17, wherein, The X first image blocks are X image blocks with the lowest correlation to other image blocks in a plurality of image blocks included in the third video frame.

20. The apparatus of claim 17, wherein, The first image block and the second image block are interleaved with each other in the third video frame.

21. A computer storage medium, comprising, The computer storage medium stores one or more instructions, which, when executed by one or more computers, cause the one or more computers to perform the operations of the method of any one of claims 1 to 10.

22. A computer program product, characterised in that, The computer storage medium stores one or more instructions, which, when executed by one or more computers, cause the one or more computers to perform the operations of the method of any one of claims 1 to 10.

23. A video encoding system comprising at least one processor and at least one memory; the processor, the memory are connected through a communication bus and complete the communication between each other; The at least one memory is configured to store code; The at least one processor is configured to execute the code to perform the method of any one of claims 1 to 10.

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