Power-on and power-off sonic boom reduction in audio systems

Abstract

An apparatus comprising: a first power stage (PS1) having a first power stage input (output of 308) and a first power stage output (voltage VN at the PS1 output); a second power stage having a second power stage input and a second power stage output; and a first driver circuit (408) having a first driver input (having audio signals VINM and VINP) and a first driver output (output of 408), the first driver output coupled to the first power stage input (output of 308). The control circuit (310) is configured to set the first power stage output (VN) in response to the first driver input being in an inactive state (VINM and VINP being inactive). The apparatus also includes a second driver circuit having a second driver input and a second driver output, the second driver output coupled to the second power stage input, and the second driver input coupled to the first power stage output, and the second driver circuit is configured to set the second power stage output to track the first power stage output.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to U.S. patent application No. 17 / 402,264, filed on August 13, 2021, entitled “Method and Apparatus for Generating an Output Audio Modulation Protocol,” U.S. patent application No. 17 / 491,133, filed on September 30, 2021, entitled “Switching Amplifier with Linear Transition Totem Pole Modulation,” and U.S. patent application No. 18 / 362,265, filed on July 31, 2023, entitled “Reduction of Power-On Pops in Audio Systems,” the entire contents of which are incorporated herein by reference. Background Art

[0002] Various audio systems may include an audio amplifier and a speaker. The audio amplifier may receive an audio signal representing a sound from an audio source, amplify and / or process the audio signal, and provide the amplified / processed audio signal at two electrical terminals of the speaker. The amplified / processed electrical signal may set a voltage difference between the two electrical terminals of the speaker, and the speaker may generate the sound represented in these signals based on the voltage difference. In some cases, the audio amplifier may transmit a transient signal that is not from the audio source to the speaker. For example, such a transient signal may occur when the audio amplifier is powered on (e.g., from a cold start or after a system reset) or powered off. Such a transient signal may be within an audible frequency band. The transient signal may introduce a transient voltage difference between the two electrical terminals of the speaker, which may produce an audible pop in response to the transient signal. Such a pop is unwelcome. Summary of the invention

[0003] In one example, a device includes: a first power stage having a first power stage input and a first power stage output; and a second power stage having a second power stage input and a second power stage output. The device also includes: a first driver circuit having a first driver input and a first driver output, the first driver output coupled to the first power stage input; a control circuit configured to set the first power stage output in response to the first driver input being in an inactive state; and a second driver circuit having a second driver input and a second driver output, the second driver output coupled to the second power stage input, and the second driver input coupled to the first power stage output. In one example, the second driver circuit is configured to set the second power stage output to track the first power stage output.

[0004] In another example, a device includes: a first power stage having a first power input coupled to a power terminal, a first power stage input, and a first power stage output; and a second power stage having a second power input coupled to the power terminal, a second power stage input, and a second power stage output. The device also includes: a first driver circuit having a first driver input and a first driver output, the first driver output coupled to the first power stage input; a second driver circuit having a second driver input and a second driver output, the second driver output coupled to the second power stage input, and the second driver input coupled to the first power stage output, and the second driver circuit is configured to set the second power stage output to track the first power stage output; and a control circuit configured to set a DC voltage of the first power stage output based on a second voltage at the power terminal.

[0005] In yet another example, a device includes: a first power stage having a power terminal, a first power stage input, and a first power stage output; and a second power stage having a power terminal, a second power stage input, and a second power stage output. In one example, the device also includes: a first driver circuit having a first driver input and a first driver output, the first driver output coupled to the first power stage input. In one example, the device also includes: a second driver circuit having a second driver input and a second driver output, the second driver output coupled to the second power stage input, and the second driver input coupled to the first power stage output, and the second driver circuit is configured to set a state of the second power stage output to track a state of the first power stage output. In one example, the device also includes: a control circuit coupled to the first power stage output terminal and configured to: at a first time, start setting the first power stage output terminal to a first voltage and disable the second driver circuit to set the second power stage output terminal, wherein the first voltage increases from a first voltage level to a second voltage level over time; and at a second time after the first time, when the first voltage is provided, enable the second driver circuit to set the second power stage output terminal.

[0006] In another example, a method includes providing a first voltage signal at a first power stage output terminal of a first power stage during a first time interval when an input terminal of a first driver circuit is inactive, wherein the first voltage signal increases from a first voltage level to a second voltage level over time. The method also includes enabling a second driver circuit to drive a second power stage to provide a second voltage signal at a second power stage output terminal that tracks the first voltage signal; and providing a third voltage signal having a second voltage level as a DC bias signal at the first power stage output terminal during a second time interval after the first time interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A and Figure 1B is a schematic diagram illustrating an example of an audio system.

[0008] Figure 2 , Figure 3 , Figure 4 and Figure 5 It is a graphic Figure 1A and Figure 1B Schematic diagram of an additional example of an audio system.

[0009] Figure 6 and Figure 7 Picture shows Figure 1A and Figure 1B A timing diagram of an example operation of an audio system.

[0010] Figure 8 and Fig. 9 It is a graphic Figure 1A and Figure 1B Schematic diagram of the auxiliary circuit of the audio system.

[0011] Fig.10 It is a graphic Figure 1A and Figure 1B Schematic diagram of the blocking logic of the audio system.

[0012] Fig.11 and Fig.12 Picture shows Figure 1A and Figure 1B A timing diagram of an example operation of an audio system.

[0013] Fig.13A , 13B and 13C diagram Figure 1A-10 An example control signal generating circuit for an audio system of the present invention is provided.

[0014] Fig.14 is a flow chart showing an example of a method of operating a speaker. DETAILED DESCRIPTION

[0015] The techniques described herein are used to eliminate or reduce popping sounds that sometimes occur during startup or shutdown of an audio system, or during changes in the voltage level of a power supply voltage. In one example, a device includes: a first power stage circuit having a first output and coupled to a power terminal; and a second power stage circuit having a second output and coupled to the power terminal. The first output and the second output are coupled to a first speaker terminal and a second speaker terminal, respectively. In some cases, such coupling can be achieved, for example, by an inductor-capacitor (LC) low-pass filter circuit. The device also includes a first modulator circuit driving the first power stage and a second modulator circuit driving the second power stage. In some examples, and under certain operating conditions, such as during startup and shutdown, the first modulator circuit can operate as a master modulator circuit, and the second stage can operate as a slave modulator circuit, so that the second voltage at the second speaker terminal tracks the first voltage at the first speaker terminal. The device can be, for example, a component of an audio amplifier system, such as those included in a desktop computer, a laptop computer, a mobile computer (e.g., a smartphone), a game console, or any other electronic device or system that includes a speaker driven by an audio amplifier.

[0016] In some examples, switching amplifiers are used to output audio in various electronic devices, including mobile phones, televisions, hearing aids, home theater systems, vehicle audio systems, instrument amplifiers, radio frequency amplifiers, subwoofers, etc. A switching amplifier includes a power stage that generates a multi-level signal (e.g., a binary signal, a three-level signal, etc.) by selectively connecting the power stage output to one of a plurality of voltage sources. In some examples, the switching amplifier can be operated as a class D amplifier. The switching amplifier can be driven by a modulation circuit that receives a sinusoidal audio signal and generates a pulse width modulation (PWM) signal, a pulse density signal, and / or any other type of modulation control signal to control the power stage to also generate a modulation signal with discrete signal levels (e.g., binary, ternary, etc.). The modulation signal provided by the power stage can have timing properties, such as duty cycle, pulse width, etc., that are modulated / changed to reflect the instantaneous amplitude of the audio signal. The modulation signal generated by the power stage can be filtered (e.g., by a low-pass filter, or by an inductor of a speaker) to generate an amplified version of the sinusoidal audio signal, and the amplified sinusoidal audio signal can be fed to the speaker. The low pass filter may include an LC filter including a series inductor coupled between the output of the switching amplifier and the speaker, and a shunt inductor coupled between the speaker and ground. In some examples, the audio amplifier may include two switching amplifiers as two power stages to provide two modulation signals with opposite polarities at two terminals of the speaker, and an LC filter coupled between the output of each power stage and a corresponding terminal of the speaker. The switching amplifier may improve the power efficiency of driving the speaker, but having two LC filters (especially the inductors) may significantly increase the footprint of the audio system.

[0017] In some examples, the audio system may also include a non-switching amplifier. The non-switching amplifier may include another power stage driven by a control circuit including a linear amplifier. The control circuit may receive a sinusoidal audio signal and provide a control signal having an amplitude that varies (e.g., linearly or nearly linearly) according to the instantaneous amplitude of the audio signal to the non-switching amplifier. In response to the control signal, the non-switching amplifier may also generate an analog signal having an amplitude that continuously tracks the audio signal. In some examples, the non-switching amplifier may operate as a class A amplifier, a class AB amplifier, etc. The output of the non-switching amplifier may also be filtered (e.g., by another low-pass filter) to remove high-frequency components (e.g., noise). However, because the signal at the output of the non-switching amplifier is in analog and continuous form, the low-pass filter may have fewer elements. For example, instead of an LC filter, the audio system may include a capacitor at the output of the non-switching amplifier to perform filtering. In some examples, the audio system may include two non-switching amplifiers as two power stages to provide analog signals with opposite polarities at two terminals of a speaker, and capacitors coupled to each power stage output (and the corresponding terminals of the speaker) to perform filtering. The absence of an inductor reduces the footprint of the filter and audio system, but the power efficiency of a non-switching amplifier can be much worse than that of a switching amplifier.

[0018] In some examples, the audio system may further include a switching amplifier driving a first terminal of the speaker and a non-switching amplifier driving a second terminal of the speaker. The audio system may include an LC filter having an inductor connected in series with the switch output and the first speaker terminal, and a capacitor connected in parallel between the first and second terminals of the speaker. With this type of arrangement, the total number of inductors included in the low pass filter may be halved compared to a case where the audio system includes two switching amplifiers. Power efficiency may also be improved compared to a case where the audio system includes two non-switching amplifiers.

[0019] In all of these audio system examples, there may be asymmetry in the power stage driving the speaker (e.g., relatively small asymmetry despite having two switched outputs). The asymmetry may be due to random mismatches between two amplifiers of the same type (e.g., between two switched or non-switched amplifiers), and / or may be due to system mismatches (e.g., linearity and bandwidth differences between switched and non-switched amplifiers, asymmetry between output filters, etc.), and / or may be due to random mismatches between passive components such as capacitors and / or inductors. Due to the asymmetry, the power stage may introduce a time-varying / transient voltage difference at the speaker terminals during startup or reset of the audio system when the power supply voltage of the power stage is ramping up and an audio signal has not yet been provided to the amplifier. Additionally or alternatively, the power stage may also introduce a time-varying / transient voltage difference at the speaker terminals during shutdown of the audio system when the power supply voltage of the power stage is ramping down and an audio signal has not yet been provided to the amplifier, and / or when there is a change in the level of the power supply voltage. If the time-varying voltage difference has a frequency within the human audio band, the speaker may generate an audible pop, which is undesirable. Examples disclosed herein provide techniques for avoiding such pop noises during the startup or reset process.

[0020] Figure 1AAn example audio system 100 is illustrated. As shown, system 100 includes a first amplifier (labeled amplifier A) and a second amplifier (labeled amplifier B) driving a speaker 102. Amplifier A may be coupled to a terminal 104 of speaker 102, and amplifier B may be coupled to a terminal 106 of speaker 102. Amplifiers A and B may be different types with different control schemes (e.g., one is a switching amplifier and the other is a non-switching amplifier), the same type with the same control scheme, or have different linearity and / or bandwidth. Due to the asymmetry between the amplifiers A and B (e.g., random device mismatch or system mismatch, and different types with different control schemes), the amplifiers may introduce a time-varying / transient voltage difference between the terminals 104 and 106, for example, during startup or initialization of the system 100 (e.g., when the power supply voltage PVDD is rising (or ramping up / ramping up) and / or no audio signal is provided to the amplifiers A and B), during shutdown of the system 100 (e.g., when the power supply voltage PVDD is falling (or ramping down / ramping down) and / or no audio signal is provided to the amplifiers A and B), and / or during a voltage level change of the power supply voltage PVDD (e.g., when the mode of the audio system changes, during a class H operating mode, etc., causing a change in the voltage level of the power supply voltage PVDD). Such a time-varying / transient voltage difference between the terminals 104 and 106 (e.g., during startup, shutdown, and / or PVDD voltage level change) may cause the output of the speaker 102 to produce popping sounds. Later, as terminals 104 and 106 reach a steady-state value (eg, become fully charged or reach zero volts), the popping sound may end.

[0021] Specifically, during startup or reset of system 100, the power supply voltage PVDD of amplifiers A and B may rise (e.g., as part of a power sequencing operation) and no audio signals may be provided to amplifiers A and B. During this period, the VN and VP voltages may track each other such that the voltage difference is zero, or is at a DC (direct current) value, or varies over time but has a very low value (e.g., <10 mV) to avoid (or reduce) the possibility of audible pop noise being generated by the speaker. However, since there is no audio signal, transient noise signals may be coupled to the output terminals of amplifiers A and B. In addition, due to the asymmetry described above, when the power supply voltage PVDD rises (e.g., during a startup or reset process), the VN and VP voltages may rise differently. All of this may cause amplifiers A and B to generate a transient voltage difference, which may cause a transient difference between the VN voltage and the VP voltage, causing a pop noise to be generated by speaker 102.

[0022] Similar phenomena may also be observed during shutdown of the system 100 (e.g., a transient voltage difference is generated between the VN voltage and the VP voltage). For example, during shutdown of the system 100, no audio signals are provided to amplifiers A and B. The power supply voltage PVDD of amplifiers A and B may also be ramped down (e.g., as part of a power-off sequence operation). During this period, the VN and VP voltages may track each other, such that the voltage difference may be zero, or a DC value, or vary over time but have a very low value (e.g., <10 mV) with no audible content in the frequency spectrum. Such an arrangement may avoid (or reduce) the generation of audible popping noise by the speaker. However, due to the aforementioned asymmetry and the fact that the amplifiers are not driven by an audio signal, transient noise signals may be coupled into the output terminals of amplifiers A and B. In addition, during the ramp-down of PVDD, due to the aforementioned asymmetry, the VP and VN voltages may also be ramped down differently. All of these may result in a transient difference between the VN voltage and the VP voltage, resulting in a popping sound being generated by the speaker 102. Example techniques for mitigating or at least reducing such pops are described in related U.S. application Ser. No. 18 / 362,265, filed on July 31, 2023, and entitled “Power-On Pop Reduction in Audio Systems,” the entire contents of which are incorporated herein by reference as described above.

[0023] Such popping sound may also be produced during a change in the PVDD voltage level (e.g., when the mode of the audio system changes, causing the voltage level of the power supply voltage PVDD to change), thereby causing a corresponding change in the voltage levels of VN and VP. Such changes may also introduce a momentary difference between the VN voltage and the VP voltage, which may cause a popping sound to be heard at the speaker 102.

[0024] The intensity of the pop noise can be based on the instantaneous difference between the VP voltage and the VN voltage. If the difference is relatively large, such as greater than 1mV, 5mV, 10mV, 20mV, or 50mV, the pop noise can be heard. The instantaneous difference between the VP voltage and the VN voltage can cause audible pop noise, and can also be determined by other factors, such as PVDD level, power stage gain, switching frequency, modulator bandwidth, etc.

[0025] Figure 1B Picture shows Figure 1A 100. Figure 1B The system 100 includes a first power stage PS1 having a first output terminal 108 and a second power stage PS2 having a second output terminal 110. The first power stage PS1 may represent Figure 1A The amplifier A (or a component thereof), the second power stage PS2 can be represented by Figure 1BThe first output terminal 108 and the second output terminal 110 are coupled to an LC filter circuit 112. The two speaker terminals 104 and 106 of the LC filter circuit 112 (also refer to Figure 1A Description) is coupled to the speaker 102.

[0026] The power stage PS1 includes a first transistor S1 and a second transistor S2 coupled in series between a power terminal 116a (e.g., receiving power supply PVDD) and a ground terminal. For example, a first current terminal of transistor S1 is coupled to the power terminal 116a, and a second current terminal of transistor S1 is coupled to the output terminal 108. A first current terminal of transistor S2 is coupled to the output terminal 108, and a second current terminal of transistor S2 is coupled to the ground terminal.

[0027] Transistor S1 also includes a control terminal coupled to a first power stage input terminal that receives a control signal CS1 from a driver D1, and transistor S2 includes a control terminal coupled to a second power stage input terminal that receives a control signal CS2 from another driver D2. In response to control signals CS1 and CS2, transistors S1 and S2 can set a voltage VN at an output terminal 108 of power stage PS1. Figure 1B In the embodiment of the present invention, the power stage PS1 can be controlled as a non-switching amplifier (e.g., class AB, class A, etc.), wherein CS1 and CS2 can each have an amplitude that varies according to the instantaneous amplitude of the audio signal. For example, during the first half cycle of the audio signal, transistor S1 is turned on or enabled, transistor S2 is turned off or disabled, and transistor S1 can change the amplitude of voltage VN based on the amplitude of CS1, and the amplitude of CS1 reflects / tracks the instantaneous amplitude of the audio signal during the first half cycle. In addition, during the second half cycle of the audio signal, transistor S1 is turned off or disabled, transistor S2 is turned on or enabled, and transistor S2 can change the amplitude of voltage VN based on the amplitude of CS2, and the amplitude of CS2 also reflects / tracks the instantaneous amplitude of the audio signal during the second half cycle. In the case where the audio signal is a sinusoidal signal, voltage VN can be (or close to) an amplified version of the sinusoidal signal.

[0028] In addition, the power stage PS2 includes a third transistor S3 and a fourth transistor S4 coupled in series between a power terminal 116b (e.g., receiving power supply PVDD) and a ground terminal. In one example, the power terminals 116a and 116b may be the same power terminal shared by the power stages PS1 and PS2 (or the power terminals 116a and 116b may be coupled to a common power terminal), while in another example, the power terminals 116a and 116b may be coupled to different voltage sources.

[0029] As shown, a first current terminal of transistor S3 is coupled to power terminal 116b and a second current terminal of transistor S3 is coupled to output terminal 110 having a VY voltage. A first current terminal of transistor S4 is coupled to output terminal 110 and a second current terminal of transistor S4 is coupled to a ground terminal.

[0030] Transistor S3 also includes a control terminal coupled to a third power stage input terminal, which receives a control signal CS3 from a driver D3, and transistor S4 also includes a control terminal coupled to a fourth power stage input terminal, which receives a control signal CS4 from another driver D4. In response to the control signals CS3 and CS4, transistors S3 and S4 can set a voltage VY at an output terminal 110 of the power stage PS2.

[0031] exist Figure 1B In the embodiment of the present invention, power stage PS2 can be controlled as a switching amplifier (e.g., class D), wherein control signals CS3 and CS4 are pulse width modulation signals, pulse density signals, and / or any other type of modulation control signals with binary amplitude. Depending on the amplitude of the audio signal, one of transistors S3 or S4 can be turned on to connect one of power terminal 116b or ground terminal to output terminal 110. In response to CS3 and CS4, power stage PS2 can also generate a modulation signal. The modulation signal provided by the power stage can have timing attributes, such as duty cycle, pulse width, etc., which are modulated / changed to reflect the instantaneous amplitude of the audio signal. Transistors S3 and S4 can provide VY as a modulation signal at output terminal 110 in response to CS4.

[0032] exist Figure 1B In the embodiment, transistors S1, S2, S3, and S4 are shown as n-channel metal oxide semiconductor (NMOS) field effect transistors (FETs). In other examples, transistors S1, S2, S3, and S4 may be other types of transistors, such as p-channel MOSFET (PMOS), laterally diffused metal oxide semiconductor (LDMOS) FET, gallium nitride (GaN) FET, NPN or PNP bipolar junction transistors (BJT), etc.

[0033] The LC filter circuit 112 includes an inductor L1 coupled between the output terminal 110 and the speaker terminal 106, a capacitor C1 coupled between the speaker terminals 104 and 106, and another capacitor C2 coupled between the speaker terminal 104 and the ground terminal. The inductor L1 and the capacitor C1 filter the modulation signal VY provided at the output terminal 110 into a sinusoidal signal VP at the speaker terminal 106, which is output to the speaker 102 to output the corresponding audio. The capacitor C2 can also filter the signal VN to further suppress nonlinearity in the signal VN.

[0034] System 100 also includes a control circuit ( Figure 1B ), the control circuit generates a control signal that drives the drive circuits D1, D2, D3, and D4, respectively, based on the audio signal. Example operations of the system 100 are described in related U.S. application Ser. No. 17 / 402,264, filed on Aug. 13, 2021, entitled “Method and Apparatus for Generating a Modulation Protocol for Output Audio,” and related U.S. application Ser. No. 17 / 491,133, filed on Sept. 30, 2021, entitled “Switching Amplifier with Linear Switching Totem Pole Modulation,” which, as noted above, are incorporated herein by reference in their entirety.

[0035] Figure 2 An example of internal components of system 100 is illustrated. Figure 2 The system 100 is illustrated as including, in addition to the power stages PS1 and PS2, a control circuit 202 that provides control signals CS1 and CS2 to the power stage PS1, and a control circuit 204 that provides control signals CS3 and CS4 to the power stage PS2. During startup and shutdown, the control circuits 202 and 204 may not both receive the audio signal 206. During normal operation, the control circuits 202 and 204 may receive the audio signal 206.

[0036] exist Figure 2 In an example of, the control circuit 202 may control the power stage PS1 to operate as a non-switching amplifier (e.g., a class AB amplifier). The control circuit 202 may include a linear amplifier to generate control signals CS1 and CS2 by amplifying the audio signal 206 (if present). The power stage PS1 may provide a VN voltage having an amplitude that tracks the audio signal 206 at the first output terminal 108. In addition, the control circuit 204 may control the power stage PS2 to operate as a switching amplifier (e.g., a class D amplifier). The control circuit 204 may include a modulation signal generator to generate control signals CS3 and CS4 as modulation signals. In some examples, the control circuit 204 may include a pulse width modulation (PWM) signal generator to generate control signals CS3 and CS4 as PWM signals, wherein the pulse widths of CS3 and CS4 may be modulated based on the instantaneous amplitude of the audio signal 206. After being filtered by the LC filter circuit 112, VN and VP may have matching amplitudes but opposite polarities and become fully differential signals.

[0037] like Figure 2As shown, in order to further improve the matching between the common mode voltage between VN and VP, PS1 control circuit 202 and PS2 control circuit 204 can operate in a master-slave configuration. In the master-slave configuration, PS1 control circuit 202 and power stage PS1 are master devices, and PS2 control circuit 204 and power stage PS2 are slave devices. Specifically, PS1 control circuit can drive power stage PS1 based on audio signal 206 (if present, and not present when starting and shutting down) or other signals. On the other hand, PS2 control circuit 204 may include subtraction circuit 210 (e.g., amplifier), which receives VN and VP (or a filtered version of VY) as feedback signals, and generates a difference signal 212 representing the difference between VN and VP. PS2 control circuit 204 can adjust control signals CS3 and CS4 (and VY / VP) based on difference signal 212. For example, PS2 control circuit 204 can adjust control signals CS3 and CS4 to minimize (or reduce) difference signal 212, thereby improving the matching between the common mode voltage of VN and VP. PS2 control circuit 204 may have a higher bandwidth than PS1 control circuit 202 , which allows PS2 control circuit 204 to adjust CS3 and CS4 in response to audio signal 206 and difference signal 212 .

[0038] In some examples, as described below, the PS1 control circuit 202 may include a signal generator ( Figure 2 2 (not shown) to reduce the pop noise when the audio signal 206 is not present. As described above, during startup and shutdown of the system 100, the audio signal 206 is not present and is not provided to the PS1 control circuit 202 and the PS2 control circuit 204. In addition, in some examples, the PVDD voltage may also rise during startup and fall (or ramp down) during shutdown. The transient noise signal may be coupled to the first output terminal 108 and the second output terminal 110, which may cause the pop noise. In addition, in response to the transient noise signal, the power stages PS1 and PS2 may provide output voltages VP and VN with different amplitudes and linear characteristics, which may further increase the pop noise.

[0039] When the audio signal 206 is not present, the signal generator may control the power level PS1, or set the voltage VN at the first output terminal 108 to a determined value. In addition, due to the master-slave configuration, the PS2 control circuit 204 may also set the voltage VY at the second output terminal 110 (and VP at the speaker terminal 106) to match VN. By setting VN to a deterministic value, which also enables the PS2 control circuit 204 to generate VY / VP to match VN, the transient difference signal between the output terminals 108 and 110 (and the resulting pop noise) may be reduced.

[0040] In some examples, the signal generator may also be a component of a common mode feedback loop that sets a common mode / DC bias voltage at the output terminal 108. When both the PS1 control circuit 202 and the PS2 control circuit 204 receive the audio signal 206, the signal generator may set a common mode at the output terminal 108 during normal operation of the system 100. The signal generator may set the common mode / DC bias voltage to a specific ratio of the PVDD voltages of the power stages PS1 and PS2. For example, by setting the common mode voltage to half of the PVDD voltage, the available swing of VN may be maximized, thereby increasing the output power. In all of these examples, the signal generator may ramp up (or ramp up) VN from zero volts to a target common mode / DC bias voltage during system 100 startup, and ramp down (or ramp down) VN from a specific common mode / DC bias voltage to zero volts during system 100 shutdown. The signal generator may ramp up the VN voltage at a slow rate (e.g., below the bandwidth PS2 control circuit 204 and power stage PS2), which allows PS2 control circuit 204 and power stage PS2 to adjust the VY / VP voltage to track the VN voltage and reduce / eliminate transient voltage differences across the speaker 102 and pop noise.

[0041] In some examples, the system 100 may also include an auxiliary circuit. The auxiliary circuit may equalize the VN and VP voltages during startup and shutdown, and bypass the power stages PS1 and PS2 (and the master-slave configuration). Such an arrangement may reduce the transient voltage difference across the speaker 102 caused by the asymmetry between the power stages PS1 and PS2, and the delay caused by the master-slave configuration when equalizing the VN and VY / VP voltages, which may reduce pop noise during startup and shutdown of the system 100.

[0042] Figure 3 Picture shows Figure 2 Examples of internal components of the system 100, including components for reducing pop noise. Figure 3 , the PS1 control circuit 202 includes a signal generator 304 and an amplifier 308. In some examples, the amplifier 308 can be a linear differential amplifier 308. During normal operation, the amplifier 308 can receive the sinusoidal audio signal 106, which can include differential audio signals 206a (also labeled as VINP) and 206b (also labeled as VINM), and provide control signals CS1 and CS2 by amplifying the audio signals 206a and 206b to set the voltage VN at the first output terminal 106.

[0043] In addition, the control circuit 202 includes a signal generator 304. The signal generator 304 may provide a signal 306 to the amplifier 308 to also set the voltage VN. During startup of the system 100, when there is no audio signal 206, the signal generator 304 may provide the signal 306 in the form of a ramp signal, which causes the amplifier 308 to provide control signals CS1 and CS2 to ramp the voltage VN from zero volts to a target common-mode voltage. Furthermore, during shutdown of the system 100, when there is no audio signal 206, the signal generator 304 may provide the signal 306 in the form of another ramp signal, which causes the amplifier 308 to provide control signals CS1 and CS2 to ramp the voltage VN from the common-mode voltage to zero volts. Furthermore, during normal operation of the amplifier 308 receiving the audio signal 206, the signal generator 304 may maintain the common-mode voltage at a target value, such as a predetermined fraction of PVDD, to set a maximum swing of the voltage VN. For example, signal generator 304 may set the common mode voltage to half of the PVDD voltage, which may increase / maximize the allowable swing of voltage VN and improve the efficiency of driving speaker 102 and reduce noise.

[0044] The system 100 may include a controller 310 to generate a control signal 312 and provide the control signal 312 to the signal generator 304, which may generate a signal 306 in response to the control signal 312. The control signal 312 may indicate, for example, a ramp-up signal 306 (e.g., during startup), a ramp-down signal 306 (e.g., during shutdown), or a DC signal 306 (e.g., during normal operation). The controller 310 may receive a status signal 314 from other components indicating an operating state of the system 100 (e.g., startup, shutdown, normal operation). The controller 310 may also monitor PVDD and set the control signal 312 based on PVDD (or other predetermined fraction of PVDD).

[0045] In addition, the PS2 control circuit 204 includes a filter 320, a subtraction circuit 322, a subtraction circuit 324, a periodic ramp generator 326, and a comparator 328. The system 100 also includes a voltage scaler circuit 329 that provides a scaled-down version of the VN voltage as a feedback signal 330. The voltage scaler circuit 329 can also remove the common-mode / DC bias component of the VN voltage and provide a scaled-down version of the AC (alternating current) component of the VN voltage.

[0046] Filter 320 may receive and filter audio differential signals 106a and 106b. In some examples, filter 320 may include a multi-stage loop filter. System 100 may also include resistors RIN and RFB to set the passband gain of filter 320. In addition, subtraction circuit 322 may generate a difference signal 332 representing the difference between filtered audio signals 206a and 206b, wherein difference signal 332 may have an opposite polarity to the VN voltage (and feedback signal 330). Subtraction circuit 324 may also generate another difference signal 334 representing the difference between signals 330 and 332. Subtraction circuit 324 may represent Figure 2 The subtraction circuit 210, and the difference signal 334 may represent Figure 2 The difference signal 212.

[0047] In addition, the comparator 328 can generate control signals CS3 and CS4 by comparing the difference signal 334 with the periodic ramp signal provided by the periodic ramp generator 326 and modulating the duty cycle / pulse width of CS3 and CS4 based on the difference. The difference signal 334 can have a component representing the audio signal 206 and another component representing the difference between VP and VN, which is caused by, for example, the aforementioned asymmetry and nonlinear effects. Therefore, the duty cycle / pulse width of CS3 and CS4 can reflect the instantaneous amplitude of the audio signals 206a and 206b (represented by the difference signal 332) and the difference between VP and VN (as part of the master-slave configuration), and the control circuit 204 can adjust CS3 and CS4 to reduce / minimize the difference between VP and VN. During startup and shutdown, when the audio signal 206 is not present, the difference signal 334 may represent only (or primarily) the voltage VN, and the comparator 328 may generate the modulation control signals CS3 and CS4 primarily based on VN so that the voltage VP may track VN to reduce the transient voltage difference across the speaker 102 and reduce pop noise.

[0048] Figure 4 Examples of internal components of the signal generator 304, amplifier 308, and controller 310 are shown. Figure 4 , Figure 3 The amplifier 308, which in one example can be a linear amplifier, includes a common-mode feedback stage 404 (also referred to herein as stage 404), a first differential stage 408, and a second differential stage 412. The first differential stage 408 and the second differential stage 412 are both linear amplifiers. The amplifier 308 can be referred to as a driver circuit because the amplifier 308 drives the transistors S1 and S2 of the power stage PS1. For similar reasons, the individual stages 404, 408, and 412 of the amplifier 308 can also be referred to as driver circuits.

[0049] Stage 404 includes a differential pair of transistors Ta and Tb. Transistor Ta is coupled between power supply AVDD and second differential stage 412, and similarly, transistor Tb is coupled between power supply AVDD and second differential stage 412. Stage 404 has an output coupled to terminals 440a and 440b, and terminals 440a and 440b are coupled to the input of second differential stage 412. The control terminal of transistor Ta is coupled to the output of signal generator 304 via buffer 434. Signal generator 304 includes voltage-controlled current source 428, current-controlled digital-to-analog converter (IDAC) 424, and resistor Rz. In addition, the control terminal of transistor Tb is coupled to the first output terminal 108 via buffer 436 and a resistor ladder including resistors Rx and Ry. In addition, first differential stage 408 includes a differential pair of transistors Tc and Td. The control terminals of transistors Tc and Td receive audio signals 206a (VINP) and 206b (VINM). The output of the first differential stage 408 is also coupled to the input of the second differential stage 412 via terminals 440a and 440b. The second differential stage 412 can amplify the signals at the terminals 440a and 440b and drive the drivers D1 and D2. Figure 1B As shown, driver D1 drives the control terminal of transistor S1, and driver D2 drives the control terminal of transistor S2.

[0050] During normal operation, the stage 404 can set the common mode / DC bias of the voltage VN at the first output terminal 108 to the target voltage set by the signal generator 304 by negative feedback. The transistor Ta can receive an analog voltage signal 306 representing the target voltage from the signal generator 304, and the transistor Tb can receive a voltage-divided version of the voltage VN. The difference between the target voltage and the voltage-divided version of VN can represent an error voltage. The differential pair of transistors Ta and Tb can set the voltage difference between terminals 440a and 440b by amplifying the error voltage. The second differential stage 412 can generate control signals CS1 and CS2 to reduce the error voltage so that the common mode / DC bias of the VN voltage (divided by the resistor ladder of Rx and Ry) is stabilized near the target voltage. In some examples, the Rx and Ry resistors (or the ratio between Rx and Ry) are configurable to compensate for the gain variation of the power stage PS1. In addition, the first differential stage 408 can drive the terminals 440a and 440b based on the audio signals VINP and VINM, and the second differential stage 412 can also generate control signals CS1 and CS2 based on the audio signals to provide an AC component of the VN voltage. Therefore, the VN voltage includes an AC component representing the audio signal provided by the second differential stage 412 superimposed on the DC component provided by the stage 404.

[0051] The signal generator 304 may set a target common-mode voltage based on the PVDD voltage. Specifically, as described above, the signal generator 304 includes a voltage-controlled current source 428, a current-controlled digital-to-analog converter (IDAC) 424, and a resistor Rz. The voltage-controlled current source 428 may provide a current whose size is controlled by the PVDD voltage. When the PVDD reaches a steady-state value, the output current of the voltage-controlled current source 428 is based on the steady-state voltage level of the PVDD. In addition, any changes in the PVDD value (e.g., a ramp up or down of the PVDD, class H operation, etc.) are reflected in the output current of the voltage-controlled current source 428. The IDAC 424 may receive a current from the voltage-controlled current source 428 and generate a voltage signal 306 (which represents a target voltage) by providing a scaled copy of the current passing through the resistor Rz. Because the current is a function of the PVDD voltage, the target voltage may also be a function of the PVDD voltage. In some examples, Rz may be configured to also compensate for gain changes in the power stage PS1. The IDAC 424 may receive a digital control signal 312 from the controller 310 indicating, for example, what portion of the PVDD voltage is represented by the target common-mode voltage, such as half of the PVDD voltage, one-quarter of the PVDD voltage, one-eighth of the PVDD voltage, etc. In addition, the common-mode feedback loop formed by the stages 404, 412 and the power stage PS1 has a limited bandwidth and may filter out transients in the PVDD voltage when generating the common-mode voltage, which may also improve the power supply rejection ratio (PSRR).

[0052] In addition to setting the target common mode voltage, the controller 310 can also control the signal generator 304, the stage 404, the second differential stage 412, and the power stage PS1 to set the voltage VN during startup and shutdown of the system 100, when the audio signal is not present and the first differential stage 408 does not drive the terminals 440a and 440b based on the audio signal. Specifically, as described above, the controller 310 can control the signal generator 304 to provide the voltage signal 306 as a ramp signal. Figure 4 , the controller 310 may include a counter 450 and a memory 452, the memory 452 storing a trim code indicating a fraction / percentage of the PVDD voltage as a target common-mode voltage (e.g., 1 / 2, 1 / 4, 1 / 8, etc.). In some examples, as described below, the trim code may also be used to trim off / reduce the mismatch between the target common-mode voltage and the actual common-mode voltage of the power stage PS1. The counter 450 may provide a count value (e.g., Figure 4, or other number of bits) as a digital control signal 312, and may increase the count value (count up) or decrease the count value (count down) based on the clock signal, which causes the IDAC 424 to increase or decrease the current through Rz over time to generate the voltage signal 306 as a ramp signal. The counter 450 may count up or down based on the state signal 314. For example, in response to the state signal 314 indicating startup, the counter 450 may count up from zero until the count value is equal to the fine-tuning code. In addition, in response to the state signal 314 indicating shutdown, the counter 450 may count down from the fine-tuning code until the count value reaches zero. In some examples, the controller 310 may also control the counter 450 to count up in response to detecting a startup condition (e.g., a rise in PVDD), and count down in response to detecting a shutdown condition (e.g., a fall in PVDD), or dynamically adjust the common mode during normal operation when the audio signal is provided to the first differential stage 408. Counter 450 can count up / down linearly or based on any mode, and can update the count value at a relatively slow rate (e.g., lower than the bandwidth of PS2 control circuit 204 and power stage PS2), so that power stage PS2 can update VY / VP voltage to track ramp VN voltage. Using counter 450 and IDAC 424 can improve the accuracy and fine-tunability of the generated voltage signal compared to the case where the capacitor is charged / discharged to generate the voltage ramp. In addition, because no charging / discharging capacitor is required, the total area / footprint can also be reduced.

[0053] Although the common-mode feedback stage 404 can set the common-mode voltage VN based on the target voltage defined by the trim code, there can be a considerable difference between the common-mode voltage and the target voltage. This difference can be attributed to various factors, such as the finite loop gain of the common-mode feedback loop, mismatches in the feedback resistor divider network, and / or mismatches between transistors Ta and Tb, which can introduce offsets. In some examples, the system 100 can include a calibration loop that can adjust the trim code stored in the memory 452 to reduce / minimize the difference between the common voltage and the target voltage.

[0054] Figure 5 An example of a system 100 including such a calibration loop is illustrated. Figure 5, the system 100 may include a calibration controller 500. The calibration controller 500 may include an amplifier 502 and a control logic circuit 504. The output of the amplifier 502 may be coupled to the control logic circuit 504, and the control logic circuit 504 has an output terminal coupled to the counter 450 and / or the memory 452. A first input terminal of the amplifier 502 is coupled to a reference voltage VREF, which may be a specific fraction of the PVDD voltage (e.g., PVDD / 2, PVDD / 4, etc.). A second input terminal of the amplifier 502 is coupled to the first output terminal 108 to receive VN.

[0055] In one example, the output of the control logic circuit 504 is coupled to the counter 450. Based on the output of the amplifier 502 indicating whether VN exceeds or falls below VREF, the control logic circuit 504 can control the counter 450 to count up or count down even after the count value reaches the trim code value. In another example, the output of the control logic circuit 504 is coupled to the memory 452. The control logic circuit 504 can read the count value from the counter 450 when VN matches VREF and update the trim code in the memory 452 with the count value.

[0056] In one example, when the audio signals VINM and VINP are not present or inactive, the calibration controller 500 may be enabled. The calibration controller 500 may be disabled during normal operation of the system 100 when the audio signals VINM and VINP are provided to the system 100.

[0057] Figure 6 A timing diagram 600 depicting an example operation of the system 100 is illustrated. Figure 6 The exemplary operations described in include a startup phase, a shutdown phase, a phase in which PVDD reaches a steady state, and a phase in which PVDD undergoes a change in the steady-state value. For example, between time t0 and t1, in the absence of audio input signals VINM and VINP, such as during startup or reset of the audio system 100, the power supply voltage PVDD ramps up from 0 to a steady-state voltage. Between t0 and t2, the output voltage VN of the power stage PS1 is 0 volts. Between t2 and t3, the controller 310 may control the signal generator 304 to provide the voltage signal 306 as a ramp signal, and VN also ramps up from 0 to a preconfigured fraction of PVDD (e.g., PVDD / n, where n is 2, 4, 8, or another appropriate positive number). After time t3, the voltage signal 306 stops rising and stays at a stable value, and VN stays at a preconfigured portion of PVDD. Although Figure 6, but due to the master-slave configuration discussed above, the voltage VP of the power stage PS2 also rises to match VN. In addition, because VN rises at a slow rate (e.g., below the bandwidth of the power stage PS2 and the PS2 control circuit), VP can match VN while both rise, which can reduce (or eliminate) transient voltage differences and pop noise across the speaker 102.

[0058] At time t5, the power supply voltage PVDD undergoes a level change. For example, due to a change in the power supply voltage PVDD, or due to a change in an audio mode that requires a lower power supply voltage, such as class H operation, the voltage PVDD may decrease starting at time t5. Because the signal generator 304 generates a voltage signal 306 as a function of PVDD (through the voltage-controlled current source 428), the voltage level of the voltage signal 306 also changes, and the amplifier 308 (common-mode feedback stage 404 and second differential stage 412) may control the power stage PS1 to correspondingly change the output voltage VN starting at time t6. Similarly, the amplifier 308 may control the power stage PS1 to increase the output voltage VN starting at time t8 in response to the level increase of PVDD at time t7.

[0059] At time t9, the audio system 100 receives a shutdown command (eg, via the enable / disable control signal 318). Accordingly, the controller 310 may control the signal generator 304 to ramp down the voltage signal 306, and the amplifier 308 may control the power stage PS1 to ramp down the output voltage VN to zero volts.

[0060] Figure 7 Timing diagrams 700 and 702 are illustrated. Timing diagram 700 depicts an example operation of system 100 during startup and shutdown. Referring to timing diagram 700, the output voltage VP of power stage PS2 in system 100 tracks the output voltage VN of power stage PS2. For example, as described above, power stage PS1 has a master control loop 204, and power stage PS2 has a slave control loop 208. Therefore, during startup and shutdown of system 100, the output voltage VP of power stage PS2 tracks the output voltage VN of power stage PS2. Note that Figure 7 (as well as Figure 6 ) does not depict the presence of an audio input signal. In the presence of an audio input signal, there is a deviation between voltages VP and VN, causing the speaker 102 to generate a sound representative of the audio input signal.

[0061] Also shown in timing diagram 702 are transient differences between the VP voltage and the VN voltage. As shown, VP closely tracks VN so that such offset transients, if present, are less than 1 mV, such as during startup and shutdown of system 100. Such small transient voltage differences may not generate an audible pop in the speaker.

[0062] Figure 8 A system 100 is illustrated that includes an example of an auxiliary circuit 802 for setting an output voltage VN of a power stage PS1. The auxiliary circuit 802 can be coupled directly to the first output terminal 108 and can set the voltage VN directly without using the power stage PS1. For example, the auxiliary circuit 802 can include a driver coupled to a voltage source that sets VN to a particular DC voltage, for example, during startup of the system 100 and / or shutdown of the system 100. The auxiliary circuit 802 can operate independently of or in conjunction with the power stage PS1. In one example, the auxiliary circuit 802 can be active during a startup / shutdown sequence, for example, when no audio input signal is present. In addition, the master-slave architecture can ensure that when the voltage VN is set by the auxiliary circuit 802, the voltage VP tracks the voltage VN, also as described above with respect to Figure 7 Discussed.

[0063] In some examples, during startup and shutdown, the controller 310 may provide a control signal 804 to disable the power stage PS1. For example, the controller 310 may provide a control signal 804 to drivers D1 and D2 to disable transistors S1 and S2. The controller 310 may also provide a control signal 806 to the auxiliary circuit 802, which enables the auxiliary circuit to set the voltage VN. In addition, during normal operation when an audio signal is present, the controller 310 may enable the common-mode feedback differential stage 404 to set the common mode of the VN voltage when an audio signal is present.

[0064] Fig. 9 A system 100 including another example of an auxiliary circuit is illustrated. Fig. 9, the auxiliary circuit 902 includes a switch coupled between the first output terminal 108 and the speaker terminal 106. In some examples, the system 100 may also include a blocking logic 904 coupled between the comparator 328 and the power stage PS2. The blocking logic 904, if enabled, may block the PWM CS3 and CS4 signals from reaching the power stage PS2 and disable the power stage PS2. During startup and shutdown of the system 100, the controller 310 may provide a control signal 906 to enable the switch of the auxiliary circuit 902, and provide a control signal 908 to the blocking logic 904 to disable the power stage PS2. With the switch enabled, the first output terminal 108 and the speaker terminal 106 may be electrically shorted together, and the VN and VP voltages may be equalized. The signal generator 304 may drive the power stage PS1 via the amplifier 308 to set the VN voltage, and the auxiliary circuit 902 may set the VP voltage equal to VN, independent of the master-slave configuration (or in combination with the master-slave configuration if the power stage PS2 is not disabled). Thus, because the transient voltage difference across speaker 102 is substantially zero, popping sounds from speaker 102 may be reduced or eliminated. Controller 310 may disable switches of auxiliary circuit 902 and blocking logic 904 during normal operation of system 100 when an audio signal is provided to system 100.

[0065] In some examples, system 100 supports enabling and disabling both power stages PS1 and PS2 to reduce power consumption. Fig.10 Such an example of a system 100 is illustrated. Fig.10 , the controller 310 may generate a control signal 1002 to enable or disable the PS1 control circuit 202 including the signal generator 304 and the amplifier 308, and provide a control signal 804 to enable / disable the power stage PS1. In some examples, the control signal 1002 may be provided to enable / disable, for example, the voltage-controlled current source 428 of the signal generator 304, the current source coupled between the AVDD power supply and the differential pair of transistors Ta and Tb of the stage 404, the current source coupled between the AVDD power supply and the differential pair of transistors Tc and Td of the first differential stage 408, and the second differential stage 412 to enable / disable the PS1 control circuit 202.

[0066] Fig.11 A timing diagram 1100 is illustrated. The timing diagram 1100 depicts an example operation of the system 100 including startup and shutdown. Fig.11 In FIG. 1 , power stage PS1 and control circuit 202 are enabled at time ta by control signals 804 and 1002 (collectively referred to as EN_N), and disabled at time tq. In addition, power stage PS2 is enabled at time ta by control signal 908 (also labeled EN_P), and disabled at time tq. Fig.11In the following figures, assertion of control signal 908 may disable blocking logic 904 and allow power stage PS2 to be driven by control circuit 204 , and de-assertion of control signal 908 may enable blocking logic 904 and disable power stage PS2 .

[0067] Simultaneously enabling or disabling power stages PS1 and PS2 may cause a momentary voltage difference and an audible popping noise across the speaker 102. Specifically, at time ta, both EN_P and EN_N are asserted (and power stages PS1 and PS2 are enabled). After asserting the EN_N signal, the controller 310 may start a counter 450 that counts up from time tb after time ta and provides an updated count value as the digital control signal 312, such as Fig.11 Therefore, the voltage VN starts to rise (or ramp up) from time tb (eg, in a linear or nearly linear manner).

[0068] The output voltage VP of power stage PS2 tracks the output voltage VN of power stage PS1, for example, using the master-slave configuration described above. Thus, the modulator of power stage PS2 generates a PWM signal for power stage PS2 starting at time tb. Note that, as described above, power stage PS2 is a switching amplifier and the output VY is a modulated voltage similar to a PWM signal, such as Fig.11 The voltage VP is a filtered version of the voltage VY.

[0069] However, at or near time tb (e.g., immediately thereafter), the PWM pulse fed to the power stage PS2 is relatively narrow (e.g., has a relatively low duty cycle, such as less than 5%). This is because VN has just begun to rise from 0 and has a relatively low voltage at this time. Therefore, for VP to track the low voltage of VN, the duty cycle of VY becomes relatively small, resulting in a narrow pulse at time tb or immediately after time TB. The narrow pulse filtered by the L1 inductor and capacitor C1 becomes the voltage VP. However, the voltage VP of the narrow pulse may not match the voltage VN, due to, for example, the limited accuracy of the control circuit 204 and the power stage PS2 in generating the modulation voltage VY to track the low voltage VN. This may cause a relatively large transient difference between the VN voltage and the VP voltage, for example in the range of 1mv, 2mV, 5mV, or 10mV, which may cause an audible popping sound from the speaker during startup. In another example, the system may have a minimum pulse width controller (e.g., a PWM controller that outputs PWM pulses having at least a minimum threshold pulse width) to eliminate pulse swallowing (e.g., ignoring relatively narrow pulses) (e.g., for electromagnetic interference (EMI) and / or electromagnetic compatibility (EMC) purposes). As a result, the Class D switching amplifier may not actually generate narrow pulses (e.g., with a width narrower than the minimum threshold pulse width), and thus the system may have an error when VY replicates VN. This may also contribute to audible popping.

[0070] A similar phenomenon can occur during shutdown when the VN voltage decreases (or ramps down). For example, during shutdown, when VN is almost zero (e.g., immediately before time tq), the pulses of power stage PS2 are relatively narrow, causing power stage PS2 to miss pulses, resulting in a relatively large transient difference between the VN voltage and the VP voltage, such as Fig.11 This can also cause a popping noise from the speaker when shutting down the device.

[0071] Fig.12 A timing diagram 1200 is illustrated that describes another example operation of the system 100, including startup and shutdown to reduce popping sound. Fig.12 During startup, after a delay of T from the validity of EN_N (enabling of power stage PS1 and control circuit 202), delay Afterwards, EN_P is asserted (and power stage PS2 is enabled). In addition, during shutdown, after a delay T has elapsed from the de-assertion of EN_P (and the disabling of power stage PS2). delayAfterwards, EN_N is set to invalid (and the power stage PS1 and the control circuit 202 are disabled). With this type of arrangement, narrow pulses generated by the power stage PS2 when the VN voltage is low can be avoided, which can reduce or eliminate the transient difference between the VP voltage and the VN voltage and the pop noise during startup and shutdown. In addition, this type of arrangement can relax the design of the power stage PS2, so that even if the power stage PS2 has a relatively low accuracy when generating the modulation voltage VY to track the low voltage VN, the pop noise caused by the mismatch between VP and VN can be reduced or even eliminated.

[0072] For example, refer to Fig.12 , EN_N is set to be valid at time ta, and the counter 450 can count up from time tb after time ta, such as Fig.12 Therefore, the voltage VN starts to rise (or ramp up) from time tb (eg, in a linear or nearly linear manner).

[0073] The control signal EN_P is asserted at time tc, which occurs after time ta and time tb. Between time tb and tc, the power stage PS2 remains disabled and does not generate pulses. Starting from or after time tc, the power stage PS2 begins to generate the voltage VY, as shown in FIG. Fig.12 Therefore, the blocking logic 904 blocks the relatively narrow PWM pulses between times tb and tc from reaching the power stage PS2.

[0074] As shown, the initial pulse at or immediately after time tc is relatively wide (e.g., Fig.11 Therefore, by Fig.12 By delaying the enabling of EN_P from time ta to time tc, the initial pulse received by power stage PS2 is relatively wider and can track the VN voltage more accurately, which can reduce or eliminate the transient difference between the VN voltage and the VP voltage. Fig.12 The transient difference is less than Fig.11 The transient difference may be less than 5 mV, 2 mV or 1 mV. This results in eliminating or at least reducing the pop noise generated by the speaker 102.

[0075] Similarly, during shutdown, EN_P is deasserted at time tp and EN_N is asserted at time tq, which occurs after time tp. Deasserting EN_P before deasserting EN_N ensures that power stage PS2 does not generate narrow pulses between time tp and time tq, thereby reducing or eliminating pop noise.

[0076] In one example, during startup, when power stage PS1 is enabled and PS2 is disabled (e.g., between time tb and tc), voltage VN is relatively low. At this time, capacitor C1 can help equalize the VP and VN voltages between speaker terminals 104 and 106, for example, to eliminate or reduce popping sounds during this time period. In one example, the switches of auxiliary circuit 902 (see Fig. 9 ) may also be turned on at this time, which may also help to equalize the VP and VN voltages to eliminate or reduce popping sounds during this time period. Similarly, the VP and VN voltages may also be equalized between times tp and tq (during the off period), for example, by capacitor C1 and / or by switches of auxiliary circuit 902.

[0077] Figures 13A-13C An example technique for generating a control signal EN_P (control signal 908) for controlling power stage PS2 is illustrated. Fig.13A , during startup of the system 100, EN_P is asserted (to disable the blocking logic 904) after a preconfigurable delay 1304 from when EN_N (control signals 804 and 1002) is asserted. The delay may be preconfigured and tuned to avoid enabling EN_P when the PWM pulses to the power stage PS2 are relatively narrow. The delay may be based on, for example, the ramp rate of VN, the accuracy with which the power stage PS2 and control circuit 204 modulate the VY voltage in tracking VN, etc. Additionally, during shutdown, the deactivation of EN_N may be delayed by the same delay 1304 as the deactivation of EN_P, as described above with respect to Fig.12 Discussed.

[0078] exist Fig. 13B In the embodiment, the EN_P generation circuit 1308 sets EN_P to be valid based on detecting that EN_N is set to be valid and based on the comparison of the voltage VN (or the difference between VN and VP) and one or more threshold voltages. For example, during startup, the EN_P generation circuit 1308 receives VN and a first threshold VN of VN (or a difference between VN and VP and a first threshold of the difference). In response to VN (or the difference between VN and VP) being equal to or greater than the first threshold, and in response to EN_N being set to be valid, the EN_P generation circuit 1308 may set EN_P to be valid. For example, in Fig.12 , VN becomes equal to or higher than the first threshold at time tc, based on which the EN_P generating circuit 1308 enables EN_P at time tc.

[0079] Similarly, during the shutdown period, EN_P generation circuit 1308 receives VN and a second threshold value of VN. In response to VN being equal to or less than the second threshold value, EN_P generation circuit 1308 sets EN_P to be invalid. Fig.12In the example, VN becomes equal to or less than the second threshold at time tp, based on which the EN_P generating circuit 1308 disables EN_P at time tp. In one example, the first and second thresholds of VN may be the same or different.

[0080] exist Fig. 13C , the EN_P generating circuit 1312 has a first input terminal coupled to the output terminal of the comparator 328 (of the control circuit 204) to receive the PWM signal generated by the comparator 328, and a second input terminal to receive a signal representing a duty cycle threshold. During startup, the EN_P generating circuit 1312 can measure the duty cycle of the PWM signal and set EN_P to be valid in response to detecting that EN_N is set to be valid and the duty cycle of the PWM signal is equal to or exceeds the first duty cycle threshold. For example, between time tb and tc and between time tp and tq, the PWM pulse is relatively narrow, for example, the duty cycle of the PWM pulse is less than the threshold duty cycle. Therefore, between time tb and tc and between time tp and tq, EN_P is disabled, and the blocking logic 904 blocks the PWM pulse from reaching the power stage PS2. In addition, during shutdown, the EN_P generating circuit 1312 can set EN_P to be invalid in response to detecting that the duty cycle of the PWM signal drops below the second duty cycle threshold.

[0081] Fig.14 1400 is an example flow chart representing a method 1400 of operating a speaker, such as speaker 102. Method 1400 may be performed by, for example, control circuit 316 and linear amplifier 308 in conjunction with Figure 2-13C The first power stage PS1 and the second power stage PS2 are performed.

[0082] In block 1404 of method 1400, a first voltage signal is provided at a first power stage output of a first power stage during a first time interval in which an input of a first driver circuit is inactive, wherein the first voltage signal increases over time from a first voltage level to a second voltage level. For example, the first time interval is Fig.12 The first driver circuit is the amplifier 308 or the differential stage 408 thereof. The input of the first driver circuit is Figure 4 The audio input signal VINM and VINP are provided to any one of the transistors Tc and Td, respectively. When VN rises (or ramps up) between time tb and td, the audio input signal is not present and the inputs of transistors Tc and Td are inactive.

[0083] Method 1400 proceeds from 1404 to 1408. At 1408, a second driver circuit is enabled to drive a second power stage to provide a second voltage signal at a second power stage output that tracks the first voltage signal. The second power stage is, for example, a PS2 power stage. The second driver circuit is, for example, a modulator for power stage PS2. The second voltage signal at the second power stage output is, for example, a voltage VP at speaker terminal 106 that tracks voltage VN.

[0084] From 1408, method 1400 proceeds to 1412. At 1412, a third voltage signal having a second voltage level at the output of the first power stage is provided as a DC bias signal in a second time interval after the first time interval. The second time interval is when the audio signals VINN and VINM are enabled, and the speaker 102 generates audio based on the audio signals VINN and VINM. The second voltage level of voltage VN is provided as a DC bias, and voltage VN swings around the DC bias, for example, based on the audio signals VINN and VINM, so that the speaker 102 generates an audio output. Additional Examples

[0085] In this specification, the term "couple" may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action: (a) in the first example, device A is coupled to device B through a direct connection; or (b) in the second example, if the intermediate component C does not change the functional relationship between device A and device B, device A is coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal generated by device A.

[0086] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or may be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be programmable through the device's firmware and / or software, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0087] As used herein, the terms "terminal", "node", "interconnection", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to an interconnection or its endpoint between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components.

[0088] Circuits or devices described herein that include certain components may be adapted to be coupled to these components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and / or inductors), and / or one or more sources (such as voltage and / or current sources) may be adapted to include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources during or after manufacturing, such as by an end user and / or a third party, to form the described structure.

[0089] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used. For example, a p-channel field effect transistor (PFET) may be used in place of an n-channel field effect transistor (NFET) with little or no change to the circuit. In addition, other types of transistors may be used, such as laterally diffused metal oxide semiconductor (LDMOS) FETs and bipolar junction transistors (BJTs). In addition, the device may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0090] The reference herein to a field effect transistor (FET) being in the "on" state means that a conductive channel of the field effect transistor exists and drain current can flow through the field effect transistor. The reference herein to a FET being "off" means that a conductive channel does not exist and drain current does not flow through the FET. However, an off FET can have current flowing through the body diode of the transistor.

[0091] The circuits described herein may be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available before the component was replaced. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may be replaced with a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may be replaced with a plurality of resistors or capacitors, respectively, which are coupled in series between the same two nodes as a single resistor or capacitor.

[0092] The use of the aforementioned term "ground" includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground and / or any other form of ground connection applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "approximately" or "substantially" before a parameter means within + / -10% of the parameter.

[0093] Modifications may be made to the described embodiments and examples within the scope of the claims, as well as to other embodiments and examples, such as the examples below.

[0094] Example 1. A device comprising: a first power stage having a first power stage input and a first power stage output; a second power stage having a second power stage input and a second power stage output; a first driver circuit having a first driver input and a first driver output, the first driver output being coupled to the first power stage input; a control circuit configured to set the first power stage output in response to the first driver input being in an inactive state; and a second driver circuit having a second driver input and a second driver output, the second driver output being coupled to the second power stage input, and the second driver input being coupled to the first power stage output, and the second driver circuit being configured to set the second power stage output to track the first power stage output.

[0095] Example 2. An apparatus according to Example 1, wherein the control circuit has at least one of an enable input or a disable input, and is configured to determine that the first driver input is in an inactive state in response to an enable signal at the enable input or a disable signal at the disable input.

[0096] Example 3. An apparatus according to any of Examples 1-2, wherein the control circuit is configured to set the first power stage output terminal to one of a first voltage or a second voltage, wherein the first voltage increases from a first voltage level to a second voltage level over time, and the second voltage decreases from the second voltage level to the first voltage level over time; and the second driver circuit is configured to control the second power stage output terminal to provide a third voltage to track the first voltage signal, and to provide a fourth voltage to track the second voltage.

[0097] Example 4. The apparatus of Example 3, wherein each of the first voltage and the second voltage comprises a respective linear voltage ramp.

[0098] Example 5. An apparatus according to any of Examples 1-4, wherein the control circuit includes an auxiliary power stage having an auxiliary output terminal coupled to the first power stage output terminal, and the control circuit is configured to: in response to the first driver input terminal being in an inactive state, control the auxiliary power stage to set the first power stage output terminal via the auxiliary output terminal; and in response to the first driver input terminal being in an active state, disable the auxiliary power stage.

[0099] Example 6. An apparatus according to any one of Examples 1-5, wherein the first driver circuit includes a first stage and a second stage, the first stage having a first driver input and a first stage output, the second stage having a second stage input coupled to the first stage output and the first driver output, and the control circuit is configured to set the first power stage output by providing a signal at the second stage input.

[0100] Example 7. An apparatus according to any one of Examples 3-6, wherein the control circuit is configured to: at a first time, start setting the first power stage output terminal to a first voltage and disable the second driver circuit to set the second power stage output terminal; at a second time after the first time, when providing a first voltage signal, enable the second driver circuit to set the second power stage output terminal; between a third time and a fourth time, provide a second voltage; and at a fifth time before the fourth time, disable the second driver circuit to set the second power stage output terminal.

[0101] Example 8. The apparatus of Example 7, wherein the control circuit is configured to determine the second time based on a preconfigured time difference from the first time, and to determine the fifth time based on a preconfigured time difference from the fourth time.

[0102] Example 9. An apparatus according to any of Examples 7-8, wherein the controller is configured to determine the second time based on the first voltage signal exceeding the first threshold, and determine the fifth time based on the second voltage below the second threshold.

[0103] Example 10. An apparatus according to any of Examples 7-9, wherein the control circuit includes an auxiliary circuit and is configured to control the auxiliary circuit to provide a signal at the second power stage output to track the first power stage output when the second driver circuit is disabled.

[0104] Example 11. The apparatus of Example 10, wherein the auxiliary circuit comprises at least one of: a switch coupled between the first power stage output and the second power stage output, or an amplifier having an amplifier output coupled to the first power stage output.

[0105] Example 12. An apparatus according to any of Examples 1-11, wherein the control circuit is configured to set a direct current (DC) voltage at the first power stage output when the first driver input is active.

[0106] Example 13. An apparatus according to Example 12, wherein the first power stage has a first power input coupled to the power terminal, the second power stage has a second power input coupled to the power terminal, and the control circuit is configured to set the DC voltage based on a second voltage at the power terminal.

[0107] Example 14. An apparatus according to any one of Examples 12-13, wherein the DC voltage is a first DC voltage, the first driver circuit includes a first stage and a second stage, the first stage has a first driver input terminal and a first stage output terminal, the second stage has a second stage input terminal coupled to the first stage output terminal and the first driver output terminal, and the control circuit is configured to set the first DC voltage by setting the second DC voltage at the second stage input terminal.

[0108] Example 15. An apparatus according to Example 14, wherein the second stage input terminal includes a first differential input terminal, and the controller includes: a differential pair having a second differential input terminal and a differential output terminal, the differential output terminal coupled to the first differential input terminal; and a voltage generator having a generator output terminal having a first input terminal coupled to the second differential input terminal; and wherein a second input terminal of the second differential input terminal is coupled to the first power stage output terminal.

[0109] Example 16. An apparatus according to Example 15, wherein the voltage generator has a control input terminal, and the apparatus further includes a calibration circuit having a reference input terminal, a calibration input terminal and a calibration output terminal, the calibration input terminal is coupled to the first power stage output terminal, and the calibration output terminal is coupled to the control input terminal.

[0110] Example 17. An apparatus according to any of Examples 1-16, wherein the first driver circuit is configured to provide a first driver signal at a first driver output terminal, and the first driver signal is linearly related to the signal at the first driver input terminal; and the second driver circuit is configured to provide a second driver signal at a second driver output terminal, and the second driver signal is a pulse width modulated (PWM) signal.

[0111] Example 18. The device according to Example 17 further includes: a first capacitor coupled between the first power stage output and the ground terminal; an inductor coupled between the second power stage output and the speaker output terminal; and a second capacitor coupled between the first power stage output and the speaker output terminal.

[0112] Example 19. The apparatus of Example 18, further comprising a speaker coupled between the first power stage output and the speaker output terminal.

[0113] Example 20. A device comprising: a first power stage having a first power input terminal coupled to a power terminal, a first power stage input terminal, and a first power stage output terminal; a second power stage having a second power input terminal coupled to the power terminal, a second power stage input terminal, and a second power stage output terminal; a first driver circuit having a first driver input terminal and a first driver output terminal, the first driver output terminal being coupled to the first power stage input terminal; a second driver circuit having a second driver input terminal and a second driver output terminal, the second driver output terminal being coupled to the second power stage input terminal, and the second driver input terminal being coupled to the first power stage output terminal, and the second driver circuit being configured to set the second power stage output terminal to track the first power stage output terminal; and a control circuit being configured to set a DC voltage at the first power stage output terminal based on a second voltage at the power terminal.

[0114] Example 21. An apparatus according to Example 20, wherein the control circuit is configured to set the first power stage output to one of a first voltage or a second voltage in response to the first driver input being in an inactive state, wherein the first voltage increases from a first voltage level to a second voltage level over time and the second voltage decreases from the second voltage level to the first voltage level over time.

[0115] Example 22. A device comprising: a first power stage having a power terminal, a first power stage input, and a first power stage output; a second power stage having a power terminal, a second power stage input, and a second power stage output; a first driver circuit having a first driver input and a first driver output, the first driver output being coupled to the first power stage input; a second driver circuit having a second driver input and a second driver output, the second driver output being coupled to the second power stage input, and the second driver input being coupled to the first power stage output, and the second driver circuit being configured to set a state of the second power stage output to track a state of the first power stage output; and a control circuit coupled to the first power stage output and configured to: at a first time, start setting the first power stage output at a first voltage, and disable the second driver circuit to set the second power stage output, wherein the first voltage increases from a first voltage level to a second voltage level over time; and at a second time after the first time, when the first voltage is provided, enable the second driver circuit to set the second power stage output.

[0116] Example 23. An apparatus according to Example 22, wherein the control circuit is configured to: provide a second voltage between a third time and a fourth time, wherein the second voltage decreases from a second voltage level to a first voltage level over time; and disable the second driver circuit to set the second power stage output terminal at a fifth time before the fourth time.

[0117] Example 24. The apparatus of Example 23, wherein the first voltage increases over time from a first voltage level to a second voltage level, and the second voltage decreases over time from the second voltage level to the first voltage level.

[0118] Example 25. A method comprising: providing a first voltage signal at a first power stage output terminal of a first power stage during a first time interval in which an input terminal of a first driver circuit is in an inactive state, wherein the first voltage signal increases from a first voltage level to a second voltage level over time; enabling a second driver circuit to drive a second power stage to provide a second voltage signal at a second power stage output terminal that tracks the first voltage signal; and providing a third voltage signal having a second voltage level as a DC bias signal at the first power stage output terminal during a second time interval after the first time interval.

[0119] Example 26. The method of Example 25, wherein the second voltage level is based on a supply voltage of the first power stage and the second power stage.

[0120] Example 27. The method of any of Examples 25-26, wherein the input of the first driver circuit is active during the second time interval.

[0121] Example 28. The method of any one of Examples 25-27 further includes providing a fourth voltage signal at the first power stage output during a third time interval when the input is inactive, wherein the fourth voltage signal decreases from the second voltage level to the first voltage level over time.

[0122] Example 29. The method of Example 28, wherein each of the first voltage signal and the fourth voltage signal comprises a respective linear ramp signal.

[0123] Example 30. A method according to any of Examples 25-29, wherein providing a first voltage signal within a first time interval in which the input terminal of the first driver circuit is in an inactive state includes: disabling the second driver circuit to set the state of the second power stage output terminal within a first sub-interval of the first time interval; and enabling the second driver circuit to set the state of the second power stage output terminal within a second sub-interval of the first time interval, wherein the voltage level of the first voltage signal increases from the first sub-interval to the second sub-interval.

Claims

1. A device comprising: a first power stage having a first power stage input and a first power stage output; a second power stage having a second power stage input and a second power stage output; a first driver circuit having a first driver input and a first driver output, wherein the first driver output is coupled to the first power stage input; a control circuit configured to set the first power stage output in response to the first driver input being in an inactive state; as well as a second driver circuit having a second driver input and a second driver output, the second driver output being coupled to the second power stage input, and the second driver input being coupled to the first power stage output, and the second driver circuit being configured to set the second power stage output to track the first power stage output.

2. The apparatus of claim 1 , wherein the control circuit has at least one of an enable input or a disable input, and is configured to determine that the first driver input is in the inactive state in response to an enable signal at the enable input or a disable signal at the disable input.

3. The apparatus of claim 1 , wherein the control circuit is configured to set the first power stage output to one of a first voltage or a second voltage, wherein the first voltage increases from a first voltage level to a second voltage level over time, and the second voltage decreases from the second voltage level to the first voltage level over time; and The second driver circuit is configured to control the second power stage output to provide a third voltage to track the first voltage signal and to provide a fourth voltage to track the second voltage. 4 . The device of claim 3 , wherein each of the first voltage and the second voltage comprises a respective linear voltage ramp.

5. The apparatus of claim 1 , wherein the control circuit comprises an auxiliary power stage having an auxiliary output coupled to an output of the first power stage, and the control circuit is configured to: In response to the first driver input being in the inactive state, controlling the auxiliary power stage to set the first power stage output via an auxiliary output; and In response to the first driver input being in an active state, the auxiliary power stage is disabled.

6. The apparatus of claim 1 , wherein the first driver circuit comprises a first stage and a second stage, the first stage having the first driver input and a first stage output, the second stage having a second stage input coupled to the first stage output and the first driver output, the control circuit being configured to set the first power stage output by providing a signal at the second stage input.

7. The apparatus of claim 3, wherein the control circuit is configured to: At a first time, begin setting the first power stage output at the first voltage and disable a second driver circuit to set the second power stage output; At a second time after the first time, when the first voltage signal is provided, enabling the second driver circuit to set the second power stage output terminal; between the third time and the fourth time, providing the second voltage; and At a fifth time before the fourth time, the second driver circuit is disabled to set the second power stage output. 8 . The apparatus of claim 7 , wherein the control circuit is configured to determine the second time based on a preconfigured time difference from the first time, and to determine the fifth time based on the preconfigured time difference from the fourth time. 9 . The apparatus of claim 7 , wherein the controller is configured to determine the second time based on the first voltage signal exceeding a first threshold, and to determine the fifth time based on the second voltage signal being below a second threshold.

10. The apparatus of claim 7, wherein the control circuit comprises an auxiliary circuit and is configured to control the auxiliary circuit to provide a signal at the second power stage output to track the first power stage output when the second driver circuit is disabled.

11. The apparatus of claim 10, wherein the auxiliary circuit comprises at least one of: a switch coupled between the first power stage output and the second power stage output, or an amplifier having an amplifier output coupled to the first power stage output.

12. The apparatus of claim 1, wherein the control circuit is configured to set a direct current (DC) voltage at the first power stage output when the first driver input is active.

13. The apparatus of claim 12, wherein the first power stage has a first power input coupled to a power terminal, the second power stage has a second power input coupled to the power terminal, and the control circuit is configured to set the DC voltage based on a second voltage at the power terminal.

14. The apparatus of claim 12 , wherein the DC voltage is a first DC voltage, the first driver circuit comprises a first stage and a second stage, the first stage having the first driver input and a first stage output, the second stage having a second stage input coupled to the first stage output and the first driver output, the control circuit being configured to set the first DC voltage by setting a second DC voltage at the second stage input.

15. The apparatus of claim 14, wherein the second stage input comprises a first differential input, and the controller comprises: a differential pair, the differential pair having a second differential input terminal and a differential output terminal, the differential output terminal being coupled to the first differential input terminal; as well as a voltage generator having a generator output terminal coupled to a first input terminal of the second differential input terminal; as well as The second input terminal of the second differential input terminal is coupled to the first power stage output terminal.

16. The apparatus of claim 15, wherein the voltage generator has a control input, and the apparatus further comprises a calibration circuit having a reference input, a calibration input, and a calibration output, the calibration input being coupled to the first power stage output, and the calibration output being coupled to the control input.

17. The apparatus of claim 1, wherein the first driver circuit is configured to provide a first driver signal at the first driver output, the first driver signal being linearly related to a signal at the first driver input; and The second driver circuit is configured to provide a second driver signal at the second driver output, the second driver signal being a pulse width modulated (PWM) signal.

18. The apparatus according to claim 17, further comprising: a first capacitor coupled between an output terminal of the first power stage and a ground terminal; an inductor coupled between an output terminal of the second power stage and an output terminal of a speaker; as well as A second capacitor is coupled between the first power stage output and the speaker output terminal.

19. The apparatus of claim 18, further comprising a speaker coupled between the first power stage output and the speaker output terminal.

20. An apparatus comprising: a first power stage having a first power input coupled to the power terminal, a first power stage input, and a first power stage output; a second power stage having a second power input coupled to the power terminal, a second power stage input, and a second power stage output; a first driver circuit having a first driver input and a first driver output, wherein the first driver output is coupled to the first power stage input; a second driver circuit having a second driver input and a second driver output, the second driver output coupled to the second power stage input, and the second driver input coupled to the first power stage output, and the second driver circuit configured to set the second power stage output to track the first power stage output; as well as A control circuit is configured to set a DC voltage at an output of the first power stage based on a second voltage at the power terminal.

21. The apparatus of claim 20, wherein the control circuit is configured to set the first power stage output to one of a first voltage or a second voltage in response to the first driver input being in an inactive state, wherein the first voltage increases from a first voltage level to a second voltage level over time and the second voltage decreases from the second voltage level to the first voltage level over time.

22. An apparatus comprising: a first power stage having a power terminal, a first power stage input, and a first power stage output; a second power stage having the power terminal, a second power stage input, and a second power stage output; a first driver circuit having a first driver input and a first driver output, wherein the first driver output is coupled to the first power stage input; a second driver circuit having a second driver input and a second driver output, the second driver output coupled to the second power stage input, and the second driver input coupled to the first power stage output, and the second driver circuit configured to set a state of the second power stage output to track the state of the first power stage output; as well as A control circuit, the control circuit is coupled to the first power stage output terminal and is configured to: at a first time, beginning to set the first power stage output at a first voltage and disabling the second driver circuit to set the second power stage output, wherein the first voltage increases over time from a first voltage level to a second voltage level; as well as At a second time after the first time, the second driver circuit is enabled to set the second power stage output terminal when the first voltage is provided.

23. The apparatus of claim 22, wherein the control circuit is configured to: Between a third time and a fourth time, providing a second voltage, wherein the second voltage decreases from the second voltage level to the first voltage level over time; and At a fifth time before the fourth time, the second driver circuit is disabled to set the second power stage output.

24. The apparatus of claim 23, wherein the first voltage increases from a first voltage level to a second voltage level over time, and the second voltage decreases from the second voltage level to the first voltage level over time.

25. A method comprising: providing a first voltage signal at a first power stage output of a first power stage during a first time interval when an input of the first driver circuit is inactive, wherein the first voltage signal increases over time from a first voltage level to a second voltage level; enabling a second driver circuit to drive a second power stage to provide a second voltage signal at an output of the second power stage that tracks the first voltage signal; as well as In a second time interval after the first time interval, a third voltage signal having the second voltage level is provided as a DC bias signal at the output terminal of the first power stage.

26. The method of claim 25, wherein the second voltage level is based on a supply voltage of the first power stage and the second power stage.

27. The method of claim 25, wherein the input of the first driver circuit is active during the second time interval.

28. The method of claim 25, further comprising providing a fourth voltage signal at the first power stage output during a third time interval when the input is in the inactive state, wherein the fourth voltage signal decreases from the second voltage level to the first voltage level over time.

29. The method of claim 28, wherein each of the first and fourth voltage signals comprises a respective linear ramp signal.

30. The method of claim 25, wherein providing the first voltage signal during the first time interval when the input terminal of the first driver circuit is in the inactive state comprises: disabling the second driver circuit to set a state of the second power stage output during a first subinterval of the first time interval; as well as The second driver circuit is enabled to set the state of the second power stage output during a second subinterval of the first time interval, wherein the voltage level of the first voltage signal increases from the first subinterval to the second subinterval.

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