Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate and a semiconductor device on the substrate; the semiconductor device includes a channel structure including a channel layer and a gate insulating layer, and a first electrode, a gate electrode, and a second electrode spaced and sequentially stacked in a vertical direction, the channel structure extending in the vertical direction through the gate electrode and connected between the first electrode and the second electrode, the gate insulating layer is located between the gate electrode and the channel layer. According to the scheme, the channel layer has better crystallization characteristics, meanwhile, the channel layer can have various shapes and structures, the channel layer is not limited to a circular ring shape any more, the channel area can be increased, electric leakage can be improved, working current can be improved, and then the electrical performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory with the advantages of large capacity and low cost, and has been widely used in various fields. The basic memory unit of conventional DRAM is 1T1C (1Transistor-1Capacitor) memory unit, which requires one transistor and one capacitor.

[0003] With the development of three-dimensional memory technology, there are more and more vertical channel transistor structures. In the vertical channel structure transistor, the channel layer between the lead layers is the word line (WL) to control the switch. However, the channel layer in the related art is often limited to a circular ring shape, and the channel layer is prepared after the WL, which makes the crystallization characteristics of the channel layer poor, thereby causing the electrical performance of the memory to deteriorate. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, the present application provides a semiconductor device, including:

[0006] A substrate, and a semiconductor device located on the substrate;

[0007] The semiconductor device includes a channel structure and a first electrode, a gate electrode and a second electrode spaced apart and stacked sequentially in a vertical direction, the channel structure includes a channel layer and a gate insulating layer, the channel structure extends through the gate electrode in the vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer.

[0008] Exemplarily, the semiconductor device further includes a first insulating layer, which is prepared at the same layer as the gate insulating layer and extends horizontally between the first electrode and the gate electrode.

[0009] Exemplarily, the first insulating layer contacts the first electrode.

[0010] Exemplarily, the first insulating layer contacts the gate electrode.

[0011] Exemplarily, a distance between an end of the channel layer connected to the second electrode and the gate electrode is smaller than a distance between an end of the gate insulating layer contacting the second electrode and the gate electrode.

[0012] Exemplarily, the second electrode includes a first portion in contact with the channel layer, and a second portion located on a side of the first portion away from the channel layer;

[0013] The semiconductor device further includes an insulating dielectric layer, which is located between the second portion and the gate electrode, and an orthographic projection of the insulating dielectric layer on the substrate does not overlap with the channel structure.

[0014] Exemplarily, the semiconductor device further includes a first signal line, which is integrally formed with the first electrode and extends along a first horizontal direction, and an orthographic projection of the first electrode on the substrate is located within the first signal line.

[0015] Exemplarily, a positive projection boundary of the channel layer on the substrate exceeds the first signal line; or

[0016] An orthographic projection boundary of the channel layer on the substrate overlaps with an edge portion of the first signal line and does not exceed the first signal line.

[0017] Exemplarily, the orthographic projection of the channel structure on the substrate includes a ring shape, and the orthographic projection of the gate electrode on the substrate includes a third portion located within the ring shape and a fourth portion located outside the ring shape.

[0018] Exemplarily, the orthographic projection of the channel structure on the substrate includes a plurality of fifth portions, the gate electrode includes a sixth portion surrounding each of the fifth portions, and the sixth portions in a gate electrode are formed as one body.

[0019] Exemplarily, the orthographic projections of the fifth portion on the substrate are strips that are parallel to each other; or

[0020] The orthographic projection of the fifth portion on the substrate is a ring shape, and the gate electrode further includes a seventh portion located inside the ring shape.

[0021] Exemplarily, the first electrode includes a first contact material layer and a conductor layer, and the first contact material layer is located between the conductor layer and the channel layer;

[0022] The second electrode includes a second contact material layer.

[0023] Another aspect of the present application provides a method for manufacturing a semiconductor device, comprising the following steps:

[0024] providing a substrate;

[0025] Sequentially preparing a first electrode, a channel layer, a gate insulating layer and a gate electrode on the substrate;

[0026] preparing a second electrode on the substrate;

[0027] The channel layer extends in a vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer.

[0028] Exemplarily, preparing the channel layer includes:

[0029] preparing a semiconductor material layer on the first electrode;

[0030] preparing a first patterned mask layer on the semiconductor material layer;

[0031] The semiconductor material layer is etched using the first patterned mask layer as a mask to form the channel layer.

[0032] Exemplarily, the first patterned mask layer includes at least one portion, the orthographic projection of the portion on the substrate includes a ring or a rectangle; and / or

[0033] An orthographic projection of the first patterned mask layer on the substrate includes a plurality of parallel strips.

[0034] Exemplarily, preparing the second electrode includes:

[0035] Before preparing the first patterned mask layer, preparing a contact material layer on the semiconductor material layer;

[0036] While etching the semiconductor material layer using the first patterned mask layer as a mask, patterning the contact material layer to form an upper contact portion;

[0037] The second electrode includes the upper contact portion.

[0038] Exemplarily, the method further includes: preparing a first signal line, the first signal line and the first electrode are prepared simultaneously, and an orthographic projection of the first electrode on the substrate is located within the first signal line;

[0039] Preparing the gate insulating layer and the gate electrode comprises:

[0040] preparing a gate insulating material layer, wherein the gate insulating material layer covers the channel layer, the upper contact portion, the first electrode and the first signal line;

[0041] preparing a gate electrode material layer, wherein the gate electrode material layer covers the gate insulating material layer;

[0042] Patterning and etching the gate electrode material layer to form the gate electrode, wherein a surface of the gate electrode away from the substrate is lower than the channel layer;

[0043] preparing an insulating dielectric layer, wherein the insulating dielectric layer covers the gate insulating material layer and the gate electrode;

[0044] A portion of the insulating dielectric layer and a portion of the gate insulating material layer are removed to expose the upper contact portion, and the gate insulating material layer located on a side of the gate electrode close to the channel layer is formed as the gate insulating layer.

[0045] Exemplarily, the preparing the second electrode further comprises:

[0046] After the upper contact portion is exposed, a connection portion is prepared at one end of the upper contact portion away from the channel layer, and the second electrode further includes the connection portion.

[0047] Exemplarily, in an orthographic projection on the substrate:

[0048] The first patterned mask layer includes a ring shape, and the gate electrode includes a portion located inside the ring shape and a portion located outside the ring shape; or

[0049] The first patterned mask layer includes a plurality of portions, and the gate electrode surrounds each of the portions.

[0050] Exemplarily, the method also includes: preparing a first signal line, the first signal line and the first electrode are prepared simultaneously, the orthographic projection of the first electrode on the substrate is located within the first signal line, and the orthographic projection boundary of the first patterned mask layer on the substrate exceeds the first signal line, or overlaps with the edge portion of the first signal line and does not exceed the first signal line.

[0051] Exemplarily, the first electrode includes a conductor layer and a lower contact portion located on a side of the conductor layer away from the substrate;

[0052] After preparing the semiconductor material layer, the method further comprises the step of: performing a heat treatment so as to reduce the resistance between the semiconductor material layer and the lower contact portion.

[0053] Illustratively, after preparing the contact material layer on the semiconductor material layer, the method further comprises the step of: heat treatment so as to reduce the impedance between the semiconductor material layer and the contact material layer.

[0054] The semiconductor device and manufacturing method of the embodiments of the present application have a channel layer with better crystallization characteristics. At the same time, the channel layer can have a variety of shape structures. The channel layer is no longer limited to a circular ring shape, which can increase the channel area, help improve leakage and increase the operating current, thereby improving the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The following drawings of the present application are used as a part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0056] In the attached figure:

[0057] Figure 1A-Figure 1N A schematic cross-sectional view of a device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application along a first horizontal direction and a second horizontal direction is shown;

[0058] Figure 2A-2G A schematic top view of a device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown;

[0059] Figure 3A-Figure 3F A schematic diagram of an orthographic projection of a semiconductor device according to a specific embodiment of the present application is shown;

[0060] Figure 4 A flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown.

[0061] Description of reference numerals:

[0062] 100 - substrate, 101 - conductor layer, 102 - lower contact portion, 103 - semiconductor material layer,

[0063] 104-contact material layer, 105-first dielectric layer, 106-second dielectric layer,

[0064] 107 - first patterned mask layer, 108 - channel layer, 109 - upper contact portion,

[0065] 110 - gate insulating material layer, 111 - gate electrode material layer,

[0066] 112 - second patterned mask layer, 113 - gate electrode, 114 - insulating dielectric layer,

[0067] 115 - gate insulating layer, 116 - first insulating layer, 117 - material layer, 118 - connection part,

[0068] 130-Part 3, 140-Part 4, 150-Part 5, 160-Part 6,

[0069] 170-Part VII. DETAILED DESCRIPTION

[0070] Next, the present application will be described more completely in conjunction with the accompanying drawings, in which embodiments of the present application are shown. However, the present application can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, for clarity, the sizes and relative sizes of layers and regions may be exaggerated. The same reference numerals throughout represent the same elements.

[0071] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0072] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0073] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0074] Embodiments of the application are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the present application. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the present application should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the present application.

[0075] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by ordinary technicians in the field of this application. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined as such herein.

[0076] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementations.

[0077] In the manufacturing process of the transistor of the DRAM of the related art, generally, WL (Word Line) is formed first, then WL is etched to form a channel hole penetrating WL, and then filled to form a channel layer. Due to the limitation of the process, the shape of the channel layer formed by this manufacturing process is often limited to a circular ring, and the channel area of ​​the channel layer is small, and the electrical performance is poor. At the same time, when the filled channel layer is subjected to heat treatment, the crystallization characteristics of the channel layer are poor. The above two problems will lead to the degradation of the electrical performance of the memory.

[0078] Therefore, in view of the existence of the aforementioned technical problems, the present application proposes a semiconductor device, comprising:

[0079] A substrate, and a semiconductor device located on the substrate;

[0080] The semiconductor device includes a channel structure and a first electrode, a gate electrode and a second electrode spaced apart and stacked sequentially in a vertical direction. The channel structure includes a channel layer and a gate insulating layer. The channel structure extends through the gate electrode in a vertical direction and is connected between the first electrode and the second electrode. The gate insulating layer is located between the gate electrode and the channel layer.

[0081] In the semiconductor device of the present application, the channel layer can be prepared before the gate electrode, so that it can have better crystallization characteristics. At the same time, the channel layer can have a variety of shape structures. The channel layer is no longer limited to a circular ring shape, and can also increase the channel area, which helps to improve leakage and increase the operating current, thereby improving the electrical performance of the semiconductor device.

[0082] Below, reference Figures 1A to 3F The semiconductor device of the present application is described in detail, wherein: Figure 1A-Figure 1N A schematic cross-sectional view of a device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application along a first horizontal direction and a second horizontal direction is shown. Figure 2A-2G A schematic top view of a device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown. Figure 3A-Figure 3F FIG. 1 is a schematic diagram of an orthographic projection of a semiconductor device according to a specific embodiment of the present application. For example, Figure 1A-Figure 1N FIG. (a) shows a cross-sectional view of a semiconductor device along a first direction. Figure 1A-Figure 1N (b) in the figure shows a cross-sectional schematic diagram of the semiconductor device along the second direction, wherein the first direction intersects the second direction, and optionally, the first direction is perpendicular to the second direction. Exemplarily, the semiconductor device of the embodiment of the present application can be manufactured using the semiconductor device manufacturing method described below.

[0083] The semiconductor device of the present application may be any suitable type of device known to those skilled in the art. In this embodiment, the technical solution of the present application is explained and illustrated mainly by taking the case where the semiconductor device is a DRAM as an example.

[0084] In one example, if Figure 1NAs shown, the semiconductor device of the present application includes a substrate 100, and the substrate 100 is a substrate with at least a surface insulation, and at least the surface and the first electrode are insulated. The substrate 100 can be a substrate with overall insulation, or a composite substrate including a surface insulation layer and a semiconductor substrate, and a transistor can be formed in the semiconductor substrate. Although several examples of the substrate 100 are described here, any material / structure that can be used as a substrate falls within the spirit and scope of the present application.

[0085] In one example, if Figure 1N As shown, the semiconductor device of the present application further includes a semiconductor device located on the substrate 100, the semiconductor device includes a channel structure and a first electrode, a gate electrode 113 and a second electrode spaced and sequentially stacked in a vertical direction, the channel structure includes a channel layer 108 and a gate insulating layer 115, the channel structure extends through the gate electrode 113 in the vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer 115 is located between the gate electrode 113 and the channel layer 108. Exemplarily, a signal line electrically connected to the gate electrode 113, such as a word line WL, extends along the second horizontal direction.

[0086] The vertical direction includes two directions perpendicular to the substrate 100 and away from or toward the substrate 100. When the semiconductor device is manufactured on the substrate 100, or is manufactured on a temporary substrate and then transferred to the substrate 100 in the same direction, the vertical direction is away from the substrate 100; when the semiconductor device is manufactured on a temporary substrate and then transferred to the substrate 100 in a flipped manner, the vertical direction is toward the substrate 100.

[0087] The channel structure is connected between the first electrode and the second electrode, and at least includes a channel layer 108 connected between the first electrode and the second electrode; optionally, a gate insulating layer 115 is also connected between the first electrode and the second electrode.

[0088] In one example, if Figure 1N As shown, the first electrode includes a lower contact portion 102 and a conductor layer 101, and the lower contact portion 102 is located between the conductor layer 101 and the channel layer 108. Exemplarily, the material of the conductor layer 101 includes but is not limited to tungsten, polysilicon, doped polysilicon, tantalum nitride, tantalum, copper, etc. Exemplarily, the lower contact portion 102 is arranged corresponding to the conductor layer 101, and is used to reduce the resistance of the electrical connection channel between the conductor layer 101 and the channel layer 108. The material of the lower contact portion 102 can be a contact material layer, including but not limited to cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc., the present application is not limited thereto, and the material combination of the channel layer 108, the conductor layer 101 and the lower contact portion 102 can be set according to actual needs.

[0089] In one example, the second electrode includes a first portion in contact with the channel layer 108, and a second portion located on a side of the first portion away from the channel layer 108. More specifically, Figure 1N As shown, the second electrode includes an upper contact portion 109 and a connecting portion 118 , wherein the upper contact portion 109 is a first portion of the second electrode in contact with the channel layer 108 , and the connecting portion 118 is a second portion of the second electrode located away from the channel layer 108 and away from the first portion.

[0090] Exemplarily, the materials of the upper contact 109 and the connecting portion 118 may be the same or different. The material of the upper contact 109 may be a contact material layer, including but not limited to cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc. When the materials of the upper contact 109 and the connecting portion 118 are different, the material of the connecting portion 118 may include but not limited to tungsten, polysilicon, doped polysilicon, tantalum nitride, tantalum, copper, etc., wherein the upper contact 109 is used to reduce the resistance of the electrical connection channel between the channel layer 108 and the connecting portion 118; or the material of the connecting portion 118 may also be a contact material layer, including but not limited to cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc. Exemplarily, the materials of the lower contact 102, the upper contact 109 and the connecting portion 118 are the same, and are all contact material layers; or the material of the lower contact 102 and the material of the second electrode are both contact material layers, but the materials are different.

[0091] Exemplarily, the upper contact portion 109 has the same shape as the channel layer 108 (ie, has the same horizontal cross-sectional shape), such as Figure 2G As shown, the shape of the connection portion 118 can be circular, or the shape of the connection portion 118 can also be rectangular or long strip. Exemplarily, the connection portions 118 above different channel layers 108 are independently arranged, and the connection portions 118 can be used to increase the contact area and reduce the resistance. Exemplarily, the connection portion 118 is independently connected to the storage structure above, and taking the semiconductor device as a DRAM memory including a 1T1C unit structure as an example, each connection portion 118 can be connected to a capacitor (storage structure). Exemplarily, the semiconductor device of the present application is not limited to the 1T1C structure, and can also be applied to memories of other unit structures (for example, 1T3C, 2T0C, etc.), and the present application is not limited to this. Exemplarily, the first electrode is equivalent to the source of the transistor, the gate electrode 113 is equivalent to the gate of the transistor, and the second electrode can serve as the drain of the transistor, and the second electrode (the connection portion 118 in the second electrode) is directly connected to the capacitor (taking the 1T1C unit structure as an example); or another film layer can be formed on the second electrode to serve as the drain of the transistor; the present application is not limited to this.

[0092] In one example, if Figure 1NAs shown, the semiconductor device further includes a first insulating layer 116, which is prepared in the same layer as the gate insulating layer 115 and extends horizontally between the first electrode and the gate electrode 113. Specifically, the first insulating layer 116 is located between the lower contact portion 102 and the gate electrode 113. Exemplarily, the materials of the gate insulating layer 115 and the first insulating layer 116 include but are not limited to silicon oxide, silicon oxynitride, etc. Exemplarily, the first insulating layer 116 contacts the first electrode. Exemplarily, the first insulating layer 116 contacts the gate electrode 113.

[0093] In one example, if Figure 1N As shown, the distance between one end of the channel layer 108 contacting the second electrode (i.e., one end of the channel layer 108 contacting the upper contact portion 109) and the gate electrode 113 is smaller than the distance between one end of the gate insulating layer 115 contacting the second electrode (i.e., one end of the gate insulating layer 115 contacting the connecting portion 118) and the gate electrode 113, where the distance refers to the distance in the vertical direction.

[0094] In one example, if Figure 1N As shown, the semiconductor device of the present application further includes an insulating dielectric layer 114, which is located between the second portion of the second electrode (i.e., the connecting portion 118) and the gate electrode 113, and the orthographic projection of the insulating dielectric layer 114 on the substrate 100 does not overlap with the channel structure. Exemplarily, the insulating dielectric layer 114 covers the gate electrode 113 and the channel structure. Exemplarily, the insulating dielectric layer 114 can be made of conventional insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant materials, etc., and the present application does not limit this.

[0095] In one example, the semiconductor device further includes a first signal line, the first signal line is formed integrally with the first electrode and extends along the first horizontal direction, and the orthographic projection of the first electrode on the substrate 100 is located within the first signal line. Exemplarily, the first electrode is arranged corresponding to the first signal line and the two edges of the orthographic projection on the substrate 100 completely overlap, but not limited thereto, in some embodiments, the orthographic projection of the first electrode on the substrate 100 is completely within the range of the first signal line and does not overlap with the edge of the first signal line.

[0096] Exemplarily, the signal line electrically connected to the first electrode includes the same structure as the first electrode, that is, the conductor layer and the lower contact portion located on the side of the conductor layer close to the channel layer 108. It can be understood that only the materials and film structures are the same. The present application is not limited to this. In some embodiments, the first signal line only includes a conductor layer in the same layer as the conductor layer 101, which can be determined according to specific circumstances.

[0097] Exemplarily, in a DRAM memory having a 1T1C memory cell structure arranged in an array and a semiconductor device, the first signal line is a bit line (BL).

[0098] In one example, if Figure 3F As shown, the orthographic projection boundary of the channel layer 108 on the substrate 100 exceeds the lower contact portion 102, that is, the orthographic projection boundary of the channel layer 108 on the substrate 100 exceeds the first electrode, and the first electrode is formed integrally with the first signal line, then the orthographic projection boundary of the channel layer 108 on the substrate 100 exceeds the first signal line.

[0099] Optionally, the orthographic projection boundary of the channel layer 108 on the substrate 100 just overlaps with a portion of the edge of the first signal line and does not exceed the boundary of the first signal line, such as Figure 2B shown.

[0100] Exemplarily, the orthographic projection boundary of the channel layer 108 on the substrate 100 does not exceed the gate electrode 113 .

[0101] In one example, if Figure 3A , Figure 3B As shown in FIG. 1 , the orthographic projection of the channel structure on the substrate 100 includes a ring shape, and the orthographic projection of the gate electrode 113 on the substrate 100 includes a third portion 130 located inside the ring shape and a fourth portion 140 located outside the ring shape. Figure 1N The insulating dielectric layer 114 also includes a portion located within the ring shape, and the insulating dielectric layer 114 is located between the gate electrode 113 and the connecting portion 118 in the vertical direction.

[0102] In one example, if FIG. 3C to FIG. 3F As shown, the orthographic projection of the channel structure on the substrate 100 includes a plurality of fifth portions 150 , the gate electrode 113 includes a sixth portion 160 surrounding each fifth portion 150 , and the sixth portions 160 in a gate electrode 113 are formed as one body.

[0103] Specifically, Figure 3D , Figure 3E and Figure 3F As shown, the orthographic projections of the fifth portion 150 on the substrate 100 are strip-shaped and parallel to each other; or Figure 3C As shown, the orthographic projection of the fifth portion 150 on the substrate 100 is a ring, and the gate electrode 113 further includes a seventh portion 170 located inside the ring.

[0104] In one example, if Figure 3E and Figure 3F As shown, the orthographic projection of the channel structure on the substrate 100 includes a rectangle.

[0105] Exemplarily, the orthographic projection of the channel structure on the substrate 100 is completely located within the orthographic projection range of the gate electrode 113 and is at least partially located within the orthographic projection range of the first electrode.

[0106] When the channel structure is prepared before the gate electrode, good crystal characteristics can be obtained, thereby improving electrical performance; further, when the orthographic projection of the channel structure on the substrate 100 is a plurality of strips, the control area of ​​the gate electrode can be increased, the channel area can be increased, leakage can be improved, and the working current can be increased, or, when the orthographic projection of the channel structure on the substrate 100 is a ring, a uniform current distribution can be obtained; further, when the orthographic projection of the channel structure on the substrate 100 is a plurality of rings, the control area of ​​the gate electrode can be increased, the channel area can be increased, and a uniform current distribution can be obtained. In some embodiments not shown, the orthographic projection of the channel structure on the substrate also includes a plurality of solid circles or a plurality of rectangles, and the present application does not limit the specific shape of the orthographic projection of the fifth part 150 on the substrate 100.

[0107] In one example, the semiconductor device of the present application can be connected to the storage structure above it to form a memory. Taking the 1T1C unit structure as an example, when it is necessary to read the information stored in a certain unit structure, it is only necessary to pass a high level to the word line of the unit, and the level state of the capacitor of the unit will be added to the corresponding bit line. The bit line is connected to the read-write drive circuit, and the level state of the capacitor can be read by the read-write drive circuit to complete the reading of the information; or, the read-write drive circuit outputs a high level or a low level to charge or discharge the capacitor to complete the writing of the information.

[0108] This completes the introduction to the semiconductor device of the present application. The complete semiconductor device may also include other components and structures, which will not be described in detail here.

[0109] In summary, the semiconductor device of the present application has a channel layer with better crystallization characteristics. At the same time, the channel layer can have a variety of shape structures. The channel layer is no longer limited to a circular ring shape, which can increase the channel area, help improve leakage and increase the operating current, thereby improving the electrical performance of the semiconductor device.

[0110] Below, reference Figures 1A to 4 The manufacturing method of the semiconductor device of the present application is described in detail, wherein: Figure 1A-Figure 1N A schematic cross-sectional view of a device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application along a first horizontal direction and a second horizontal direction is shown. Figure 2A-2G A schematic top view of a device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown. Figure 3A-Figure 3F FIG. 1 is a schematic diagram of an orthographic projection of a semiconductor device according to a specific embodiment of the present application. Figure 4 The flowchart of a method for manufacturing a semiconductor device according to a specific embodiment of the present application is shown. For example, Figure 1A-Figure 1N FIG. (a) shows a cross-sectional view of a semiconductor device along a first direction. Figure 1A-Figure 1N Figure (b) shows a schematic cross-sectional view of the semiconductor device along the second direction, wherein the first horizontal direction intersects the second horizontal direction, and optionally, the first horizontal direction is perpendicular to the second horizontal direction.

[0111] For example, Figure 4 As shown, the method for manufacturing a semiconductor device of the present application includes the following steps:

[0112] First, execute step S1, such as Figure 1A As shown, a substrate 100 is provided.

[0113] The semiconductor device of the present application may be any suitable type of device known to those skilled in the art. In this embodiment, the technical solution of the present application is explained and illustrated mainly by taking the case where the semiconductor device is a DRAM as an example.

[0114] In one example, the substrate 100 is a substrate with at least a surface insulation, at least the surface and the first electrode are insulated. The substrate 100 may be an entirely insulated substrate, or a composite substrate including a surface insulation layer and a semiconductor substrate, a semiconductor substrate having transistors formed therein, etc. Although several examples of the substrate 100 are described herein, any material / structure that can be used as a substrate falls within the spirit and scope of the present application.

[0115] Next, perform step S2: prepare a first electrode, a channel layer, a gate insulating layer and a gate electrode in sequence on the substrate 100, and prepare a second electrode on the substrate 100; the channel layer extends in a vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer.

[0116] In one example, if Figure 1A and Figure 2A As shown, firstly, a first electrode is prepared, and the first electrode includes a conductor layer 101 and a lower contact portion 102 located on a side of the conductor layer away from the substrate 100. Exemplarily, the material of the conductor layer 101 includes, but is not limited to, tungsten, polysilicon, doped polysilicon, tantalum nitride, tantalum, copper, etc. Exemplarily, the lower contact portion 102 is arranged corresponding to the conductor layer 101, and the material of the lower contact portion 102 includes, but is not limited to, cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc. Exemplarily, the conductor layer 101 and the lower contact portion 102 can be formed by a deposition method commonly used in the art, for example, they can be formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method, or an atomic layer deposition (ALD) method, etc., and the present application does not limit this.

[0117] In one example, the method of the present application further includes: preparing a first signal line, the first signal line and the first electrode are prepared simultaneously, and the orthographic projection of the first electrode on the substrate 100 is located within the first signal line. Exemplarily, the first signal line is formed integrally with the first electrode and extends along the first horizontal direction, and the first signal line is a bit line (BL). Exemplarily, the orthographic projection of the first electrode on the substrate 100 coincides with two edges of the first signal line.

[0118] Optionally, the method further includes forming an insulating layer between the first electrodes and making the surface of the insulating layer flush with the first electrodes. The insulating layer is formed as a part of the substrate 100 .

[0119] In one example, after the first electrode is formed, the channel layer is prepared. Specifically, Figures 1B to 1E as well as Figure 2B As shown, preparing the channel layer 108 includes:

[0120] First, if Figure 1B As shown, a semiconductor material layer 103 is prepared on the first electrode, and the semiconductor material layer 103 covers the surface of the first electrode and the substrate 100. Exemplarily, after the semiconductor material layer 103 is prepared, the method of the present application further includes the steps of: performing a heat treatment to reduce the impedance between the semiconductor material layer 103 and the lower contact portion 102; at the same time, the heat treatment process can also change the crystallization characteristics of the semiconductor material layer 103, for example, when the semiconductor material layer 103 includes amorphous silicon, the amorphous silicon can be converted into crystalline silicon, such as polycrystalline silicon, by the heat treatment process; the above-mentioned heat treatment can adopt various known heat treatment processes in the art, such as rapid thermal annealing, etc. Since the semiconductor material layer 103 used to prepare the channel layer 108 is prepared before the gate electrode, its heat treatment can make it have better crystallization characteristics.

[0121] Then, if Figure 1D As shown, a first patterned mask layer 107 is prepared on the semiconductor material layer 103 .

[0122] Take the preparation of the annular channel layer 108 as an example. Figure 1C and Figure 1DAs shown, preparing the first patterned mask layer 107 includes: sequentially preparing a first dielectric layer 105 and a second dielectric layer 106 on the semiconductor material layer 103, wherein a plurality of through holes exposing the semiconductor material layer 103 are formed in the first dielectric layer 105, and the second dielectric layer 106 covers the bottom and side walls of the through holes and the surface of the first dielectric layer 105; then, removing the second dielectric layer 106 at the bottom of the through holes and on the surface of the first dielectric layer 105, retaining the second dielectric layer 106 located on the side walls of the through holes as the first patterned mask layer 107, and removing the first dielectric layer 105. However, the present invention is not limited thereto, as long as the first patterned mask layer 107 in a ring shape can be formed.

[0123] By way of example, the thickness of the first patterned mask layer 107 in the horizontal direction can be defined, that is, the thickness of the second dielectric layer 106 is controlled to define the thickness of the formed channel layer 108 in the horizontal direction. By way of example, the first dielectric layer 105 and the second dielectric layer 106 can be made of conventional insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc., as long as the two have a suitable etching selectivity ratio, and the present application does not impose any limitation thereto.

[0124] Then, if Figure 1E As shown, the semiconductor material layer 103 is etched with the first patterned mask layer 107 as a mask to form a channel layer 108. By way of example, various etching processes commonly used in the art can be used to etch the semiconductor material layer 103 with the first patterned mask layer 107 as a mask, and the present application does not limit this. It can be understood that the shape of the formed channel layer 108 can be defined by defining the shape of the first patterned mask layer 107, that is, the channel layer 108 has the same shape as the first patterned mask layer 107 in the orthographic projection on the substrate 100.

[0125] In one example, the orthographic projection of the first patterned mask layer 107 on the substrate 100 coincides with the orthographic projection of the channel layer 108 on the substrate 100. FIG. 3A to FIG. 3F As shown, the orthographic projection of the channel layer 108 on the substrate 100 may include at least one portion, the orthographic projection of the portion on the substrate 100 includes a ring or a rectangle; and / or, the orthographic projection of the channel layer 108 on the substrate 100 includes a plurality of parallel strips. That is, the orthographic projection of the first patterned mask layer 107 on the substrate 100 may include at least one portion, the orthographic projection of the portion on the substrate 100 includes a ring or a rectangle; and / or, the orthographic projection of the first patterned mask layer 107 on the substrate 100 includes a plurality of parallel strips.

[0126] In one example, the orthographic projection boundary of the first patterned mask layer 107 on the substrate 100 may exceed the first signal line, that is, the orthographic projection of the first patterned mask layer 107 on the substrate 100 only needs to be at least partially located within the first signal line.

[0127] In one example, the orthographic projection boundary of the annular first patterned mask layer 107 on the substrate 100 partially overlaps with the boundary of the first signal line. Figure 2B As shown, the orthographic projection boundary of the annular channel layer 108 on the substrate 100 partially overlaps with the boundary of the first signal line.

[0128] It can be understood that in the prior art, after etching the gate to form a channel hole, a gate insulating layer and a channel layer are sequentially prepared in the channel hole. In order to reduce defects at the bottom of the channel hole etching, the bottom surface of the channel hole is usually completely located in the signal line, so that the channel width is small and the electrical performance is reduced. The present application can further expand the channel width by first making the channel layer, then making the gate insulating layer and the gate electrode, so that the boundary of the channel layer can overlap with the signal line or even exceed the signal line, thereby improving the electrical performance of the semiconductor device, that is, the transistor.

[0129] In one example, if Figures 1B to 1E As shown, preparing the second electrode includes: preparing a contact material layer 104 on the semiconductor material layer 103 before preparing the first patterned mask layer 107; while etching the semiconductor material layer 103 using the first patterned mask layer 107 as a mask, patterning the contact material layer 104 to form an upper contact portion 109; the second electrode includes the upper contact portion 109. Exemplarily, the material of the upper contact portion 109 includes but is not limited to cobalt silicide, nickel silicide, titanium silicide, tungsten silicide, doped polysilicon, etc.

[0130] In one example, after the contact material layer 104 is prepared on the semiconductor material layer 103, the method of the present application further includes: heat treatment to reduce the impedance between the semiconductor material layer 103 and the contact material layer 104. Exemplarily, after the semiconductor material layer 103 is formed on the lower contact portion 102, the heat treatment may not be performed first, and the heat treatment may be performed after the contact material layer 104 is prepared, so as to simultaneously reduce the impedance between the semiconductor material layer 103 and the contact material layer 104, and between the semiconductor material layer 103 and the lower contact portion 102, and improve the crystallization characteristics of the semiconductor material layer 103.

[0131] In one example, the present application performs a heat treatment process after forming the semiconductor material layer 103 (when forming the contact material layer 104, the heat treatment process is performed after the contact material layer 104 is formed). Compared with the related art of filling the holes obtained by etching the WL control layer with channel materials to form a channel layer and then performing a heat treatment process, the channel layer 108 of the present application has better crystallization characteristics and lower impedance with the upper contact portion 109 and the lower contact portion 102, thereby improving the electrical performance of the device.

[0132] In one example, the present application first forms a semiconductor material layer 103, and then etches the semiconductor material layer 103 to obtain a channel layer 108, which can improve the shape structure of the channel layer 108, so that the channel layer 108 is no longer limited to a circular ring shape, for example, it can also be a plurality of long strips, etc., which can increase the channel area, improve leakage and increase the working current, and thus improve the electrical performance of the device.

[0133] In one example, after forming the channel layer 108, preparing the gate insulating layer 115 and the gate electrode 113 includes:

[0134] First, if Figure 1F and Figure 2C As shown, a gate insulating material layer 110 is prepared, and the gate insulating material layer 110 covers the channel layer 108, the upper contact portion 109, the first electrode and the first signal line. Exemplarily, the gate insulating material layer 110 can be formed by a deposition method commonly used in the art, for example, it can be formed by a chemical vapor deposition (CVD) method, a physical vapor deposition (PVD) method or an atomic layer deposition (ALD) method, etc., and this application is not limited to this. Exemplarily, the material of the gate insulating material layer 110 includes but is not limited to silicon oxide, silicon oxynitride, etc.

[0135] Illustratively, the first insulating layer 116 and the gate insulating layer 115 are prepared simultaneously.

[0136] Then, if Figure 1G As shown, a gate electrode material layer 111 is prepared, and the gate electrode material layer 111 covers the gate insulating material layer 110. Exemplarily, the gate electrode material layer 111 may be formed by a deposition method commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), and the present application does not limit this.

[0137] Then, if Figure 1J and Figure 2E As shown, the gate electrode material layer 111 is patterned and etched to form a gate electrode 113. Optionally, the surface of the gate electrode 113 away from the substrate 100 is lower than the channel layer 108. Specifically, the gate electrode 113 is formed by: first, Figure 1H As shown, a portion of the gate electrode material layer 111 is etched back to remove so that the surface of the gate electrode material layer 111 away from the substrate 100 is lower than the channel layer 108; then, as shown in Fig. 1I and Figure 2DAs shown, a second patterned mask layer 112 is formed on the gate electrode material layer 111, and the second patterned mask layer 112 is used to pattern and prepare the gate electrode 113. Optionally, the second patterned mask layer 112 extends along the second horizontal direction so as to simultaneously prepare the gate electrode 113 and a signal line connected to the gate electrode 113, such as a word line WL; finally, as shown Figure 1J As shown, the second patterned mask layer 112 is used as a mask to etch away the exposed remaining gate electrode material layer 111 to form a gate electrode 113. Exemplarily, the material of the gate electrode 113 includes but is not limited to tungsten, polysilicon, doped polysilicon, tantalum nitride, tantalum, copper, etc.

[0138] Then, if Figure 1K As shown, an insulating dielectric layer 114 is prepared, and the insulating dielectric layer 114 covers the gate insulating material layer 110 and the gate electrode 113. By way of example, the insulating dielectric layer 114 can be formed by a deposition method commonly used in the art, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD), etc., and the present application does not limit this. By way of example, the insulating dielectric layer 114 can be made of conventional insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, etc., and the present application does not limit this.

[0139] Finally, if Figure 1L and Figure 2F As shown, part of the insulating dielectric layer 114 and part of the gate insulating material layer 110 are removed to expose the upper contact portion 109, and the gate insulating material layer located on the side of the gate electrode 113 close to the channel layer 108 is formed as a gate insulating layer 115. Exemplarily, the gate insulating material layer located between the gate electrode 113 and the first electrode becomes the first insulating layer 116. In one embodiment, the removal process is chemical mechanical polishing (CMP), and the end point of the polishing is the upper contact portion 109, or the polishing also removes part of the thickness of the upper contact portion 109. The present application does not impose specific restrictions on the removal process. By setting the upper contact portion, it is avoided that the side of the channel layer 108 close to the second electrode is damaged due to the manufacturing process and affects the electrical performance.

[0140] In one example, in the orthographic projection on the substrate 100: the first patterned mask layer 107 includes a ring, and the gate electrode 113 includes a portion located inside the ring and a portion located outside the ring; or, the first patterned mask layer 107 includes multiple portions, and the gate electrode surrounds each of the portions. Specifically, since the orthographic projection of the first patterned mask layer 107 on the substrate 100 is the same as the orthographic projection of the channel layer 108 on the substrate 100, the orthographic projection of the channel layer 108 on the substrate 100 can be used to represent the orthographic projection of the first patterned mask layer 107 on the substrate 100:

[0141] In one example, if Figure 3A As shown, the orthographic projection of the channel layer 108 on the substrate 100 includes a ring shape, and the orthographic projection of the gate electrode 113 on the substrate 100 includes a third portion 130 located inside the ring shape and a fourth portion 140 located outside the ring shape.

[0142] In one example, if Figures 3D to 3F As shown, the orthographic projection of the channel layer 108 on the substrate 100 includes a plurality of fifth portions 150, the gate electrode 113 includes a sixth portion 160 surrounding each fifth portion 150, and the sixth portions 160 in a gate electrode 113 are formed as one body. Figure 3D , Figure 3E and Figure 3F As shown, the orthographic projections of the fifth portion 150 on the substrate 100 are strip-shaped and parallel to each other; or Figure 3C As shown, the orthographic projection of the fifth portion 150 on the substrate 100 is a ring, and the gate electrode 113 further includes a seventh portion 170 located inside the ring. Exemplarily, the orthographic projection of the channel structure on the substrate 100 is completely located within the orthographic projection range of the gate electrode 113 and at least partially located within the orthographic projection range of the first electrode.

[0143] In one example, preparing the second electrode further comprises: Figure 1N and Figure 2G As shown, after the upper contact portion 109 is exposed, a connecting portion 118 is prepared at one end of the upper contact portion 109 away from the channel layer 108, and the second electrode also includes the connecting portion 118. Specifically, preparing the connecting portion 118 includes: first, as shown in Figure 1M As shown, a material layer 117 for preparing a connecting portion 118, such as a conductor layer or a contact material layer, is first deposited on the upper contact portion 109 and the insulating dielectric layer 114; Figure 1N As shown, the material layer 117 is patterned to obtain connecting portions 118 that are independently arranged. Figure 2GAs shown, the shape of the connection portion 118 can be circular, or the shape of the connection portion 118 can also be rectangular or long strip, which can be set according to actual needs. Exemplarily, the connection portions 118 above different channel layers 108 are independently set, and the connection portions 118 can be used to increase the contact area and reduce the resistance. Exemplarily, the connection portion 118 is independently connected to the storage structure above. Taking the 1T1C unit structure as an example, each connection portion 118 can be connected to a capacitor. Exemplarily, the semiconductor device of the present application is not limited to the 1T1C structure, but can also be applied to memories of other unit structures (for example, 1T3C, 2T0C, etc.), and the present application does not limit this. Exemplarily, the first electrode is equivalent to the source of the transistor, the gate electrode 113 is equivalent to the gate of the transistor, and the second electrode can serve as the drain of the transistor; or another film layer can be formed on the second electrode to serve as the drain of the transistor; or a film layer serving as the drain of the transistor can be formed without forming the film layer, and the second electrode (the connection portion 118 in the second electrode) is directly connected to the capacitor (taking the 1T1C unit structure as an example).

[0144] In one example, the semiconductor device of the present application may also include a storage structure located on the second electrode and electrically connected to the second electrode to constitute a storage unit. The storage unit array is arranged to form a memory. Taking the 1T1C unit structure as an example, when it is necessary to read the information stored in a certain unit structure, it is only necessary to pass a high level to the word line of the unit, and the level state of the capacitor of the unit will be added to the corresponding bit line. The bit line is connected to the read-write drive circuit, and the level state of the capacitor can be read by the read-write drive circuit to complete the reading of the information; or, the read-write drive circuit outputs a high level or a low level to charge or discharge the capacitor to complete the writing of the information.

[0145] The description of the key steps of the method for manufacturing the semiconductor device of the present application has been completed. The preparation of a complete semiconductor device may also include other steps, which will not be described one by one here. It is worth mentioning that the above steps are only used as examples, and the order of the above steps can be adjusted without conflict.

[0146] In summary, the manufacturing method of the semiconductor device of the present application advances the process of the channel layer, forms the channel layer first, and then forms the gate electrode, which can improve the crystallization characteristics of the channel layer, and at the same time improve the shape structure of the channel layer, so that the channel layer is no longer limited to a circular ring shape, and can increase the channel area, which helps to improve leakage and increase the operating current, thereby improving the electrical performance of the semiconductor device.

[0147] Although multiple embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be conceived by those skilled in the art, all of which will fall within the spirit and scope of the concepts disclosed herein. More particularly, various modifications and changes may be made to the arrangements and / or components of the combined arrangements of the subject matter within the scope of the disclosure, drawings, and appended claims of the present application. In addition to modifications and changes to the components and / or arrangements, the use of alternatives is also an obvious option for those skilled in the art.

Claims

1. A semiconductor device, characterized in that: include: A substrate, and a semiconductor device located on the substrate; The semiconductor device includes a channel structure and a first electrode, a gate electrode and a second electrode spaced apart and stacked sequentially in a vertical direction, the channel structure includes a channel layer and a gate insulating layer, the channel structure extends through the gate electrode in the vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer.

2. The semiconductor device according to claim 1, wherein The semiconductor device further includes a first insulating layer, which is prepared at the same layer as the gate insulating layer and horizontally extends between the first electrode and the gate electrode.

3. The semiconductor device according to claim 2, wherein: The first insulating layer contacts the first electrode.

4. The semiconductor device according to claim 2, wherein: The first insulating layer contacts the gate electrode.

5. The semiconductor device according to claim 2, wherein: The distance between one end of the channel layer connected to the second electrode and the gate electrode is smaller than the distance between one end of the gate insulating layer contacting the second electrode and the gate electrode.

6. The semiconductor device according to claim 5, wherein: The second electrode includes a first portion in contact with the channel layer, and a second portion located on a side of the first portion away from the channel layer; The semiconductor device further includes an insulating dielectric layer, which is located between the second portion and the gate electrode, and an orthographic projection of the insulating dielectric layer on the substrate does not overlap with the channel structure.

7. The semiconductor device according to claim 2, wherein: The semiconductor device further includes a first signal line, which is formed integrally with the first electrode and extends along a first horizontal direction, and an orthographic projection of the first electrode on the substrate is located within the first signal line.

8. The semiconductor device according to claim 7, wherein: The orthographic projection boundary of the channel layer on the substrate exceeds the first signal line; or An orthographic projection boundary of the channel layer on the substrate overlaps with an edge portion of the first signal line and does not exceed the first signal line.

9. The semiconductor device according to claim 1, wherein: The orthographic projection of the channel structure on the substrate includes a ring shape, and the orthographic projection of the gate electrode on the substrate includes a third portion located inside the ring shape and a fourth portion located outside the ring shape.

10. The semiconductor device according to claim 1, wherein The orthographic projection of the channel structure on the substrate includes a plurality of fifth portions, the gate electrode includes a sixth portion surrounding each of the fifth portions, and the sixth portion in a gate electrode is formed as a whole.

11. The semiconductor device according to claim 10, wherein: The orthographic projections of the fifth portion on the substrate are strips and parallel to each other; or The orthographic projection of the fifth portion on the substrate is a ring shape, and the gate electrode further includes a seventh portion located inside the ring shape.

12. The semiconductor device according to claim 1, wherein The first electrode comprises a first contact material layer and a conductor layer, wherein the first contact material layer is located between the conductor layer and the channel layer; The second electrode includes a second contact material layer.

13. A method for manufacturing a semiconductor device, characterized in that: The steps include: providing a substrate; Sequentially preparing a first electrode, a channel layer, a gate insulating layer and a gate electrode on the substrate; preparing a second electrode on the substrate; The channel layer extends in a vertical direction and is connected between the first electrode and the second electrode, and the gate insulating layer is located between the gate electrode and the channel layer.

14. The method according to claim 13, characterized in that The step of preparing the channel layer comprises: preparing a semiconductor material layer on the first electrode; preparing a first patterned mask layer on the semiconductor material layer; The semiconductor material layer is etched using the first patterned mask layer as a mask to form the channel layer.

15. The method according to claim 14, characterized in that The first patterned mask layer includes at least one portion, the orthographic projection of the portion on the substrate includes a ring or a rectangle; and / or An orthographic projection of the first patterned mask layer on the substrate includes a plurality of parallel strips.

16. The method according to claim 14, characterized in that The step of preparing the second electrode comprises: Before preparing the first patterned mask layer, preparing a contact material layer on the semiconductor material layer; While etching the semiconductor material layer using the first patterned mask layer as a mask, patterning the contact material layer to form an upper contact portion; The second electrode includes the upper contact portion.

17. The method according to claim 16, characterized in that The method further includes: preparing a first signal line, the first signal line and the first electrode are prepared simultaneously, and the orthographic projection of the first electrode on the substrate is located within the first signal line; Preparing the gate insulating layer and the gate electrode comprises: preparing a gate insulating material layer, wherein the gate insulating material layer covers the channel layer, the upper contact portion, the first electrode and the first signal line; preparing a gate electrode material layer, wherein the gate electrode material layer covers the gate insulating material layer; Patterning and etching the gate electrode material layer to form the gate electrode, wherein a surface of the gate electrode away from the substrate is lower than the channel layer; preparing an insulating dielectric layer, wherein the insulating dielectric layer covers the gate insulating material layer and the gate electrode; A portion of the insulating dielectric layer and a portion of the gate insulating material layer are removed to expose the upper contact portion, and the gate insulating material layer located on a side of the gate electrode close to the channel layer is formed as the gate insulating layer.

18. The method according to claim 17, characterized in that The preparing the second electrode further comprises: After the upper contact portion is exposed, a connection portion is prepared at one end of the upper contact portion away from the channel layer, and the second electrode further includes the connection portion.

19. The method according to claim 17, characterized in that In orthographic projection on the substrate: The first patterned mask layer includes a ring shape, and the gate electrode includes a portion located inside the ring shape and a portion located outside the ring shape; or The first patterned mask layer includes a plurality of portions, and the gate electrode surrounds each of the portions.

20. The method of claim 16, wherein: The method further includes: preparing a first signal line, the first signal line and the first electrode are prepared simultaneously, and the orthographic projection of the first electrode on the substrate is located within the first signal line; An orthographic projection boundary of the first patterned mask layer on the substrate exceeds the first signal line, or overlaps with an edge portion of the first signal line and does not exceed the first signal line.

21. The method of claim 14, wherein: The first electrode comprises a conductor layer and a lower contact portion located on a side of the conductor layer away from the substrate; After preparing the semiconductor material layer, the method further comprises the step of: performing a heat treatment so as to reduce the resistance between the semiconductor material layer and the lower contact portion.

22. The method of claim 16, wherein: After preparing the contact material layer on the semiconductor material layer, the method further comprises the step of: performing a heat treatment so as to reduce the impedance between the semiconductor material layer and the contact material layer.

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