Semiconductor element
By placing the capacitor in the edge virtual block of the memory block in the semiconductor component, the problem of capacitor space occupied by the three-dimensional NAND flash memory chip is solved, and the chip area saving and capacity improvement are achieved.
Patent Information
- Application Number
- CN202410014463.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-09-27
- Filing Date
- 2024-01-04
- Publication Date
- 2025-03-28
AI Technical Summary
In a three-dimensional NAND flash memory chip, capacitors occupy the existing space of the peripheral circuit area and memory area, resulting in a waste of chip area.
On the substrate of the semiconductor element, a plurality of memory array regions and virtual blocks are provided, and the capacitors are placed in the edge virtual blocks of the memory block, rather than in the peripheral circuit region or memory region.
In this way, the capacitor does not occupy the area of the peripheral circuit area and memory area, thereby saving the total area of the chip. At the same time, due to the design of the stacking structure, the capacitor can have a larger capacity.
Smart Images
Figure CN119730256A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to an integrated circuit, and more particularly to a semiconductor device including a memory and a capacitor. Background Art
[0002] Non-volatile memory elements (eg, flash memory) have become a widely used memory element in personal computers and other electronic devices because they have the advantage that stored data will not disappear even after power is turned off.
[0003] The flash memory arrays that are currently more commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each storage unit in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory. For example, the current three-dimensional NAND flash memory chip will be equipped with a capacitor, but the capacitor will occupy the space of the existing peripheral circuit area. Summary of the invention
[0004] The present invention provides a semiconductor element, which can be provided with a capacitor without increasing the area.
[0005] An embodiment of the present invention provides a semiconductor device, comprising a substrate, a plurality of memory arrays, and a plurality of capacitors. The substrate comprises a plurality of memory array regions, each of the memory array regions comprises a plurality of memory blocks and a plurality of virtual blocks, and the plurality of virtual blocks are located at the edges of the plurality of memory blocks. A plurality of memory arrays are arranged in the plurality of memory blocks. A plurality of capacitors are arranged in the plurality of virtual blocks at the edges of the plurality of memory blocks.
[0006] An embodiment of the present invention provides a semiconductor element, comprising a substrate, a stacking structure, a plurality of memory arrays, and a plurality of capacitors. The stacking structure is above the substrate, and the stacking structure comprises a plurality of insulating layers and a plurality of conductive layers alternately stacked with each other. The plurality of memory arrays are arranged in the stacking structure. The plurality of capacitors are arranged in the stacking structure and adjacent to the plurality of memory arrays.
[0007] Based on the above, the embodiment of the present invention sets the capacitor in the stacked structure of the virtual block, not in the peripheral circuit area, nor in the memory block. Since the capacitor of the present invention does not occupy the area of the peripheral circuit area and the memory area, the chip area can be saved. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figure 1A It is a cross-sectional schematic diagram of a semiconductor device with a complementary metal oxide semiconductor device under a memory array (CMOS-Under-Array, CUA) structure in a memory block according to an embodiment of the present invention.
[0009] Figure 1B It is a cross-sectional schematic diagram of a semiconductor element with a CUA structure in a virtual block according to an embodiment of the present invention.
[0010] Figure 2A It is a top view of the layout of a semiconductor element according to an embodiment of the present invention.
[0011] Figure 2B It is a top view of a memory array area having a plurality of memory blocks and a plurality of virtual blocks according to an embodiment of the present invention.
[0012] Figure 2C is a top view of multiple virtual blocks according to an embodiment of the present invention.
[0013] Figure 3A It is a partial cross-sectional schematic diagram of a semiconductor element in a memory block according to an embodiment of the present invention.
[0014] Figure 3B It is a partial cross-sectional schematic diagram of a semiconductor element in a virtual block according to an embodiment of the present invention.
[0015] Figure 3C is a cross-sectional schematic diagram of a capacitor disposed in a dummy block according to an embodiment of the present invention.
[0016] Description of Reference Numerals
[0017] 10: Base
[0018] 20: Component layer
[0019] 30, 40: Internal connection structure
[0020] 95: Stop Structure
[0021] 102: Insulation layer
[0022] 108: Charge storage structure
[0023] 108′: Virtual charge storage structure
[0024] 126: Conductor layer
[0025] ARY: memory array
[0026] BLK: memory block
[0027] CL1, CL2: Wire
[0028] COA1, COA2: Contact window
[0029] CSL: Common Source Line
[0030] D1: Dielectric layer
[0031] DBLK: Virtual Block
[0032] DCSL: Virtual Common Source Line
[0033] DSSLC: Virtual Select Source Line Cut Wall
[0034] DVC: Virtual Vertical Channel Column
[0035] E1: First End
[0036] E2: Second end
[0037] ISL: Intermediate Layer
[0038] LP: Lower Level
[0039] MC: Storage Unit
[0040] MIM: Capacitor
[0041] MU: Capacitor Unit
[0042] PL1: First electrode plate
[0043] PL2: Second electrode plate
[0044] R0, R1, R2, R3, R4, R5: Area
[0045] PR: Peripheral circuit
[0046] SB: Subblock
[0047] SDB: Virtual Subblock
[0048] SK: Stacked structure
[0049] SSLC: Select source line cutting wall
[0050] UP: Upper level
[0051] VC: Vertical Channel Column
[0052] WL: Word Line DETAILED DESCRIPTION
[0053] Figure 1AIt is a cross-sectional schematic diagram of a semiconductor device with a complementary metal oxide semiconductor device under a memory array (CMOS-Under-Array, CUA) structure in a memory block according to an embodiment of the present invention. Figure 1B It is a cross-sectional schematic diagram of a semiconductor element with a CUA structure in a virtual block according to an embodiment of the present invention.
[0054] Reference Figure 1A The semiconductor device of the embodiment of the present invention is a complementary metal oxide semiconductor device under memory array (CUA) structure. The CUA structure includes a substrate 10, a lower level LP and an upper level UP. The lower level LP is formed above the substrate 10, and the upper level UP is formed above the lower level LP.
[0055] The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. The lower level LP may include a component layer 20 and an internal connection structure 30. The component layer 20 may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. The transistor may be an N-type metal oxide semiconductor (NMOS) transistor, a P-type metal oxide semiconductor (PMOS) transistor, or a complementary metal oxide semiconductor component (CMOS). The component layer 20 may include a plurality of peripheral circuits PR, a plurality of row decoders and column decoders XDEC, and a plurality of page buffers PB (such as Figure 2A The upper level UP includes a stop structure 95, a stack structure SK, a step structure SC and an inner connection structure 40. The stop structure 95 can be a single layer or a multi-layer semiconductor layer (such as Figure 3A As shown in FIG. 1 ). The stop structure 95 can be used as a source line, and can also be called a common source conductor layer. The stacked structure SK includes a plurality of conductor layers 126 and a plurality of insulating layers 102 that are alternately stacked. The material of the conductor layer 126 includes tungsten. The material of the insulating layer 102 includes silicon oxide. The stacked structure SK includes a memory array ARY composed of a plurality of memory cells MC.
[0056] Reference Figure 1B The upper level UP of the CUA structure of the embodiment of the present invention also includes a plurality of capacitors MIM. The plurality of capacitors MIM are also arranged in the stacked structure SK. The plurality of capacitors MIM and the memory array ARY are arranged in the same upper level UP, so the plurality of capacitors MIM and the memory array ARY have the same height and are laterally adjacent.
[0057] Figure 2A It is a top view of the layout of a semiconductor element according to an embodiment of the present invention. Figure 2B It is a top view of a memory array area having a plurality of memory blocks and a plurality of virtual blocks according to an embodiment of the present invention. Figure 2C is a top view of multiple virtual blocks according to an embodiment of the present invention.
[0058] Reference Figure 2A From a top view, a plurality of peripheral circuits PR, a plurality of row decoders and column decoders XDEC, and a plurality of page buffers PB of the semiconductor element are respectively arranged in regions R0, R1, and R2 of the lower level LP (or regions R0, R1, and R2 of the substrate 10). The memory array ARY is arranged in region R3 of the upper level UP (or region R3 of the substrate 10). A plurality of capacitors MIM are arranged in region R4 of the upper level UP (or region R4 of the substrate 10).
[0059] Reference Figure 2A and Figure 2B , the upper level UP includes a plurality of memory array areas R5 (or a plurality of areas R5 of the substrate 10). Each memory array area R5 includes areas R3 and R4. Area R4 is located at the edge or both sides of area R3. Area R3 has a plurality of memory blocks BLK. Area R4 has a virtual block DBLK. The virtual block DBLK is at the edge of the plurality of memory blocks BLK, for example, on both sides of the plurality of memory blocks BLK. Since the plurality of capacitors MIM are not arranged in the areas R0, R1 or R2 of the lower level LP, they do not occupy the area of the area R2 (or the peripheral circuit area) used to form the plurality of peripheral circuits PR. The plurality of capacitors MIM are arranged in the area R4 of the upper level UP, and the area R4 does not originally form a memory cell. Therefore, the plurality of capacitors MIM do not occupy the area of the memory block BLK used to form the memory cell. In other words, the embodiment of the present invention forms a plurality of capacitors MIM using the stacking structure SK of the virtual blocks DBLK that do not form functional elements or circuits.
[0060] Figure 3A It is a partial cross-sectional schematic diagram of a semiconductor element in a memory block according to an embodiment of the present invention. Figure 3B It is a partial cross-sectional schematic diagram of a semiconductor element in a virtual block according to an embodiment of the present invention.
[0061] Reference Figure 3A and Figure 3B , the multiple memory arrays ARY and the multiple capacitors MIM of the embodiment of the present invention are all arranged in the stack structure SK. The stack structure SK is divided into multiple memory blocks BLK by multiple common source lines CSL, and is divided into multiple virtual blocks DBLK by multiple virtual common source lines DCSL. Each memory block BLK is divided into multiple sub-blocks SB by the selection source line cutting wall SSLC, and each of the multiple virtual blocks DBLK is divided into multiple virtual sub-blocks SDB by the virtual selection source line cutting wall DSSLC.
[0062] A plurality of memory arrays ARY are arranged in a plurality of memory blocks BLK or a plurality of sub-blocks SB. A plurality of capacitors MIM are arranged in a plurality of virtual blocks DBLK or a plurality of virtual sub-blocks SDB. A plurality of components of the virtual block DBLK may be the same as or similar to a plurality of components of the memory block BLK, but a memory cell MC is not formed in the virtual block DBLK, but a capacitor MIM is arranged.
[0063] More specifically, refer to Figure 3A In the stacked structure SK of multiple memory blocks BLK, multiple vertical channels (VC), multiple charge storage structures 108, multiple common source lines CSL, and multiple selection source line cutting walls SSLC extend through. Multiple conductor layers 126 of the stacked structure SK serve as multiple word lines WL. The charge storage structure 108 is set between the word lines WL and the vertical channel pillars VC, and multiple memory cells MC are formed at the intersections thereof. Therefore, in the stacked structure SK, there are multiple memory arrays ARY composed of multiple memory cells MC.
[0064] Reference Figure 3B In the stacked structure SK of multiple virtual blocks DBLK, multiple virtual vertical channel columns DVC, multiple virtual charge storage structures 108′, multiple virtual common source lines DCSL, and multiple virtual selection source line cutting walls DSSLC extend through. Multiple conductor layers 126 of SK in the stacked structure serve as the first electrode plate PL1 and the second electrode plate PL2 of the capacitor MIM. Multiple insulating layers 102 of SK in the stacked structure serve as multiple dielectric layers D1 of the capacitor MIM. The virtual charge storage structure 108′ is arranged between the first electrode plate PL1 and the virtual vertical channel column DVC, and between the second electrode plate PL2 and the virtual vertical channel column DVC, however, no storage cell MC is formed at the intersections thereof.
[0065] Reference Figure 2A and Figure 2C , a plurality of memory arrays ARY are arranged in a stack structure SK of a plurality of memory blocks BLK in region R3. A plurality of capacitors MIM are arranged in a stack structure SK of a dummy block DBLK. A plurality of capacitors MIM are laterally adjacent to the memory array ARY. In this embodiment, referring to Figure 2A There are multiple (for example, two) adjacent virtual blocks DBLK between the multiple memory blocks BLK of two adjacent memory array regions R3, and multiple (for example, two) capacitors MIM arranged in the adjacent virtual blocks DBLK are adjacent to each other.
[0066] Reference Figure 2C, the virtual block DBLK may include multiple virtual sub-blocks SDB. The multiple capacitors MIM of the embodiment of the present invention are arranged in the multiple sub-blocks SDB of the virtual block DBLK. Each capacitor MIM may be composed of a single capacitor unit MU or multiple capacitor units MU. A single capacitor unit MU or multiple capacitor units MU may be arranged in each virtual block DBLK. Figure 2C In the embodiment, each virtual sub-block SDB is provided with a single capacitor unit MU, and the two capacitor units MU of the two virtual sub-blocks SDB of each virtual block DBLK form a capacitor MIM. However, the present invention is not limited to this. Multiple capacitor units MU in the same virtual block DBLK or virtual sub-block SDB can be connected in parallel or in series to form a single capacitor MIM or multiple capacitors MIM. Multiple capacitor units MU in different virtual blocks DBLK can also be connected in parallel or in series to form a single capacitor MIM or multiple capacitors MIM. In other words, the present invention can design capacitors with various different capacitances, which is very flexible in application.
[0067] For example, refer to Figure 3A , the memory array ARY includes a plurality of odd word lines WLn+1, a plurality of even word lines WLn, and a plurality of separation layers ISL separating the plurality of odd word lines WLn+1 and the plurality of even word lines WLn. For example, referring to Figure 3B , the capacitor MIM includes a plurality of first electrode plates PL1, a plurality of second electrode plates PL2, and a plurality of dielectric layers D1. The plurality of first electrode plates PL1 are electrically connected to each other. The plurality of second electrode plates PL2 are electrically connected to each other. A dielectric layer D1 is sandwiched between adjacent first electrode plates PL1 and a plurality of second electrode plates PL2. The height of the plurality of first electrode plates PL1 is, for example, the same as the height of a plurality of odd word lines WLn+1. The height of the plurality of second electrode plates PL2 is, for example, the same as the height of a plurality of even word lines WLn. The height of the plurality of dielectric layers D1 is the same as the height of a plurality of separation layers ISL. In some embodiments, the first portion of the plurality of odd conductor layers 126 of the stacked structure SK serves as a plurality of first electrode plates PL1, and the second portion of the plurality of odd conductor layers 126 of the stacked structure SK serves as a plurality of odd word lines WLn+1, and are insulated from each other. Similarly, the first portion of the plurality of even conductor layers 126 of the stacked structure SK serves as a plurality of second electrode plates PL2, and the second portion of the plurality of even conductor layers 126 of the stacked structure SK serves as a plurality of even word lines WLn, and are insulated from each other. Similarly, a first portion of the insulating layer 102 of the stack structure SK is used as a plurality of dielectric layers D1 , and a second portion of the insulating layer 102 of the stack structure SK is used as a plurality of separation layers ISL.
[0068] Figure 3C is a cross-sectional schematic diagram of a capacitor disposed in a dummy block according to an embodiment of the present invention.
[0069] Reference Figure 3C The capacitor MIM or the capacitor unit MU includes a plurality of first electrode plates PL1, a plurality of second electrode plates PL2, and a plurality of dielectric layers D1. The plurality of first electrode plates PL1 and the plurality of second electrode plates PL2 are alternately arranged, and a dielectric layer D1 is arranged between adjacent first electrode plates PL1 and second electrode plates PL2. The plurality of first electrode plates PL1 are electrically connected to the first end E1, and the plurality of second electrode plates PL2 are electrically connected to the second end E2. Figure 3C In the embodiment, all the even-numbered conductor layers 126 and all the odd-numbered conductor layers 126 are used as the second electrode plate PL2 and the first electrode plate PL1 of a single capacitor MIM or a single capacitor unit MU, respectively. However, in other embodiments, a portion of the even-numbered conductor layers 126 and a portion of the odd-numbered conductor layers 126 in the stacked structure SK can be used as the second electrode plate PL2 and the first electrode plate PL1 of a single capacitor MIM or a single capacitor unit MU, respectively, and another portion of the even-numbered conductor layers 126 and another portion of the odd-numbered conductor layers 126 in the stacked structure SK can be used as the second electrode plate PL2 and the first electrode plate PL1 of another single capacitor MIM or another single capacitor unit MU, respectively.
[0070] Reference Figure 1B and Figure 3C , the electrical connection relationship between the multiple first electrode plates PL1 and the multiple second electrode plates PL2 is described as follows. The multiple first electrode plates PL1 and the multiple second electrode plates PL2 at the end of the step structure SC can be electrically connected to the upper wires CL1 and CL2 via contact windows COA1 and COA2 respectively. The wire CL1 can be connected to the first end E1 via other vias and wires. The wire CL2 can be connected to the second end E2 via other vias and wires. Since the stacked structure SK has a considerable number of conductor layers 126, the capacitor MIM or the capacitor unit MU has a considerable number of first electrode plates PL1 and second electrode plates PL2, and therefore, the capacitor of the present invention has a considerable capacitance.
[0071] In the embodiment of the present invention, one or more capacitors are arranged in the stacked structure of the virtual block of the upper level, rather than being arranged in the peripheral circuit area of the lower level, nor being arranged in the memory block of the upper level. Since the capacitor of the present invention does not occupy the area of the peripheral circuit area and the memory area, the area of the chip can be saved. Furthermore, since the stacked structure has a considerable number of conductor layers, the capacitor can have a considerable number of first electrode plates and second electrode plates, and therefore, can be used to form a capacitor with a relatively large capacitance. In addition, the present invention can also design capacitors with various different capacitances, which are very flexible in application.
Claims
1. A semiconductor element, comprising: A substrate, comprising a plurality of memory array areas, each of the memory array areas comprising a plurality of memory blocks and a plurality of virtual blocks, the plurality of virtual blocks being located at the edges of the plurality of memory blocks; A plurality of memory arrays are disposed in the plurality of memory blocks; as well as A plurality of capacitors are disposed in the plurality of dummy blocks at the edges of the plurality of memory blocks. 2 . The semiconductor device according to claim 1 , wherein the plurality of capacitors are laterally adjacent to the plurality of memory arrays. 3 . The semiconductor device according to claim 1 , wherein each of the plurality of capacitors is a metal-insulator-metal capacitor. 4 . The semiconductor device according to claim 1 , wherein the plurality of memory arrays include a plurality of odd word lines, a plurality of even word lines, and a plurality of separation layers separating the plurality of odd word lines and the plurality of even word lines from each other.
5. The semiconductor device of claim 4 , wherein the plurality of first electrode plates of the plurality of capacitors are at the same height as the plurality of odd word lines, the plurality of second electrode plates of the plurality of capacitors are at the same height as the plurality of even word lines, and the plurality of dielectric layers of the plurality of capacitors are at the same height as the plurality of separation layers.
6. The semiconductor device according to claim 5, further comprising: A stacked structure is located above the substrate of the plurality of memory array regions, the stacked structure comprising a plurality of conductor layers and a plurality of insulating layers stacked alternately, wherein The first part of the plurality of odd-numbered conductor layers of the plurality of conductor layers is used as the plurality of first electrode plates, and the second part of the plurality of odd-numbered conductor layers of the stacked structure is used as the plurality of odd-numbered word lines. wherein the first part of the plurality of even-numbered conductor layers of the plurality of conductor layers is used as the plurality of second electrode plates, and the second part of the plurality of even-numbered conductor layers of the stacked structure is used as the plurality of even-numbered word lines, The first part of the plurality of insulating layers is used as the plurality of dielectric layers, and the second part of the plurality of insulating layers of the stacked structure is used as the plurality of separation layers.
7. A semiconductor element, comprising: substrate; A stacking structure, above the substrate, the stacking structure comprising a plurality of insulating layers and a plurality of conductor layers alternately stacked with each other; A plurality of memory arrays are arranged in the stacked structure; as well as A plurality of capacitors are disposed in the stack structure and adjacent to the plurality of memory arrays.
8. The semiconductor device according to claim 7, wherein the substrate comprises a first region and a plurality of second regions, the first region is between the plurality of second regions, and wherein the plurality of memory arrays are disposed in the stacked structure on the first region, and the plurality of capacitors are disposed in the stacked structure on the plurality of second regions.
9. The semiconductor element according to claim 8, wherein the multiple conductor layers located in the first area serve as multiple word lines of the multiple memory arrays, the multiple conductor layers located in the multiple second areas serve as multiple first electrode plates and multiple second electrode plates of multiple capacitors, and the multiple insulating layers located in the multiple second areas serve as multiple dielectric layers of multiple capacitors, wherein each of the multiple dielectric layers is sandwiched between adjacent first electrode plates and second electrode plates. 10 . The semiconductor device according to claim 9 , wherein the plurality of first electrode plates are electrically connected to each other, and the plurality of second electrode plates are electrically connected to each other.