Semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of reducing energy loss during transient conduction. The semiconductor device includes a first transistor, a second transistor, and a control unit. The control unit applies a second off-voltage lower than the first off-voltage to the second gate before the first transistor enters the transient off-state, turns on the second transistor before the first transistor enters the transient on-state, and applies the first off-voltage to the second gate after the first transistor is turned on to turn off the second transistor.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] In a power transistor with a switching function, it is ideal that the voltage in the stable on state and the energy loss during the transition to cutoff are as small as possible. Basically, the voltage in the stable on state and the energy loss during the transition to cutoff are in a trade-off relationship, so various technologies for reducing these have been proposed so far.

[0003] For example, Patent Document 1 proposes a technique for reducing the voltage in a stable on-state and the energy loss in transition to off-state by controlling the control timing of two gates in a dual-gate structure.

[0004] In addition, a technology has been proposed that uses a dual gate structure to limit the saturation current for a certain period of time to prevent the element from being destroyed when the power supply is short-circuited.

[0005] Patent Document 1: Japanese Patent Application Publication No. 2004-319624

[0006] However, there is room for improvement in the prior art in terms of gate control during transient turn-on and reduction of energy loss during transient turn-on. Summary of the invention

[0007] Therefore, the present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to provide a technology capable of reducing energy loss during a transient on period.

[0008] The semiconductor device involved in the present disclosure includes: a first transistor, including a first gate and a first emitter region arranged along the above-mentioned first gate; a second transistor, including a second gate and a second emitter region arranged along the above-mentioned second gate, and adjacent to the above-mentioned first transistor; and a control unit, which controls the conduction and cutoff of the above-mentioned first transistor and the above-mentioned second transistor, when viewed from above, the length of the part of the above-mentioned second emitter region opposite to the above-mentioned second gate is greater than the length of the part of the above-mentioned first emitter region opposite to the above-mentioned first gate, and the above-mentioned control unit applies a second cutoff voltage lower than the first cutoff voltage to the above-mentioned second gate before the above-mentioned first transistor enters a transient cutoff state, turns on the above-mentioned second transistor before the above-mentioned first transistor enters a transient on state, and applies the above-mentioned first cutoff voltage to the above-mentioned second gate after the above-mentioned first transistor is turned on to turn off the above-mentioned second transistor.

[0009] According to the present disclosure, the control unit applies a second cutoff voltage lower than the first cutoff voltage to the second gate before the first transistor enters a transient cutoff state, turns on the second transistor before the first transistor enters a transient on state, and applies the first cutoff voltage to the second gate to turn off the second transistor after the first transistor is turned on. According to such a structure, energy loss during transient on can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a diagram showing the structure of a semiconductor device according to the first embodiment.

[0011] Figure 2 This is a diagram showing a partial structure of a semiconductor module according to the first embodiment.

[0012] Figure 3 It is a plan view showing the structure of the chip involved in the first embodiment.

[0013] Figure 4 This is an enlarged plan view showing the structure of the semiconductor device according to the first embodiment.

[0014] Figure 5 (a) and (b) are cross-sectional views showing the structure of the semiconductor device according to the first embodiment.

[0015] Figure 6 This is an enlarged plan view showing the structure of the semiconductor device according to the first embodiment.

[0016] Figure 7 (a) and (b) are cross-sectional views showing the structure of the semiconductor device according to the first embodiment.

[0017] Figure 8 (a) and (b) are cross-sectional views showing the structure of the semiconductor device according to the first embodiment.

[0018] Fig. 9 This is a timing chart showing control performed by the control unit according to the first embodiment.

[0019] Fig.10 This is a timing chart showing control performed by the control unit according to the first embodiment.

[0020] Fig.11 This is an enlarged plan view showing the structure of a semiconductor device according to the second embodiment.

[0021] Fig.12 It is an enlarged plan view showing the structure of a semiconductor device according to the third embodiment.

[0022] Fig.13It is an enlarged plan view showing the structure of a semiconductor device according to a fourth embodiment.

[0023] Fig.14 FIG. 4 is a diagram showing impurity profiles of the first emitter region and the second emitter region according to the fourth embodiment.

[0024] Fig.15 It is a timing chart showing control performed by the control unit according to the fifth embodiment.

[0025] Fig.16 It is a graph showing the relationship between Δt1 / tm and energy loss Eon.

[0026] Fig.17 It is a timing chart showing control performed by the control unit according to the sixth embodiment.

[0027] Fig.18 It is a timing chart showing control by the control unit according to the seventh embodiment.

[0028] Fig.19 It is a timing chart showing control by the control unit according to the seventh embodiment.

[0029] Fig. 20 It is a timing chart showing control by the control unit according to the eighth embodiment.

[0030] Description of Reference Numerals

[0031] 1…first transistor; 1a…first gate; 1b…first emitter region; 2…second transistor; 2a…second gate; 2b…second emitter region; 3…control unit. DETAILED DESCRIPTION

[0032] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in the following embodiments are examples, and not all of the features are necessary. In addition, in the description shown below, the same or similar figure marks are marked on the same components in multiple embodiments, and mainly different components are described. In addition, in the description recorded below, specific positions and directions such as "up", "down", "left", "right", "front" or "back" may not be consistent with the positions and directions during actual implementation. In addition, the concentration of a certain part is higher than the concentration of other parts, for example, it means that the average of the concentration of a certain part is higher than the average of the concentration of other parts. On the contrary, the concentration of a certain part is lower than the concentration of other parts, for example, it means that the average of the concentration of a certain part is lower than the average of the concentration of other parts.

[0033] <Implementation method 1>

[0034] Figure 1 This is a diagram showing the structure of a semiconductor device according to the first embodiment. Figure 1 The semiconductor device includes a first transistor 1, a second transistor 2, and a control unit 3.

[0035] The first transistor 1 and the second transistor 2 are disposed adjacent to each other on the chip 51. The following mainly describes the structures of the first transistor 1 and the second transistor 2 as trench-type IGBTs (Insulated Gate Bipolar Transistors), but is not limited thereto, and may be, for example, MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0036] The control unit 3 controls the voltage of the first gate 1a of the first transistor 1 and the voltage of the second gate 2a of the second transistor 2, thereby controlling the on and off of the first transistor 1 and the second transistor 2. The control unit 3 includes, for example, a CPU (Central Processing Unit).

[0037] Figure 2 Yes means including Figure 1 FIG. 4 is a diagram showing the structure of a semiconductor module having a structure of an IGBT module. Figure 2 The upper part and the lower part have the same structure, so one of these parts is described here.

[0038] The collector of the first transistor 1 is connected to the collector of the second transistor 2, and the emitter of the first transistor 1 is connected to the emitter of the second transistor 2, so that the first transistor 1 and the second transistor 2 are connected in parallel. Furthermore, the diode 6 is connected in parallel to the first transistor 1 and the second transistor 2. The diode 6 may be a diode using a PN junction or a Schottky barrier diode. Figure 2 In the embodiment, the diode 6 is provided outside the chip 51 , but may be provided in the same chip 51 as the first transistor 1 and the second transistor 2 like an RC-IGBT (Reverse Conducting-IGBT).

[0039] Figure 3 : is a plan view showing the structure of a chip 51. The chip 51 includes a unit portion 52 provided with a first transistor 1 and a second transistor 2, and a peripheral portion of the unit portion 52. The unit portion 52 is provided with a first gate 1a of the first transistor 1 and a second gate 2a of the second transistor 2.

[0040] exist Figure 3In the example of FIG. 5 , pads 53 and 54 electrically connected to the first gate 1a and the second gate 2a are provided at the periphery in order to input a signal from the control unit 3 outside the chip 51 to the first gate 1a and the second gate 2a, respectively. In addition, the control unit 3 may be provided instead of the pads 53 and 54, so that the chip 51 and the control unit 3 are formed as a single chip (integrated).

[0041] Figure 4 is an enlarged top view showing the structure of the semiconductor device according to the first embodiment, specifically, an enlarged top view showing the structure of the semiconductor device according to the first embodiment. Figure 3 An enlarged top view of the dotted line portion of Figure 4 In the example of FIG. 1 , the first transistor 1 and the second transistor 2 are alternately arranged one by one, but may be alternately arranged in units other than one, such as two by two, for example. Figure 5 (a) means along Figure 4 A cross-sectional view of the structure along line AA. Figure 5 (b) means along Figure 4 A cross-sectional view of the structure of line BB. Figure 4 For the convenience of the drawings, the Figure 5 Illustration of part of the components of (a) and (b).

[0042] Hereinafter, the structures of the first transistor 1 and the second transistor 2 will be described. In the following description, the n-type and the p-type may be reversed.

[0043] like Figure 4 and Figure 5 As shown in (a) and (b), the first transistor 1 includes: a first gate 1a, n + Type or n ++ The first emitter region 1b, n － type drift layer 11, n-type CS (charge storage) layer 12, p-type base layer 13, p + n-type contact layer 14, gate insulating film 17, interlayer insulating film 21, emitter 22, n-type buffer layer 23, p + Type collector region 24, and collector 25.

[0044] A CS layer 12 is provided on the drift layer 11 , a base layer 13 is provided on the CS layer 12 , and a first emitter region 1 b and a contact layer 14 are selectively provided on the base layer 13 .

[0045] The trench 16 is provided over the first emitter region 1b, the base layer 13 and the CS layer 12, and the upper part of the drift layer 11. The first gate 1a is an electrode provided on the inner wall of the trench 16 via a gate insulating film 17. The gate insulating film 17 is, for example, an oxide film, and the first gate 1a is made of, for example, doped polysilicon.

[0046] The interlayer insulating film 21 insulates the first gate 1a from the emitter 22. The interlayer insulating film 21 is, for example, an oxide film. The emitter 22 is an electrode electrically connected to the first emitter region 1b and the contact layer 14 via a contact hole in the interlayer insulating film 21. A buffer layer 23, a collector region 24, and a collector electrode 25 are sequentially stacked on the lower surface of the drift layer 11.

[0047] like Figure 4 and Figure 5 As shown in (a) and (b), the second transistor 2 includes a second gate 2a and a second gate 2b. + Type or n ++ In addition, the second transistor 2 includes a drift layer 11, a CS layer 12, a base layer 13, a contact layer 14, a gate insulating film 17, an interlayer insulating film 21, an emitter 22, a buffer layer 23, a collector region 24, and a collector 25, similarly to the first transistor 1.

[0048] The structure of the second transistor 2 is substantially the same as that of the first transistor 1 except for the first emitter region 1 b and the second emitter region 2 b . Figure 4 The first emitter region 1b is intermittently (eg, periodically) arranged along the first gate 1a, so that Figure 5 In the cross-sectional structure along the AA line of (a), a first emitter region 1b is provided, but in Figure 5 In the cross-sectional structure along line BB of (b), the first emitter region 1b is not provided. Figure 4 The second emitter region 2b is continuously arranged along the second gate 2a, so that Figure 5 (a) is the cross-sectional structure along the AA line, and Figure 5 The second emitter region 2b is provided in the cross-sectional structure along the BB line of (b). Figure 4 When , the length of the portion of the second emitter region 2 b facing the second gate 2 a is greater than the length of the portion of the first emitter region 1 b facing the first gate 1 a .

[0049] In addition, the first emitter region 1b, the second emitter region 2b, the drift layer 11, the CS layer 12, the base layer 13, the contact layer 14, the gate insulating film 17, the buffer layer 23 and the collector region 24 are included in at least one of the semiconductor substrate and the epitaxial growth layer, that is, the semiconductor layer. In this specification, for example, at least one of A, B, C, ..., and Z refers to any one of all combinations in which one or more are extracted from the group of A, B, C, ..., and Z. The semiconductor layer can be composed of conventional silicon (Si) or a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), diamond, etc. When the semiconductor layer is composed of a wide bandgap semiconductor, stable operation at high temperature and high voltage, and high switching speed can be achieved.

[0050] exist Figure 4 and Figure 5 In the examples (a) and (b), the entire table surface (that is, Figure 5 The upper part of the semiconductor layer sandwiched between the first gate 1a and the second gate 2a of (a) and (b) is in contact with the emitter 22, but it is not limited to this. For example, Figure 6 and respectively represent along Figure 6 The cross section of the AA and BB lines Figure 7 As shown in (a) and (b) of FIG. 1 , the interlayer insulating film 21 may be made larger than Figure 4 The interlayer insulating film 21 is formed so that only a part of the mesa portion is in contact with the emitter 22.

[0051] In addition, Figure 7 In (a) and (b), the mesa portion covered by the interlayer insulating film 21 and the mesa portion not covered by the interlayer insulating film 21 have the same height relative to the vertical direction of the paper. However, this is not limited to this. Figure 6 Another section of the AA line and the BB line Figure 8 As shown, the height of the mesa portion covered by the interlayer insulating film 21 may be different from the height of the mesa portion not covered by the interlayer insulating film 21 .

[0052] Then, in the above structure, Figure 1 or Figure 2The control unit 3 controls the voltage of the first gate 1a of the first transistor 1 and the voltage of the second gate 2a of the second transistor 2. If a voltage greater than the threshold voltage VGE(th) is applied to the first gate 1a of the first transistor 1, a portion of the semiconductor layer near the gate insulating film 17 of the first gate 1a substantially functions as an n-type semiconductor layer to form a channel. On the other hand, if a negative bias voltage, which is a negative voltage, is applied to the first gate 1a, a portion of the semiconductor layer near the gate insulating film 17 of the first gate 1a substantially functions as a p-type semiconductor layer. Similarly, if a voltage greater than the threshold voltage VGE(th) is applied to the second gate 2a of the second transistor 2, a portion of the semiconductor layer near the gate insulating film 17 of the second gate 2a substantially functions as an n-type semiconductor layer to form a channel. On the other hand, if a negative bias voltage is applied to the second gate 2a, a portion of the semiconductor layer near the gate insulating film 17 of the second gate 2a substantially functions as a p-type semiconductor layer.

[0053] Fig. 9 It is a timing chart showing control by the control unit 3 according to the first embodiment. Fig. 9 Shows Figure 3 The voltage of the pad 53 and the pad 54 of the chip 51, that is, the voltage of the first gate 1a and the second gate 2a. The threshold voltage VGE(th) of the first transistor 1 and the second transistor 2 is greater than 0V.

[0054] Strictly speaking, the transient off-state of the first transistor 1 is the state where the first transistor 1 changes from being on to being off. Fig. 9 1 shows a transient off period including a transient off state. Similarly, the transient on state of the first transistor 1 is strictly speaking a state in which the first transistor 1 changes from off to on. Fig. 9 A transient on period including a transient on state is shown.

[0055] The control unit 3 applies a second cutoff voltage V2, which is lower than the first cutoff voltage V1, to the second gate 2a before the first transistor 1 enters the transient cutoff state. The control unit 3 turns on the second transistor 2 before the first transistor 1 enters the transient on state. Furthermore, the control unit 3 applies the first cutoff voltage V1 to the second gate 2a to turn off the second transistor 2 after the first transistor 1 is turned on through the transient on state.

[0056] In addition, Fig. 9 In the example, the first cutoff voltage V1 is 0 V and the second cutoff voltage V2 is a negative bias voltage. However, as long as the first cutoff voltage V1 and the second cutoff voltage V2 are lower than the threshold voltage VGE(th), and the second cutoff voltage V2 is lower than the first cutoff voltage V1, it is not limited thereto.

[0057] In addition, Fig. 9 In the example of FIG. 1 , during the stable off period from the transient off period to the transient on period of the first transistor 1, the control unit 3 maintains the application of the second off voltage V2 (i.e., negative bias voltage) to the second gate 2a. In addition, during the stable on period from the transient on period to the transient off period of the first transistor 1, the control unit 3 maintains the application of the first off voltage V1 (i.e., 0V) to the second gate 2a. However, the voltage of the second gate 2a during the stable off period and the stable on period is not limited to this. For example, Fig.10 As shown, during the stable off period, the control unit 3 may apply a third off voltage V3 of 0 or more and less than the threshold voltage VGE(th) to the second gate 2a. The control of the control unit 3 described above can achieve the first to third effects.

[0058] <First Effect>

[0059] Before the first transistor 1 enters the transient off state, the control unit 3 applies the second off voltage V2 (that is, negative bias) to the second gate 2a. As a result, the portion of the semiconductor layer near the gate insulating film 17 of the second gate 2a substantially functions as a p-type semiconductor layer. Therefore, it has the effect that the holes retained in the drift layer 11 are easily discharged from the surface via the p-type semiconductor layer. As a result, the total amount of holes that contribute to the conductivity modulation of the first transistor 1 and the second transistor 2 as a whole is reduced. As a result, after this action, the number of holes discharged when the first transistor 1 is turned off becomes less, so the tail current becomes smaller, which can reduce the energy loss (Eoff) during the transient off period of the first transistor 1.

[0060] <Second effect>

[0061] The control unit 3 turns on the second transistor 2 before the first transistor 1 enters the transient on state. As a result, the energy loss during the transient on period is mainly generated in the second transistor 2 that is turned on first. Here, in the present embodiment 1, when viewed from above, the length of the portion of the second emitter region 2b that is opposite to the second gate 2a is greater than the length of the portion of the first emitter region 1b that is opposite to the first gate 1a. Therefore, when the first transistor 1 and the second transistor 2 are turned on independently, the amount of electrons injected at the moment when the second transistor 2 is turned on becomes greater than the amount of electrons injected into the first transistor 1, so the switching of the second transistor 2 is completed earlier than the switching of the first transistor 1.

[0062] Thus, the energy loss during the transient on period when the second transistor 2 is turned on independently is smaller than the energy loss during the transient on period when the first transistor 1 is turned on independently. As a result, the energy loss Eon during the transient on period of the first transistor 1 and the second transistor 2 as a whole can be reduced. In addition, by turning on the first transistor 1 after turning on the second transistor 2, the first transistor 1 and the second transistor 2 can be turned on with a smaller gate charge than when the first transistor 1 and the second transistor 2 are turned on at the same time.

[0063] <Third Effect>

[0064] After the first transistor 1 is turned on, the control unit 3 applies the first cutoff voltage V1 to the second gate 2a to cut off the second transistor 2, thereby improving the behavior in the short-circuit action mode. Among them, the short-circuit action mode refers to a mode in which the main power supply is directly short-circuited to the collector 25 due to a failure of the peripheral circuit, etc. In the short-circuit action mode, it is preferred that the duration of the stable conduction period after the completion of the transient conduction period is long. Moreover, the duration corresponds to the time until the cumulative power determined by the voltage applied to the IGBT (that is, the voltage of the main power supply) and the current (that is, the saturation current of the IGBT) exceeds the energy allowable value of the IGBT. In addition, the current (saturation current of the IGBT) mentioned here depends on the size of the emitter region of the transistor that has been turned on.

[0065] Here, in the first embodiment, the length of the portion of the second emitter region 2b facing the second gate 2a is greater than the length of the portion of the first emitter region 1b facing the first gate 1a when viewed from above. Since the above-mentioned length of the emitter region corresponds to the size of the emitter region, the saturation current of the first transistor 1 that has been turned on becomes smaller than the saturation current of the second transistor 2 that has been turned on. In the first embodiment, since the second transistor 2 with a large saturation current is turned off after the first transistor 1 with a small saturation current is turned on, the duration of the short-circuit operation mode can be extended.

[0066] <Implementation method 2>

[0067] Fig.11 1 is an enlarged plan view showing the structure of a semiconductor device according to the second embodiment. Figure 4 In the present embodiment 2, the second emitter region 2b is continuously provided along the second gate 2a. Fig.11 This point is different from the first embodiment in that the second emitter region 2b is provided intermittently (eg, periodically) along the second gate 2a.

[0068] like Fig.11As shown in the example of , the first emitter region 1b and the second emitter region 2b may also be arranged alternately in a manner such that the lower part and the upper part of the first emitter region 1b correspond to the upper part and the lower part of the second emitter region 2b, respectively, when viewed from above. Alternatively, the first emitter region 1b and the second emitter region 2b may also be arranged in a certain regular manner such that the upper part of the first emitter region 1b corresponds to the upper part of the second emitter region 2b, respectively, when viewed from above.

[0069] According to such a structure, by thinning out the second emitter regions 2 b , the potential directly below the second emitter regions 2 b can be lowered, and thus the latch-up tolerance of the semiconductor device can be improved.

[0070] <Implementation method 3>

[0071] Fig.12 It is an enlarged plan view showing the structure of a semiconductor device according to Embodiment 3. Embodiment 3 is different from Embodiment 1 in that a first emitter region 1b and a second emitter region 2b are connected to each other in a plan view.

[0072] Here, the first emitter region 1b and the second emitter region 2b need to be electrically connected to the emitter 22 via the contact hole of the interlayer insulating film 21. Therefore, in the first and second embodiments, the width of the contact hole of the interlayer insulating film 21 is limited by the arrangement of the first emitter region 1b and the second emitter region 2b. In contrast, in the third embodiment, Fig.12 As shown, the first emitter region 1 b and the second emitter region 2 b are connected to each other, and there is no such restriction on the width of the contact hole 21 a of the interlayer insulating film 21 , so that the degree of freedom in designing the contact hole can be increased.

[0073] <Implementation method 4>

[0074] Fig.13 is an enlarged plan view showing the structure of a semiconductor device according to the fourth embodiment. Fig.14 It is a diagram showing the impurity distribution curves of the first emitter region 1 b and the second emitter region 2 b . Fig.14 The horizontal axis of represents the depth from the surface of the semiconductor layer (that is, the surface of each of the first emitter region 1b and the second emitter region 2b), Fig.14 The vertical axis represents the impurity concentration.

[0075] like Fig.14As shown, the peak value of the n-type impurity concentration of the first emitter region 1b and the peak value of the n-type impurity concentration of the second emitter region 2b are located on the upper surface side of the semiconductor layer. In the fourth embodiment, the peak value of the n-type impurity concentration of the second emitter region 2b is greater than the peak value of the n-type impurity concentration of the first emitter region 1b, which is different from the first embodiment.

[0076] According to such a structure, since the amount of electrons injected at the moment of turning on the second transistor 2 is large, the switch is completed earlier than the first transistor. Therefore, since the amount of electrons injected at the moment of turning on the second transistor 2 is greater than the amount of electrons injected into the first transistor 1, the energy loss Eon during the transient conduction period of the first transistor 1 and the second transistor 2 as a whole can be reduced. In addition, the above-mentioned embodiment 4 can also be applied to embodiments 2 and 3.

[0077] <Implementation method 5>

[0078] Fig.15 1 is a timing chart showing the control of the control unit 3 according to the fifth embodiment, and specifically, showing the control of the transient on period of the first transistor 1. In the fifth embodiment, when the time from the turn-on of the second transistor 2 to the turn-on of the first transistor 1 is Δt1 and the Miller interval of the second transistor 2 is tm, 0<Δt1<tm is established, which is different from the first embodiment. The Miller interval is a period during which the gate voltage becomes constant when the transistor is turned on due to the effective capacitance between the gate and the collector.

[0079] Fig.16 It is a graph showing the relationship between the ratio of Δt1 to tm, i.e., Δt1 / tm (horizontal axis) and the energy loss Eon (vertical axis) during the transient conduction period of the first transistor 1 and the second transistor 2 as a whole. The energy loss Eon shown on the vertical axis is normalized by the energy loss Eon in the case of Δt1 / tm=-0.2 (that is, the case where the first transistor 1 rises before the Miller interval of the second transistor).

[0080] In the part where 0<Δt1<tm holds, that is, Fig.16 In the portion where the horizontal axis is greater than 0 and less than 1, the energy loss Eon can be reduced compared to the energy loss Eon in the case of Δt1 / tm=-0.2. Fig.16 From the results, when Δt1 / tm=0.3, the energy loss Eon can be reduced the most. In addition, the fifth embodiment as described above can also be applied to the second to fourth embodiments.

[0081] <Implementation method 6>

[0082] Fig.171 is a timing chart showing the control of the control unit 3 according to the sixth embodiment, specifically, the control during the transient on period and the main voltage VCE and the main current IC of the semiconductor device. The sixth embodiment is different from the first embodiment in that the voltage of the first gate 1a exceeds the Miller voltage before the voltage of the second gate 2a becomes lower than the Miller voltage during the period when the first transistor 1 is in the transient on state.

[0083] Fig.17 The dotted line shows a waveform in which the voltage of the first gate 1a exceeds the Miller voltage after the voltage of the second gate 2a becomes lower than the Miller voltage. In this case, the voltage VCE, which was once 0, becomes greater than 0 during the period from the rise of the voltage of the first gate 1a to the voltage of the second gate 2a becoming lower than the Miller voltage, and therefore the energy loss Eon increases accordingly.

[0084] Fig.17 The solid line represents the waveform of the control based on the present embodiment 6, that is, the waveform of the case where the voltage of the first gate 1a exceeds the Miller voltage before the voltage of the second gate 2a becomes lower than the Miller voltage. In this case, since the voltage VCE that once becomes 0 is maintained at 0, the energy loss Eon can be reduced compared with the above case. In addition, the present embodiment 6 as described above can also be applied to embodiments 2 to 5.

[0085] <Implementation method 7>

[0086] Fig.18 1 is a timing chart showing the control of the control unit 3 according to the seventh embodiment, and specifically, showing the control of the transient on period and the transient off period of the first transistor 1. The seventh embodiment is different from the first embodiment. Fig.10 That is, in the seventh embodiment, when the first transistor 1 enters the transient off state immediately after the transient on state, the control unit 3 controls the voltage of the second gate 2a from the on-level to the second off-voltage V2 instead of maintaining the on-voltage at the first off-voltage V1, which is different from the first embodiment.

[0087] Fig.19 Yes Fig.18 A magnified portion of the image. Fig.19 The dot-dash line represents a waveform when the control unit 3 controls the voltage of the second gate 2a from the on-voltage to the third off-voltage V3. Fig.19 The solid line represents a waveform based on the control of the control unit 3 involved in the seventh embodiment.

[0088] In order to turn off the second transistor 2 earlier than the first transistor 1, the voltage of the second gate 2a needs to reach the threshold voltage VGE(th) earlier than the voltage of the first gate 1a. In contrast, according to the seventh embodiment, compared with the case where the control unit 3 controls the voltage of the second gate 2a from the on-voltage to the third off-voltage V3, the second transistor 2 can be turned off earlier. Fig.19 As a result, the period during which the first transistor 1 is in the on state can be shortened. In addition, the above-described seventh embodiment can also be applied to the embodiment described in the first embodiment. Fig. 9 In this case, the voltage of the second gate 2a is maintained at the second off-voltage V2 during the stable off-period after the transient off-period. In addition, the seventh embodiment can also be applied to the second to sixth embodiments.

[0089] <Implementation method 8>

[0090] Fig. 20 1 is a timing chart showing control of the control unit 3 according to the eighth embodiment. The eighth embodiment is different from the first embodiment in that the second cutoff voltage V2 is equal to or higher than 0 V, the first cutoff voltage V1 is higher than the second cutoff voltage V2, and the third cutoff voltage V3 is higher than the second cutoff voltage V2.

[0091] According to such a structure, it is not necessary to prepare a power supply for the control unit 3 to make the second gate 2a negatively biased, so the structure of the semiconductor device can be simplified. Fig. 9 , and can also be applied to implementation modes 2 to 7.

[0092] In addition, the embodiments and the modifications can be freely combined, or the embodiments and the modifications can be appropriately modified or omitted.

[0093] Hereinafter, each aspect of the present disclosure will be collectively described as supplementary notes.

[0094] (Note 1)

[0095] A semiconductor device comprising:

[0096] A first transistor comprising a first gate and a first emitter region disposed along the first gate;

[0097] a second transistor comprising a second gate and a second emitter region disposed along the second gate and adjacent to the first transistor; and

[0098] a control unit, controlling the on and off of the first transistor and the second transistor,

[0099] When viewed from above, a length of a portion of the second emitter region facing the second gate is greater than a length of a portion of the first emitter region facing the first gate.

[0100] The control unit applies a second cutoff voltage lower than the first cutoff voltage to the second gate before the first transistor enters a transient cutoff state, turns on the second transistor before the first transistor enters a transient on state, and applies the first cutoff voltage to the second gate to turn off the second transistor after the first transistor is turned on.

[0101] (Note 2)

[0102] A semiconductor device according to Supplementary Note 1, wherein:

[0103] In a plan view, the first emitter region is intermittently provided along the first gate, and the second emitter region is continuously provided along the second gate.

[0104] (Note 3)

[0105] A semiconductor device according to Supplementary Note 1, wherein:

[0106] In a plan view, the first emitter region is intermittently provided along the first gate, and the second emitter region is intermittently provided along the second gate.

[0107] (Note 4)

[0108] The semiconductor device according to any one of Supplementary Notes 1 to 3, wherein:

[0109] The first emitter region and the second emitter region are connected to each other in a plan view.

[0110] (Note 5)

[0111] The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein:

[0112] A peak value of the impurity concentration of the second emitter region is greater than a peak value of the impurity concentration of the first emitter region.

[0113] (Note 6)

[0114] The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein:

[0115] When the time from when the second transistor is turned on to when the first transistor is turned on is Δt1 and the Miller interval of the second transistor is tm, 0<Δt1<tm holds.

[0116] (Note 7)

[0117] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein:

[0118] While the first transistor is in the transient on state, the voltage of the first gate exceeds the Miller voltage before the voltage of the second gate becomes lower than the Miller voltage.

[0119] (Note 8)

[0120] The semiconductor device according to any one of Supplementary Notes 1 to 7, wherein:

[0121] When the first transistor enters the transient off state immediately after the transient on state, the control unit controls the voltage of the second gate to be the second off voltage instead of maintaining the voltage at the first off voltage from the on voltage.

[0122] (Note 9)

[0123] The semiconductor device according to any one of Supplementary Notes 1 to 8, wherein:

[0124] The second cut-off voltage is greater than 0V.

Claims

1. A semiconductor device, wherein: have: A first transistor comprising a first gate and a first emitter region disposed along the first gate; a second transistor comprising a second gate and a second emitter region disposed along the second gate and adjacent to the first transistor; as well as a control unit, controlling the on and off of the first transistor and the second transistor, When viewed from above, a length of a portion of the second emitter region that is opposite to the second gate is greater than a length of a portion of the first emitter region that is opposite to the first gate. The control unit applies a second cutoff voltage lower than the first cutoff voltage to the second gate before the first transistor enters a transient cutoff state, turns on the second transistor before the first transistor enters a transient on state, and applies the first cutoff voltage to the second gate to turn off the second transistor after the first transistor is turned on.

2. The semiconductor device according to claim 1, wherein In a plan view, the first emitter region is intermittently provided along the first gate, and the second emitter region is continuously provided along the second gate.

3. The semiconductor device according to claim 1, wherein In a plan view, the first emitter region is intermittently disposed along the first gate, and the second emitter region is intermittently disposed along the second gate.

4. The semiconductor device according to any one of claims 1 to 3, wherein The first emitter region and the second emitter region are connected to each other in a plan view.

5. The semiconductor device according to any one of claims 1 to 4, wherein A peak value of the impurity concentration of the second emitter region is greater than a peak value of the impurity concentration of the first emitter region.

6. The semiconductor device according to any one of claims 1 to 5, wherein When the time from when the second transistor is turned on to when the first transistor is turned on is Δt1 and the Miller interval of the second transistor is tm, 0<Δt1<tm holds.

7. The semiconductor device according to any one of claims 1 to 6, wherein During the time when the first transistor is in the transient on state, the voltage of the first gate exceeds the Miller voltage before the voltage of the second gate becomes lower than the Miller voltage.

8. The semiconductor device according to any one of claims 1 to 7, wherein When the first transistor enters the transient off state immediately after the transient on state, the control unit controls the voltage of the second gate to be changed from the on voltage to the second off voltage instead of maintaining the voltage at the first off voltage.

9. The semiconductor device according to any one of claims 1 to 8, wherein The second cut-off voltage is greater than 0V.

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