Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a buffer structure, an energy barrier structure, a channel structure, a grid electrode, a source electrode and a drain electrode. The buffer structure is located on the substrate. The energy barrier structure is located on the buffer structure and comprises a first oxide layer. The energy barrier structure is located between the channel structure and the buffer structure. The gate, the source, and the drain are over the channel structure.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] A high electron mobility transistor (HEMT) is a transistor that includes a heterojunction formed by two semiconductor materials with different energy gaps. This heterojunction can generate a two-dimensional electron gas or a two-dimensional hole gas, which can serve as a conductive channel for the HEMT. HEMT is widely used in the field of high-power electronic components because of its advantages such as low resistance, high breakdown voltage, and fast switching frequency.

[0003] HEMTs can be classified as either depletion mode or enhancement mode, depending on whether the channel is normally open or normally closed. Enhancement mode HEMTs offer additional safety and are more easily controlled by simple, low-cost drive circuits, so they have received widespread attention in the industry. Summary of the invention

[0004] The invention provides a semiconductor device and a manufacturing method thereof, which can improve electrical performance by setting an oxide layer.

[0005] At least one embodiment of the present invention provides a semiconductor device, which includes a substrate, a buffer structure, an energy barrier structure, a channel structure, a gate, a source and a drain. The buffer structure is located on the substrate. The energy barrier structure is located on the buffer structure and includes a first oxide layer. The energy barrier structure is located between the channel structure and the buffer structure. The gate, the source and the drain are located above the channel structure.

[0006] At least one embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising the following steps: forming a buffer structure on a substrate; forming an energy barrier structure on the buffer structure, wherein the energy barrier structure includes a first oxide layer; forming a channel structure on the energy barrier structure; and forming a gate, a source, and a drain above the channel structure.

[0007] Based on the above, the first oxide layer helps to confine carriers in the channel structure, thereby improving the electrical performance of the semiconductor device. In addition, the first oxide layer helps to reduce unexpected defects in the film layer located thereon. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0009] Figure 2FIG. 4 is a schematic diagram of an energy band of a semiconductor device according to an embodiment of the present invention.

[0010] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0011] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0012] Figure 5 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0013] Figure 6 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0014] Figure 7 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0015] FIG. 8A to FIG. 8E It is a cross-sectional schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0016] [Explanation of symbols]

[0017] 10,20,30,40,50,60: semiconductor devices;

[0018] 100: substrate;

[0019] 200: Buffer structure;

[0020] 210: nucleation layer;

[0021] 220: Superlattice structure;

[0022] 222: GaN layer;

[0023] 224: aluminum nitride layer;

[0024] 230: buffer layer;

[0025] 300: Energy barrier structure;

[0026] 310,310A,310P: first oxide layer;

[0027] 310B: second oxide layer;

[0028] 320: nitride layer;

[0029] 400: channel structure;

[0030] 410: channel layer;

[0031] 415: Two-dimensional electron gas;

[0032] 420: IIIV barrier layer;

[0033] 510: capping layer;

[0034] 510P: patterned capping layer;

[0035] 520: passivation layer;

[0036] 610: gate;

[0037] 620: source;

[0038] 630: drain;

[0039] E230,E310,E320: Bandgap width. DETAILED DESCRIPTION

[0040] Figure 1 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 1 The semiconductor device 10 includes a substrate 100 , a buffer structure 200 , an energy barrier structure 300 , a channel structure 400 , a gate 610 , a source 620 , and a drain 630 . In the present embodiment, the semiconductor device 10 further includes a cap layer 510 and a passivation layer 520 .

[0041] The substrate 100 includes a semiconductor substrate or a semiconductor on insulator (SOI) substrate, wherein the semiconductor material in the semiconductor substrate or SOI substrate may include an elemental semiconductor, an alloy semiconductor, or a compound semiconductor. For example, the elemental semiconductor may include Si or Ge. The alloy semiconductor may include SiGe, SiGeC, etc. The compound semiconductor may include SiC, a III-V semiconductor material, or a II-VI semiconductor material. The III-V semiconductor material may include GaN, GaP, GaAs, AlN, AlP, AlAs, InN, InP, InAs, GaNP, GaNAs, GaPAs, AlNP, AlNAs, AlPAs, InNP, InNAs, InPAs, GaAlNP, GaAlNAs, GaAlPAs, GaInNP, GaInNAs, GaInPAs, InAlNP, InAlNAs, or InAlPAs. The II-VI semiconductor material may include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, HgS, HgSe, HgTe, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe or HgZnSTe. In addition, the semiconductor material may be doped to a first conductivity type or a second conductivity type complementary to the first conductivity type. For example, the first conductivity type may be N-type, and the second conductivity type may be P-type.

[0042] The buffer structure 200 is located on the substrate 100. In this embodiment, the buffer structure 200 is a multi-layer structure, and includes a nucleation layer 210 and a buffer layer 230. In some embodiments, the buffer structure 200 is used to reduce stress caused by the difference in lattice constant and / or thermal expansion coefficient between the substrate 100 and the channel structure 300.

[0043] The nucleation layer 210 contacts the upper surface of the substrate 100, and the buffer layer 230 is formed on the nucleation layer 210. The nucleation layer 210 is located between the buffer layer 230 and the substrate 100.

[0044] In some embodiments, the thickness of the nucleation layer 210 is 100 nanometers to 300 nanometers. In some embodiments, the thickness of the buffer layer 230 is 3000 nanometers to 6000 nanometers.

[0045] In some embodiments, the materials of the nucleation layer 210 and the buffer layer 230 include group III (III) nitrides, III-V semiconductor materials, or other suitable materials. In some embodiments, the material of the nucleation layer 210 includes AlN, GaN, AlGaN, or a combination thereof. In some embodiments, the buffer layer 230 is a single-layer or multi-layer structure, and its material includes AlN, GaN, AlGaN, InGaN, AlInN, AlGaInN, or a combination thereof. In some embodiments, the buffer layer 230 is doped gallium nitride. For example, gallium nitride is doped with carbon, iron, or other elements to form the buffer layer 230. In some embodiments, the buffer layer 230 is a compositionally graded layer. For example, the buffer layer 230 is a graded aluminum gallium nitride layer with a graded aluminum component, thereby further alleviating stress caused by differences in lattice constants and / or thermal expansion coefficients.

[0046] The energy barrier structure 300 is located on the buffer structure 200. In the present embodiment, the energy barrier structure 300 includes a first oxide layer 310 and a nitride layer 320. The first oxide layer 310 is located on the buffer structure 200. For example, the first oxide layer 310 is formed on the buffer layer 230, and the buffer layer 230 contacts the first oxide layer 310. The nitride layer 320 is located on the first oxide layer 310, and the first oxide layer 310 is located between the nitride layer 320 and the buffer structure 200.

[0047] In some embodiments, the first oxide layer 310 has a thickness of 1 nm to 30 nm. In some embodiments, the nitride layer 320 has a thickness of 5 nm to 20 nm.

[0048] In some embodiments, the material of the first oxide layer 310 includes aluminum oxide or other wide energy gap materials (e.g., materials with energy gap width greater than the energy gap width of the nitride layer 320 and the energy gap width of the buffer layer 230). In some embodiments, the energy gap width of the first oxide layer 310 is 6eV to 8eV. In some embodiments, the material of the nitride layer 320 includes aluminum nitride, aluminum gallium nitride, or other suitable materials. In some embodiments, the difference between the energy gap width of the first oxide layer 310 and the energy gap width of the nitride layer 320 is greater than or equal to 0.5eV.

[0049] The channel structure 400 is located on the energy barrier structure 300, and the energy barrier structure 300 is located between the channel structure 400 and the buffer structure 200. In this embodiment, the channel structure 400 includes a channel layer 410 and a III-V barrier layer 420. The channel layer 410 is located between the III-V barrier layer 420 and the energy barrier structure 300.

[0050] In some embodiments, the thickness of the channel layer 410 is 200 nanometers to 400 nanometers. In some embodiments, the thickness of the channel layer 410 is less than the thickness of the buffer layer 230. In some embodiments, the thickness of the III-V barrier layer 420 is 20 nanometers to 35 nanometers.

[0051] In some embodiments, the material of the channel layer 410 includes a group III nitride, such as GaN or other suitable materials. In some embodiments, the channel layer 410 does not have a dopant or the doping concentration of the channel layer 410 is less than or equal to the doping concentration of the buffer layer 230. In some embodiments, the channel layer 410 has a two-dimensional electron gas (2DEG) 415, which is located at the interface between the channel layer 410 and the overlying group III-V barrier layer 420.

[0052] The III-V barrier layer 420 is disposed on the channel layer 410. In some embodiments, the material of the III-V barrier layer 420 includes a III-V semiconductor material and may have a single layer or a multilayer structure. In some embodiments, the III-V barrier layer 420 includes AlGaN, AlInN, AlGaInN or other suitable materials or a combination of the foregoing materials. The III-V barrier layer 420 may be a doped or undoped layer. In some embodiments, the III-V barrier layer 420 is AlGaN, and the aluminum content in the AlGaN is 20% to 30%.

[0053] In this embodiment, the first oxide layer 310 and the nitride layer 320 in the energy barrier structure 300 can block the flow of carriers between the buffer layer 230 and the channel layer 410. Therefore, the carriers (such as electrons) are confined in the potential energy well of the channel layer 410, thereby improving the electrical characteristics of the channel structure 400.

[0054] The capping layer 510 is located on the channel structure 400. In the present embodiment, the capping layer 510 is formed on the III-V barrier layer 420. The passivation layer 520 is located on the capping layer 510.

[0055] The material of the capping layer 510 includes a group III nitride, such as GaN or other suitable materials. In some embodiments, the capping layer 510 is gallium nitride, which may be doped or undoped. In some embodiments, the passivation layer 520 includes silicon nitride, aluminum oxide or other suitable insulating materials. In some embodiments, the capping layer 510 may be omitted.

[0056] In some embodiments, the capping layer 510 has a thickness of less than 3 nanometers. In some embodiments, the passivation layer 520 has a thickness of 30 nanometers to 80 nanometers.

[0057] The gate 610, the source 620 and the drain 630 are located above the channel structure 400. In this embodiment, the gate 610, the source 620 and the drain 630 pass through the passivation layer 520 and contact the cap layer 510. The cap layer 510 is located between the gate 610 and the channel structure 400.

[0058] The gate 610 is disposed on the cap layer 510. In some embodiments, the material of the gate 610 includes metal or metal nitride (such as Ta, TaN, Ti, TiN, W, Pd, Ni, Au, Al or a combination thereof), metal silicide (such as WSix) or other suitable materials.

[0059] In the present embodiment, the source 620 and the drain 630 are electrically connected to the channel structure 400, respectively. In the present embodiment, the source 620 and the drain 630 are disposed on the cap layer 510, but the present invention is not limited thereto. In other embodiments, at least one of the source 620 and / or the drain 630 may extend into the channel structure 400 and be electrically connected to the two-dimensional electron gas 415. In one embodiment, the material of the source 620 and the drain 630 includes a metal (e.g., Al, Ti, Ni, Au or an alloy thereof) or other material that can form an ohmic contact with a semiconductor. In other words, there is an ohmic contact between the source 620 and the channel structure 400, and there is an ohmic contact between the drain 630 and the channel structure 400, but the present invention is not limited thereto. In other embodiments, the source 620 and the drain 630 may also be made of a material that can form a Schottky contact with a semiconductor.

[0060] Figure 2 FIG. 4 is a schematic diagram of an energy band of a semiconductor device according to an embodiment of the present invention. Figure 2 The structure of the corresponding semiconductor device is as follows Figure 1 As shown. Figure 2 In the embodiment, the buffer layer 230 is gallium nitride, the first oxide layer 310 is aluminum oxide, the nitride layer 320 is aluminum nitride, the channel layer 410 is gallium nitride, the III-V barrier layer 420 is aluminum gallium nitride, and the cap layer 510 is gallium nitride. Figure 2 It can be seen that the energy gap width E310 of the first oxide layer 310 in the energy barrier structure 300 is greater than the energy gap width E320 of the nitride layer 320 and the energy gap width E230 of the buffer layer 220. The first oxide layer 310 can prevent carriers from flowing from the channel layer 410 to the buffer layer 230, thereby improving the reliability of the semiconductor device.

[0061] Figure 3 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 3 The implementation examples are used Figure 1The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0062] Figure 3 The semiconductor device 20 and Figure 1 The main difference between the semiconductor device 10 and the semiconductor device 20 is that the buffer structure 200 of the semiconductor device 20 further includes a superlattice structure 220 .

[0063] Please refer to Figure 3 In this embodiment, the superlattice structure 220 is located between the buffer layer 230 and the nucleation layer 210. In some embodiments, the superlattice structure 220 includes a stack of a gallium nitride layer 222 and an aluminum nitride layer 224. By providing the superlattice structure 220, the stress caused by the difference in lattice constant and / or thermal expansion coefficient between the substrate 100 and the buffer layer 230 can be reduced. In some embodiments, the total thickness of the superlattice structure 220 is 1000 nanometers to 3000 nanometers.

[0064] Figure 4 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 4 The implementation examples are used Figure 1 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0065] Figure 4 The semiconductor device 30 and Figure 1 The main difference between the semiconductor device 10 and the semiconductor device 30 is that in the semiconductor device 30 , a patterned cap layer 510P is included between the gate 610 and the channel structure 400 .

[0066] Please refer to Figure 4 , the patterned cap layer 510P is P-type gallium nitride, which is used to form a disconnection area of ​​the two-dimensional electron gas 415 or an area with relatively low electron density. The material of P-type gallium nitride is gallium nitride doped with dopants (such as magnesium). In some embodiments, in order to suppress the redistribution of dopants in P-type gallium nitride, a low-temperature aluminum nitride layer (not shown) is disposed under the P-type gallium nitride. The "low-temperature" aluminum nitride layer in this article refers to an aluminum nitride layer formed using an epitaxial temperature lower than the temperature (such as more than one thousand degrees Celsius) commonly used in the epitaxial process of HEMT devices, such as an aluminum nitride layer formed at an epitaxial temperature between 700°C and 800°C.

[0067] Figure 5is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 5 The implementation examples are used Figure 3 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0068] Figure 5 The semiconductor device 40 and Figure 3 The main difference between the semiconductor device 20 and the semiconductor device 40 is that in the semiconductor device 40 , the source 620 and the drain 630 extend into the channel structure 400 .

[0069] Figure 6 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 6 The implementation examples are used Figure 5 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0070] Figure 6 The semiconductor device 50 and Figure 5 The main difference between the semiconductor device 40 and the semiconductor device 50 is that in the semiconductor device 50 , the barrier structure 300 includes a first oxide layer 310A, a second oxide layer 310B and a nitride layer 320 .

[0071] Please refer to Figure 6 , the second oxide layer 310B is located between the first oxide layer 310A and the nitride layer 320. In some embodiments, the first oxide layer 310A and the second oxide layer 310B include aluminum oxide or other wide bandgap materials (e.g., materials with a bandgap width greater than the bandgap width of the nitride layer 320 and the bandgap width of the buffer layer 230). In some embodiments, the first oxide layer 310A and the second oxide layer 310B include the same or different materials.

[0072] Figure 7 is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention. It must be noted here that Figure 7 The implementation examples are used Figure 5 The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0073] Figure 7 The semiconductor device 60 and Figure 5 The main difference between the semiconductor device 40 and the semiconductor device 60 is that in the semiconductor device 60, the first oxide layer 310P of the barrier structure 300 is a patterned film layer.

[0074] The first oxide layer 310P is located on the buffer structure 200. For example, the first oxide layer 310P is formed on the buffer layer 230, and the buffer layer 230 contacts the first oxide layer 310P. In the present embodiment, the first oxide layer 310P is patterned to partially cover the top surface of the buffer structure 200, and the nitride layer 320 covers the side of the first oxide layer 310P. The first oxide layer 310P is located between the gate 610 and the buffer layer 230.

[0075] In the present embodiment, the material of the first oxide layer 310P includes aluminum oxide or other wide bandgap materials (eg, materials having a bandgap width greater than the bandgap width of the nitride layer 320 and the bandgap width of the buffer layer 230 ).

[0076] FIG. 8A to FIG. 8E is a cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention. For example, FIG. 8A to FIG. 8E yes Figure 1 A schematic cross-sectional view of a method for manufacturing a semiconductor device 10 is shown in FIG.

[0077] Please refer to Fig. 8A , providing a substrate 100.

[0078] Please refer to Figure 8B , forming a buffer structure 200 on the substrate 100. In the present embodiment, a nucleation layer 210 is formed on the substrate 100, and then a buffer layer 230 is formed on the nucleation layer 210. In some embodiments, the method of forming the nucleation layer 210 and the buffer layer 230 includes chemical vapor deposition, physical vapor deposition, metal organic chemical vapor deposition, plasma assisted chemical vapor deposition, metal organic chemical vapor epitaxy or other suitable methods.

[0079] Please refer to Figure 8C, forming an energy barrier structure 300 on the buffer structure 200. In the present embodiment, a first oxide layer 310 is formed on the buffer layer 230, and then a nitride layer 320 is formed on the first oxide layer 310. The first oxide layer 310 is located between the nitride layer 320 and the buffer structure 200. In some embodiments, the method of forming the first oxide layer 310 includes atomic layer deposition (Atomic layer deposition), and therefore, the first oxide layer 310 can be formed with a lower process temperature than the nucleation layer 210 and the buffer layer 230. For example, the process temperature of the first oxide layer 310 is 100 degrees Celsius to 200 degrees Celsius. Therefore, the quality of the thin film formed in the subsequent high temperature process (such as metal organic chemical vapor deposition) can be improved.

[0080] In some embodiments, the method of forming the nitride layer 320 includes chemical vapor deposition, physical vapor deposition, metal organic chemical vapor deposition, plasma assisted chemical vapor deposition, metal organic chemical vapor epitaxy or other suitable methods.

[0081] Please refer to Fig.8D , forming a channel structure 400 on the barrier structure 300. In the present embodiment, a channel layer 410 is formed on the nitride layer 320, and then a III-V barrier layer 420 is formed on the channel layer 410. In some embodiments, the method of forming the channel layer 410 and the III-V barrier layer 420 includes chemical vapor deposition, physical vapor deposition, metal organic chemical vapor deposition, plasma assisted chemical vapor deposition, metal organic chemical vapor epitaxy or other suitable methods. In the present embodiment, the film formation quality of the channel layer 410 is improved by using the first oxide layer 310 formed by atomic layer deposition. Therefore, even if the channel layer 410 and the buffer layer 230 include the same material, the probability of unexpected defects (such as cracks, holes, etc.) in the channel layer 410 is lower than the probability of unexpected defects (such as cracks, holes, etc.) in the buffer layer 230.

[0082] Please refer to Fig. 8E , a capping layer 510 is formed on the channel structure 400 , and then a passivation layer 520 is formed on the capping layer 510 .

[0083] Finally, please return Figure 1 , a gate 610 , a source 620 , and a drain 630 are formed above the channel structure 400 . In the present embodiment, the gate 610 , the source 620 , and the drain 630 are formed in the opening of the passivation layer 520 and contact the capping layer 510 .

[0084] In summary, by disposing the first oxide layer between the channel structure and the buffer structure, carriers can be prevented from flowing from the channel structure to the buffer structure, thereby improving the reliability of the semiconductor device.

Claims

1. A semiconductor device, characterized in that: include: substrate; A buffer structure, located on the substrate; An energy barrier structure, located on the buffer structure and comprising a first oxide layer; A channel structure, wherein the energy barrier structure is located between the channel structure and the buffer structure; The gate, the source and the drain are located above the channel structure.

2. The semiconductor device according to claim 1, wherein: The energy barrier structure also includes: A nitride layer, wherein the first oxide layer is located between the nitride layer and the buffer structure.

3. The semiconductor device according to claim 2, wherein: The energy barrier structure also includes: The second oxide layer is located between the first oxide layer and the nitride layer.

4. The semiconductor device according to claim 2, wherein: The first oxide layer is patterned to partially cover a top surface of the buffer structure.

5. The semiconductor device according to claim 2, wherein: The energy gap width of the first oxide layer is greater than the energy gap width of the nitride layer.

6. The semiconductor device according to claim 1, wherein: The buffer structure comprises: a buffer layer, wherein the buffer layer contacts the first oxide layer; and A nucleation layer is located between the buffer layer and the substrate.

7. The semiconductor device according to claim 6, wherein: The channel structure comprises: A channel layer, wherein a thickness of the channel layer is less than a thickness of the buffer layer.

8. The semiconductor device according to claim 1, wherein: The channel structure comprises: a channel layer; and A III-V barrier layer is provided, wherein the channel layer is located between the III-V barrier layer and the energy barrier structure, and a two-dimensional electron gas is located at an interface between the channel layer and the III-V barrier layer.

9. The semiconductor device according to claim 1, wherein: Also includes: A cap layer, located between the gate and the channel structure; as well as The passivation layer is located on the cap layer.

10. The semiconductor device according to claim 9, wherein: The capping layer includes P-type gallium nitride or N-type gallium nitride, and the passivation layer includes silicon nitride or aluminum oxide.

11. A method for manufacturing a semiconductor device, characterized in that: include: forming a buffer structure on a substrate; forming an energy barrier structure on the buffer structure, wherein the energy barrier structure comprises a first oxide layer; forming a channel structure on the barrier structure; and A gate, a source and a drain are formed above the channel structure.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The method of forming the buffer structure on the substrate includes: forming a nucleation layer on the substrate; and A buffer layer is formed on the nucleation layer, wherein the method of forming the energy barrier structure on the buffer structure comprises: forming the first oxide layer on the buffer layer; and A nitride layer is formed on the first oxide layer, wherein the first oxide layer is located between the nitride layer and the buffer structure, wherein a material of the first oxide layer includes aluminum oxide.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: The process temperature for forming the first oxide layer is 100 degrees Celsius to 200 degrees Celsius.

14. The method for manufacturing a semiconductor device according to claim 12, wherein: The method of forming the channel structure on the barrier structure includes: forming a channel layer on the nitride layer; and A III-V barrier layer is formed on the channel layer.

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