Semiconductor device and manufacturing method thereof
By forming a MIS structure at the drain of the GaN HEMT device, the problem of difficulty in achieving reverse blocking of the device is solved, the reverse blocking function is realized, and the good forward conduction performance is maintained, which enhances the application potential of the device in related fields.
Patent Information
- Application Number
- CN202411139101.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-19
- Publication Date
- 2025-03-28
AI Technical Summary
GaN HEMT devices themselves have the ability to conduct reverse conduction, making it difficult to achieve reverse blocking function, and cannot meet the market demand in areas such as power protection, inverter and motor control.
A metal-insulator-semiconductor (MIS) structure is formed at the drain, and a groove is formed in a stacked structure composed of a channel layer and a barrier layer, and an isolation dielectric layer and a drain are provided in the groove to achieve the reverse blocking function.
The reverse blocking function of GaN HEMT devices is realized, enhancing the device's application potential in the fields of power protection, inverter and motor control, while maintaining low turn-on voltage and low leakage current when forward conduction is carried out.
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Figure CN119730292A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor devices, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art
[0002] At present, in current-type AC-DC rectifiers or DC-AC inverters, unidirectional bidirectional blocking switches have broad application prospects. Among them, devices with reverse blocking function have a large market demand in the fields of power protection, inverters and motor control.
[0003] Gallium Nitride High Electron Mobility Transistor (GaN HEMT) has excellent characteristics such as high operating frequency, high breakdown voltage, high temperature resistance, small on-resistance, and high electron mobility. In harsh environments such as high temperature and strong radiation, the performance of GaN HEMT devices can still remain stable. Therefore, it would be a good choice to apply GaN HEMT devices in power protection, inverters, motor control and other fields.
[0004] However, the GaN HEMT device itself has the ability to conduct in the reverse direction, and it is difficult to achieve the reverse blocking function. Therefore, it is necessary to provide a new semiconductor device and a manufacturing method thereof to improve the above problems. Summary of the invention
[0005] In view of the above problems, the present disclosure provides a semiconductor device and a method for manufacturing the same, which enables the device to achieve a reverse blocking function by forming a Metal-Insulator-Semiconductor (MIS) structure at the drain.
[0006] According to one aspect of an embodiment of the present disclosure, there is provided a semiconductor device, including:
[0007] Channel layer;
[0008] A barrier layer is located on the channel layer, and the barrier layer contacts the channel layer to form a two-dimensional electron gas channel;
[0009] A first groove extending from the surface of the barrier layer to the channel layer;
[0010] an isolation dielectric layer, at least a portion of which extends from a sidewall of the first groove to a portion of a bottom surface of the first groove; and
[0011] Gate, source and drain,
[0012] The drain electrode is arranged in the first groove, and includes a first portion and a second portion connected to each other, and the first portion forms an ohmic contact with the channel layer.
[0013] The isolation dielectric layer is sandwiched between the second portion and the channel layer, and the isolation dielectric layer is sandwiched between the second portion and the barrier layer.
[0014] When the potential of the source is higher than the potential of the drain, the second portion of the drain, the isolation dielectric layer, and the channel layer block the two-dimensional electron gas channel.
[0015] Optionally, the second portion and the isolation dielectric layer form a field plate structure.
[0016] At the first groove, the field plate structure is used to adjust the electric field at the intersection of the barrier layer, the channel layer and the isolation dielectric layer.
[0017] Optionally, it also includes:
[0018] a buffer layer, the channel layer being located between the buffer layer and the barrier layer; and
[0019] a buried layer located in the buffer layer, the channel layer and the buried layer are separated by the buffer layer, and a depletion region is formed at a contact position between the buried layer and the buffer layer,
[0020] Wherein, an orthographic projection of at least part of the buried layer on the surface of the channel layer coincides with an orthographic projection of the drain on the surface of the channel layer.
[0021] Optionally, along the direction from the drain toward the source, an end of the buried layer close to the source exceeds an intersection of the barrier layer, the channel layer and the isolation dielectric layer.
[0022] Optionally, the gate includes a cap layer and a gate conductor stacked on the barrier layer,
[0023] The material of the cap layer includes P-type doped GaN.
[0024] Optionally, the gate passes through the barrier layer, and the gate includes a gate conductor and a gate dielectric layer located between the gate conductor and the channel layer.
[0025] Wherein, the barrier layer and the gate conductor are separated by the gate dielectric layer.
[0026] Optionally, the source electrode is located on the barrier layer and forms an ohmic contact with the barrier layer.
[0027] According to another aspect of an embodiment of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:
[0028] forming a channel layer;
[0029] forming a barrier layer on the channel layer, wherein the barrier layer contacts the channel layer to form a two-dimensional electron gas channel;
[0030] forming a first groove extending from a surface of the barrier layer to the channel layer;
[0031] forming an isolation dielectric layer, at least a portion of the isolation dielectric layer extending from a sidewall of the first groove to a portion of a bottom surface of the first groove; and
[0032] forming a gate, a source, and a drain;
[0033] The drain electrode is arranged in the first groove, and includes a first portion and a second portion connected to each other, and the first portion forms an ohmic contact with the channel layer.
[0034] The isolation dielectric layer is sandwiched between the second portion and the channel layer, and the isolation dielectric layer is sandwiched between the second portion and the barrier layer.
[0035] When the potential of the source is higher than the potential of the drain, the second portion of the drain, the isolation dielectric layer, and the channel layer block the two-dimensional electron gas channel.
[0036] Optionally, the method further comprises forming a buffer layer and a buried layer before forming the channel layer.
[0037] The channel layer is located between the buffer layer and the barrier layer, the buried layer is located in the buffer layer, the channel layer and the buried layer are separated by the buffer layer, and a depletion region is formed at a contact position between the buried layer and the buffer layer.
[0038] Wherein, an orthographic projection of at least part of the buried layer on the surface of the channel layer coincides with an orthographic projection of the drain on the surface of the channel layer.
[0039] Optionally, along the direction from the drain toward the source, an end of the buried layer close to the source exceeds an intersection of the barrier layer, the channel layer and the isolation dielectric layer.
[0040] Optionally, the step of forming the buffer layer and the buried layer includes:
[0041] forming a first buffer layer on the substrate;
[0042] forming a buried layer on the first buffer layer, wherein the buried layer covers a portion of a surface of the first buffer layer; and
[0043] A second buffer layer is formed to cover the first buffer layer and the buried layer. The first buffer layer and the second buffer layer constitute the buffer layer and surround the buried layer.
[0044] Optionally, the step of forming the buffer layer and the buried layer includes:
[0045] forming a first buffer layer on the substrate;
[0046] forming a second groove in the first buffer layer;
[0047] forming a buried layer in the second groove; and
[0048] A second buffer layer is formed to cover the first buffer layer and the buried layer. The first buffer layer and the second buffer layer constitute the buffer layer and surround the buried layer.
[0049] One of the above technical solutions has the following beneficial effects:
[0050] A groove is formed in a stacked structure composed of a channel layer and a barrier layer, and an isolation dielectric layer and a drain are arranged in the groove, wherein the groove extends from the surface of the barrier layer to the channel layer, thereby cutting off the two-dimensional electron gas channel in the channel layer. The first part of the drain forms an ohmic contact with the channel layer, and the second part of the drain is separated from the channel layer and the barrier layer by the isolation dielectric layer. At the groove, the second part of the drain, the isolation dielectric layer and the channel layer form a MIS structure. When the source potential is higher than the drain potential (VSD>0), the two-dimensional electron gas channel between the source and the first part of the drain is cut off, and the current cannot flow to the drain, thereby achieving a reverse blocking function.
[0051] Furthermore, since the second part of the drain and the isolation dielectric layer form a field plate structure, the field plate structure is used to adjust the electric field at the intersection of the isolation dielectric layer, the barrier layer and the channel layer located at the first groove. In the reverse blocking state, the field plate structure can reduce the electric field at the intersection to avoid premature breakdown of the semiconductor device at the intersection.
[0052] In some embodiments, by setting a floating buried layer corresponding to the drain position in the buffer layer, the contact area of the floating buried layer and the buffer layer forms a depletion region. In the reverse blocking state of the device, as the source voltage continues to increase, the area of the depletion region expands accordingly, and the depletion region and the field plate structure cooperate to adjust the electric field at the intersection to prevent the semiconductor device from breaking down prematurely at the intersection. Furthermore, the end of the floating buried layer close to the source exceeds the preset distance of the intersection, thereby ensuring that the expansion area of the depletion region is sufficient to shield the electric field at the intersection.
[0053] In addition, when the drain potential is higher than the source potential voltage (VDS>0), the device operates in the forward state, and the depletion region formed by the contact between the buffer layer and the floating buried layer can block the injection of electrons from the drain to the substrate, thereby reducing the leakage current between the drain and the substrate.
[0054] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.
[0056] Figure 1 A schematic diagram of the three-dimensional structure of a semiconductor device according to the first embodiment of the present disclosure is shown.
[0057] Figure 2 Shown along Figure 1 Schematic diagram of the cross section taken along line AA.
[0058] Figure 3 Shows Figure 2 Schematic diagram of the current path of the semiconductor device in the reverse blocking state.
[0059] Figure 4 Shows Figure 2 Schematic diagram of the current path of the semiconductor device in the forward conduction state.
[0060] Figure 5 A schematic structural diagram of a semiconductor device according to a second embodiment of the present disclosure is shown.
[0061] Figures 6 to 17 A schematic cross-sectional view showing a partial stage in a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. DETAILED DESCRIPTION
[0062] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.
[0063] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.
[0064] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".
[0065] Many specific details of the present disclosure are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.
[0066] Due to the polarization effect, a two-dimensional electron gas (2DEG) channel with a high electron density is formed at the AlGaN / GaN heterojunction interface in the GaN HEMT device. When the GaN HEMT device is in the forward conduction state, VDS>0 and the gate has a high potential relative to the source (for example, the source is grounded, the gate voltage is 2V, and the drain voltage is 10V), the 2DEG channel under the gate is turned on; when the GaN HEMT device is in the reverse blocking state, VSD>0 and the gate has a high potential relative to the drain (for example, the source and gate are grounded, and the drain is connected to a negative potential), the 2DEG channel under the gate will also be turned on to a certain extent. Whether in the forward conduction or reverse blocking state, the 2DEG channel under the gate will be turned on. This is due to the symmetry of the two-dimensional electron gas channel naturally formed in the GaN HEMT device due to polarization. In the related art, in order to make the GaN HEMT device have a reverse blocking function, a Schottky barrier will be formed at the drain of the device.
[0067] However, due to the large bandgap of GaN, the formation of a Schottky barrier at the drain will cause the GaN HEMT device to have a large forward turn-on voltage VON when it is forward-conducting. In other words, if the device needs to be forward-conducting, a large voltage needs to be applied to the drain to allow the device to turn on normally. Therefore, the Schottky barrier formed at the drain will affect the forward conduction performance of the device. In addition, the reverse blocking voltage resistance of the Schottky barrier is often poor, so designs such as drain field plates, fluorine ion implantation, and fin structures are derived to reduce the drain electric field.
[0068] Among them, the effect of the drain field plate is limited, and the traditional field plate cannot solve the problem of large leakage current caused by the Schottky junction. The potential barrier formed by fluorine ion implantation varies greatly with temperature, which poses a great challenge to the reliability of devices at high temperatures. The fin structure process is relatively complex, so the cost is relatively high. Increasing the channel length by increasing the MIS gate structure can increase the reverse withstand voltage of the device, but the increase is limited. In addition, it will significantly increase the forward turn-on voltage VON of the device.
[0069] In short, the formation of a Schottky barrier at the drain will bring a series of disadvantages to the device, such as high turn-on voltage, high temperature resistance, and limited reverse voltage resistance.
[0070] In view of the above problems, the purpose of the present disclosure is to provide a semiconductor device and a manufacturing method thereof, by forming a MIS structure at the drain, preferably forming a floating buried layer in the buffer layer corresponding to the drain position, so that the device can achieve a reverse blocking function without affecting forward conduction.
[0071] Figure 1 FIG. 1 is a schematic diagram showing a three-dimensional structure of a semiconductor device according to a first embodiment of the present disclosure.
[0072] Figure 2 Shown along Figure 1 Schematic diagram of the cross section taken along line AA, wherein the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other.
[0073] See also Figure 1 and Figure 2 The semiconductor device of the first embodiment of the present disclosure includes: a substrate 101, a buffer layer 102, a buried layer 103, a channel layer 110, a barrier layer 120, a gate 130, a source 140, a first groove 60, an isolation dielectric layer 150 and a drain 160, wherein along the X-axis direction, the source 140 and the drain 160 are respectively located on both sides of the gate 130.
[0074] Along the Z-axis direction, the buffer layer 102, the channel layer 110 and the barrier layer 120 are sequentially stacked on the substrate 101, wherein the channel layer 110 contacts the barrier layer 120 to form a 2DEG channel in the channel layer 110 (at Figure 2 In the embodiment, the dotted line in the channel layer 110 represents a 2DEG channel. In the present embodiment, the substrate 101 is, for example, a Si substrate, the materials of the buffer layer 102 and the channel layer 110 are, for example, GaN, and the material of the barrier layer 120 is, for example, AlGaN.
[0075] The buried layer 103 is located in the buffer layer 102, and the buried layer 103 is in a floating state and does not contact the channel layer 110, wherein the contact position between the buried layer 103 and the buffer layer 102 forms a depletion region 10. In this embodiment, the material of the buried layer 103 is, for example, P-type doped GaN, and the doping impurity is, for example, Mg. The thickness of the buried layer 103 along the Z-axis direction is 50 to 300 nm, and the doping concentration is 1*10 17 ~1*10 18 cm -3 .
[0076] The gate 130 includes a cap layer 131 and a gate conductor 132 sequentially stacked on the barrier layer 120 along the Z-axis direction. The source 140 is located on the barrier layer 120 and forms an ohmic contact with the barrier layer 120. In this embodiment, the material of the cap layer 131 is, for example, P-type doped GaN, the doping impurity is, for example, Mg, and the materials of the gate conductor 132, the source 140 and the drain 160 are metals.
[0077] The first groove 60 extends from the surface of the barrier layer 120 to near the surface of the channel layer 110. The isolation dielectric layer 150 is located on the sidewalls of the gate 130 and the source 140, on the surface of the barrier layer 120 between the gate 130, the source 140 and the drain 160, and on the sidewall of the first groove 60 and extending to the surface of a portion of the channel layer 110 at the bottom of the first groove 60. In this embodiment, the material of the isolation dielectric layer 150 is, for example, aluminum oxide or silicon nitride.
[0078] The drain 160 includes a first portion 161 and a second portion 162 connected to each other, and the first portion 161 forms an ohmic contact with the channel layer 110. Along the X-axis direction, the second portion 162 is separated from the barrier layer 120 by the isolation dielectric layer 150, and along the Z-axis direction, the second portion 162 is separated from the channel layer 110 by the isolation dielectric layer 150. Alternatively, it can be described that the isolation dielectric layer 150 is sandwiched between the second portion 162 and the channel layer 110, and the isolation dielectric layer 150 is sandwiched between the second portion 162 and the barrier layer 120. In this embodiment, the second portion 162 of the drain 160 at the first groove 60, the isolation dielectric layer 150 and the channel layer 110 form a MIS structure, and the second portion 162 and the isolation dielectric layer 150 thereunder form a field plate structure 20. Along the Z-axis direction, the drain 160 and the buried layer 103 are opposite to each other, and the orthographic projection of at least part of the buried layer 103 on the surface of the channel layer 110 coincides with the orthographic projection of the drain 160 on the surface of the channel layer 110. Figure 3, at the corner of the first groove 60, the barrier layer 120, the channel layer 110 and the isolation dielectric layer 150 intersect, and the dotted circle 30 represents the intersection of the three. In some preferred embodiments, along the direction from the drain 160 to the source 140, the end of the buried layer 103 close to the source 140 exceeds the intersection 30, and the exceeding distance is a preset distance.
[0079] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other settings for the materials, doping impurities, and size parameters of the substrate 101, buffer layer 102, buried layer 103, channel layer 110, barrier layer 120, gate 130, source 140, and drain 160 as needed.
[0080] Figure 3 Shows Figure 2 Schematic diagram of the current path of the semiconductor device in the reverse blocking state, wherein the white arrow in the channel layer 110 represents the current path, and the path ends at the intersection 30.
[0081] See also Figure 3 When the semiconductor device is in a reverse blocking state, the potential of the source 140 is higher than the potential of the drain 160 (VSD>0), the gate 130 and the source 140 can be short-circuited and grounded, or the gate 130 and the source 140 can be connected to a low potential, such as 0.5 V. Assume that the gate 130 and the source 140 are grounded, and the drain 160 is connected to a negative potential. In the channel layer 110, the 2DEG channel near the drain 160 is cut off by the first groove (it can also be expressed as being cut off by the MIS structure composed of the second part 162 of the drain 160, the isolation dielectric layer 150 and the channel layer 110), and because the drain 160 is connected to a negative potential, in the MIS structure at the drain 160, the conductive channel under the isolation dielectric layer 150 will not be restored, and electrons cannot be transferred from the drain 160 to the source 140 through the channel layer 110. The 2DEG channel located under the gate 130 will not be restored, and the MIS structure at the drain 160 suppresses the leakage current.
[0082] As the potential difference between the source 140 and the drain 160 continues to increase (VSD continues to increase), the 2DEG channel under the gate 130 is turned on. At this time, the voltage drop between the source 140 and the drain 160 will be concentrated at the intersection 30, so the electric field at the intersection 30 is very high, and the field plate structure 20 can reduce the electric field at the intersection 30 to prevent the device from being broken down prematurely at the intersection 30.
[0083] As VSD increases further, the effect of the field plate structure 20 in suppressing leakage current reaches its upper limit. Under the action of high electric field, the electric field peak at the intersection 30 is large, and the leakage current continues to increase, which will affect the reverse blocking withstand voltage. At this time, the floating buried layer 103 begins to play a role. The PN junction of the buried layer 103 close to the source 140 is reverse biased, and the depletion region expands, wrapping the intersection 30, and the electric field peak is transferred to the left end of the buried layer 103 (the end of the buried layer 103 close to the source 140), thereby playing the role of electric field shielding for the intersection 30, effectively modulating the electric field, thereby reducing the leakage current of the device and improving the reverse blocking withstand voltage. Among them, the change amplitude of the electric field at the intersection 30 and the left end of the buried layer 103 is different in different withstand voltage stages (different VSD), realizing the optimization of the lateral distribution of the electric field by the buried layer 103.
[0084] Figure 4 Shows Figure 2 Schematic diagram of current path of the semiconductor device in the forward conduction state, wherein the white arrow in the channel layer 110 represents the current path.
[0085] See also Figure 4 , since the 2DEG channel at the corresponding drain 160 is cut off, in order to turn on the device in the forward direction, it is necessary to restore the channel at the drain 160 first. Specifically, a forward voltage is applied to the drain 160. As the voltage continues to rise, an electron accumulation layer 40 is formed in the channel layer 110 below the drain 160 in the area close to the isolation dielectric layer 150, so that the drain 160 is connected to the 2DEG channel through the electron accumulation layer 40. At this time, the forward voltage applied to the drain 160 is the turn-on voltage VON. When VDS is greater than VON, the device will be controlled by the gate voltage VGS to be forward turned on. Then, when the gate voltage VGS is greater than the threshold voltage VTH, the 2DEG channel under the gate 130 is restored, and the channel is fully turned on.
[0086] Since GaN is a wide bandgap semiconductor, the formation of a Schottky barrier at the drain end will cause the device to require a large turn-on voltage when it is turned on in the forward direction, for example, 2 to 3V. In this embodiment, the turn-on voltage required for the formation of the MIS structure at the drain end can be controlled at about 1V. When forward-conducting, the loss of the drain 160 in this embodiment is small, and the power consumption is reduced by about 1 times. In addition, the Schottky junction at the drain end of the related art will inject a large number of electrons into the channel layer and the buffer layer, while in this embodiment, the drain end forms a MIS structure, and the electrons are blocked by the isolation dielectric layer 150, thereby greatly reducing the leakage current.
[0087] See again Figure 2 and Figure 3When the semiconductor device is in the forward blocking state, the potential of the drain 160 is higher than the potential of the source 140 (VDS>0), and the gate 130 and the source 140 can be short-circuited and grounded, or the gate 130 can be connected to a negative potential. As the voltage of the drain 160 continues to rise, a vertical leakage path from the drain 160 to the substrate 101 is formed (the substrate 101 is generally connected to 0 potential). At this time, the PN junction above the buried layer 103 (on the side close to the drain 160) is reverse biased, and the depletion region expands, effectively reducing the leakage current during forward blocking, and realizing the optimization of the vertical distribution of the electric field by the buried layer 103.
[0088] Figure 5 A schematic structural diagram of a semiconductor device according to a second embodiment of the present disclosure is shown.
[0089] See also Figure 5 The similarities between this embodiment and the first embodiment are not described here, except that, in this embodiment, the gate 130 penetrates the barrier layer 120 along the Z-axis direction. The gate 130 includes a gate conductor 134 and a gate dielectric layer 133 between the gate conductor 134 and the channel layer 110, and along the X-axis direction, the barrier layer 120 and the gate conductor 134 are separated by the gate dielectric layer 133.
[0090] In this embodiment, the gate 130 is a MIS structure, and its blocking capability for the 2DEG channel below it is stronger than that of the gate 130 of the P-cap structure in the first embodiment. In order to simplify the process steps of the semiconductor device, the structure of the buried layer 103 can be omitted. However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art can also set a floating P buried layer as needed.
[0091] Figures 6 to 17 A schematic cross-sectional view showing a partial stage in a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure.
[0092] like Figure 6 As shown, along the Z-axis direction, a first buffer layer 1021 and a buried layer 103 are stacked in sequence on the substrate 101 .
[0093] Further, a portion of the buried layer 103 is removed to expose a portion of the surface of the first buffer layer 1021, such as Figure 7 shown.
[0094] Further, a second buffer layer 1022 is formed covering the first buffer layer 1021 and the buried layer 103, as shown in FIG. Figure 8 The first buffer layer 1021 and the second buffer layer 1022 form the buffer layer 102 and surround the buried layer 103 .
[0095] The method of forming the buffer layer 102 and the buried layer 103 can also refer to Figures 9 to 11 .
[0096] like Fig. 9 As shown, a first buffer layer 1021 is formed on the substrate 101 , a mask layer 50 is formed on the first buffer layer 1021 , and the first buffer layer 1021 is etched through the mask layer 50 to form a second groove 51 .
[0097] Furthermore, a buried layer 103 is formed in the second groove 51, such as Fig.10 As shown, the mask layer 50 is then removed.
[0098] Further, a second buffer layer 1022 is formed covering the first buffer layer 1021 and the buried layer 103, as shown in FIG. Fig.11 The first buffer layer 1021 and the second buffer layer 1022 form the buffer layer 102 and surround the buried layer 103 .
[0099] Furthermore, along the Z-axis direction, a stacked channel layer 110, a barrier layer 120, a cap layer 131 and a gate conductor layer 132 are sequentially formed on the buffer layer 102, such as Fig.12 shown.
[0100] Further, a portion of the cap layer 131 and the gate conductor layer 132 are removed, and the remaining cap layer 131 and the gate conductor layer 132 constitute the gate 130, as shown in FIG. Fig.13 shown.
[0101] Further, a source electrode 140 is formed on the barrier layer 120, such as Fig.14 As shown, the source electrode 140 and the barrier layer 120 are in ohmic contact.
[0102] Further, the barrier layer 120 is etched to form a first groove 60, such as Fig.15 shown.
[0103] In some specific embodiments, the barrier layer 120 has a thickness of about tens of nanometers, which can be used to form a conventional GaN HEMT. Therefore, the first groove 60 is formed to extend from the surface of the barrier layer 120 to the vicinity of the surface of the channel layer 110, so that the 2DEG channel in the channel layer 110 can be completely cut off at the first groove 60. Different from the conventional GaN HEMT, in the thin barrier GaN HEMT (the barrier layer thickness is not greater than 4nm), the 2DEG channel can be blocked by etching the dielectric layer above the barrier layer without etching the barrier layer.
[0104] Furthermore, an isolation dielectric layer 150 is formed to cover the source 140, the gate 130, the barrier layer 120 and the channel layer 110. Fig.16 As shown, corresponding to the position of the first groove 60 , the isolation dielectric layer 150 covers the sidewall and the bottom surface of the first groove 60 .
[0105] Furthermore, the isolation dielectric layer 150 on the surface of the source 140 and the gate 130 is removed, and a portion of the isolation dielectric layer 150 located at the bottom of the first groove 60 is removed, thereby exposing a portion of the channel layer 110, such as Fig.17 shown.
[0106] Furthermore, a drain electrode 160 is formed in the first groove 60, such as Figure 1 and Figure 2 As shown, the drain 160 includes a first part 161 and a second part 162, the first part 161 forms an ohmic contact with the channel layer 110, along the X-axis direction, the second part 162 is separated from the barrier layer 120 by the isolation dielectric layer 150, and along the Z-axis direction, the second part 162 is separated from the channel layer 110 by the isolation dielectric layer 150.
[0107] In some other embodiments, when the gate 130 is a MIS structure, the gate 130 and the MIS structure at the drain 160 can be formed simultaneously, saving process steps.
[0108] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A semiconductor device, comprising: Channel layer; A barrier layer is located on the channel layer, wherein the barrier layer contacts the channel layer to form a two-dimensional electron gas channel; A first groove extending from the surface of the barrier layer to the channel layer; an isolation dielectric layer, at least a portion of which extends from a sidewall of the first groove to a portion of a bottom surface of the first groove; as well as Gate, source and drain, The drain electrode is arranged in the first groove, and includes a first portion and a second portion connected to each other, and the first portion forms an ohmic contact with the channel layer. The isolation dielectric layer is sandwiched between the second portion and the channel layer, and the isolation dielectric layer is sandwiched between the second portion and the barrier layer. When the potential of the source is higher than the potential of the drain, the second portion of the drain, the isolation dielectric layer, and the channel layer block the two-dimensional electron gas channel.
2. The semiconductor device according to claim 1, wherein The second portion and the isolation dielectric layer form a field plate structure, At the first groove, the field plate structure is used to adjust the electric field at the intersection of the barrier layer, the channel layer and the isolation dielectric layer.
3. The semiconductor device according to claim 1, further comprising: a buffer layer, wherein the channel layer is located between the buffer layer and the barrier layer; as well as a buried layer located in the buffer layer, the channel layer and the buried layer are separated by the buffer layer, and a depletion region is formed at a contact position between the buried layer and the buffer layer, Wherein, an orthographic projection of at least part of the buried layer on the surface of the channel layer coincides with an orthographic projection of the drain on the surface of the channel layer.
4. The semiconductor device according to claim 3, wherein: Along the direction from the drain toward the source, the end of the buried layer close to the source exceeds the intersection of the barrier layer, the channel layer and the isolation dielectric layer.
5. The semiconductor device according to any one of claims 1 to 4, wherein: The gate includes a cap layer and a gate conductor stacked on the barrier layer, The material of the cap layer includes P-type doped GaN.
6. The semiconductor device according to any one of claims 1 to 4, wherein: The gate penetrates the barrier layer, and the gate includes a gate conductor and a gate dielectric layer located between the gate conductor and the channel layer. Wherein, the barrier layer and the gate conductor are separated by the gate dielectric layer.
7. The semiconductor device according to any one of claims 1 to 4, wherein: The source electrode is located on the barrier layer and forms an ohmic contact with the barrier layer.
8. A method for manufacturing a semiconductor device, comprising: forming a channel layer; forming a barrier layer on the channel layer, wherein the barrier layer contacts the channel layer to form a two-dimensional electron gas channel; forming a first groove extending from a surface of the barrier layer to the channel layer; forming an isolation dielectric layer, wherein at least a portion of the isolation dielectric layer extends from a sidewall of the first groove to a portion of a bottom surface of the first groove; as well as forming a gate, a source, and a drain; The drain electrode is arranged in the first groove, and includes a first portion and a second portion connected to each other, and the first portion forms an ohmic contact with the channel layer. The isolation dielectric layer is sandwiched between the second portion and the channel layer, and the isolation dielectric layer is sandwiched between the second portion and the barrier layer. When the potential of the source is higher than the potential of the drain, the second portion of the drain, the isolation dielectric layer, and the channel layer block the two-dimensional electron gas channel.
9. The manufacturing method according to claim 8, further comprising forming a buffer layer and a buried layer before forming the channel layer, The channel layer is located between the buffer layer and the barrier layer, the buried layer is located in the buffer layer, the channel layer and the buried layer are separated by the buffer layer, and a depletion region is formed at a contact position between the buried layer and the buffer layer. in, An orthographic projection of at least a portion of the buried layer on the surface of the channel layer coincides with an orthographic projection of the drain on the surface of the channel layer.
10. The manufacturing method according to claim 9, wherein: Along the direction from the drain toward the source, the end of the buried layer close to the source exceeds the intersection of the barrier layer, the channel layer and the isolation dielectric layer.
11. The manufacturing method according to claim 9 or 10, wherein: The steps of forming the buffer layer and the buried layer include: forming a first buffer layer on the substrate; forming a buried layer on the first buffer layer, wherein the buried layer covers a portion of a surface of the first buffer layer; and A second buffer layer is formed to cover the first buffer layer and the buried layer. The first buffer layer and the second buffer layer constitute the buffer layer and surround the buried layer.
12. The manufacturing method according to claim 9 or 10, wherein: The steps of forming the buffer layer and the buried layer include: forming a first buffer layer on the substrate; forming a second groove in the first buffer layer; forming a buried layer in the second groove; and A second buffer layer is formed to cover the first buffer layer and the buried layer. The first buffer layer and the second buffer layer constitute the buffer layer and surround the buried layer.