High-breakdown honeycomb-shaped quasi-vertical enhanced GaN transistor and preparation method thereof

Abstract

The invention discloses a high-breakdown honeycomb-shaped quasi-vertical enhanced GaN transistor and a preparation method thereof, and belongs to the technical field of semiconductor devices. The honeycomb-shaped quasi-vertical enhanced GaN transistor comprises an epitaxial substrate, a low-resistance substrate, a drain contact electrode, a low-doped channel layer, a gate field plate medium, a gate medium, a gate metal electrode, a gate source isolation medium, a honeycomb-shaped channel structure, a high-doped channel layer, an isolation passivation layer and a source contact electrode, and the honeycomb channel structure is a columnar three-dimensional structure with a hexagonal section. Based on the structural design of the honeycomb-shaped channel structure, enhancement can be achieved based on a charge depletion structure of a columnar channel, meanwhile, relieving of a terminal peak electric field under high voltage is effectively achieved, and therefore the high-breakdown quasi-vertical enhancement GaN transistor is obtained.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a high-breakdown honeycomb quasi-vertical enhancement-type GaN transistor and a preparation method thereof. Background Art

[0002] The third-generation semiconductor GaN material has excellent properties such as wide band gap, high breakdown field strength, high saturated electron drift velocity and high-concentration heterojunction two-dimensional electron gas. It is the preferred structure for preparing high-power, high breakdown voltage and high-frequency power electronic devices, and has important application prospects in wireless communications, power systems, detection and other fields.

[0003] Lateral power devices based on AlGaN / GaN heterostructures have achieved excellent performance in the past decade. Power devices operating on silicon substrates have been tested and applied. However, for high-voltage and high-current applications, quasi-vertical structures should be preferred because they have the following advantages: 1) The module unit area does not affect the breakdown voltage; 2) The surface is away from the high electric field area, thereby minimizing the impact of the trap effect; 3) When the source and drain contacts are placed vertically on opposite sides of the wafer, it is easier to extract current to achieve high current levels; 4) Due to the wider distribution of current and electric field, it has better thermal performance. However, quasi-vertical devices still face some problems. Common Fin-strip-based structures are strongly dependent on electron beam direct writing equipment, which greatly affects production efficiency and increases production costs, thus limiting their application scenarios.

[0004] Therefore, developing a quasi-vertical enhancement-mode GaN transistor with high breakdown that can be efficiently realized based on step-by-step lithography is of great significance for practical applications. Summary of the invention

[0005] Purpose of the invention: The first purpose of the present invention is to provide a high-breakdown honeycomb quasi-vertical enhancement-type GaN transistor. The second purpose of the present invention is to provide a method for preparing the above-mentioned quasi-vertical enhancement-type GaN transistor.

[0006] Technical solution: The high-breakdown honeycomb quasi-vertical enhancement-mode GaN transistor of the present invention comprises an epitaxial substrate, a low-resistance substrate, a drain contact electrode, a low-doped channel layer, a gate field plate dielectric, a gate dielectric, a gate metal electrode, a gate-source isolation dielectric, a plurality of honeycomb channel structures, a high-doped channel layer, an isolation passivation layer and a source contact electrode; wherein the low-resistance substrate is arranged on the epitaxial substrate, the drain contact electrode and the low-doped channel layer are arranged on the low-resistance substrate, the drain contact electrodes are distributed at both ends of the low-doped channel layer, and the honeycomb channel structure is arranged on the low-doped On the channel layer, the angle surface formed by the honeycomb channel structure and the low-doped channel layer is composed of a gate field plate dielectric, a gate dielectric, a gate metal electrode and a gate-source isolation dielectric from bottom to top. The heights of the gate dielectric and the gate metal electrode are consistent and higher than the height of the gate field plate dielectric. The top of the gate-source isolation dielectric is filled with an isolation passivation layer and is in the same horizontal plane as the top of the honeycomb channel structure. The highly doped channel layer is arranged on the honeycomb channel structure, and the tops of the highly doped channel layer and the isolation passivation layer are source contact electrodes. The honeycomb channel structure is a columnar three-dimensional structure with a hexagonal cross-section.

[0007] Furthermore, the epitaxial substrate is any one of SiC, Si, sapphire, diamond and GaN self-supporting substrate; the low-resistance substrate is any one of SiC, Si, diamond and GaN substrate materials, and the effective carrier concentration should be greater than 10 18 The low-doped channel layer and the honeycomb channel structure are made of materials with an n-type carrier concentration of less than 10 17 GaN material; the highly doped channel layer has an n-type carrier concentration greater than 10 18 GaN material.

[0008] Furthermore, the gate dielectric is a single layer or a combination of multiple stacked structures of HfO2, ZrO2, Si3N4, SiO2, Al2O3, AlNO, with a total thickness of 5-20nm.

[0009] Furthermore, the gate metal electrode is a high work function metal, located on the upper part of the gate dielectric and surrounding the honeycomb channel structure; the high work function metal is one of W, Ni, Pt, and TiN.

[0010] Furthermore, the source contact electrode and the drain contact electrode are ohmic contacts formed by annealing a low work function metal.

[0011] Furthermore, the low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy, and Ti-Al-Mo-Au alloy.

[0012] Furthermore, the gate field plate dielectric is one or more of SiO2, Si3N4, Al2O3 dielectrics with a thickness of 200-400nm.

[0013] Furthermore, the isolation passivation layer is one or more of SiO2, Si3N4, and Al2O3 media.

[0014] The method for preparing the quasi-vertical enhancement mode GaN transistor comprises the following steps:

[0015] 1) preparing a low-resistance substrate, a low-doped channel layer, a honeycomb channel structure layer and a high-doped channel layer in sequence on the epitaxial substrate by using an epitaxial growth method;

[0016] 2) defining a mask layer on the highly doped channel layer, and then forming a main mesa by etching;

[0017] 3) Patterning is performed on the formed main table surface to generate an etching mask layer, and a honeycomb channel structure (9) is obtained by etching;

[0018] 4) depositing and etching a gate field plate dielectric on the honeycomb channel structure and the low-doped channel layer;

[0019] 5) depositing and etching a gate dielectric and a gate metal electrode layer on the gate field plate dielectric to form a gate control structure;

[0020] 6) growing a gate-source isolation dielectric and an isolation passivation layer on the formed gate-controlled structure, and exposing the honeycomb channel structure and the top of the highly doped channel layer by etching;

[0021] 7) A mask for source contact electrode and drain contact electrode is defined above the isolation passivation layer and the low-resistance substrate, a low work function metal is deposited by evaporation or sputtering, and the source contact electrode and drain contact electrode are formed by a lift-off annealing process to obtain a high-breakdown honeycomb quasi-vertical enhancement-mode GaN transistor.

[0022] Furthermore, in step 1), the epitaxial growth method includes metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) and hydride vapor phase epitaxy (HVPE).

[0023] Furthermore, in step 2), the mask is manufactured by optical lithography or electron beam direct writing.

[0024] Furthermore, in step 3), the etching method includes dry etching and wet etching.

[0025] Furthermore, in step 4) and step 5), the growth methods of the gate field plate dielectric, gate source isolation dielectric and isolation passivation layer include low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) and atomic layer deposition (ALD).

[0026] Principle of the invention: In the present invention, the honeycomb quasi-vertical enhancement-type GaN transistor includes an epitaxial substrate, a low-resistance substrate, a low-doped channel layer, a high-doped channel layer, an insulating dielectric, a contact electrode and a passivation layer. The source and drain electrodes are ohmic contacts formed by depositing low-work function metal on the high-doped channel layer and the low-resistance substrate and annealing. The gate electrode is a voltage-controlled structure composed of metal and gate dielectric. The honeycomb quasi-vertical structure can make full use of the large-area depletion gate formed by its interaction to realize the preparation of high-efficiency enhancement-type devices that do not rely on direct writing of electronic books. The use of this structure can simplify the epitaxial layer design, thereby reducing wafer and production costs.

[0027] Beneficial effects: Compared with the prior art, the present invention has the following significant effects: (1) The conventional quasi-vertical enhancement-mode GaN transistor adopts a top Fin strip structure. The preparation of this structure needs to rely on electron beam direct writing to achieve a sufficiently thin structure for sidewall depletion to achieve enhancement. Its complex process and the high cost and low efficiency of electron beam direct writing make it difficult to apply in a process production environment. The honeycomb structure of the present invention adopts a hexagonal columnar structure similar to a honeycomb. The sidewall depletion of this structure is more efficient, so it can be completed using a step-and-repeat lithography machine, which has the huge advantages of high efficiency and low cost, and solves the key technical problems of quasi-vertical devices in practical applications; (2) Compared with the traditional Fin strip structure, the honeycomb columnar structure adopted by the present invention can link the electric field concentration effect at the bottom of the column under high voltage through more electric field terminal dispersion points at the bottom, thereby achieving a higher breakdown voltage and a smaller leakage current than the traditional structure; (3) The epitaxial structure adopted by the present invention is simpler and easier to obtain than the material structure required for the aperture-type vertical GaN crystal structure that requires a P-type or I-type GaN layer, which also greatly reduces the cost of the substrate material required for the process. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the structure of a honeycomb-shaped quasi-vertical enhancement-mode GaN transistor, (a) is a cross-sectional schematic diagram, and (b) is a top view of the honeycomb channel structure;

[0029] Figure 2 Schematic diagram of the preparation process of high-breakdown honeycomb quasi-vertical enhancement-mode GaN transistor. DETAILED DESCRIPTION

[0030] The present invention is further described in detail below in conjunction with the embodiments and drawings.

[0031] Example 1: Figure 1 As shown, the high breakdown honeycomb quasi-vertical enhancement-mode GaN transistor provided in this embodiment includes an epitaxial substrate 1, a low-resistance substrate 2, a drain contact electrode 3, a low-doped channel layer 4, a gate field plate dielectric 5, a gate dielectric 6, a gate metal electrode 7, a gate-source isolation dielectric 8, a honeycomb channel structure 9, a highly doped channel layer 10, an isolation passivation layer 11 and a source contact electrode 12; wherein the low-resistance substrate 2 is arranged on the epitaxial substrate 1, the drain contact electrode 3 and the low-doped channel layer 4 are arranged on the low-resistance substrate 2, the drain contact electrode 3 is distributed at both ends of the low-doped channel layer 4, and the honeycomb channel structure 9 is arranged at the low-doped channel On layer 4, the angle surface formed by the honeycomb channel structure 9 and the low-doped channel layer 4 is, from bottom to top, a gate field plate dielectric 5, a gate dielectric 6, a gate metal electrode 7 and a gate-source isolation dielectric 8. The heights of the gate dielectric 6 and the gate metal electrode 7 are consistent and higher than the height of the gate field plate dielectric 5. The top of the gate-source isolation dielectric 8 is filled with an isolation passivation layer 11 and is in the same horizontal plane as the top of the honeycomb channel structure 9. The highly doped channel layer 10 is arranged on the honeycomb channel structure 9, and the tops of the highly doped channel layer 10 and the isolation passivation layer 11 are source contact electrodes 12; the honeycomb channel structure 9 is a columnar three-dimensional structure with a hexagonal cross-section.

[0032] like Figure 2 As shown, the method for preparing the above-mentioned honeycomb quasi-vertical enhancement-mode GaN transistor comprises the following specific steps:

[0033] 1) If Figure 2 As shown in (a), a low-resistance substrate 2, a low-doped channel layer 4, a honeycomb channel structure layer and a high-doped channel layer 10 are sequentially grown on an epitaxial substrate 1 by an epitaxial growth method, wherein the epitaxial substrate 1 is any one of SiC, Si, sapphire, diamond and GaN self-supporting substrates; the low-resistance substrate 2 is any one of SiC, Si, diamond and GaN substrate materials, and the effective carrier concentration should be greater than 10 18 ; The material used for the low-doped channel layer 4 and the honeycomb channel structure layer is an n-type carrier concentration less than 10 17 GaN material; the highly doped channel layer 10 has an n-type carrier concentration greater than 10 18 GaN materials;

[0034] 2) If Figure 2 As shown in (a), a mask layer is defined on the highly doped channel layer 10, and then a main mesa is formed by an etching method;

[0035] 3) If Figure 2 As shown in (b), patterning is performed on the formed main table surface to generate an etching mask layer, and a honeycomb channel structure 9 is obtained by etching, as shown in FIG. Figure 2 As shown in (c);

[0036] 4) If Figure 2 As shown in (d), a gate field plate dielectric 5 is deposited and etched on the honeycomb channel structure 9 and the low-doped channel layer 4, wherein the gate field plate dielectric 5 is one or more of SiO2, Si3N4, and Al2O3 dielectrics with a thickness of 200-400 nm obtained by different growth methods;

[0037] 5) If Figure 2 As shown in (e), a gate dielectric 6 and a gate metal electrode 7 layer are deposited on the gate field plate dielectric 5 and etched to form a gate control structure, wherein the gate dielectric 6 is a single layer or a combination of multiple stacked structures of HfO2, ZrO2, Si3N4, SiO2, Al2O3, AlNO based on different growth technologies, with a total thickness of 5-20nm, and the high work function metal is one of W, Ni, Pt, and TiN as the gate metal electrode 7;

[0038] 6) If Figure 2 As shown in (f), a gate-source isolation dielectric 8 and an isolation passivation layer 11 are grown on the formed gate control structure, and the top of the honeycomb channel structure 9 and the highly doped channel layer 10 are exposed by etching, wherein the isolation passivation layer 11 is one or more of SiO2, Si3N4, and Al2O3 dielectrics obtained by different growth methods;

[0039] 7) If Figure 2 As shown in (g), a mask for defining a source contact electrode 12 and a drain contact electrode 3 is formed above the isolation passivation layer 11 and the low-resistance substrate 2, a low work function metal is deposited by evaporation or sputtering, and the source contact electrode 12 and the drain contact electrode 3 are formed by a lift-off annealing process, wherein the low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy, and Ti-Al-Mo-Au alloy.

[0040] So far, the present embodiment has been described in detail in conjunction with the accompanying drawings. Based on the above description, those skilled in the art should have a clear understanding of the present invention "a high breakdown honeycomb quasi-vertical enhancement-type GaN transistor and a preparation method". Based on the preparation method proposed in the present invention, while having a lower production cost, the breakdown voltage of the device can be increased, thereby enabling efficient and reliable manufacture of quasi-vertical enhancement-type GaN transistors with high breakdown voltage.

[0041] It should be noted that the implementation methods not shown or described in the drawings or the text of the specification are all forms known to ordinary technicians in the relevant technical field and are not described in detail. In addition, the above definitions of various elements and methods are not limited to the various specific structures, shapes or methods mentioned in the embodiments. Ordinary technicians in this field can simply change or replace them. For example, the GaN layer can be replaced by an AlGaN layer.

[0042] It should also be noted that this document may provide demonstrations of parameters containing specific values, but these parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint. The directional terms mentioned in the embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only reference directions of the accompanying drawings and are not intended to limit the scope of protection of the present invention. In addition, unless the steps are specifically described or must occur in sequence, the order of the above steps is not limited to those listed above, and can be changed or rearranged according to the desired design. And the above embodiments can be mixed and matched with each other or with other embodiments based on design and reliability considerations, that is, the technical features in different embodiments can be freely combined to form more embodiments.

[0043] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A high breakdown honeycomb quasi-vertical enhancement-mode GaN transistor, characterized in that: The invention comprises an epitaxial substrate (1), a low-resistance substrate (2), a drain contact electrode (3), a low-doped channel layer (4), a gate field plate dielectric (5), a gate dielectric (6), a gate metal electrode (7), a gate-source isolation dielectric (8), a honeycomb channel structure (9), a highly doped channel layer (10), an isolation passivation layer (11) and a source contact electrode (12); wherein the low-resistance substrate (2) is arranged on the epitaxial substrate (1), the drain contact electrode (3) and the low-doped channel layer (4) are arranged on the low-resistance substrate (2), the drain contact electrode (3) is distributed at both ends of the low-doped channel layer (4), the honeycomb channel structure (9) is arranged on the low-doped channel layer (4), and the honeycomb channel structure (12) is provided on the low-doped channel layer (4). 9) and the low-doped channel layer (4), from bottom to top, are a gate field plate dielectric (5), a gate dielectric (6), a gate metal electrode (7) and a gate-source isolation dielectric (8); the heights of the gate dielectric (6) and the gate metal electrode (7) are consistent and higher than the height of the gate field plate dielectric (5); the top of the gate-source isolation dielectric (8) is filled with an isolation passivation layer (11) and is at the same horizontal plane as the top of the honeycomb channel structure (9); the highly doped channel layer (10) is arranged on the honeycomb channel structure (9); the tops of the highly doped channel layer (10) and the isolation passivation layer (11) are source contact electrodes (12); and the honeycomb channel structure (9) is a columnar three-dimensional structure with a hexagonal cross-section.

2. The quasi-vertical enhancement mode GaN transistor according to claim 1, characterized in that: The epitaxial substrate (1) is any one of SiC, Si, sapphire, diamond and GaN self-supporting substrates; the low-resistance substrate (2) is any one of SiC, Si, diamond and GaN substrate materials, and the effective carrier concentration should be greater than 10 18 The low-doped channel layer (4) and the honeycomb channel structure (9) are made of materials with an n-type carrier concentration of less than 10 17 GaN material; the highly doped channel layer (10) has an n-type carrier concentration greater than 10 18 GaN material.

3. The quasi-vertical enhancement mode GaN transistor according to claim 1, characterized in that: The gate dielectric (6) is a single layer or a combination of multiple stacked structures of HfO2, ZrO2, Si3N4, SiO2, Al2O3, AlNO, with a total thickness of 5-20nm.

4. The quasi-vertical enhancement mode GaN transistor according to claim 1, characterized in that: The gate metal electrode (7) is a high work function metal, located on the upper part of the gate dielectric (6) and surrounding the honeycomb channel structure (9); the high work function metal is one of W, Ni, Pt and TiN.

5. The quasi-vertical enhancement mode GaN transistor according to claim 1, characterized in that: The source contact electrode (12) and the drain contact electrode (3) are ohmic contacts formed by annealing low work function metal.

6. The quasi-vertical enhancement mode GaN transistor according to claim 5, characterized in that: The low work function metal is one of Ti-Al alloy, Ti-Al-Ti-Au alloy, Ti-Al-Ni-Au alloy and Ti-Al-Mo-Au alloy.

7. The quasi-vertical enhancement mode GaN transistor according to claim 1, characterized in that: The gate field plate medium (5) is one or more of SiO2, Si3N4, and Al2O3 medium with a thickness of 200-400nm.

8. The quasi-vertical enhancement-mode GaN transistor according to claim 1, characterized in that: The isolation passivation layer (11) is one or more of SiO2, Si3N4, and Al2O3 media.

9. A method for preparing a quasi-vertical enhancement mode GaN transistor according to any one of claims 1 to 8, characterized in that: The following steps are involved: 1) on an epitaxial substrate (1), a low-resistance substrate (2), a low-doped channel layer (4), a honeycomb channel structure layer and a high-doped channel layer (10) are sequentially prepared by an epitaxial growth method; 2) defining a mask layer on the highly doped channel layer (10), and then forming a main mesa by an etching method; 3) Patterning is performed on the formed main table surface to generate an etching mask layer, and a honeycomb channel structure (9) is obtained by etching; 4) depositing and etching a gate field plate dielectric (5) on the honeycomb channel structure (9) and the low-doped channel layer (4); 5) depositing and etching a gate dielectric (6) and a gate metal electrode (7) layer on the gate field plate dielectric (5) to form a gate control structure; 6) growing a gate-source isolation dielectric (8) and an isolation passivation layer (11) on the formed gate control structure, and exposing the top of the honeycomb channel structure (9) and the highly doped channel layer (10) by etching; 7) A mask for a source contact electrode (12) and a drain contact electrode (3) is defined above the isolation passivation layer (11) and the low-resistance substrate (2), a low-work-function metal is deposited by evaporation or sputtering, and the source contact electrode (12) and the drain contact electrode (3) are formed by a lift-off annealing process, thereby obtaining a high-breakdown honeycomb quasi-vertical enhancement-mode GaN transistor.

10. The preparation method according to claim 9, characterized in that: In step 3), the etching method includes dry etching and wet etching.

Images