Semiconductor device and preparation method thereof, chip and electronic equipment

Abstract

The invention provides a semiconductor device and a preparation method thereof, a chip and electronic equipment, relates to the technical field of semiconductors, and aims to improve the stability and reliability of the semiconductor device, the semiconductor device comprises a substrate, a barrier layer, a protection layer and a cap layer, the barrier layer is arranged on one side of the substrate, the protection layer is arranged on one side, away from the substrate, of the barrier layer, and the cap layer is arranged on the substrate. The cap layer is arranged on the side, away from the substrate, of the protection layer, the protection layer and the cap layer are made of different materials, and the concentration of the P-type impurities in the cap layer is larger than that of the P-type impurities in the protection layer. The semiconductor device is applied to a chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a manufacturing method thereof, a chip, and an electronic device. Background Art

[0002] Gallium nitride (GaN) semiconductor materials are called third-generation semiconductor materials. Compared with first-generation semiconductor materials represented by silicon, they have higher bandgap width, critical breakdown field strength, and electron saturation drift velocity. They have significant advantages in high frequency, high voltage resistance, high power, and low on-resistance, and can be used as core devices in various power conversion systems.

[0003] High-electron-mobility transistors (HEMTs) based on gallium nitride (GaN) are widely used in power amplifier devices in electronic devices. For example, in wireless communication base stations, radar systems, high-speed data transmission equipment, and motor drive systems of electric vehicles, high-electron-mobility transistors based on GaN play a vital role. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, a chip, and an electronic device, aiming to improve the stability and reliability of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor device is provided. The semiconductor device includes a substrate, a barrier layer, a protective layer and a cap layer. The barrier layer is disposed on one side of the substrate. The protective layer is disposed on a side of the barrier layer away from the substrate. The cap layer is disposed on a side of the protective layer away from the substrate. The material of the protective layer is different from the material of the cap layer. The concentration of P-type impurities in the cap layer is greater than the concentration of P-type impurities in the protective layer.

[0007] The semiconductor device provided by the above-mentioned embodiments of the present disclosure includes a protective layer, and the protective layer is arranged between the barrier layer and the cap layer, and the concentration of P-type impurities in the cap layer is greater than the concentration of P-type impurities in the protective layer. On the one hand, since the protective layer is located between the cap layer and the barrier layer, in the process of forming the cap layer in the semiconductor device, when the P-type impurities in the cap layer diffuse, the P-type impurities in the cap layer will first diffuse into the protective layer, which can avoid or alleviate the diffusion of P-type impurities in the cap layer into the barrier layer, which can reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer and interfering with the polarization effect of the barrier layer, which is beneficial to improving the polarization effect of the barrier layer, and can also reduce the probability of changes in the characteristics of the connection interface between the protective layer and the barrier layer (for example, the density of trap states at the connection interface between the protective layer and the barrier layer increases, etc.), and affecting the control ability of the gate in the semiconductor device, which is beneficial to reducing the probability of problems such as threshold voltage drift and dynamic on-resistance degradation in the semiconductor device, and further beneficial to improving the stability and reliability of the semiconductor device.

[0008] On the other hand, since the concentration of P-type impurities in the capping layer is greater than that in the protective layer, that is, the doping concentration of the protective layer is relatively small, the P-type impurities in the protective layer may not diffuse into the barrier layer or may diffuse in small amounts. This can further reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer and interfering with the polarization effect of the barrier layer, which is beneficial to further improve the polarization effect of the barrier layer. It can also further reduce the probability of changes in the characteristics of the connection interface between the protective layer and the barrier layer (for example, an increase in the density of trap states at the connection interface between the protective layer and the barrier layer, etc.), and affect the control ability of the gate in the semiconductor device, which is beneficial to further reduce the probability of problems such as threshold voltage drift and dynamic on-resistance degradation in semiconductor devices, and thus help to further improve the stability and reliability of semiconductor devices.

[0009] On the other hand, the protection layer can protect the barrier layer and avoid damaging the barrier layer during the formation of the cap layer, which is beneficial to improving the stability and reliability of the barrier layer and further to improving the performance of the semiconductor device.

[0010] In some embodiments, the material of the capping layer includes polysilicon and / or metal oxide.

[0011] In some embodiments, the P-type impurities in the capping layer include Group III elements.

[0012] In some embodiments, the material of the protective layer includes a Group III nitride semiconductor.

[0013] In some embodiments, the concentration of the P-type impurities in the protective layer is less than or equal to 1×10 17 cm-3 .

[0014] In some embodiments, the semiconductor device further includes a source and a drain. The source and the drain are respectively located on opposite sides of the protective layer along a first direction and are in contact with two sides of the barrier layer, respectively. The first direction is parallel to the substrate. The size of the protective layer along the first direction is greater than or equal to the size of the cap layer along the first direction.

[0015] In some embodiments, the dimension of the protection layer along the first direction is greater than the dimension of the cap layer along the first direction. A surface of the protection layer close to the source electrode contacts the source electrode, and / or a surface of the protection layer close to the drain electrode contacts the drain electrode.

[0016] In some embodiments, a dimension of the protection layer along the second direction is the same as a dimension of the capping layer along the second direction, the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

[0017] In some embodiments, the semiconductor device further includes an insertion layer, wherein the insertion layer is located between the protection layer and the capping layer.

[0018] In some embodiments, a dimension of the insertion layer along the first direction is greater than or equal to a dimension of the capping layer along the first direction.

[0019] In some embodiments, the material of the insertion layer is different from the material of the capping layer.

[0020] In some embodiments, the material of the insertion layer includes at least one of aluminum nitride, aluminum gallium nitride, and metal oxide.

[0021] In another aspect, a method for preparing a semiconductor device is provided. The method for preparing a semiconductor device comprises the following steps:

[0022] A barrier layer is formed on one side of the substrate.

[0023] A protection layer is formed on a side of the barrier layer away from the substrate.

[0024] A cap layer is formed on a side of the protective layer away from the substrate, wherein the concentration of the P-type impurities in the cap layer is greater than the concentration of the P-type impurities in the protective layer.

[0025] In some embodiments, forming a protective layer on a side of the barrier layer away from the substrate comprises the following steps:

[0026] An initial protection layer is formed on a side of the barrier layer away from the substrate.

[0027] Part of the initial protective layer is removed to form a protective layer.

[0028] In some embodiments, the temperature when forming the capping layer on the side of the protection layer away from the substrate is 500° C.-600° C.

[0029] In some embodiments, the material of the capping layer includes polysilicon and / or metal oxide.

[0030] In another aspect, a chip is provided, wherein the chip includes the semiconductor device as described in any one of the above embodiments.

[0031] In another aspect, an electronic device is provided, wherein the electronic device comprises a circuit board and the chip as described above, wherein the chip is electrically connected to the circuit board.

[0032] It can be understood that the beneficial effects that can be achieved by the semiconductor device manufacturing method, chip and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0034] Figure 1 is a schematic structural diagram of an electronic device according to some embodiments;

[0035] Figure 2 is a cross-sectional schematic diagram of a chip according to some embodiments;

[0036] Figure 3 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 1 ;

[0037] Figure 4 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 2 ;

[0038] Figure 5 is a schematic cross-sectional view of a cap layer and a protection layer in a semiconductor device according to some embodiments;

[0039] Figure 6 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 3 ;

[0040] Figure 7 FIG. 1 is a cross-sectional view of a semiconductor device according to some embodiments. Figure 4 ;

[0041] Figure 8 is a flow chart of a method for preparing a semiconductor device according to some embodiments;

[0042] Fig. 9 for Figure 8 A schematic structural diagram of a semiconductor device corresponding to step S1 in the flowchart of the method for preparing a semiconductor device in FIG. 1 ;

[0043] Fig.10 for Figure 8 Schematic diagram of the structure of the semiconductor device corresponding to step S2 and step S3 in the flowchart of the method for preparing the semiconductor device Figure 1 ;

[0044] Fig.11 for Figure 8 Schematic diagram of the structure of the semiconductor device corresponding to step S2 and step S3 in the flowchart of the method for preparing the semiconductor device Figure 2 . DETAILED DESCRIPTION

[0045] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0046] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0047] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0048] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0049] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0050] For the convenience of the following description, an XYZ coordinate system is established. The third direction Z is the thickness direction of the substrate, the XY plane is perpendicular to the third direction Z, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other.

[0051] like Figure 1 As shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include communication equipment (e.g., satellite communication equipment, wireless television receiver, etc.), radar equipment (e.g., millimeter wave radar, weather radar, etc.), radio navigation equipment (e.g., GPS receiver, etc.), etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic device 1000.

[0052] In some embodiments, please refer to Figure 1 , the electronic device 1000 includes a chip 100 and a circuit board 200. The chip 100 and the circuit board 200 are electrically connected.

[0053] By way of example, the circuit board 200 in the electronic device 1000 may include a printed circuit board (PCB) or the like.

[0054] For example, the circuit board 200 in the electronic device 1000 may include a plurality of conductive layers. The plurality of conductive layers in the circuit board 200 may be separated from each other by a dielectric layer.

[0055] The chip 100 is described in detail below.

[0056] In some embodiments, Figure 2 As shown, Figure 2 FIG. 1 is a schematic cross-sectional view of a chip 100 according to some embodiments. The chip 100 includes a semiconductor device 10 .

[0057] Exemplarily, the chip 100 may include a processor chip. For example, the processor chip may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0058] The semiconductor device 10 described above will be described in detail below.

[0059] In some embodiments, please refer to Figure 2 , a semiconductor device 10 may include a substrate 1 .

[0060] Exemplarily, the material of the substrate 1 in the semiconductor device 10 may include one of silicon (Si), silicon carbide (SiC), sapphire, and the like.

[0061] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a buffer layer 2. The buffer layer 2 may be disposed on one side of the substrate 1.

[0062] By setting a buffer layer 2 in the semiconductor device 10, and the buffer layer 2 is set on one side of the substrate 1, the lattice mismatch and the difference in thermal expansion coefficient between other film layer structures set on the side of the buffer layer 2 in the semiconductor device 10 away from the substrate 1 and the substrate 1 can be reduced, thereby reducing the stress between the film layers, reducing dislocations, and helping to improve the growth quality of the film layers.

[0063] For example, the material of the buffer layer 2 in the semiconductor device 10 may include a plurality of nitride Al x In y Ga (1-x-y) One or more (greater than or equal to two) of N, (0≤x, y≤1).

[0064] For example, the material of the buffer layer 2 may include aluminum gallium nitride (AlGaN).

[0065] For example, the buffer layer 2 in the semiconductor device 10 can be formed by a process such as a metal-organic chemical vapor deposition (MOCVD) process, a molecular beam epitaxy (MBE) process or a physical vapor deposition (PVD) process.

[0066] Exemplarily, the buffer layer 2 in the semiconductor device 10 may be a single-layer structure, that is, along the third direction Z (ie, the thickness direction of the substrate 1 ), the buffer layer 2 may include a film layer structure.

[0067] Alternatively, the buffer layer 2 in the semiconductor device 10 may be a multi-layer (greater than or equal to two layers) structure. That is, along the third direction Z, the buffer layer 2 may include a multi-layer film structure.

[0068] In some embodiments, please refer to Figure 2, the semiconductor device 10 may further include a channel layer 3. The channel layer 3 may be disposed on one side of the substrate 1.

[0069] Exemplarily, please continue to refer to Figure 2 , in the case where the semiconductor device 10 includes a buffer layer 2, the channel layer 3 in the semiconductor device 10 may be disposed on the side of the buffer layer 2 away from the substrate 1.

[0070] Exemplarily, the material of the channel layer 3 in the semiconductor device 10 may include gallium nitride (GaN).

[0071] Exemplarily, the channel layer 3 in the semiconductor device 10 may be formed by processes such as metalorganic chemical vapor deposition process, molecular beam epitaxy process, or physical vapor deposition process.

[0072] In some embodiments, please continue to refer to Figure 2 , the semiconductor device 10 may further include a barrier layer 4. The barrier layer 4 is disposed on one side of the substrate 1 within the semiconductor device 10.

[0073] Exemplarily, the material of the barrier layer 4 in the semiconductor device 10 may include nitrides Al with various different components x In y Ga (1-x-y) N, one or more (greater than or equal to two) of (0 < x ≤ 1, 0 ≤ y ≤ 1).

[0074] For example, the material of the barrier layer 4 may include aluminum gallium nitride (AlGaN).

[0075] Exemplarily, the barrier layer 4 in the semiconductor device 10 may be formed by processes such as metalorganic chemical vapor deposition process, molecular beam epitaxy process, or physical vapor deposition process.

[0076] Exemplarily, the barrier layer 4 in the semiconductor device 10 may be a single-layer structure. That is, along the third direction Z, the barrier layer 4 includes a single film layer structure.

[0077] Exemplarily, please continue to refer to Figure 2 , the barrier layer 4 in the semiconductor device 10 may be disposed on the side of the channel layer 3 away from the substrate 1. That is, the channel layer 3 may be disposed between the barrier layer 4 and the substrate 1.

[0078] When the barrier layer 4 in the semiconductor device 10 is arranged on the side of the channel layer 3 away from the substrate 1, and the band gap width (Band gap) of the material of the barrier layer 4 (for example, aluminum gallium nitride (AlGaN)) is different from the band gap width (Band gap) of the material of the channel layer 3 (for example, gallium nitride (GaN)), there will be a spontaneous polarization effect and a piezoelectric polarization effect between the barrier layer 4 and the channel layer 3, and the polarization electric field will easily cause the band structure of the channel layer 3 to bend, thereby forming a potential well in the channel layer 3. In order to balance the charge distribution at the connection interface between the barrier layer 4 and the channel layer 3, the electrons in the barrier layer 4, the electrons in the channel layer 3, and the electrons in the substrate 1 will all transfer to the potential well in the channel layer 3. The potential well in the channel layer 3 can restrict the electrons so that the electrons can only move freely in the direction parallel to the connection interface between the barrier layer 4 and the channel layer 3, thereby inducing the formation of a two-dimensional electron gas (Two-dimensional electron gas, 2DEG) near the connection interface between the barrier layer 4 and the channel layer 3, which is beneficial to improving the electron mobility and enhancing the performance of the semiconductor device 10.

[0079] The band gap refers to the fact that the energy of electrons in solids cannot take continuous values, but forms some discontinuous energy bands, where the energy difference between the conduction band and the valence band is the band gap. Specifically, for bound electrons to become free electrons or holes, they must obtain enough energy to jump from the valence band to the conduction band, and the minimum value of this energy is the band gap.

[0080] For example, please refer to Figure 2 When a two-dimensional electron gas is formed in the semiconductor device 10 , the semiconductor device 10 can be used to form a high electron mobility transistor (HEMT).

[0081] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a gate G. The gate G may be disposed on a side of the barrier layer 4 in the semiconductor device 10 away from the substrate 1 .

[0082] The gate G in the semiconductor device 10 is a key electrode for controlling the conductivity of the semiconductor device 10 . The gate G does not directly participate in the conduction of current, but controls the carrier concentration in the channel layer 3 in the semiconductor device 10 through the electric field effect, thereby controlling the current in the semiconductor device 10 .

[0083] By way of example, the material of the gate G in the semiconductor device 10 may include one or more (or more than two) of conductive materials such as nickel (Ni), gold (Au), titanium (Ti), and titanium nitride (TiN).

[0084] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a source S and a drain D. The source S and the drain D are located at opposite sides of the gate G along a first direction X and contact two sides of the barrier layer 4 respectively. The first direction X is parallel to the substrate 1 in the semiconductor device 10 .

[0085] For example, please refer to Figure 2 When a two-dimensional electron gas is formed in the semiconductor device 10, the source S and the drain D in the semiconductor device 10 can form an ohmic contact with the two-dimensional electron gas, which can reduce the contact resistance between the source S in the semiconductor device 10 and the two-dimensional electron gas, and the contact resistance between the drain D in the semiconductor device 10 and the two-dimensional electron gas. A low-impedance current channel can be formed between the source S, the drain D and the two-dimensional electron gas in the semiconductor device 10, so that the current can flow smoothly, which is beneficial to improving the performance of the semiconductor device 10.

[0086] In some embodiments, please refer to Figure 2 The semiconductor device 10 may further include a cap layer 5. The cap layer 5 may be disposed between the barrier layer 4 and the gate G in the semiconductor device 10. The cap layer 5 includes a P-type material.

[0087] By making the semiconductor device 10 include a cap layer 5, the cap layer 5 is arranged between the barrier layer 4 and the gate G in the semiconductor device 10, and the cap layer 5 includes a P-type material, it is possible to have an energy band difference (for example, a conduction band difference) between the cap layer 5 and the barrier layer 4, and the energy band difference between the cap layer 5 and the barrier layer 4 can be used to regulate the two-dimensional electron gas near the connection interface between the barrier layer 4 and the channel layer 3, which is beneficial to depleting the two-dimensional electron gas below the cap layer 5, thereby enabling the semiconductor device 10 to achieve an enhanced operating mode.

[0088] By way of example, the material of the cap layer 5 in the semiconductor device 10 may include polysilicon (Poly Si) and / or metal oxide.

[0089] For example, the material of the cap layer 5 may include polysilicon (Poly Si).

[0090] For another example, the material of the capping layer 5 may include metal oxides. In the case where the material of the capping layer 5 includes metal oxides, the material of the capping layer 5 may specifically include one or more of nickel oxide (NiO), stannous oxide (SnO), tungsten trioxide (WO3), vanadium pentoxide (V2O5), manganese trioxide (MnO3), manganese monoxide (MnO), cuprous oxide (Cu2O) and chromium trioxide (Cr2O3).

[0091] For another example, the material of the cap layer 5 may include polysilicon (Poly Si) and metal oxide.

[0092] Exemplarily, the material of the cap layer 5 in the semiconductor device 10 may further include P-type impurities, so that the cap layer 5 can provide hole carriers, thereby adjusting the conductivity of the cap layer 5 .

[0093] In the case where the material of the cap layer 5 in the semiconductor device 10 includes P-type impurities, by making the material of the cap layer 5 in the semiconductor device 10 also include polysilicon (Poly Si) and / or metal oxide, that is, the material of the cap layer 5 includes P-type doped polysilicon (Poly Si) and / or metal oxide, the growth temperatures of polysilicon (Poly Si) and metal oxide are both low, and in the process of forming the cap layer 5, the diffusion of P-type impurities in the cap layer 5 to the barrier layer 4 can be effectively suppressed, which can reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer 4 and interfering with the polarization effect of the barrier layer 4, which is beneficial to improving the polarization effect of the barrier layer 4, and can also reduce the probability of changes in the characteristics of the connection interface between the cap layer 5 and the barrier layer 4 (for example, the increase in the trap state density of the connection interface between the cap layer 5 and the barrier layer 4, etc.), and affecting the control ability of the gate G in the semiconductor device 10, which is beneficial to reducing the probability of problems such as threshold voltage drift and dynamic on-resistance degradation in the semiconductor device 10, and further beneficial to improving the stability and reliability of the semiconductor device 10.

[0094] For example, the P-type impurities in the cap layer 5 may include group III elements. Specifically, the P-type impurities in the cap layer 5 may include one or more of boron (B) and aluminum (Al).

[0095] By making the P-type impurities in the cap layer 5 include Group III elements (for example, boron (B), aluminum (Al), etc.), the Group III elements will not produce complexes in the cap layer 5, which is beneficial to improving the doping effect of the P-type impurities in the cap layer 5.

[0096] In the case where the material of the capping layer 5 includes polycrystalline silicon (Poly Si), by making the P-type impurities in the capping layer 5 include group III elements (for example, boron (B), aluminum (Al), etc.), the ionization energy of group III elements in silicon is very small, about 0.045eV-0.065eV, so that group III elements are easily ionized in polycrystalline silicon (Poly Si), which is beneficial to improving the doping effect of group III elements in polycrystalline silicon (Poly Si), and further beneficial to further improving the doping effect of P-type impurities in the capping layer 5.

[0097] When the material of the cap layer 5 includes one or more metal oxides such as nickel oxide (NiO), stannous oxide (SnO), tungsten trioxide (WO3), vanadium pentoxide (V2O5), manganese trioxide (MnO3), manganese monoxide (MnO), cuprous oxide (Cu2O) and chromium trioxide (Cr2O3), the above materials, as intrinsic P-type semiconductor materials, can exhibit p-type conductivity without being doped with P-type impurities or with a small amount of P-type impurities, which can avoid or alleviate the diffusion of P-type impurities in the cap layer 5 to the barrier layer 4, and can further reduce the diffusion of P-type impurities to the barrier layer 4. 4 and the probability of interfering with the polarization effect of the barrier layer 4 is beneficial to further improve the polarization effect of the barrier layer 4, and can also further reduce the probability of changes in the characteristics of the connection interface between the cap layer 5 and the barrier layer 4 (for example, the increase in the density of trap states at the connection interface between the cap layer 5 and the barrier layer 4, etc.), and affecting the control ability of the gate G in the semiconductor device 10, which is beneficial to further reduce the probability of problems such as threshold voltage drift and dynamic on-resistance degradation in the semiconductor device 10, and further help to further improve the stability and reliability of the semiconductor device 10.

[0098] In some embodiments, Figure 3 As shown, Figure 3 is a cross-sectional schematic diagram of a semiconductor device 10 according to some embodiments. The semiconductor device 10 may further include a protective layer 6. The protective layer 6 is disposed on a side of the barrier layer 4 away from the substrate 1, and is disposed on a side of the cap layer 5 close to the substrate 1. That is, the cap layer 5 is disposed on a side of the protective layer 6 away from the substrate 1.

[0099] In the case where the material of the cap layer 5 includes P-type impurities, the concentration of the P-type impurities in the cap layer 5 is greater than the concentration of the P-type impurities in the protection layer 6 .

[0100] By making the semiconductor device 10 include a protective layer 6, the protective layer 6 is arranged between the barrier layer 4 and the cap layer 5, and the concentration of the P-type impurities in the cap layer 5 is greater than the concentration of the P-type impurities in the protective layer 6. On the one hand, since the protective layer 6 is located between the cap layer 5 and the barrier layer 4, in the process of forming the cap layer 5 in the semiconductor device 10, when the P-type impurities in the cap layer 5 diffuse, the P-type impurities in the cap layer 5 will first diffuse into the protective layer 6, which can avoid or alleviate the diffusion of the P-type impurities in the cap layer 5 into the barrier layer 4, and can reduce the diffusion of the P-type impurities into the barrier layer 4. 4, and the probability of interfering with the polarization effect of the barrier layer 4 is beneficial to improving the polarization effect of the barrier layer 4, and can also reduce the probability of changes in the characteristics of the connection interface between the protective layer 6 and the barrier layer 4 (for example, the increase in the density of trap states at the connection interface between the protective layer 6 and the barrier layer 4, etc.), and affecting the control ability of the gate G in the semiconductor device 10, which is beneficial to reducing the probability of problems such as threshold voltage drift and dynamic on-resistance degradation in the semiconductor device 10, and further helps to improve the stability and reliability of the semiconductor device 10.

[0101] On the other hand, since the concentration of P-type impurities in the cap layer 5 is greater than the concentration of P-type impurities in the protective layer 6, that is, the doping concentration of the protective layer 6 is relatively small, the P-type impurities in the protective layer 6 may not diffuse into the barrier layer 4 or may diffuse in small amounts. This can further reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer 4 and interfering with the polarization effect of the barrier layer 4, which is beneficial to further improve the polarization effect of the barrier layer 4. It can also further reduce the probability of changes in the characteristics of the connection interface between the protective layer 6 and the barrier layer 4 (for example, the density of trap states at the connection interface between the protective layer 6 and the barrier layer 4 increases, etc.), and affect the control ability of the gate G in the semiconductor device 10, which is beneficial to further reduce the probability of problems such as threshold voltage drift and dynamic on-resistance degradation in the semiconductor device 10, and thus is beneficial to further improve the stability and reliability of the semiconductor device 10.

[0102] On the other hand, the protection layer 6 can protect the barrier layer 4 to avoid damage to the barrier layer 4 during the formation of the cap layer 5 , which is beneficial to improving the stability and reliability of the barrier layer 4 and further beneficial to improving the performance of the semiconductor device 10 .

[0103] For example, the concentration of the P-type impurities in the cap layer 5 may be 1×10 19 cm -3 -1×10 20 cm -3 .

[0104] For example, the concentration of P-type impurities in the cap layer 5 may be 1×10 19 cm -3, 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 ,7×10 19 cm -3 , 8×10 19 cm -3 ,9×10 19 cm -3 or 1×10 20 cm -3 wait.

[0105] For example, the concentration of the P-type impurities in the protective layer 6 may be less than or equal to 1×10 17 cm -3 .

[0106] For example, the concentration of P-type impurities in the protective layer 6 may be 1×10 17 cm -3 , 8×10 16 cm -3 , 6×10 16 cm -3 , 3×10 16 cm -3 , 8×10 15 cm -3 or 6×10 15 cm -3 wait.

[0107] For example, please refer to Figure 3 In the case where the semiconductor device 10 includes the protection layer 6 , the source S and the drain D may be located at opposite sides of the protection layer 6 along the first direction X, respectively.

[0108] Exemplarily, the material of the protection layer 6 and the material of the cap layer 5 in the semiconductor device 10 are different.

[0109] Exemplarily, the material of the protection layer 6 in the semiconductor device 10 may include a Group III nitride semiconductor.

[0110] For example, the material of the protection layer 6 may include one or more of gallium nitride (GaN), aluminum gallium nitride (AlGaN), aluminum indium nitride (InAlN), indium gallium nitride (InGaN), aluminum nitride (AlN), and the like.

[0111] For example, please refer to Figure 3 , and combined with Figure 4 , Figure 4 Dimension h6 of protection layer 6 along first direction X (ie, arrangement direction of source S and drain D in semiconductor device 10 ) may be greater than or equal to dimension h5 of cap layer 5 along first direction X.

[0112] For example, see Figure 3 , a dimension h6 of the protection layer 6 along the first direction X may be equal to a dimension h5 of the capping layer 5 along the first direction X.

[0113] The above “the dimension h6 of the protective layer 6 along the first direction X may be equal to the dimension h5 of the cap layer 5 along the first direction X” means that the difference between the dimension h6 of the protective layer 6 along the first direction X and the dimension h5 of the cap layer 5 along the first direction X is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range may be a process accuracy range when forming the cap layer 5 and the protective layer 6 of the same size along the first direction X.

[0114] When the dimension h6 of the protective layer 6 along the first direction X is equal to the dimension h5 of the cap layer 5 along the first direction X, the threshold range of the difference between the dimension h6 of the protective layer 6 along the first direction X and the dimension h5 of the cap layer 5 along the first direction X may be 0-0.1 μm.

[0115] Please continue reading Figure 3 When the dimension h6 of the protective layer 6 along the first direction X is equal to the dimension h5 of the cap layer 5 along the first direction X, in the orthographic projection onto the substrate 1, along the first direction X, the boundary of the protective layer 6 may coincide with the boundary of the cap layer 5.

[0116] For another example, please continue to see Figure 4 , a dimension h6 of the protection layer 6 along the first direction X may be greater than a dimension h5 of the capping layer 5 along the first direction X.

[0117] When the dimension h6 of the protection layer 6 along the first direction X is greater than the dimension h5 of the cap layer 5 along the first direction X, the surface of the protection layer 6 close to the source electrode S may contact the source electrode S.

[0118] Alternatively, a surface of the protective layer 6 close to the drain electrode D may be in contact with the drain electrode D.

[0119] Alternatively, please continue reading Figure 4 The surface of the protective layer 6 close to the source S can contact the source S, and the surface of the protective layer 6 close to the drain D can contact the drain D.

[0120] For example, Figure 5 As shown, Figure 5Schematic cross-sectional view of the cap layer 5 and the protective layer 6 in the semiconductor device 10 according to some embodiments. The dimension L6 of the protective layer 6 along the second direction Y may be the same as the dimension L5 of the cap layer 5 along the second direction Y. The second direction Y is perpendicular to the first direction X, and the second direction Y is parallel to the substrate 1.

[0121] The above “dimension L6 of the protective layer 6 along the second direction Y may be the same as the dimension L5 of the cap layer 5 along the second direction Y” means that the difference between the dimension L6 of the protective layer 6 along the second direction Y and the dimension L5 of the cap layer 5 along the second direction Y is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range may be a process accuracy range when forming the cap layer 5 and the protective layer 6 with the same dimensions along the second direction Y.

[0122] When the dimension L6 of the protective layer 6 along the second direction Y is the same as the dimension L5 of the cap layer 5 along the second direction Y, the threshold range of the difference between the dimension L6 of the protective layer 6 along the second direction Y and the dimension L5 of the cap layer 5 along the second direction Y can be 0-0.1 μm.

[0123] In some embodiments, Figure 6 and Figure 7 As shown, Figure 6 and Figure 7 1 and 2 are schematic cross-sectional views of a semiconductor device 10 according to some embodiments. The semiconductor device 10 may further include an insertion layer 8. The insertion layer 8 may be located between the protection layer 6 and the cap layer 5.

[0124] By setting an insertion layer 8 between the protective layer 6 and the cap layer 5, on the one hand, in the case where the lattice constant between the protective layer 6 and the cap layer 5 does not match or there is a difference in the thermal expansion coefficient, the insertion layer 8 can alleviate the stress caused by the lattice constant mismatch or the thermal expansion coefficient difference between the protective layer 6 and the cap layer 5, thereby avoiding the stress caused by the lattice constant mismatch or the thermal expansion coefficient difference between the protective layer 6 and the cap layer 5 from affecting the performance of the semiconductor device 10, which is beneficial to improving the performance of the semiconductor device 10.

[0125] On the other hand, the insertion layer 8 in the semiconductor device 10 can improve the interface characteristics between the protection layer 6 and the cap layer 5 , reduce the interface defects between the protection layer 6 and the cap layer 5 , and help to further improve the stability and reliability of the semiconductor device 10 .

[0126] For example, please refer to Figure 6 and Figure 7 , a dimension h8 of the insertion layer 8 along the first direction X may be the same as a dimension h6 of the protection layer 6 along the first direction X.

[0127] For example, please refer to Figure 6 and Figure 7 , a dimension h8 of the insertion layer 8 along the first direction X may be greater than or equal to a dimension h5 of the cap layer 5 along the first direction X.

[0128] For example, see Figure 6 , a dimension h8 of the insertion layer 8 along the first direction X may be equal to a dimension h5 of the capping layer 5 along the first direction X.

[0129] The above “the dimension h8 of the insertion layer 8 along the first direction X may be equal to the dimension h5 of the cap layer 5 along the first direction X” means that the difference between the dimension h8 of the insertion layer 8 along the first direction X and the dimension h5 of the cap layer 5 along the first direction X is within a preset threshold range. The threshold range is a relatively small numerical range, for example, the threshold range may be a process accuracy range when forming the cap layer 5 and the insertion layer 8 of the same size along the first direction X.

[0130] When the dimension h8 of the insertion layer 8 along the first direction X is equal to the dimension h5 of the cap layer 5 along the first direction X, the threshold range of the difference between the dimension h8 of the insertion layer 8 along the first direction X and the dimension h5 of the cap layer 5 along the first direction X may be 0-0.1 μm.

[0131] For another example, please continue to see Figure 7 , a dimension h8 of the insertion layer 8 along the first direction X may be greater than a dimension h5 of the capping layer 5 along the first direction.

[0132] Exemplarily, the material of the insertion layer 8 is different from the material of the cap layer 5 .

[0133] For example, the material of the insertion layer 8 may include at least one of aluminum nitride (AlN), aluminum gallium nitride (AlGaN), metal oxide, and the like.

[0134] The above-mentioned metal oxide may include aluminum oxide (Al2O3) and the like.

[0135] Please continue reading Figure 7When the dimension h8 of the insertion layer 8 along the first direction X is greater than the dimension h5 of the cap layer 5 along the first direction, by making the material of the insertion layer 8 different from the material of the cap layer 5, when the cap layer 5 in the semiconductor device 10 is formed by the etching process, the etching rate of the material of the insertion layer 8 and the etching rate of the material of the cap layer 5 are different. When the cap layer 5 is formed by the etching process, the material of the insertion layer 8 and the material of the cap layer 5 can be selectively etched, and the etching process can be stopped at the insertion layer 8, so that the insertion layer 8 can protect the protective layer 6 arranged on the side of the insertion layer 8 away from the cap layer 5, thereby avoiding damage to the protective layer 6 caused by the etching process, which is beneficial to improving the performance of the finally formed semiconductor device 10 and enhancing the reliability of the semiconductor device 10.

[0136] In some embodiments, please refer to Figure 3 , Figure 4 , Figure 6 and Figure 7 The semiconductor device 10 may further include a passivation layer 7 . The passivation layer 7 may cover the gate G, the source S, and the drain D in the semiconductor device 10 .

[0137] By setting a passivation layer 7 in the semiconductor device 10, and the passivation layer 7 covers the gate G, source S and drain D in the semiconductor device 10, on the one hand, the passivation layer 7 can block harmful substances in the external environment (for example, oxygen, water, etc.), and avoid direct contact between harmful substances in the external environment and the source S, drain D, and gate G in the semiconductor device 10, thereby preventing the source S, drain D and gate G in the semiconductor device 10 from being damaged, which is beneficial to improving the stability of the semiconductor device 10 and extending the service life of the semiconductor device 10.

[0138] On the other hand, the passivation layer 7 has a certain mechanical strength, which can protect the source S, drain D and gate G in the semiconductor device 10 to a certain extent, and prevent the source S, drain D and gate G in the semiconductor device 10 from being mechanically damaged, which is beneficial to further improve the stability of the semiconductor device 10 and further extend the service life of the semiconductor device 10.

[0139] Exemplarily, the material of the passivation layer 7 in the semiconductor device 10 may include one or more of silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), aluminum nitride (AlN), and aluminum oxide (Al 2 O 3 ).

[0140] Exemplarily, the passivation layer 7 in the semiconductor device 10 may be a single-layer structure, that is, along the third direction (ie, the thickness direction of the substrate 1 ) Z, the passivation layer 7 includes a film layer structure.

[0141] Alternatively, the passivation layer 7 in the semiconductor device 10 may be a multi-layer structure, that is, along the third direction Z, the passivation layer 7 includes a multi-layer film structure.

[0142] For example, the passivation layer 7 in the semiconductor device 10 may be a two-layer structure. Along the third direction Z, the passivation layer 7 may include a silicon nitride (Si3N4) layer and an aluminum nitride (AlN) layer.

[0143] Exemplarily, the passivation layer 7 in the semiconductor device 10 may be formed by at least one of a chemical vapor deposition (CVD) process and a physical vapor deposition (PVD) process.

[0144] The method for manufacturing the semiconductor device 10 is described in detail below.

[0145] In some embodiments, Figure 8 As shown, Figure 8 1 and 2 are flowcharts of methods for manufacturing a semiconductor device 10 according to some embodiments. It should be noted that: Figure 8 The method for preparing the semiconductor device 10 shown in FIG. 1 is not exclusive and may also be Figure 8 Other steps are performed before, after or between any steps in the method for manufacturing the semiconductor device 10. The method for manufacturing the semiconductor device 10 includes steps S1 to S3.

[0146] S1: Fig. 9 As shown, Fig. 9 for Figure 8 A schematic structural diagram of the semiconductor device 10 corresponding to step S1 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0147] S2: Fig.10 As shown, Fig.10 for Figure 8 A schematic structural diagram of the semiconductor device 10 corresponding to step S2 and step S3 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0148] S3: Please continue reading Fig.10 A cap layer 5 is formed on a side of the protective layer 6 away from the substrate 1 . The concentration of the P-type impurities in the cap layer 5 is greater than the concentration of the P-type impurities in the protective layer 6 .

[0149] By forming a protective layer 6 in the semiconductor device 10, the protective layer 6 is formed between the barrier layer 4 and the cap layer 5, and the concentration of the P-type impurities in the cap layer 5 is greater than the concentration of the P-type impurities in the protective layer 6. On the one hand, since the protective layer 6 is located between the cap layer 5 and the barrier layer 4, in the process of forming the cap layer 5 in the semiconductor device 10, when the P-type impurities in the cap layer 5 diffuse, the P-type impurities in the cap layer 5 will diffuse into the protective layer 6 first, which can avoid or alleviate the diffusion of the P-type impurities in the cap layer 5 into the barrier layer 4, and can reduce the diffusion of the P-type impurities into the barrier layer 4. 4, and the probability of interfering with the polarization effect of the barrier layer 4 is beneficial to improving the polarization effect of the barrier layer 4, and can also reduce the probability of changes in the characteristics of the connection interface between the protective layer 6 and the barrier layer 4 (for example, the increase in the density of trap states at the connection interface between the protective layer 6 and the barrier layer 4, etc.), and affecting the control ability of the gate G in the semiconductor device 10, which is beneficial to reducing the probability of problems such as threshold voltage drift and dynamic on-resistance degradation in the semiconductor device 10, and further helps to improve the stability and reliability of the semiconductor device 10.

[0150] On the other hand, since the concentration of P-type impurities in the cap layer 5 is greater than the concentration of P-type impurities in the protective layer 6, that is, the doping concentration of the protective layer 6 is relatively small, the P-type impurities in the protective layer 6 may not diffuse into the barrier layer 4 or may diffuse in small amounts. This can further reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer 4 and interfering with the polarization effect of the barrier layer 4, which is beneficial to further improve the polarization effect of the barrier layer 4. It can also further reduce the probability of changes in the characteristics of the connection interface between the protective layer 6 and the barrier layer 4 (for example, the density of trap states at the connection interface between the protective layer 6 and the barrier layer 4 increases, etc.), and affect the control ability of the gate G in the semiconductor device 10, which is beneficial to further reduce the probability of problems such as threshold voltage drift and dynamic on-resistance degradation in the semiconductor device 10, and thus is beneficial to further improve the stability and reliability of the semiconductor device 10.

[0151] For example, please refer to Figure 8 , step S2 (ie, forming a protective layer 6 on a side of the barrier layer 4 away from the substrate 1 ) in the method for preparing the semiconductor device 10 may include step S21 and step S22 .

[0152] S21: Fig.11 As shown, Fig.11 for Figure 8 The schematic diagram of the structure of the semiconductor device 10 corresponding to step S2 and step S3 in the flowchart of the method for preparing the semiconductor device 10 in FIG.

[0153] For example, the material of the initial protection layer 6 a may not include P-type impurities.

[0154] S22: Please continue reading Fig.11 , remove part of the initial protective layer 6a to form a protective layer 6.

[0155] For example, a portion of the initial protective layer 6 a may be removed by using a mixed gas such as Cl 2 / N 2 / O 2 to form the protective layer 6 .

[0156] For example, please refer to Figure 8 , step S3 (ie, forming the cap layer 5 on the side of the protection layer 6 away from the substrate 1 ) in the method for preparing the semiconductor device 10 may include step S31 and step S32 .

[0157] S31: Please continue reading Fig.11 , an initial capping layer 5a is formed on a side of the initial protection layer 6a away from the substrate 1. The material of the initial capping layer 5a includes P-type impurities.

[0158] S32: Please continue reading Fig.11 , remove part of the initial capping layer 5a to form the capping layer 5.

[0159] For example, the cap layer 5 may be formed by removing part of the initial cap layer 5 a through an etching process using gases such as SF 6 and CF 4 .

[0160] When the material of the initial protective layer 6a does not include P-type impurities and the material of the initial cap layer 5a includes P-type impurities, during the process of forming the initial cap layer 5a in the semiconductor device 10, the P-type impurities in the initial cap layer 5a easily diffuse into the initial protective layer 6a, so that the material of the protective layer 6 finally formed includes a small amount of P-type impurities.

[0161] Exemplarily, the temperature when forming the cap layer 5 on the side of the protection layer 6 away from the substrate 1 is 500° C.-600° C.

[0162] For example, the temperature when the cap layer 5 is formed on the side of the protective layer 6 away from the substrate 1 is 500° C., 530° C., 550° C., 560° C., 580° C. or 600° C., etc.

[0163] In the process of forming the cap layer 5, by making the temperature when forming the cap layer 5 500℃-600℃, that is, the temperature when forming the cap layer 5 is low, the diffusion of P-type impurities in the cap layer 5 to the barrier layer 4 can be effectively suppressed, which can further reduce the probability of P-type impurities introducing additional charges and electric fields into the barrier layer 4 and interfering with the polarization effect of the barrier layer 4, which is beneficial to further improve the polarization effect of the barrier layer 4, and can also further reduce the probability of changes in the characteristics of the connection interface between the cap layer 5 and the barrier layer 4 (for example, the increase in the density of trap states at the connection interface between the cap layer 5 and the barrier layer 4, etc.), and affecting the control ability of the gate G in the semiconductor device 10, which is beneficial to further reduce the probability of problems such as threshold voltage drift and dynamic on-resistance degradation in the semiconductor device 10, and thus is beneficial to further improve the stability and reliability of the semiconductor device 10.

[0164] Exemplarily, the material of the capping layer 5 may include polysilicon and / or metal oxide.

[0165] For example, the cap layer 5 may be formed by depositing polysilicon material through a low pressure chemical vapor deposition (LPCVD) process.

[0166] For another example, the cap layer 5 may be formed by depositing a metal oxide material through a magnetron sputtering process (also known as a high-speed low-temperature sputtering process).

[0167] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A barrier layer, disposed on one side of the substrate; A protective layer, disposed on a side of the barrier layer away from the substrate; A capping layer is arranged on a side of the protective layer away from the substrate; the material of the protective layer is different from that of the capping layer; Wherein, the concentration of the P-type impurities in the capping layer is greater than the concentration of the P-type impurities in the protection layer.

2. The semiconductor device according to claim 1, wherein: The material of the capping layer includes polysilicon and / or metal oxide.

3. The semiconductor device according to claim 2, characterized in that The P-type impurities in the capping layer include group III elements.

4. The semiconductor device according to claim 1, wherein: The material of the protective layer includes a Group III nitride semiconductor.

5. The semiconductor device according to claim 1, wherein: The concentration of P-type impurities in the protective layer is less than or equal to 1×10 17 cm -3 .

6. The semiconductor device according to any one of claims 1 to 5, characterized in that: The semiconductor device further comprises a source electrode and a drain electrode, which are respectively located on opposite sides of the protective layer along a first direction and are respectively in contact with two sides of the barrier layer; the first direction is parallel to the substrate; A dimension of the protection layer along the first direction is greater than or equal to a dimension of the capping layer along the first direction.

7. The semiconductor device according to claim 6, characterized in that The dimension of the protection layer along the first direction is greater than the dimension of the cap layer along the first direction; A surface of one side of the protection layer close to the source electrode is in contact with the source electrode; and / or A surface of the protection layer close to the drain electrode is in contact with the drain electrode.

8. The semiconductor device according to claim 6, characterized in that The dimension of the protection layer along the second direction is the same as the dimension of the cap layer along the second direction; the second direction is perpendicular to the first direction, and the second direction is parallel to the substrate.

9. The semiconductor device according to any one of claims 1 to 5, characterized in that: The semiconductor device further includes an insertion layer located between the protection layer and the capping layer.

10. The semiconductor device according to claim 9, characterized in that A dimension of the insertion layer along the first direction is greater than or equal to a dimension of the capping layer along the first direction.

11. The semiconductor device according to claim 9, characterized in that The material of the insert layer is different from that of the cap layer.

12. The semiconductor device according to claim 11, characterized in that The material of the insertion layer includes at least one of aluminum nitride, aluminum gallium nitride and metal oxide.

13. A method for preparing a semiconductor device, characterized in that: include: forming a barrier layer on one side of the substrate; forming a protective layer on a side of the barrier layer away from the substrate; A cap layer is formed on a side of the protective layer away from the substrate; the concentration of the P-type impurities in the cap layer is greater than the concentration of the P-type impurities in the protective layer.

14. The method for preparing a semiconductor device according to claim 13, characterized in that: The step of forming a protective layer on a side of the barrier layer away from the substrate comprises: forming an initial protection layer on a side of the barrier layer away from the substrate; A portion of the initial protective layer is removed to form a protective layer.

15. The method for preparing a semiconductor device according to claim 13 or 14, characterized in that: The temperature when forming the capping layer on the side of the protection layer away from the substrate is 500° C.-600° C.

16. The method for preparing a semiconductor device according to claim 15, characterized in that: The material of the capping layer includes polysilicon and / or metal oxide.

17. A chip, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 12.

18. An electronic device, characterized in that: include: Circuit boards; The chip as claimed in claim 17, wherein the chip is electrically connected to the circuit board.

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