Semiconductor device and semiconductor memory device

Abstract

The embodiment of the invention provides a semiconductor device and a semiconductor memory device. The semiconductor device with good quality can be manufactured. According to one embodiment, a semiconductor device includes: an oxide semiconductor having a first end and a second end and extending in a first direction from the second end toward the first end; a first electrode in contact with the first end of the oxide semiconductor; a second electrode in contact with the second end of the oxide semiconductor; a gate electrode that surrounds the oxide semiconductor between the first end and the second end of the oxide semiconductor with a first insulating film interposed therebetween; and a second insulating film provided on the first direction side of the gate electrode and surrounding the oxide semiconductor with the first insulating film interposed therebetween. The gate electrode and the second insulating film form a hole portion that accommodates at least a portion of the oxide semiconductor. The inner wall of the hole part is provided with a step surface facing the opposite direction of the first direction.

Description

[0001] References to related applications

[0002] This application claims priority based on Japanese Patent Application No. 2023-156463 ​​(filing date: September 21, 2023). This application incorporates all the contents of the basic application by reference. Technical Field

[0003] The present embodiment relates to a semiconductor device and a semiconductor memory device. Background Art

[0004] Some semiconductor devices use metal oxides containing indium and tin for electrodes.

[0005] In the manufacturing process of semiconductor elements using metal oxides for electrodes, a technology for manufacturing semiconductor devices with good quality is required. Summary of the invention

[0006] The problem to be solved by the present invention is to provide a semiconductor device and a semiconductor storage device capable of manufacturing semiconductor devices with good quality.

[0007] A semiconductor device of an embodiment comprises: an oxide semiconductor having a first end and a second end, extending in a first direction from the second end toward the first end; a first electrode connected to the first end of the oxide semiconductor; a second electrode connected to the second end of the oxide semiconductor; a gate electrode, between the first end and the second end of the oxide semiconductor, surrounding the oxide semiconductor via a first insulating film; and a second insulating film, disposed on the first direction side of the gate electrode, surrounding the oxide semiconductor via the first insulating film; and a hole portion for accommodating at least a portion of the oxide semiconductor is formed by the gate electrode and the second insulating film; and a step surface facing in an opposite direction to the first direction is formed on an inner wall of the hole portion.

[0008] The semiconductor device of the embodiment comprises: a plurality of oxide semiconductors having a first end and a second end, extending in a first direction from the second end toward the first end; a plurality of first electrodes respectively connected to the first ends of the plurality of oxide semiconductors; a plurality of second electrodes respectively connected to the second ends of the plurality of oxide semiconductors; a gate electrode extending along the second direction, and between the first end and the second end of each of the plurality of oxide semiconductors arranged along the second direction, a plurality of first insulating films are respectively interposed to surround the oxide semiconductors; a fourth insulating film is arranged in the opposite direction to the first direction relative to the gate electrode; and a fifth insulating film is arranged between two oxide semiconductors adjacent in the second direction, in the opposite direction to the first direction relative to the fourth insulating film; and the etching rate of the fifth insulating film is greater than the etching rate of the fourth insulating film.

[0009] A semiconductor storage device according to an embodiment includes: the semiconductor device; a first capacitor electrode connected to the first electrode or the second electrode; a second capacitor electrode facing the first capacitor electrode; and a dielectric film provided between the first capacitor electrode and the second capacitor electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a circuit diagram for explaining an example of a circuit configuration of a memory cell array according to the first embodiment.

[0011] Figure 2 It is a schematic cross-sectional view for explaining a structural example of the semiconductor memory device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane.

[0012] Figure 3 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane of the semiconductor device according to the first example of the first embodiment.

[0013] Figure 4 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the YZ plane of the semiconductor device according to the first example of the first embodiment.

[0014] Figure 5 yes Figure 3 and Figure 4 A cross-sectional view taken along the cutting line VV is shown.

[0015] Figure 6 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0016] Figure 7It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0017] Figure 8 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0018] Fig. 9 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0019] Fig.10 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0020] Fig.11 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0021] Fig.12 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0022] Fig.13 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0023] Fig.14 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0024] Fig.15 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0025] Fig.16 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0026] Fig.17 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0027] Fig.18 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0028] Fig.19 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0029] Fig. 20 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0030] Fig.21 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0031] Fig. 22 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0032] Fig.23 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0033] Fig.24 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0034] Fig.25 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0035] Fig.26 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0036] Fig. 27 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0037] Fig.28 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0038] Fig.29 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0039] Fig.30 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0040] Fig.31 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0041] Fig.32 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0042] Fig.33 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0043] Fig.34It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0044] Fig.35 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0045] Fig.36 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0046] Fig.37 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0047] Fig.38 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0048] Fig.39 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0049] Fig.40 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0050] Fig.41 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the first example of the first embodiment.

[0051] Fig.42 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane of the semiconductor device according to the second example of the first embodiment.

[0052] Fig.43 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the YZ plane of the semiconductor device according to the second example of the first embodiment.

[0053] Fig.44 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the second example of the first embodiment.

[0054] Fig.45 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second example of the first embodiment.

[0055] Fig.46 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane of the semiconductor device according to the third example of the first embodiment.

[0056] Fig.47 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the YZ plane of the semiconductor device according to the third example of the first embodiment.

[0057] Fig.48 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the third example of the first embodiment.

[0058] Fig.49 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the third example of the first embodiment.

[0059] Fig.50 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane of the semiconductor device according to the fourth example of the first embodiment.

[0060] Fig.51 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the YZ plane of the semiconductor device according to the fourth example of the first embodiment.

[0061] Fig.52 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the fourth example of the first embodiment.

[0062] Fig.53 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the fourth example of the first embodiment.

[0063] Fig.54 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane of the semiconductor device according to the fifth example of the first embodiment.

[0064] Fig.55 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the YZ plane of the semiconductor device according to the fifth example of the first embodiment.

[0065] Fig.56 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane of the semiconductor device according to the sixth example of the first embodiment.

[0066] Fig.57 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the YZ plane of the semiconductor device according to the sixth example of the first embodiment.

[0067] Fig.58It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane of the semiconductor device according to the seventh example of the first embodiment.

[0068] Fig.59 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the YZ plane of the semiconductor device according to the seventh example of the first embodiment.

[0069] Fig.60 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the seventh example of the first embodiment.

[0070] Fig.61 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the seventh example of the first embodiment.

[0071] Fig.62 It is a cross-sectional view parallel to the ZX plane, showing the manufacturing process of the semiconductor device according to the seventh example of the first embodiment.

[0072] Fig.63 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the seventh example of the first embodiment.

[0073] Fig.64 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane of the semiconductor device according to the eighth example of the first embodiment.

[0074] Fig.65 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the YZ plane of the semiconductor device according to the eighth example of the first embodiment.

[0075] Fig.66 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the ZX plane of the semiconductor device according to the ninth example of the first embodiment.

[0076] Fig.67 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the first embodiment, and shows a cross-sectional view parallel to the YZ plane of the semiconductor device according to the ninth example of the first embodiment.

[0077] Fig.68 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the second embodiment, and shows a cross-sectional view parallel to the ZX plane.

[0078] Fig.69 It is a schematic cross-sectional view for explaining a structural example of the semiconductor device according to the second embodiment, and shows a cross-sectional view parallel to the YZ plane.

[0079] Fig.70 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0080] Fig.71 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0081] Fig.72 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0082] Fig.73 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0083] Fig.74 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0084] Fig.75 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0085] Fig.76 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0086] Fig.77 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0087] Fig.78 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0088] Fig.79 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0089] Fig.80 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0090] Fig.81 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0091] Fig.82 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0092] Fig.83 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0093] Fig.84 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0094] Fig.85 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0095] Fig.86 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0096] Fig.87 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0097] Fig.88 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0098] Fig.89 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0099] Fig.90 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0100] Fig.91 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0101] Fig.92 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0102] Fig.93 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0103] Fig.94 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0104] Fig.95 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0105] Fig.96 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0106] Fig.97 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment.

[0107] Fig.98 It is a cross-sectional view parallel to the ZX plane and shows the manufacturing process of the semiconductor device according to the second embodiment.

[0108] Fig.99 It is a cross-sectional view parallel to the YZ plane, showing the manufacturing process of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION

[0109] Hereinafter, the present embodiment will be described with reference to the drawings. In order to facilitate the description, the same components are denoted by the same reference numerals as much as possible in the drawings, and repeated descriptions are omitted.

[0110] [First embodiment]

[0111] The structure of the semiconductor storage device of the first embodiment is described. In each of the drawings, the X-axis, Y-axis and Z-axis are sometimes shown. The X-axis, Y-axis and Z-axis form a three-dimensional orthogonal coordinate system of a right-hand system. Hereinafter, the arrow direction of the X-axis is sometimes referred to as the X-axis + direction, and the direction opposite to the arrow is referred to as the X-axis - direction, and the same applies to other axes. In addition, the Z-axis + direction and the Z-axis - direction are sometimes referred to as "above" and "below", respectively. In addition, the planes orthogonal to the X-axis, Y-axis or Z-axis are sometimes referred to as YZ planes, ZX planes or XY planes. In addition, the Z-axis direction is sometimes referred to as the "up and down direction". "Above", "below" and "up and down direction" are always terms that indicate relative positional relationships within the drawings, and are not terms that determine directions based on the vertical direction.

[0112] In addition, for easy understanding of the description, the dimensions of components shown in the drawings may be shown differently from the actual dimensions unless otherwise specifically described.

[0113] In this specification, “connection” includes not only physical connection but also electrical connection, and includes not only direct connection but also indirect connection unless otherwise specified.

[0114] In this specification, “formed above” includes not only the case of being formed in contact with the upper side, but also includes the case of being formed above with another object interposed therebetween, except for the cases specifically specified. The same applies to the case of “formed below” and the like.

[0115] The semiconductor memory device 101 according to the first embodiment is an OS-RAM (Oxide Semiconductor-Random Access Memory) and includes a memory cell array.

[0116] like Figure 1As shown, the memory cell array includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0117] exist Figure 1 As an example of a plurality of word lines WL, the word line WL is shown. n , word line WL n+1 and word line WL n+2 (Here, n is a positive integer). In addition, Figure 1 As an example of the bit line BL, the bit line BL is shown. m , bit line BL m+1 and bit line BL m+2 (Here, m is a positive integer.) In addition, the number of the plurality of memory cells MC is not limited to Figure 1 The number shown.

[0118] A plurality of memory cells MC are arranged in a matrix, for example, to form a memory cell array. The memory cell MC includes a field effect transistor (FET: Field Effect Transistor), that is, a memory transistor MTR, and a memory capacitor MCP.

[0119] A series of memory cells MC arranged along the row direction are connected to a word line WL corresponding to the row to which they belong (for example, the nth row). n A series of memory cells MC arranged along the column direction are connected to the bit line BL (eg, bit line BL 1 ) corresponding to the column to which they belong (eg, the m+2th column). m+2 ).

[0120] Specifically, the gate of the memory transistor MTR included in the memory cell MC is connected to the word line WL corresponding to the row to which the memory cell MC belongs, and one of the source and the drain of the memory transistor MTR is connected to the bit line BL corresponding to the column to which the memory cell MC belongs.

[0121] One electrode of the storage capacitor MCP included in the memory cell MC is connected to the other of the source or the drain of the storage transistor MTR included in the memory cell MC. The other electrode of the memory cell MC is connected to a power supply line (not shown) that supplies a specific potential.

[0122] The memory cell MC is configured to store charge in the storage capacitor MCP by a current flowing through the corresponding bit line BL, thereby retaining data, by switching the storage transistor MTR based on the potential of the corresponding word line WL.

[0123] like Figure 2 As shown, the semiconductor memory device 101 includes a semiconductor substrate 10 , a circuit 11 , a capacitor 20 , a semiconductor device 30 , a conductor 33 , and insulating layers 34 , 35 , 45 , and 63 .

[0124] The capacitor 20 includes a conductor 21 , an insulating film 22 (an example of a “dielectric film”), a conductor 23 , a capacitor electrode 24 (an example of a “first capacitor electrode”), and a capacitor electrode 25 (an example of a “second capacitor electrode”).

[0125] The semiconductor device 30 includes a field effect transistor 40 (an example of a “semiconductor element”), an upper electrode 50 (an example of a “first electrode”) disposed above the field effect transistor 40 , and a lower electrode 32 (an example of a “second electrode”) disposed below the field effect transistor 40 .

[0126] The field effect transistor 40 includes an oxide semiconductor layer 70 (an example of an “oxide semiconductor”) corresponding to a channel, a gate insulating film 43 (an example of a “first insulating film”), and a conductive layer 42 (an example of a “gate electrode”).

[0127] The oxide semiconductor layer 70 is formed in the insulating layer 45, and has an upper end 70a (an example of a "first end") and a lower end 70b (an example of a "second end"). The oxide semiconductor layer 70 is a columnar body extending in the Z-axis + direction (an example of a "first direction") from the lower end 70b toward the upper end 70a. The oxide semiconductor layer 70 forms a channel of the field effect transistor 40, and the oxide semiconductor layer 70 has an amorphous structure.

[0128] The conductive layer 42 functions as a gate electrode of the field effect transistor 40, and surrounds the oxide semiconductor layer 70 via a gate insulating film 43 between an upper end 70a and a lower end 70b of the oxide semiconductor layer 70. The conductive layer 42 includes tungsten, for example.

[0129] The gate insulating film 43 includes, for example, a silicon nitride film (Si 3 N 4 ) containing silicon and nitrogen.

[0130] The upper electrode 50 is formed in the Z-axis + direction with respect to the oxide semiconductor layer 70 and is in contact with the upper end 70a of the oxide semiconductor layer 70. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0131] The metal film 50c includes tungsten (W). The metal oxide layer 50a is formed between the metal film 50c and the upper end 70a of the oxide semiconductor layer 70, and includes a metal oxide. The metal oxide includes, for example, indium and tin as metal elements. In the present embodiment, the metal oxide layer 50a is formed of indium-tin-oxide (ITO).

[0132] The barrier metal layer 50b includes titanium and nitrogen, and is formed between the metal oxide layer 50a and the metal film 50c. In the present embodiment, the barrier metal layer 50b is formed of, for example, titanium nitride (TiN).

[0133] The lower electrode 32 is in contact with the lower end 70b of the oxide semiconductor layer 70. The lower electrode 32 is formed of, for example, an ITO layer containing a metal oxide such as indium-tin-oxide (ITO).

[0134] In addition, the lower electrode 32 is not limited to ITO, and may be composed of at least one element selected from indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron.

[0135] The circuit 11 constitutes a peripheral circuit such as a decoder for selecting a predetermined memory cell MC, a sense amplifier connected to a bit line BL, and a register constituted by an SRAM (Static Random Access Memory) among a plurality of memory cells MC of the semiconductor memory device 101, that is, the capacitor 20 and the field effect transistor 40. The circuit 11 may include a CMOS circuit having field effect transistors of a P-channel field effect transistor (Pch-FET) and an N-channel field effect transistor (Nch-FET) formed by a CMOS (Complementary Metal Oxide Semiconductor) process.

[0136] The field effect transistor of the circuit 11 can be formed using a semiconductor substrate 10 such as a single crystal silicon substrate. Pch-FET and Nch-FET are so-called lateral field effect transistors that have a channel region, a source region, and a drain region on the semiconductor substrate 10, and have a channel for allowing carriers to flow in the X-axis direction or the Y-axis direction that is roughly parallel to the surface of the semiconductor substrate 10 in a region close to the surface of the semiconductor substrate 10. In addition, the semiconductor substrate 10 may also have a conductivity type ranging from P-type to N-type. In addition, for convenience, Figure 2 An example of a field effect transistor of the circuit 11 is shown in the figure.

[0137] The capacitor 20 is a storage capacitor MCP included in the memory cell MC (refer to Figure 1 ). Although Figure 2 Although four capacitors 20 are shown in the figure, the number of capacitors 20 is not limited to four.

[0138] In this embodiment, the capacitor 20 is provided above the semiconductor substrate 10. The capacitor electrode 24 in the capacitor 20 is connected to the conductor 21 and the lower electrode 32. The capacitor electrode 25 faces the capacitor electrode 24. The insulating film 22 is provided between the capacitor electrode 24 and the capacitor electrode 25.

[0139] The capacitor 20 is a three-dimensional capacitor such as a pillar capacitor. In addition, as the capacitor of this embodiment, other capacitors having a structure capable of storing electric charge may be adopted.

[0140] The conductor 21 is in contact with the lower end surface of the lower electrode 32 and has a shape extending downward from the end. The capacitor electrode 24 is formed so as to cover the lower electrode 32 and the conductor 21. The insulating film 22 is formed so as to cover the capacitor electrode 24. The capacitor electrode 25 surrounds a portion of the lower side of the insulating film 22 and has a lower end in contact with the upper end surface of the conductor 23.

[0141] The conductor 21 may include amorphous silicon or the like. The insulating film 22 may include hafnium oxide or the like. The conductor 23 and the capacitor electrodes 24 and 25 may include tungsten (W) and titanium nitride (TiN) or the like.

[0142] The conductor 33 includes wiring that electrically connects the circuit 11 to the semiconductor device 30. The conductor 33 may include a via wiring having, for example, Figure 2 As shown, the via wiring 33 extends in the Z-axis direction and connects the word line WL to the circuit 11 provided on the semiconductor substrate 10. The conductor 33 is made of copper, for example.

[0143] The insulating layer 34 is provided between the plurality of capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0144] The insulating layer 35 is provided on the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen.

[0145] The semiconductor device 30 is provided above the capacitor 20. The field effect transistor 40 in the semiconductor device 30 corresponds to the memory transistor MTR of the memory cell MC (refer to Figure 1 ).

[0146] In the semiconductor device 30, the field effect transistor 40 is provided above the lower electrode 32. Specifically, the oxide semiconductor layer 70 of the field effect transistor 40 is located in a direction away from the semiconductor substrate 10 relative to the lower electrode 32, that is, above.

[0147] The upper electrode 50 is located away from the semiconductor substrate 10, that is, above the oxide semiconductor layer 70. With this structure, the field effect transistor 40 is a so-called vertical transistor having a channel extending in the Z-axis direction (vertical direction) substantially perpendicular to the surface of the semiconductor substrate 10.

[0148] In addition, the oxide semiconductor layer 70 is a semiconductor that lacks oxygen and becomes a donor, and contains indium (In), zinc (Zn) and gallium (Ga) as metal elements. In detail, the oxide semiconductor layer 70 is an oxide of indium, gallium and zinc, that is, IGZO (InGaZnO). In addition, the oxide semiconductor layer 70 can also be other types of oxide semiconductors.

[0149] Figure 3 70ZX is a cross section parallel to the ZX plane, and shows a cross-sectional view of the semiconductor device 30 when viewed from the cross section 70ZX included in the oxide semiconductor layer 70 . Figure 4 70YZ is a cross section parallel to the YZ plane, and shows a cross-sectional view of the semiconductor device 30 when viewed from the cross section 70YZ included in the oxide semiconductor layer 70 . Figure 5 yes Figure 3 and Figure 4 A cross-sectional view taken along the cutting line VV is shown.

[0150] Hereinafter, a first example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the first example of the first embodiment) will be described.

[0151] (First embodiment, first example)

[0152] like Figure 3 to Figure 5 As shown, in the first example of the first embodiment, the semiconductor device 30 further includes a liner film 301 (an example of a "third insulating film") and a spacer film 311. The gate insulating film 43 includes insulating films 43a and 43b. The insulating layer 45 includes insulating films 45a, 45b, and 45c.

[0153] The plurality of conductive layers 42 are repeatedly arranged in the + direction of the X axis (an example of the "third direction"). The plurality of oxide semiconductor layers 70 are arranged in two dimensions. That is, a portion of the plurality of oxide semiconductor layers 70 is arranged along the + direction of the Y axis (an example of the "second direction"). In addition, the other portions of the plurality of oxide semiconductor layers 70 are arranged along the + direction of the X axis.

[0154] The conductive layer 42 extends along the + direction of the Y axis, and surrounds the plurality of oxide semiconductor layers 70 disposed along the + direction of the Y axis via the plurality of gate insulating films 43 .

[0155] Specifically, the conductive layer 42 includes a surrounding portion 42 b (an example of a “first portion”) surrounding the oxide semiconductor layer 70 , and a connecting portion 42 c (an example of a “second portion”) connecting the two surrounding portions 42 b .

[0156] When the conductive layer 42 is viewed from above, the width of the connecting portion 42 c in the X-axis direction is narrower than the width of the surrounding portion 42 b in the X-axis direction.

[0157] The spacer film 311 (an example of a “second insulating film”) is provided on the Z-axis + direction side of the conductive layer 42. The spacer film 311 is made of, for example, silicon oxide. The spacer film 311 includes a cylindrical portion 311a and a plate-shaped portion 311b.

[0158] The cylindrical portion 311a is provided above the surrounding portion 42b in the conductive layer 42 and extends substantially parallel to the Z axis. Specifically, the lower end of the cylindrical portion 311a forms an annular surface in contact with the upper surface 42a of the conductive layer 42. The cylindrical portion 311a surrounds the oxide semiconductor layer 70 via the gate insulating film 43. The plate-shaped portion 311b is provided above the connecting portion 42c in the conductive layer 42 and extends substantially parallel to the XY plane.

[0159] The insulating films 45a and 45b are respectively provided above the plate-shaped portion 311b and below the conductive layer 42. The insulating films 45a and 45b are made of, for example, silicon oxide.

[0160] The insulating film 45c divides two conductive layers 42 adjacent to each other in the + direction of the X axis. Specifically, the insulating film 45c is located between two conductive layers 42 adjacent to each other in the + direction of the X axis, and extends substantially parallel to the Y axis.

[0161] The upper end of the insulating film 45c is connected to the lower surface of the insulating film 45a. The lower surface of the insulating film 45c is buried in the insulating film 45b. In this embodiment, the insulating films 45a and 45c are formed integrally.

[0162] The hole portion 401 that receives at least a portion of the oxide semiconductor layer 70 is formed by the surrounding portion 42b of the conductive layer 42 and the cylindrical portion 311a of the spacer film 311. In this embodiment, the hole portion 401 receives a portion of the upper portion of the oxide semiconductor layer 70. Alternatively, the hole portion 401 may receive the entire oxide semiconductor layer 70.

[0163] A step surface 401a facing the Z-axis direction is formed on the inner wall 401b of the hole 401. The step surface 401a is located between the conductive layer 42 and the upper electrode 50. The step surface 401a is annular when viewed from below.

[0164] In this embodiment, in the hole 401, the inner diameter of the lower end of the cylindrical portion 311a is smaller than the inner diameter of the upper portion of the surrounding portion 42b, so the center portion of the lower end surface of the cylindrical portion 311a becomes the step surface 401a. The upper surface 42a of the conductive layer 42 is aligned with the step surface 401a.

[0165] The gate insulating film 43 surrounds a portion of the upper portion of the oxide semiconductor layer 70 over the entire circumference. The gate insulating film 43 is composed of two layers, namely, insulating films 43a and 43b. The insulating film 43a is provided closer to the oxide semiconductor layer 70 than the insulating film 43b. The upper ends of the insulating films 43a and 43b are in contact with the metal oxide layer 50a. The insulating film 43a includes, for example, silicon oxide. The insulating film 43b includes, for example, silicon nitride.

[0166] The liner film 301 is located at least between the conductive layer 42 and the insulating film 45b and the gate insulating film 43. The liner film 301 surrounds a portion of the lower portion of the oxide semiconductor layer 70 from the outer side of the gate insulating film 43 all around. Specifically, the lower end of the liner film 301 is in contact with the lower electrode 32. The upper end of the liner film 301 is in contact with the step surface 401a of the hole portion 401, that is, the lower end surface of the cylindrical portion 311a.

[0167] The liner film 301 includes, for example, at least one element of silicon, aluminum, zirconium, hafnium, lanthanum, titanium, and strontium, and at least one element of oxygen and nitrogen. In the present embodiment, the liner film 301 includes silicon nitride. Alternatively, the liner film 301 may include silicon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, zirconium oxide, hafnium oxide, ruthenium oxide, niobium oxide, yttrium oxide, tantalum oxide, vanadium oxide, magnesium oxide, lanthanum oxide, titanium oxide, or strontium oxide.

[0168] [Method for manufacturing semiconductor device]

[0169] Hereinafter, a method for manufacturing the semiconductor device 30 will be described as an example of the method for manufacturing the semiconductor device according to the first embodiment.

[0170] First, if Figure 6 and Figure 7 As shown in FIG. 1 , an insulating film 45b, a conductive layer 42, and an insulating film 45ba are sequentially provided on the insulating layer 35. The insulating film 45b, the conductive layer 42, and the insulating film 45ba extend substantially parallel to the XY plane. A transistor hole TH extending substantially parallel to the Z axis and penetrating the insulating film 45ba, the conductive layer 42, and the insulating film 45b is formed, and then cleaned. The lower electrode 32 is exposed at the bottom of the transistor hole TH.

[0171] Then, if Figure 8 and Fig. 9 As shown, a liner film 301 having a thickness of 3 nm or more is formed on the semiconductor device 30 by, for example, atomic layer deposition. Thus, the inner wall of the transistor hole TH is covered by the liner film 301, and the lower electrode 32 is not exposed.

[0172] Then, if Fig.10 and Fig.11 As shown, a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30 . Thus, the transistor hole TH is buried by the sacrificial amorphous silicon layer 170 .

[0173] Then, if Fig.12 and Fig.13 As shown, the sacrificial amorphous silicon layer 170 is etched back to remove a portion of the upper portion of the sacrificial amorphous silicon layer 170, exposing the upper surface of the insulating film 45ba. At this time, the upper end of the sacrificial amorphous silicon layer 170 is located above the conductive layer 42, for example, inside the transistor hole TH.

[0174] Then, if Fig.14 and Fig.15 As shown in FIG. 1 , the insulating film 45ba is removed by etching. Then, the liner film 301 exposed above the conductive layer 42 is removed by etching. Thus, the upper surface 42a of the conductive layer 42 and the upper end of the liner film 301 are aligned.

[0175] Then, if Fig.16 and Fig.17 As shown, a spacer film 311 is formed above the semiconductor device 30 . Thus, the sacrificial amorphous silicon layer 170 exposed above the conductive layer 42 and the upper surface 42 a of the conductive layer 42 are covered by the spacer film 311 .

[0176] Then, if Fig.18 and Fig.19 As shown, after forming a mask by photolithography, performing film formation, resist coating, exposure, development, and stripping on the surface of the semiconductor device 30, a groove portion 45ca extending approximately parallel to the Y axis is formed in the semiconductor device 30 by etching through the insulating film 45b. As a result, the spacer film 311 is separated into a cylindrical portion 311a and a plate-like portion 311b. In addition, the conductive layer 42 extends approximately parallel to the Y axis and is separated into a plurality of electrodes repeatedly arranged in the + direction of the X axis. The electrodes correspond to the word lines WL (reference Figure 1 ).

[0177] In addition, the surrounding portion 42b is formed by a self-alignment process in the conductive layer 42. Specifically, even if the mask formation position of the photolithography method is offset, the cylindrical portion 311a of the spacer film 311 located on the side of the sacrificial amorphous silicon layer 170 also functions as a mask, so the surrounding portion 42b is formed around the transistor hole TH in a self-aligned manner.

[0178] Then, if Fig. 20 and Fig.21As shown, insulating films 45c and 45a are integrally formed above the semiconductor device 30. Then, by chemical mechanical polishing the upper surface of the semiconductor device 30, the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 45a.

[0179] Then, if Fig. 22 and Fig.23 As shown, the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching.

[0180] Then, if Fig.24 and Fig.25 As shown, an insulating film 43 b is formed above the semiconductor device 30 .

[0181] Then, if Fig.26 and Fig. 27 As shown, an insulating film 43 a is formed above the semiconductor device 30 .

[0182] Then, if Fig.28 and Fig.29 As shown, the upper portion of the semiconductor device 30 is etched back by reactive ion etching to expose the insulating film 45 a , and the lower electrode 32 is exposed at the bottom of the transistor hole TH.

[0183] Then, if Fig.30 and Fig.31 As shown in FIG. 1 , an oxide semiconductor layer 70 is formed inside the transistor hole TH. Then, the upper surface of the semiconductor device 30 is subjected to chemical mechanical polishing.

[0184] Then, if Fig.32 and Fig.33 As shown, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top on the upper surface of the semiconductor device 30. Then, a LPHM (Landing Pad Hard Mask) film 50e made of, for example, silicon oxide is formed on the metal film 50c.

[0185] Then, if Fig.34 and Fig.35 As shown, after a mask is formed by performing film formation, resist coating, exposure, development, and stripping on the surface of the semiconductor device 30 by photolithography, an upper electrode 50 that functions as a landing pad is formed by etching on the semiconductor device 30. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0186] Then, if Fig.36 and Fig.37As shown, an LP pad film 50d containing, for example, silicon oxide is formed on the upper surface of the semiconductor device 30. An insulating layer 63 is formed on the LP pad film 50d to fill the gap formed by the LP pad film 50d. The insulating layer 63 contains, for example, silicon oxide. Then, the upper surface of the semiconductor device 30 is subjected to chemical mechanical polishing.

[0187] Then, if Fig.38 and Fig.39 As shown, a barrier metal layer 51a, a conductive layer 51b, and a barrier metal layer 51c are formed from bottom to top on the upper surface of the semiconductor device 30. The barrier metal layers 51a and 51c include, for example, titanium nitride, and the conductive layer 51b includes, for example, tungsten.

[0188] Then, on the upper surface of the barrier metal layer 51c, BLHM (Bit Line Hard Mask) films 66a and 66b are formed from the lower side to the upper side. The BLHM films 66a and 66b include, for example, silicon nitride and silicon oxide, respectively.

[0189] Then, if Fig.40 and Fig.41 As shown, after forming a mask by photolithography, performing film formation, resist coating, exposure, development, and stripping on the surface of the semiconductor device 30, a groove portion 66ca extending substantially parallel to the X-axis is formed in the semiconductor device 30 by etching through the insulating layer 63 and the metal film 50c. As a result, the barrier metal layer 51a, the conductive layer 51b, and the barrier metal layer 51c extend substantially parallel to the X-axis and are separated into electrodes repeatedly arranged in the Y-axis + direction. The electrodes correspond to the bit lines BL (reference Figure 1 ).

[0190] Then, if Figure 3 and Figure 4 As shown in FIG. 1 , an insulating film 66c that buries the groove portion 66ca is formed above the semiconductor device 30. The insulating film 66c includes, for example, silicon oxide.

[0191] (Effect)

[0192] Assume that when the sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30 in a reducing atmosphere without forming the liner film 301, the sacrificial amorphous silicon layer 170 is directly formed on the lower electrode 32 including ITO. At this time, silicon whiskers may be generated at the contact portion between the lower electrode 32 and the sacrificial amorphous silicon layer 170.

[0193] In contrast, in this embodiment, if Fig.10 and Fig.11As shown, when the sacrificial amorphous silicon layer 170 is formed, the inner wall of the transistor hole TH is covered by the liner film 301 and the lower electrode 32 is not exposed. Thus, since the lower electrode 32 and the sacrificial amorphous silicon layer 170 are not in contact, the generation of silicon whiskers can be suppressed.

[0194] Next, a second example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the second example of the first embodiment) will be described.

[0195] (First embodiment, second example)

[0196] like Fig.42 and Fig.43 As shown, the semiconductor device 30 of the second example of the first embodiment is Figure 3 and Figure 4 The semiconductor device 30 of the first example of the first embodiment shown is different in that a step surface 401 a in the hole 401 is located above the surface 42 a of the conductive layer 42 and below the lower surface of the upper electrode 50 .

[0197] [Method for Manufacturing Semiconductor Device 30 According to Second Example of First Embodiment]

[0198] In the method for manufacturing the semiconductor device 30 according to the second example of the first embodiment, after the sacrificial amorphous silicon layer 170 is etched back to remove a portion of the upper portion of the sacrificial amorphous silicon layer 170 (see Fig.12 and Fig.13 ),like Fig.44 and Fig.45 As shown, a portion of the upper portion of the liner film 301 is removed by etching. As a result, the upper end of the liner film 301 is located below the upper end of the sacrificial amorphous silicon layer 170. By controlling the amount of the liner film 301 removed, the position of the upper end of the liner film 301 can be adjusted.

[0199] Next, a third example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the third example of the first embodiment) will be described.

[0200] (First embodiment, third example)

[0201] like Fig.46 and Fig.47 As shown, the semiconductor device 30 of the third example of the first embodiment is Figure 3 and Figure 4 The semiconductor device 30 of the first example of the first embodiment shown is different in that the upper end of the liner film 301 is in contact with the upper electrode 50 and the step surface 401 a is not formed in the hole 401 .

[0202] [Method for Manufacturing Semiconductor Device 30 According to Third Example of First Embodiment]

[0203] In the method for manufacturing the semiconductor device 30 according to the third example of the first embodiment, after removing the insulating film 45ba, the liner film 301 exposed above the conductive layer 42 is removed by etching (see Fig.14 and Fig.15 ), and Fig.48 and Fig.49 As shown, only the insulating film 45 ba is removed by etching, and the liner film 301 exposed above the conductive layer 42 remains.

[0204] Next, a fourth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the fourth example of the first embodiment) will be described.

[0205] (First embodiment, fourth example)

[0206] like Fig.50 and Fig.51 As shown, the semiconductor device 30 of the fourth example of the first embodiment is Figure 3 and Figure 4 The semiconductor device 30 of the first example of the first embodiment shown is different in that the gate insulating film 43 does not include the insulating film 43 b .

[0207] [Method for Manufacturing Semiconductor Device 30 According to Fourth Example of First Embodiment]

[0208] In the method for manufacturing the semiconductor device 30 according to the fourth example of the first embodiment, instead of forming the insulating film 43b (see Fig.24 and Fig.25 ), and Fig.52 and Fig.53 As shown in FIG. 1 , an insulating film 43a is formed above the semiconductor device 30. Thus, the steps of forming the insulating film 43b including silicon nitride can be shortened.

[0209] Hereinafter, a fifth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the fifth example of the first embodiment) will be described.

[0210] (Fifth Example of the First Implementation Method)

[0211] like Fig.54 and Fig.55 As shown, the semiconductor device 30 of the fifth example of the first embodiment is Fig.50 and Fig.51 The semiconductor device 30 of the fourth example of the first embodiment shown is different in that a step surface 401 a in the hole 401 is located above the surface 42 a of the conductive layer 42 and below the lower surface of the upper electrode 50 .

[0212] With this configuration, since the possibility of the conductive layer 42 and the insulating film 43 a coming into contact with each other can be reduced, an increase in gate leakage can be suppressed.

[0213] [Method for Manufacturing Semiconductor Device 30 According to Fifth Example of First Embodiment]

[0214] In the method for manufacturing the semiconductor device 30 according to the fifth example of the first embodiment, Fig.44 and Fig.45 As shown in FIG. 1 , a portion of the upper portion of the liner film 301 is removed by etching. Fig.52 and Fig.53 As shown, an insulating film 43 a is formed above the semiconductor device 30 .

[0215] Hereinafter, a sixth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the sixth example of the first embodiment) will be described.

[0216] (Sixth example of the first embodiment)

[0217] like Fig.56 and Fig.57 As shown, the semiconductor device 30 of the sixth example of the first embodiment is Fig.50 and Fig.51 The semiconductor device 30 according to the fourth example of the first embodiment shown is different in that the upper end of the liner film 301 is in contact with the upper electrode 50 and the step surface 401 a is not formed in the hole 401 .

[0218] [Method for Manufacturing Semiconductor Device 30 According to Sixth Example of First Embodiment]

[0219] In the method for manufacturing the semiconductor device 30 according to the sixth example of the first embodiment, Fig.48 and Fig.49 As shown in FIG. 4 , only the insulating film 45ba is removed by etching, and the liner film 301 exposed above the conductive layer 42 remains. Fig.52 and Fig.53 As shown, an insulating film 43 a is formed above the semiconductor device 30 .

[0220] Hereinafter, a seventh example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the seventh example of the first embodiment) will be described.

[0221] (First Implementation Example 7)

[0222] like Fig.58 and Fig.59 As shown, the semiconductor device 30 of the seventh example of the first embodiment is Figure 3 and Figure 4 The semiconductor device 30 according to the first example of the first embodiment shown is different in that it does not include a liner film 301 .

[0223] [Method for Manufacturing Semiconductor Device 30 According to Seventh Example of First Embodiment]

[0224] In the method for manufacturing the semiconductor device 30 according to the seventh example of the first embodiment, after the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching (see Fig. 22 and Fig.23 ),like Fig.60 and Fig.61 As shown, the liner film 301 is removed by etching.

[0225] Then, if Fig.62 and Fig.63 As shown, an insulating film 43 b and an insulating film 43 a are sequentially formed above the semiconductor device 30 .

[0226] In the semiconductor device 30 of the seventh example of the first embodiment, since the liner film 301 is removed, the insulating film 43b and the insulating film 43a are formed from the inner surface of the cylindrical portion 311a in the spacer film 311 to the inner surface of the step surface 401a and the surrounding portion 42b in the conductive layer 42.

[0227] Therefore, the inner surface of the insulating film 43 a includes a step surface 43 aa that faces the Z-axis direction and has an annular shape when viewed from below.

[0228] When the semiconductor device 30 is viewed from above, part or all of the insulating film 43a facing the conductive layer 42 is blocked by the step surface 43aa and cannot be seen. Fig.28 and Fig.29 ), it is possible to prevent a portion or all of the insulating film 43a facing the conductive layer 42 from being damaged by reactive ion etching. Thus, it is possible to prevent the occurrence of gate leakage.

[0229] Hereinafter, an eighth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the eighth example of the first embodiment) will be described.

[0230] (First Implementation Example 8)

[0231] like Fig.64 and Fig.65 As shown, the semiconductor device 30 of the eighth example of the first embodiment is Fig.58 and Fig.59 The semiconductor device 30 of the seventh example of the first embodiment shown is different in that a step surface 401 a in the hole 401 is located above the surface 42 a of the conductive layer 42 and below the lower surface of the upper electrode 50 .

[0232] With this configuration, since the step surface 43 aa can be separated from the conductive layer 42 , it is possible to suppress the occurrence of gate leakage due to electric field concentration on the step surface 43 aa .

[0233] [Method for Manufacturing Semiconductor Device 30 According to Example 8 of First Embodiment]

[0234] In the method for manufacturing the semiconductor device 30 according to the eighth example of the first embodiment, Fig.44 and Fig.45 As shown in FIG. 1 , a portion of the upper portion of the liner film 301 is removed by etching. Fig.60 and Fig.61 As shown in FIG. 1 , the liner film 301 is removed by etching. Then, as shown in FIG. Fig.62 and Fig.63 As shown, an insulating film 43 b and an insulating film 43 a are sequentially formed above the semiconductor device 30 .

[0235] Hereinafter, a ninth example of the semiconductor device 30 according to the first embodiment (hereinafter sometimes referred to as the ninth example of the first embodiment) will be described.

[0236] (First Implementation Example 9)

[0237] like Fig.66 and Fig.67 As shown, the semiconductor device 30 of the ninth example of the first embodiment is Fig.58 and Fig.59 The semiconductor device 30 of the seventh example of the first embodiment shown is different in that the upper end of the liner film 301 is in contact with the upper electrode 50 and the step surface 401a in the hole 401 and the step surface 43aa in the insulating film 43a are not formed.

[0238] [Method for Manufacturing Semiconductor Device 30 According to Ninth Example of First Embodiment]

[0239] In the method for manufacturing the semiconductor device 30 according to the ninth example of the first embodiment, Fig.48 and Fig.49 As shown in FIG. 4 , only the insulating film 45ba is removed by etching, and the liner film 301 exposed above the conductive layer 42 remains. Fig.60 and Fig.61 As shown in FIG. 1 , the liner film 301 is removed by etching. Then, as shown in FIG. Fig.62 and Fig.63 As shown, an insulating film 43 b and an insulating film 43 a are sequentially formed above the semiconductor device 30 .

[0240] [Second embodiment]

[0241] A semiconductor device 30B according to the second embodiment will be described. In the second embodiment and thereafter, the description of matters common to the first embodiment will be omitted, and only the differences will be described. In particular, the same functions and effects of the same configuration will not be described in order for each embodiment.

[0242] Fig.68 70ZX is a cross section parallel to the ZX plane, and shows a cross-sectional view of the semiconductor device 30B when viewed from the cross section 70ZX included in the oxide semiconductor layer 70 . Fig.69 70YZ is a cross section parallel to the YZ plane, and is a cross-sectional view of the semiconductor device 30B when viewed from the cross section 70YZ included in the oxide semiconductor layer 70 .

[0243] like Fig.68 and Fig.69 As shown, the semiconductor device 30B of the second embodiment is Figure 3 to Figure 5 Compared with the semiconductor device 30 shown in the figure, an insulating film 501 (an example of a “fifth insulating film”) is further provided in place of the liner film 301 .

[0244] The insulating layer 45 includes a layer L1 including an insulating film 45a, a layer L2 including a plate-like portion 311b, a layer L3 including a plurality of conductive layers 42 (an example of a “first layer”), a layer L4 including an insulating film 45b (an example of a “fourth insulating film”) (an example of a “second layer”), and a layer L5 including an insulating film 501 (an example of a “third layer”).

[0245] The layers L1, L2, L3, L4 and L5 are arranged in order from the top. The insulating film 45c (an example of the "sixth insulating film") is located between two conductive layers 42 adjacent to each other in the + direction of the X axis, extends in the + direction of the Y axis, and divides the layers L2, L3, L4 and L5.

[0246] The lower end of the insulating film 45 c is in contact with the insulating layer 35 (an example of the “seventh insulating film”) provided between the two lower electrodes 32 .

[0247] The insulating film 501 is provided between two oxide semiconductor layers 70 adjacent to each other in the Y-axis + direction and below the insulating film 45b (see Fig.69 ).

[0248] In addition, the insulating film 501 is provided between two oxide semiconductor layers 70 adjacent to each other in the + direction of the X axis, and below the insulating film 45b whose two side surfaces are sandwiched by the two insulating films 45c (see Fig.68 ).

[0249] The insulating film 501 contains at least one element selected from aluminum, silicon, hafnium, lanthanum, niobium, yttrium, tantalum, vanadium and magnesium, and oxygen. In this embodiment, the insulating film 501 is aluminum oxide. The etching rate of the insulating film 501 is greater than the etching rate of the insulating film 45b.

[0250] The gate insulating film 43 surrounds a portion of the upper portion of the oxide semiconductor layer 70 along the circumferential direction of the oxide semiconductor layer 70. The oxide semiconductor layer 70 includes a large diameter portion 70c between an end portion 43c below the gate insulating film 43 and the lower electrode 32, the large diameter portion 70c having a diameter larger than that of the gate insulating film 43 at the end portion 43c.

[0251] [Method for manufacturing semiconductor device]

[0252] Hereinafter, as an example of the method for manufacturing the semiconductor device according to the second embodiment, a method for manufacturing the semiconductor device 30B will be described.

[0253] First, if Fig.70 and Fig.71 As shown in FIG. 1 , an insulating film 501, an insulating film 45b, a conductive layer 42, and an insulating film 45ba are sequentially provided above the insulating layer 35. The insulating film 501, the insulating film 45b, the conductive layer 42, and the insulating film 45ba extend substantially parallel to the XY plane. A transistor hole TH extending substantially parallel to the Z axis and penetrating through the insulating film 45ba, the conductive layer 42, and the insulating film 45b to the middle of the insulating film 501 is formed, and then cleaned. At the bottom of the transistor hole TH, the insulating film 501 is exposed, but the lower electrode 32 is not exposed.

[0254] Then, if Fig.72 and Fig.73 As shown in FIG. 1 , a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30B. Thus, the transistor hole TH is buried by the sacrificial amorphous silicon layer 170 .

[0255] Then, if Fig.74 and Fig.75 As shown, by etching back the sacrificial amorphous silicon layer 170, a portion of the upper portion of the sacrificial amorphous silicon layer 170 is removed, thereby exposing the upper surface of the insulating film 45ba.

[0256] Then, if Fig.76 and Fig.77 As shown, the insulating film 45ba is removed by etching.

[0257] Then, if Fig.78 and Fig.79 As shown in FIG. 1 , a spacer film 311 is formed above the semiconductor device 30B. Thus, the sacrificial amorphous silicon layer 170 exposed above the conductive layer 42 and the upper surface 42 a of the conductive layer 42 are covered by the spacer film 311 .

[0258] Then, if Fig.80 and Fig.81 As shown, after forming a mask by photolithography, performing film formation, resist coating, exposure, development, and stripping on the surface of the semiconductor device 30B, a groove portion 45ca extending approximately parallel to the Y axis is formed in the semiconductor device 30B by etching through the insulating film 501. As a result, the spacer film 311 is separated into a cylindrical portion 311a and a plate-like portion 311b. In addition, the conductive layer 42 extends approximately parallel to the Y axis and is separated into a plurality of electrodes repeatedly arranged in the + direction of the X axis. The electrodes correspond to the word lines WL (reference Figure 1 ).

[0259] Then, if Fig.82 and Fig.83 As shown, insulating films 45c and 45a are integrally formed above the semiconductor device 30B.

[0260] Then, if Fig.84 and Fig.85 As shown, by chemical mechanical polishing the upper surface of the semiconductor device 30B, the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 45 a .

[0261] Then, if Fig.86 and Fig.87 As shown, the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching.

[0262] Then, if Fig.88 and Fig.89 As shown, an insulating film 43 b and an insulating film 43 a are sequentially formed above the semiconductor device 30B.

[0263] Then, if Fig.90 and Fig.91 As shown, the insulating film 45 a is exposed by etching back the upper portion of the semiconductor device 30B by reactive ion etching, and the insulating film 501 is exposed at the bottom of the transistor hole TH.

[0264] Then, if Fig.92 and Fig.93 As shown in FIG. 1 , the insulating film 501 exposed at the bottom of the transistor hole TH is wet-etched to remove a portion of the insulating film 501. Since the etching rate of the insulating film 501 is higher than the etching rate of the insulating film 45b, the amount of the insulating film 501 removed is greater than the amount of the insulating film 45b removed. Then, between the end portion 43c below the gate insulating film 43 and the lower electrode 32, a space 270 having a diameter larger than the diameter of the gate insulating film 43 at the end portion 43c is formed.

[0265] Then, if Fig.94 and Fig.95As shown in FIG. 2 , an oxide semiconductor layer 70 is formed inside the transistor hole TH. At this time, the oxide semiconductor layer 70 filling the space 270 forms a large diameter portion 70 c.

[0266] Then, if Fig.96 and Fig.97 As shown, chemical mechanical polishing is performed on the upper surface of the semiconductor device 30B.

[0267] Then, if Fig.98 and Fig.99 As shown, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top on the upper surface of the semiconductor device 30B. Then, a LPHM film 50e including, for example, silicon oxide is formed on the metal film 50c.

[0268] (Effect)

[0269] If the insulating film 501 is not formed, after the transistor hole TH is formed, when the residue inside the transistor hole TH is removed by dry etching or wet etching, the ITO included in the lower electrode 32 may be damaged by the cleaning agent.

[0270] In contrast, in this embodiment, if Fig.70 and Fig.71 As shown, since the lower electrode 32 is not exposed at the bottom of the transistor hole TH, it is possible to prevent the ITO included in the lower electrode 32 from being damaged by the cleaning agent.

[0271] In addition, it is assumed that when the sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30 in a reducing atmosphere without forming the insulating film 501, the sacrificial amorphous silicon layer 170 is directly formed on the lower electrode 32 including ITO. At this time, silicon whiskers may be generated at the contact portion between the lower electrode 32 and the sacrificial amorphous silicon layer 170.

[0272] In contrast, in this embodiment, if Fig.72 and Fig.73 As shown, when the sacrificial amorphous silicon layer 170 is formed, the insulating film 501 is exposed at the bottom of the transistor hole TH instead of the lower electrode 32. Thus, since the lower electrode 32 and the sacrificial amorphous silicon layer 170 are not in contact with each other, the generation of silicon whiskers can be suppressed.

[0273] Furthermore, assuming that the insulating film 501 is not formed, when the gate insulating film 43 is formed, since the conductive layer 42 made of tungsten and the lower electrode 32 made of ITO are exposed, tungsten whiskers may be generated.

[0274] In contrast, in this embodiment, if Fig.88 and Fig.89As shown, when the gate insulating film 43 is formed, the insulating film 501 is exposed at the bottom of the transistor hole TH instead of the lower electrode 32. This prevents both the conductive layer 42 and the lower electrode 32 from being exposed, thereby suppressing the generation of tungsten whiskers.

[0275] Furthermore, since the large-diameter portion 70 c is formed below the oxide semiconductor layer 70 , the contact area between the lower end 70 b of the oxide semiconductor layer 70 and the lower electrode 32 can be increased, the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32 can be reduced.

[0276] In the semiconductor device 30 of the first embodiment, the step surface 401a is provided between the conductive layer 42 and the upper electrode 50, but the present invention is not limited thereto. The step surface 401a may be provided below the surface 42a of the conductive layer 42.

[0277] (a) The second electrode contains at least one element selected from the group consisting of indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron.

[0278] (b) The third insulating film is in contact with the gate electrode and the second electrode.

[0279] (c) The third insulating film contains at least one element of silicon, aluminum, zirconium, hafnium, lanthanum, titanium, and strontium, and at least one element of oxygen and nitrogen.

[0280] (d) The third insulating film is silicon nitride, silicon oxide, silicon nitride oxide, aluminum oxide, aluminum nitride, zirconium oxide, hafnium oxide, ruthenium oxide, niobium oxide, yttrium oxide, tantalum oxide, vanadium oxide, magnesium oxide, lanthanum oxide, titanium oxide or strontium oxide.

[0281] The present embodiment is described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Those skilled in the art can appropriately design and change these specific examples, and as long as they have the characteristics of the present disclosure, they are also included in the scope of the present disclosure. The various elements and their configurations, conditions, shapes, etc. of the specific examples are not limited to the elements illustrated, and can be appropriately changed. The various elements of the specific examples can be appropriately changed and combined as long as no technical contradiction occurs.

[0282] [Explanation of Symbols]

[0283] 10 Semiconductor substrate

[0284] 11 Circuit

[0285] 20 Capacitor

[0286] 21 Conductors

[0287] 22 Insulation film

[0288] 23 Conductors

[0289] 24,25 Capacitor electrodes

[0290] 30,30B Semiconductor devices

[0291] 32 Lower electrode

[0292] 33 Conductors

[0293] 34,35 Insulation layer

[0294] 40 Field Effect Transistor

[0295] 42 Conductive layer

[0296] 42a face

[0297] 42b Enclosure

[0298] 42c Connection part

[0299] 43. Gate insulating film

[0300] 43a,43b Insulation film

[0301] 43aa Step surface

[0302] 43c End

[0303] 45 Insulation layer

[0304] 45a,45b,45ba,45c Insulation film

[0305] 45ca groove

[0306] 50 Upper electrode

[0307] 50a Metal oxide layer

[0308] 50b Barrier metal layer

[0309] 50c Metal Film

[0310] 70 Oxide semiconductor layer

[0311] 170 Sacrificial amorphous silicon layer

[0312] 270 Space

[0313] 70a Upper

[0314] 70b Lower end

[0315] 70c large diameter part

[0316] 101 Semiconductor storage device

[0317] 301 cushion film

[0318] 311 Spacer Film

[0319] 311a Cylinder

[0320] 311b plate-shaped part

[0321] 401 Hole

[0322] 401a Step surface

[0323] 401b Inner wall

[0324] 501 Insulation film

[0325] L1, L2, L3, L4, L5 layers.

Claims

1. A semiconductor device comprising: An oxide semiconductor having a first end and a second end, and extending in a first direction from the second end toward the first end; a first electrode connected to the first end of the oxide semiconductor; a second electrode connected to the second end of the oxide semiconductor; a gate electrode, between the first end and the second end of the oxide semiconductor, surrounding the oxide semiconductor via a first insulating film; and a second insulating film disposed on the first direction side of the gate electrode and surrounding the oxide semiconductor via the first insulating film; and The gate electrode and the second insulating film form a hole portion that accommodates at least a portion of the oxide semiconductor; A step surface facing in a direction opposite to the first direction is formed on an inner wall of the hole.

2. The semiconductor device according to claim 1, wherein The first insulating film is in contact with the first electrode.

3. The semiconductor device according to claim 1, wherein The step surface is located between the gate electrode and the first electrode.

4. The semiconductor device according to claim 1, wherein A surface of the gate electrode on the first direction side is aligned with the step surface.

5. The semiconductor device according to claim 1, wherein The semiconductor device further comprises: The third insulating film is located at least between the gate electrode and the first insulating film, and an end portion on the first direction side and an end portion on the opposite direction side are in contact with the step surface and the second electrode, respectively.

6. The semiconductor device according to claim 1, wherein The semiconductor device comprises: The plurality of oxide semiconductors are arranged along a second direction intersecting with the first direction; and The gate electrode extends along the second direction and surrounds the plurality of oxide semiconductors through the plurality of first insulating films respectively; The gate electrode includes a first portion surrounding the oxide semiconductor and a second portion connecting two of the first portions; The width of the second portion is narrower than the width of the first portion.

7. A semiconductor device comprising: A plurality of oxide semiconductors having a first end and a second end, and extending in a first direction from the second end toward the first end; a plurality of first electrodes, respectively connected to the first ends of the plurality of oxide semiconductors; a plurality of second electrodes, respectively connected to the second ends of the plurality of oxide semiconductors; a gate electrode extending in a second direction intersecting the first direction, and surrounding the oxide semiconductor with a plurality of first insulating films interposed between the first end and the second end of each of the plurality of oxide semiconductors arranged in the second direction; a fourth insulating film provided in a direction opposite to the first direction of the gate electrode; and a fifth insulating film provided between two of the oxide semiconductors adjacent to each other in the second direction and in a direction opposite to the first direction of the fourth insulating film; and The etching rate of the fifth insulating film is greater than the etching rate of the fourth insulating film.

8. The semiconductor device according to claim 7, wherein The semiconductor device further comprises: The plurality of gate electrodes are repeatedly arranged in a third direction intersecting the first direction and the second direction; The first layer comprises the plurality of gate electrodes; A second layer comprising the fourth insulating film; a third layer including the fifth insulating film; and The sixth insulating film is located between two of the oxide semiconductors adjacent to each other in the third direction, extends along the second direction, and divides the first layer, the second layer, and the third layer.

9. The semiconductor device according to claim 8, wherein The semiconductor device further comprises: a seventh insulating film provided between the second electrodes; and The sixth insulating film is in contact with the seventh insulating film.

10. The semiconductor device according to claim 7, wherein The gate electrode includes a first portion surrounding the oxide semiconductor and a second portion connecting two of the first portions; and The width of the second portion is narrower than the width of the first portion.

11. The semiconductor device according to claim 7, wherein The fifth insulating film includes at least one element of aluminum, silicon, hafnium, lanthanum, niobium, yttrium, tantalum, vanadium, and magnesium, and oxygen.

12. A semiconductor device comprising: A columnar oxide semiconductor having a first end and a second end, and extending in a first direction from the second end toward the first end; a first electrode connected to the first end of the oxide semiconductor; a second electrode connected to the second end of the oxide semiconductor; a first insulating film surrounding the oxide semiconductor in a circumferential direction of the oxide semiconductor; and a gate electrode, between the first end and the second end of the oxide semiconductor, surrounding the oxide semiconductor via the first insulating film; and The oxide semiconductor, The first insulating film includes a large-diameter portion having a diameter larger than a diameter of the first insulating film at the end portion between the end portion in the direction opposite to the first direction and the second electrode.

13. A semiconductor storage device comprising: The semiconductor device according to claim 1, 6 or 11; a first capacitor electrode connected to the first electrode or the second electrode; a second capacitor electrode, facing the first capacitor electrode; and The dielectric film is provided between the first capacitor electrode and the second capacitor electrode.

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