Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention provides a semiconductor device, a preparation method thereof and electronic equipment, relates to the technical field of semiconductor chips, and aims to provide an enhanced semiconductor device and reduce the preparation difficulty of the semiconductor device. The semiconductor device comprises a substrate, a channel layer, a barrier layer, a P-type material layer, a source electrode, a drain electrode and a grid electrode. The channel layer is located on one side of the substrate. The channel layer comprises a first sub-part and second sub-parts which are connected, and the second sub-parts are located on the two opposite sides of the first sub-part. The surface of the first sub-portion away from the substrate is higher than the surface of the second sub-portion away from the substrate. The barrier layer is located on the side, away from the substrate, of the first sub-part. The P-type material layer is located on the side, away from the substrate, of the second sub-part. And the P-type material layer is in contact with the side surface of the first sub-part and is in contact with at least one part of the side surface of the barrier layer. The source electrode and the drain electrode are located on the side, away from the substrate, of the P-type material layer. The gate is located at one side of the barrier layer away from the substrate. The semiconductor device is applied to the electronic equipment.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device and a method for preparing the same, and an electronic device. Background Art

[0002] Gallium nitride (GaN) semiconductor materials are called third-generation semiconductor materials. Compared with first-generation semiconductor materials represented by silicon, they have higher bandgap width, critical breakdown field strength, and electron saturation drift velocity. They have significant advantages in high frequency, high voltage resistance, high power, and low on-resistance. They can be used as core devices in various power conversion systems and have broad prospects in optoelectronics, radio frequency, power electronics, consumer electronics, 5G radio frequency, servers, and telecommunications applications. Summary of the invention

[0003] The embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, and an electronic device, aiming to provide an enhanced semiconductor device and reduce the difficulty of manufacturing the semiconductor device.

[0004] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0005] On the one hand, a semiconductor device is provided, comprising: a substrate, a channel layer, a barrier layer, a P-type material layer, a source, a drain and a gate; the channel layer is located on one side of the substrate; the channel layer comprises a first sub-portion and a second sub-portion connected to the first sub-portion, and the second sub-portion is located on two opposite sides of the first sub-portion; relative to the substrate, a surface of the first sub-portion away from the substrate is higher than a surface of the second sub-portion away from the substrate; the barrier layer is located on a side of the first sub-portion away from the substrate; the P-type material layer is located on a side of the second sub-portion away from the substrate, and is respectively located on two opposite sides of the first sub-portion; the P-type material layer is in contact with a side of the first sub-portion, and is in contact with at least a portion of a side of the barrier layer; the source and the drain are located on a side of the P-type material layer away from the substrate, and are respectively located on two opposite sides of the first sub-portion; the gate is located on a side of the barrier layer away from the substrate.

[0006] The semiconductor device provided by the embodiments of the present disclosure is provided by setting a channel layer and a barrier layer on a substrate, the channel layer includes a first sub-portion and a second sub-portion, wherein the surface of the first sub-portion away from the substrate is higher than the surface of the second sub-portion away from the substrate, and the second sub-portion is located on two opposite sides of the first sub-portion, a barrier layer is provided on the first sub-portion, and a P-type material layer is provided on the second sub-portion, so that the P-type material layer is in contact with the side surface of the first sub-portion and the side surface of the barrier layer, and a gate is provided on the barrier layer. Therefore, under the control of the gate voltage, holes provided by the P-type material layer can be conducted through the connection interface between the barrier layer and the first sub-portion, so that the semiconductor device is an enhanced power device that utilizes hole conduction.

[0007] Furthermore, in the semiconductor device provided by the present disclosure, there is no need to prepare grooves with relatively high process difficulty, and there is no need to control the depth of the grooves. It is only necessary to form a barrier layer and a channel layer with simple structures, and the preparation process of the barrier layer and the channel layer is relatively simple, the thickness of the barrier layer and the channel layer is easy to control, and the process controllability and process stability of preparing the barrier layer and the channel layer are high, thereby reducing the difficulty of preparing the semiconductor device. It is also possible to make the size accuracy of the prepared barrier layer higher, so that the output current of the semiconductor device can be adjusted according to actual needs, thereby improving the performance of the semiconductor device.

[0008] In addition, in the semiconductor device provided by the present invention, the surface of the first sub-portion away from the substrate side has not been etched, thereby avoiding etching damage to the surface of the first sub-portion away from the substrate side, thereby avoiding affecting the hole mobility at the connection interface between the first sub-portion and the barrier layer 30, thereby ensuring that the hole mobility is high, making the channel resistance (the channel resistance here refers to the resistance between the source and the drain) small, which is beneficial to increasing the output current of the semiconductor device.

[0009] In some embodiments, the barrier layer has a thickness ranging from 3 nm to 40 nm.

[0010] In some embodiments, the barrier layer includes at least a first sublayer and a second sublayer that are stacked; the material of the first sublayer is different from the material of the second sublayer.

[0011] In some embodiments, an orthographic projection of the barrier layer on the substrate coincides with an orthographic projection of the first sub-portion on the substrate.

[0012] In some embodiments, an orthographic projection of the barrier layer on the substrate is within a range of an orthographic projection of the gate on the substrate.

[0013] In some embodiments, the side of the source electrode close to the drain electrode is in the same plane as the side of the barrier layer close to the source electrode; the side of the drain electrode close to the source electrode is in the same plane as the side of the barrier layer close to the drain electrode; the gate electrode also covers a portion of the source electrode and a portion of the drain electrode.

[0014] In some embodiments, along the arrangement direction of the source, the first sub-portion and the drain, there is a gap between the source and the barrier layer, and there is a gap between the drain and the barrier layer; the gate also covers a portion of the P-type material layer.

[0015] In some embodiments, the semiconductor device further includes a dielectric layer; the dielectric layer is located between the barrier layer and the gate, and the dielectric layer is also overlapped on the source and the drain.

[0016] In some embodiments, the dielectric layer has an opening; the gate is connected to the barrier layer through the opening.

[0017] On the other hand, a method for preparing a semiconductor device is provided, the method comprising: forming a channel layer and a barrier layer on a substrate; the channel layer comprises a first sub-portion and a second sub-portion connected to the first sub-portion, the second sub-portion being located on two opposite sides of the first sub-portion; relative to the substrate, a surface of the first sub-portion on a side away from the substrate is higher than a surface of the second sub-portion on a side away from the substrate; the barrier layer is located on a side of the first sub-portion away from the substrate; a P-type material layer is formed on the second sub-portion; the P-type material layer is respectively located on two opposite sides of the first sub-portion; the P-type material layer is in contact with a side surface of the first sub-portion and in contact with at least a portion of a side surface of the barrier layer; a source and a drain are formed on the P-type material layer; the source and the drain are respectively located on two opposite sides of the first sub-portion; and a gate is formed on the barrier layer.

[0018] It can be understood that the beneficial effects that can be achieved by the method for preparing the semiconductor device provided in the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here.

[0019] In some embodiments, a channel layer and a barrier layer are formed on a substrate, including: forming a channel film and a barrier film in sequence on the substrate; forming a mask pattern on the barrier film, the mask pattern covering the barrier layer to be formed and the first sub-portion to be formed; removing the portion of the barrier film not covered by the mask pattern, retaining the portion of the channel film covered by the mask pattern, and thinning the portion of the channel film not covered by the mask pattern, to obtain the barrier layer, the first sub-portion, and the second sub-portion.

[0020] In some embodiments, a source and a drain are formed on a P-type material layer, including: forming a conductive film on a mask pattern and the P-type material layer; removing the mask pattern and the portion of the conductive film corresponding to the mask pattern, retaining the portion of the conductive film not corresponding to the mask pattern, to form a source and a drain; the side of the source electrode close to the drain is in the same plane as the side of the barrier layer close to the source; the side of the drain electrode close to the source is in the same plane as the side of the barrier layer close to the drain.

[0021] In some embodiments, a source and a drain are formed on a P-type material layer, including: forming a conductive film on a mask pattern and the P-type material layer; patterning the conductive film to form a source and a drain; along the arrangement direction of the source, the first sub-portion and the drain, there is a gap between the source and the barrier layer, and there is a gap between the drain and the barrier layer.

[0022] In some embodiments, before forming a gate on the barrier layer, the preparation method further includes: removing the mask pattern.

[0023] In some embodiments, before forming the gate on the barrier layer, the preparation method further includes: forming a dielectric layer on the barrier layer, and a portion of the dielectric layer is also overlapped on the source and the drain.

[0024] On the other hand, an electronic device is provided, comprising the semiconductor device as described in any of the above embodiments, and a circuit board connected to the semiconductor device.

[0025] It can be understood that the beneficial effects that can be achieved by the method for preparing the electronic device and the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the present disclosure, the drawings required for use in some embodiments of the present disclosure are briefly introduced below.

[0027] Figure 1 is a structural diagram of an electronic device according to some embodiments of the present disclosure;

[0028] Figure 2 is a partial structural diagram of another electronic device according to some embodiments of the present disclosure;

[0029] Figure 3 is a structural diagram of a semiconductor device according to a possible implementation manner;

[0030] Figure 4 is a flow chart of manufacturing a semiconductor device according to some embodiments of the present disclosure;

[0031] Figure 5 is a structural diagram of a semiconductor device in a manufacturing process according to some embodiments of the present disclosure;

[0032] Figure 6 is a structural diagram of a semiconductor device in another preparation process according to some embodiments of the present disclosure;

[0033] Figure 7 is a structural diagram of a semiconductor device in another preparation process according to some embodiments of the present disclosure;

[0034] Figure 8 is a structural diagram of a semiconductor device in another preparation process according to some embodiments of the present disclosure;

[0035] Fig. 9 is a structural diagram of a semiconductor device in another preparation process according to some embodiments of the present disclosure;

[0036] Fig.10 is a structural diagram of a semiconductor device in another preparation process according to some embodiments of the present disclosure;

[0037] Fig.11 is a structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0038] Fig.12 is a structural diagram of another semiconductor device according to some embodiments of the present disclosure;

[0039] Fig.13 is a structural diagram of another semiconductor device according to some embodiments of the present disclosure;

[0040] Fig.14 is a structural diagram of yet another semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0042] In the description of the present disclosure, it is necessary to understand that the terms "upper", "lower", "front", "back", etc., indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0043] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0045] When describing some embodiments, the term "connected" and its derivative expressions may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0046] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0047] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0048] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0049] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0050] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0051] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0052] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the areas of layers and the thicknesses of regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0053] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0054] Unless otherwise defined, all technical terms used herein have the same meanings as those known to those of ordinary skill in the art.In the present disclosure, "at least one" means one or more, and "plurality" means two or more.

[0055] The embodiment of the present disclosure provides an electronic device 1000. The electronic device 1000 may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, etc. The embodiment of the present disclosure does not impose any special restrictions on the specific form of the above electronic device 1000.

[0056] For example, Figure 1 As shown, the electronic device 1000 includes a semiconductor device 100 and a circuit board 200. The semiconductor device 100 is connected to the circuit board 200 and receives a control signal provided by the circuit board 200, so that the electronic device 1000 can realize functions such as display and storage.

[0057] The circuit board 200 may be a printed circuit board (PCB).

[0058] The types of semiconductor devices 100 include, for example, multiple types, and different types of semiconductor devices 100 can, for example, implement different functions. Exemplarily, the semiconductor device 100 can be a memory, a logic chip, a processor, etc. For example, the semiconductor device 100 can be a memory, and the semiconductor device 100 can store data, etc.

[0059] Figure 2 The figure shows a partial structural diagram of an electronic device, the electronic device 1000 includes a printed circuit board (PCB) 1 and a chip packaging structure 2. The chip packaging structure 2 is electrically connected to the PCB 1 through an electrical connection structure 3, so that the chip packaging structure 2 can be interconnected with other chips or other electronic components on the PCB 1. In an optional embodiment, the electrical connection structure 3 can be a ball grid array (BGA).

[0060] Combination Figure 2 The chip packaging structure 2 includes: a chip 201 and a packaging substrate 202 . The chip 201 is integrated on the surface of the packaging substrate 202 . The chip 201 can be interconnected with other electronic devices on the packaging substrate 202 for signal interconnection.

[0061] The semiconductor device 100 is integrated in the chip 201 , and the performance of the semiconductor device 100 directly affects the performance of the chip 201 .

[0062] In the embodiment of the present disclosure, the semiconductor device 100 may be an enhancement-mode (E-mode for short) power device.

[0063] In one possible implementation, reference Figure 3 The preparation process of the semiconductor device 100' generally includes: forming a buffer layer 02, a channel layer 03, a barrier layer 04 and a P-type material layer 05 on a substrate 01 in sequence, and forming a source S and a drain D on the P-type material layer 05, etching a groove GR on the P-type material layer 05, forming a dielectric thin layer 06 in the groove GR, and then using a physical vapor deposition (Physical Vapor Deposition, referred to as PVD) process to evaporate a metal material to form a gate G, and obtain a power device. The substrate 01 can be a single crystal silicon material, and its crystal orientation can be <111> , with a thickness of about 1000 μm. The material of the buffer layer 02 can be gallium nitride (GaN), with a thickness of about 4.2 μm. The material of the channel layer 03 is UID (Unintentional Dopping)-GaN, with a thickness of about 420 nm. The material of the barrier layer 04 is Al 0.2 Ga 0.8N, and its thickness is about 15nm. The material of the P-type material layer 05 is P-type doped GaN, the depth of the groove GR is about 55nm, and the distance H between the bottom wall of the groove GR and the lower surface of the P-type material layer 05 is about 15nm. The material of the dielectric layer 06 is aluminum oxide (Al2O3), and its thickness is about 17nm. The semiconductor device formed by this preparation method can be called a GaN-based enhancement-mode power device.

[0064] The above preparation method relies on etching the P-type material layer to form a groove, and uses the groove to thin a portion of the P-type material layer so that a portion of the gate is located in the groove, thereby facilitating the gate to control the conduction of the holes in the channel layer, thereby forming an enhanced power device.

[0065] However, the process controllability and process stability of the depth of the groove formed by etching are poor, making the preparation of semiconductor devices difficult. The depth of the groove seriously affects the performance of the semiconductor device. If the depth of the groove is insufficient, it will cause the semiconductor device to be difficult to achieve enhanced mode, that is, it will be difficult to control the conduction between the source and the drain through the gate. If the depth of the groove is large, the thickness of the part of the P-type material layer that is opposite to the groove (that is, the distance H between the bottom wall of the groove and the surface of the P-type material layer close to the substrate side) is small, which can easily cause the output current of the semiconductor device to be greatly reduced, unable to meet the demand for large output current, and seriously affect the matching design between the semiconductor device and other integrated circuits. Therefore, it is urgent to provide an enhanced semiconductor device with a new structure.

[0066] Based on this, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device 100, which is used to manufacture the semiconductor device 100 described in any of the above embodiments. Figure 4 As shown, the preparation method includes: A100~A400.

[0067] A100, such as Figure 5 As shown in (c), a channel layer 20 and a barrier layer 30 are formed on a substrate 10. The channel layer 20 includes a first sub-portion 21 and a second sub-portion 22 connected to the first sub-portion 21, and the second sub-portion 22 is located on opposite sides of the first sub-portion 21. Relative to the substrate 10, the surface of the first sub-portion 21 away from the substrate 10 is higher than the surface of the second sub-portion 22 away from the substrate 10. The barrier layer 30 is located on the side of the first sub-portion 21 away from the substrate 10.

[0068] For example, the material of the substrate 10 includes silicon (Si), silicon carbide (SiC), sapphire, etc. The surface of the substrate 10 is a relatively flat surface, the channel layer 20 is located on one side of the substrate 10, and the thickness of the first sub-portion 21 is greater than the thickness of the second sub-portion 22.

[0069] For example, the material of the channel layer 20 may be gallium nitride (GaN). The material of the barrier layer 30 includes a plurality of nitride Al x In y Ga 1-x-y N (0≤x≤1, 0≤y≤1) or more. For example, the material of the barrier layer 30 may be aluminum nitride (AlN), indium nitride (InN), indium aluminum nitride (AlInN), gallium aluminum nitride (AlGaN), or x Ga 1-x N), gallium nitride (In x Ga 1- x N) or InGaN (Al x In y Ga 1-x-y N) one or more.

[0070] The material of the channel layer 20 is different from that of the barrier layer 30, and the material properties of the channel layer 20 are different from those of the barrier layer 30, so that a heterojunction is formed at the connection interface between the channel layer 20 and the barrier layer 30. In the absence of external voltage, a polarization effect is generated at the connection interface between the channel layer 20 and the barrier layer 30, and the polarization effect induces the channel layer 20 to form a two-dimensional electron gas (2DEG) at the interface close to the barrier layer 30.

[0071] The barrier layer 30 is located on the first sub-portion 21 , so that the area of ​​the connection interface between the barrier layer 30 and the first sub-portion 21 is relatively small.

[0072] A200, such as Figure 6 As shown, a P-type material layer 40 is formed on the second sub-portion 22. The P-type material layer 40 is respectively located on two opposite sides of the first sub-portion 21. The P-type material layer 40 contacts the side surface of the first sub-portion 21 and contacts at least a portion of the side surface of the barrier layer 30.

[0073] For example, a chemical vapor deposition process is used to heteroepitaxially grow a P-type material layer 40 on the second sub-portion 22. The P-type material layer 40 can provide holes.

[0074] In some examples, the material of the P-type material layer 40 may be undoped gallium nitride.

[0075] In some other examples, the material of the P-type material layer 40 may also be a P-type doped nitride, which may be Al x In y Ga 1-x-yN (0≤x≤1, 0≤y≤1) or more. For example, the material of the P-type material layer 40 may be gallium nitride (GaN) doped with iron (Fe), magnesium (Mg) or the like.

[0076] Taking the dopant of the P-type material layer 40 as iron as an example, for example, the material of the P-type material layer 40 can be lightly doped gallium nitride or heavily doped gallium nitride. For another example, in the P-type material layer 40, the doping concentration of iron in gallium nitride changes gradually, and the doping concentration of iron gradually increases or decreases along the direction from the top surface of the P-type material layer 40 to the bottom surface of the P-type material layer 40. For another example, in the P-type material layer 40, the doping concentration of iron in gallium nitride changes gradually, and the doping concentration of iron increases or decreases along the direction from the top surface of the P-type material layer 40 to the bottom surface of the P-type material layer 40. The top surface of the P-type material layer 40 refers to the surface of the P-type material layer 40 away from the substrate 10. The bottom surface of the P-type material layer 40 refers to the surface of the P-type material layer 40 close to the substrate 10.

[0077] For example, compared with the substrate 10 , the height of the surface of the P-type material layer 40 away from the substrate 10 is higher than the height of the surface of the first sub-portion 21 away from the substrate 10 .

[0078] For example, Figure 6 As shown, the P-type material layer 40 includes a first portion 41 and a second portion 42 that are spaced apart. The first portion 41 and the second portion 42 are located at two opposite sides of the first sub-portion 21, respectively.

[0079] The side surface of the first portion 41 of the P-type material layer 40 close to the second portion 42 and the side surface of the second portion 42 close to the first portion 41 are in contact with the side surface of the first sub-portion 21 and at least a portion of the side surface of the barrier layer 30 .

[0080] The side surface of the barrier layer 30 here refers to the surface connecting the top surface and the bottom surface of the barrier layer 30, wherein the top surface is the surface of the barrier layer 30 away from the substrate 10, and the bottom surface is the surface of the barrier layer 30 close to the substrate 10. At least a portion of the side surface of the barrier layer 30 here refers to the side surface of the barrier layer 30 or a portion of the side surface of the barrier layer 30.

[0081] In this way, it can be ensured that the connection interface between the channel layer 20 and the barrier layer 30 is connected to the P-type material layer 40, and that when a voltage is provided from the outside (for example, the gate 70 mentioned below provides a gate voltage), the holes in the connection interface can be conducted with the holes in the P-type material layer 40, thereby achieving conduction of the semiconductor device 100 and ensuring that the formed semiconductor device 100 is an enhanced power device.

[0082] The connection interface between the channel layer 20 and the barrier layer 30 refers to an interface formed by a surface of the first sub-portion 21 of the channel layer 20 away from the substrate 10 and a surface of the barrier layer 30 close to the substrate 10 .

[0083] Exemplarily, the thickness of the P-type material layer 40 is in the range of 1 nm to 500 nm.

[0084] For example, the thickness of the P-type material layer 40 ranges from 1 nm to 180 nm, from 200 nm to 350 nm, from 379 nm to 500 nm, from 420 nm to 500 nm, or from 20 nm to 100 nm.

[0085] For example, the thickness of the P-type material layer 40 may be 1 nm, 20 nm, 100 nm, 180 nm, 200 nm, 3501 nm, 379 nm, 420 nm, or 500 nm.

[0086] A300, such as Figure 7 (b) and Fig. 9 As shown in (c), a source electrode 50 and a drain electrode 60 are formed on the P-type material layer 40. The source electrode 50 and the drain electrode 60 are located at two opposite sides of the first sub-portion 21, respectively.

[0087] For example, the source electrode 50 is located on the first portion 41 , and the drain electrode 60 is located on the second portion 42 .

[0088] Exemplarily, the source electrode 50 and the drain electrode 60 may be made of the same material, which is a metal material, such as a nickel-gold alloy, a nickel-silver alloy, a platinum-gold alloy, or a palladium-gold alloy.

[0089] For example, the source electrode 50 and the drain electrode 60 may be formed by a sputtering process.

[0090] For example, the source electrode 50 and the P-type material layer 40 may form an ohmic contact, and the drain electrode 60 and the P-type material layer 40 may form an ohmic contact.

[0091] A400, such as Figure 7 Middle (d), Figure 8 Middle (b), Fig. 9 (e) and Fig.10 As shown in (b) , a gate 70 is formed on the barrier layer 30 .

[0092] For example, a sputtering process is adopted to form a gate film on the barrier layer 30 , and the gate film is patterned to form the gate 70 .

[0093] For example, the gate voltage applied to the gate 70 depletes the two-dimensional electron gas at the interface between the barrier layer 30 and the channel layer 20 and generates holes at the interface, thereby turning on the channel layer 20 and opening the semiconductor device 100 .

[0094] The method for preparing the semiconductor device 100 provided in the embodiment of the present disclosure forms a channel layer 20 and a barrier layer 30 on a substrate 10, wherein the channel layer 20 includes a first sub-portion 21 and a second sub-portion 22, wherein a surface of the first sub-portion 21 away from the substrate 10 is higher than a surface of the second sub-portion 22 away from the substrate 10, and the second sub-portion 22 is located on two opposite sides of the first sub-portion 21, and the barrier layer 30 is located on the first sub-portion 21. A P-type material layer 40 is formed on the second sub-portion 22, so that the P-type material layer 40 contacts the side of the first sub-portion 21 and the side of the barrier layer 30, and a gate 70 is formed on the barrier layer 30, so that under the control of the gate voltage, the holes provided by the P-type material layer 40 can be connected with the holes at the connection interface between the barrier layer 30 and the first sub-portion 21, so that the formed semiconductor device 100 is a normally-off enhancement-mode power device.

[0095] Compared with the preparation method of the semiconductor device in the above-mentioned possible implementation, the preparation method provided by the present disclosure does not need to prepare the grooves with relatively high process difficulty, and does not need to control the depth of the grooves. It only needs to form a barrier layer 30 and a channel layer 20 with simple structures. The preparation process of the barrier layer 30 and the channel layer 20 is relatively simple, the thickness of the barrier layer 30 and the channel layer 20 is easy to control, and the process controllability and process stability of preparing the barrier layer 30 and the channel layer 20 are high, thereby reducing the difficulty of preparing the semiconductor device 100. It can also make the size accuracy of the prepared barrier layer 30 higher, so that the threshold voltage of the semiconductor device 100 can be adjusted according to actual needs, and the absolute value of the threshold voltage of the semiconductor device 100 can be adjusted to be smaller, so that the switch of the semiconductor device 100 is more sensitive, which is conducive to improving the performance of the semiconductor device 100.

[0096] In addition, compared with the preparation method of the semiconductor device in the above-mentioned possible implementation mode, in the preparation method provided by the present invention, the surface of the first sub-portion 21 away from the substrate 10 is not etched, thereby avoiding etching damage to the surface of the first sub-portion 21 away from the substrate 10, thereby avoiding affecting the hole mobility at the connection interface between the first sub-portion 21 and the barrier layer 30, thereby ensuring that the hole mobility is high, making the channel resistance (the channel resistance here refers to the resistance between the source and the drain) small, which is beneficial to increase the output current of the semiconductor device 100.

[0097] In some embodiments, the barrier layer 30 has a thickness ranging from 3 nm to 40 nm.

[0098] Further, the thickness of the barrier layer 30 may range from 3 nm to 10 nm, from 10 nm to 21 nm, from 21 nm to 30 nm, from 30 nm to 40 nm, or from 15 nm to 40 nm.

[0099] For example, the thickness of the barrier layer 30 may be 3 nm, 10 nm, 15 nm, 21 nm, 30 nm, or 40 nm.

[0100] The thickness of the barrier layer 30 can adjust the threshold voltage of the semiconductor device 100. By setting the thickness of the barrier layer 30 within the above range, the absolute value of the threshold voltage of the semiconductor device 100 can be made smaller, and the semiconductor device 100 can be turned on by applying a gate voltage with a smaller absolute value, thereby making the switch of the semiconductor device 100 more sensitive and improving the performance of the semiconductor device 100.

[0101] For example, in the semiconductor device 100 provided in the present disclosure, the absolute value of the threshold voltage of the semiconductor device 100 with the barrier layer 30 having a thickness of 3 nm is smaller than the absolute value of the threshold voltage of the semiconductor device 100 with the barrier layer 30 having a thickness of 40 nm.

[0102] In some examples, the barrier layer 30 may be a single-layer structure or a multi-layer structure.

[0103] Exemplarily, the barrier layer 30 includes at least a first sub-layer and a second sub-layer which are stacked. The material of the first sub-layer is different from the material of the second sub-layer.

[0104] Therefore, the multi-layer barrier layer 30 can be used to adjust the threshold voltage of the semiconductor device 100 so that the absolute value of the threshold voltage of the semiconductor device 100 is smaller, thereby further improving the switching sensitivity of the semiconductor device 100 and improving the performance of the semiconductor device 100.

[0105] For example, the barrier layer 30 includes a first sublayer and a second sublayer stacked in layers. The material of the first sublayer may be AlN, and the material of the second sublayer may be Al. 0.25 Ga 0.75 N.

[0106] For another example, the barrier layer 30 includes a first sublayer, a second sublayer, and a third sublayer that are stacked, wherein the material of the first sublayer, the material of the second sublayer, and the material of the third sublayer are different.

[0107] In some embodiments, in the above A100 , a channel layer 20 and a barrier layer 30 are formed on a substrate 10 , including: A110 ˜ A130 .

[0108] A110, such as Figure 5 As shown in (a), a channel film 23 and a barrier film 31 are sequentially formed on a substrate 10.

[0109] Exemplarily, the channel film 23 and the barrier film 31 are heteroepitaxially grown on the substrate 10 by using a chemical vapor deposition process.

[0110] For example, a channel layer material is deposited on the substrate 10 to form the channel film 23 , and a barrier layer 30 material is deposited on the channel film 23 to form the barrier film 31 .

[0111] For another example, a channel layer material is deposited on the substrate 10 to form a channel film 23, a barrier layer material is deposited on the channel film 23 to form a barrier film 31, a cap layer material is deposited on the barrier film 31 to form a cap layer, and then the cap layer is removed. The material of the cap layer can be P-type doped gallium nitride.

[0112] A120, such as Figure 5 (b) and Figure 5 As shown in (c), a mask pattern 90 is formed on the barrier thin film 31, and the mask pattern 90 covers the barrier layer 30 to be formed and the first sub-portion 21 to be formed.

[0113] Exemplarily, a sputtering process or a deposition process is used to form a mask layer on the barrier film 31 , and the mask layer may be a hard mask. Then, an etching process is used to etch the mask layer to form a mask pattern 90 .

[0114] For example, the material of the mask pattern 90 may be silicon oxide (SiOx) or silicon nitride (SiNx).

[0115] A130, such as Figure 5 (b) and Figure 5 As shown in (c), the portion of the barrier film 31 not covered by the mask pattern 90 is removed, the portion of the channel film 23 covered by the mask pattern 90 is retained, and the portion of the channel film 23 not covered by the mask pattern 90 is thinned to obtain the barrier layer 30, the first sub-portion 21 and the second sub-portion 22.

[0116] For example, the orthographic projection of the barrier layer 30 on the substrate 10 coincides with the orthographic projection of the mask pattern 90 on the substrate 10 and coincides with the orthographic projection of the first sub-portion 21 on the substrate 10. The orthographic projection of the barrier layer 30 on the substrate 10 does not overlap with the orthographic projection of the second sub-portion 22 on the substrate 10.

[0117] For example, an etching process may be used to remove the portion of the barrier film 31 not covered by the mask pattern 90 and to thin the portion of the channel film 23 not covered by the mask pattern 90 .

[0118] The above preparation method can control the thickness of the barrier layer 30 formed by controlling the thickness of the barrier film 31 formed by deposition, so that the dimensional accuracy of the barrier layer 30 formed is high, thereby making the absolute value of the threshold voltage of the formed semiconductor device 100 small. In addition, the above embodiment of the present disclosure does not need to prepare grooves, nor does it need to control the thickness of the barrier layer 30 through an etching process, which reduces the difficulty of preparing the semiconductor device 100, and can also avoid the damage that the etching process may cause to the barrier layer 30 and the channel layer 20 (here the channel layer 20 refers to the first sub-portion 21 of the channel layer 20), ensuring the structural integrity of the barrier layer 30 and the channel layer 20, avoiding the influence of etching damage on the hole mobility at the connection interface between the barrier layer 30 and the first sub-portion 21, which is conducive to reducing the channel resistance and improving the output current of the semiconductor device 100.

[0119] There are a variety of methods for forming the source 50 and the drain 60 on the P-type material layer 40 , which can be selected according to actual conditions, and the embodiments of the present disclosure are not limited thereto.

[0120] In some embodiments, in the above A300 , a source 50 and a drain 60 are formed on the P-type material layer 40 , including: A310 ˜ A320 .

[0121] A310, such as Figure 7 As shown in (a), a conductive film 51 is formed on the mask pattern 90 and the P-type material layer 40 .

[0122] Illustratively, the conductive film 51 may be formed by a sputtering process.

[0123] For example, the conductive film 51 covers the surface of the mask pattern 90 away from the substrate 10 , and covers the surface of the P-type material layer 40 away from the substrate 10 .

[0124] A320, such as Figure 7 (a) and Figure 7 As shown in (b), the mask pattern 90 is removed, and the portion of the conductive film 51 corresponding to the mask pattern 90 is removed, and the portion of the conductive film 51 not corresponding to the mask pattern 90 is retained to form the source 50 and the drain 60. The side of the source 50 close to the drain 60 is in the same plane as the side of the barrier layer 30 close to the source 50. The side of the drain 60 close to the source 50 is in the same plane as the side of the barrier layer 30 close to the drain 60.

[0125] Exemplarily, a stripping process or a chemical mechanical polishing (CMP) process can be used to simultaneously remove the mask pattern 90 and the portion of the conductive film 51 corresponding to the mask pattern 90 , thereby simultaneously completing the removal of the mask pattern 90 and the preparation of the source 50 and the drain 60 .

[0126] For example, the orthographic projections of the formed source 50 and drain 60 on the substrate 10 do not overlap with the orthographic projection of the mask pattern 90 on the substrate 10 , the orthographic projection of the source 50 on the substrate 10 coincides with the orthographic projection of the first part 41 on the substrate 10 , and the orthographic projection of 60 on the substrate 10 coincides with the orthographic projection of the second part 42 on the substrate 10 .

[0127] Therefore, in one manufacturing process, not only the mask pattern 90 is removed, but also the source 50 and the drain 60 are manufactured, thereby simplifying the manufacturing process of the semiconductor device 100 .

[0128] Furthermore, since the side of the source 50 close to the drain 60 is in the same plane as the side of the barrier layer 30 close to the source 50, and the side of the drain 60 close to the source 50 is in the same plane as the side of the barrier layer 30 close to the drain 60, the relative positions of the drain 60, the source 50 and the barrier layer 30 in the semiconductor device 100 are relatively compact (refer to Figure 7 As shown in (d) in the figure, the size of the formed semiconductor device 100 is smaller, which is beneficial to improving the integration of the electronic device 1000 and reducing the preparation cost of the semiconductor device 100.

[0129] Understandably, Figure 7 Middle (a)~ Figure 7 The semiconductor device 100 formed by the method for preparing the semiconductor device 100 shown in (d) is a semiconductor device with a self-aligned structure.

[0130] In some other embodiments, in the above A300 , a source 50 and a drain 60 are formed on the P-type material layer 40 , including: A350 ˜ A360 .

[0131] A350, such as Fig. 9 As shown in (a), a conductive film 51 is formed on the mask pattern 90 and the P-type material layer 40 .

[0132] Illustratively, the conductive film 51 may be formed by a sputtering process.

[0133] A360, such as Fig. 9As shown in (b), the conductive film 51 is patterned to form a source electrode 50 and a drain electrode 60. Along the arrangement direction of the source electrode 50, the first sub-portion 21 and the drain electrode 60, there is a gap between the source electrode 50 and the barrier layer 30, and there is a gap between the drain electrode 60 and the barrier layer 30.

[0134] For example, the conductive film 51 may be etched to expose the surface of the mask pattern 90 away from the substrate 10 and a portion of the surface of the P-type material layer 40 away from the substrate 10 to form the source 50 and the drain 60 spaced apart.

[0135] For example, the orthographic projection of the source 50 on the substrate 10 is located within the orthographic projection range of the first portion 41 of the P-type material layer 40 on the substrate 10, and the orthographic projection of the drain 60 on the substrate 10 is located within the orthographic projection range of the second portion 42 on the substrate 10. The orthographic projections of the source 50 and the drain 60 on the substrate 10 do not overlap with the orthographic projection of the mask pattern 90 on the substrate 10.

[0136] By adopting the above-mentioned preparation method, the spacing between the source electrode 50 and the drain electrode 60 and the gate electrode 70 formed subsequently can be larger, so that the source electrode 50 and the gate electrode 70 are not likely to overlap in the thickness direction of the substrate 10, and the drain electrode 60 and the gate electrode 70 are not likely to overlap in the thickness direction of the substrate 10, thereby avoiding breakdown between the source electrode 50 and the gate electrode 70, and avoiding breakdown between the drain electrode 60 and the gate electrode 70, so that the formed semiconductor device 100 has a higher breakdown voltage, thereby improving the stability of the semiconductor device 100, and facilitating the integration of the semiconductor device 100 with other semiconductor devices on the same chip.

[0137] Understandably, Fig. 9 Middle (a)~ Fig. 9 The semiconductor device 100 formed by the method for preparing the semiconductor device 100 shown in (e) is a semiconductor device with a non-self-aligned structure.

[0138] In some examples, in the above A400, before forming the gate 70 on the barrier layer 30, as Fig. 9 (b) and Fig. 9 As shown in (c), the preparation method further includes: removing the mask pattern 90.

[0139] For example, an etching process may be used to remove the mask pattern 90 to expose the surface of the barrier layer 30 away from the substrate 10 .

[0140] In some embodiments, in A400, before forming the gate 70 on the barrier layer 30, as shown in FIG. Figure 7 Middle (c), Figure 8 Middle (a), Fig. 9 Middle (d) and Fig.10 As shown in (a), the preparation method further includes: forming a dielectric layer 80 on the barrier layer 30 , and a portion of the dielectric layer 80 is also overlapped on the source 50 and the drain 60 .

[0141] The dielectric layer 80 is used to achieve isolation and insulation. For example, the dielectric layer 80 can be formed by a deposition process.

[0142] For example, the material of the dielectric layer 80 may include: Al2O3, SiN x , SiO2, NiO, Ga x O 1-x N, Al x Si 1-x O or Al x Si 1-x N.

[0143] For example, Figure 7 As shown in (c), the dielectric layer 80 covers the surface of the barrier layer 30 away from the substrate 10 , and the dielectric layer 80 also covers a portion of the surface of the source 50 away from the substrate 10 , and a portion of the surface of the drain 60 away from the substrate 10 .

[0144] And combined Figure 7 In (d), after the gate 70 is formed, the orthographic projection of the gate 70 on the substrate 10 is within the orthographic projection range of the dielectric layer 80 on the substrate 10. The orthographic projection of the gate 70 on the substrate 10 partially overlaps with the orthographic projection of the source 50 on the substrate 10. The orthographic projection of the gate 70 on the substrate 10 partially overlaps with the orthographic projection of the drain 60 on the substrate 10. The orthographic projection of the barrier layer 30 on the substrate 10 is within the orthographic projection range of the gate 70 on the substrate 10.

[0145] For example, Fig. 9 As shown in (d), the dielectric layer 80 covers the surface of the barrier layer 30 away from the substrate 10, and the dielectric layer 80 also covers a portion of the surface of the source 50 away from the substrate 10, a portion of the surface of the drain 60 away from the substrate 10, and a portion of the surface of the P-type material layer 40 away from the substrate 10.

[0146] And combined Fig. 9 In (e), after the gate 70 is formed, the orthographic projection of the gate 70 on the substrate 10 is within the orthographic projection range of the dielectric layer 80 on the substrate 10. The orthographic projection of the gate 70 on the substrate 10 partially overlaps with the orthographic projection of the P-type material layer 40 on the substrate 10. The orthographic projection of the barrier layer 30 on the substrate 10 is within the orthographic projection range of the gate 70 on the substrate 10.

[0147] In some examples, such as Figure 8 (a) and Fig.10As shown in (a), the dielectric layer 80 includes an opening 81 , and the opening 81 exposes a portion of the surface of the barrier layer 30 away from the substrate 10 . The gate 70 is connected to the barrier layer 30 through the opening 81 .

[0148] For example, Figure 8 As shown in (a), the dielectric layer 80 covers a portion of the surface of the barrier layer 30 away from the substrate 10 , and the dielectric layer 80 also covers a portion of the surface of the source 50 away from the substrate 10 , and a portion of the surface of the drain 60 away from the substrate 10 .

[0149] And combined Figure 8 In (b), after the gate 70 is formed, the orthographic projection of the gate 70 on the substrate 10 partially overlaps with the orthographic projection of the dielectric layer 80 on the substrate 10. The orthographic projection of the gate 70 on the substrate 10 partially overlaps with the orthographic projection of the drain 60 on the substrate 10, and the orthographic projection of the gate 70 on the substrate 10 partially overlaps with the orthographic projection of the source 50 on the substrate 10. The orthographic projection of the barrier layer 30 on the substrate 10 is located within the orthographic projection range of the gate 70 on the substrate 10.

[0150] For example, Fig.10 As shown in (a), the dielectric layer 80 covers a portion of the surface of the barrier layer 30 away from the substrate 10. The dielectric layer 80 also covers a portion of the surface of the source 50 away from the substrate 10, a portion of the surface of the drain 60 away from the substrate 10, and a portion of the surface of the P-type material layer 40 away from the substrate 10.

[0151] And combined Fig.10 In (b), after the gate 70 is formed, the orthographic projection of the gate 70 on the substrate 10 partially overlaps with the orthographic projection of the dielectric layer 80 on the substrate 10. The orthographic projection of the gate 70 on the substrate 10 partially overlaps with the orthographic projection of the P-type material layer 40 on the substrate 10. The orthographic projection of the barrier layer 30 on the substrate 10 is located within the orthographic projection range of the gate 70 on the substrate 10.

[0152] Therefore, the gate 70 has a more sensitive control over holes, and the semiconductor device 100 is more sensitive to opening, which is beneficial to improving the performance of the semiconductor device 100 .

[0153] For example, Figure 8 (a) and Fig.10 As shown in (a), when the dielectric layer 80 includes an opening 81, the above-mentioned preparation method for forming the dielectric layer 80 on the barrier layer 30 includes: forming a dielectric film on the barrier layer 30, and etching the dielectric film to form the dielectric layer 80 including the opening 81.

[0154] In some examples, before forming the dielectric layer 80 on the barrier layer 30, the preparation method further includes: forming a dielectric insertion layer on the barrier layer 30. The dielectric layer 80 is formed on the dielectric insertion layer.

[0155] Exemplarily, the orthographic projection of the dielectric insertion layer on the substrate 10 coincides with the orthographic projection of the dielectric layer 80 on the substrate 10 .

[0156] The material of the dielectric insertion layer can be a single crystal material or a material close to a single crystal, such as AlN, SiN x or GaO x .

[0157] The thickness of the dielectric insertion layer ranges from 0 nm to 5 nm.

[0158] For example, the thickness of the dielectric insertion layer may be 1 nm, 2 nm, 3 nm, 4 nm, or 5 nm.

[0159] Exemplarily, the dielectric insertion layer can adjust the interface state density between the gate 70 and the barrier layer 30 , regulate the charge on the interface, and facilitate the gate 70 to control the conduction of the channel layer 20 , thereby facilitating improving the performance of the semiconductor device 100 .

[0160] The embodiment of the present disclosure further provides a semiconductor device 100. The semiconductor device 100 is formed by using the manufacturing method described in any of the above embodiments. Fig.11 As shown, the semiconductor device 100 includes: a substrate 10 , a channel layer 20 , a barrier layer 30 , a P-type material layer 40 , a source 50 , a drain 60 and a gate 70 .

[0161] Regarding the material of the substrate 10 and the material of the channel layer 20 , reference may be made to the description of some of the above embodiments in the present disclosure.

[0162] For example, Fig.11 As shown, the channel layer 20 includes a first sub-portion 21 and a second sub-portion 22 connected to the first sub-portion 21. For example, the second sub-portion 22 is composed of two spaced-apart parts, and the two parts are respectively connected to opposite sides of the first sub-portion 21. The second sub-portion 22 is located on opposite sides of the first sub-portion 21. For example, the first sub-portion 21 and the second sub-portion 22 of the channel layer 20 are an integrated structure.

[0163] Exemplarily, relative to the substrate 10 , a surface of the first sub-portion 21 away from the substrate 10 is higher than a surface of the second sub-portion 22 away from the substrate 10 .

[0164] For example, the substrate 10 is a plate-like structure with a flat surface, the thickness of the first sub-portion 21 is greater than the thickness of the second sub-portion 22 , and the first sub-portion 21 protrudes in a direction away from the substrate 10 relative to the second sub-portion 22 .

[0165] The barrier layer 30 is located on a side of the first sub-portion 21 away from the substrate 10. For the material of the barrier layer 30, reference may be made to the description of some of the above embodiments in the present disclosure.

[0166] For example, Fig.11 As shown, the P-type material layer 40 is located on a side of the second sub-portion 22 away from the substrate 10 , and is located on two opposite sides of the first sub-portion 21 .

[0167] For example, the P-type material layer 40 includes a first portion and a second portion that are spaced apart. The first portion and the second portion are located at opposite sides of the first sub-portion 21. For the material of the P-type material layer 40, reference may be made to the description of some of the above embodiments in the present disclosure.

[0168] In some examples, such as Fig.11 As shown, the P-type material layer 40 contacts the side surface of the first sub-portion 21 and contacts at least a portion of the side surface of the barrier layer 30 .

[0169] For example, the P-type material layer 40 contacts the side surface of the first sub-portion 21 and contacts the side surface of the barrier layer 30 .

[0170] Thus, the connection interface between the channel layer 20 and the barrier layer 30 can be connected to the P-type material layer 40 , ensuring that the holes at the interface can be conducted with the holes in the P-type material layer 40 , thereby achieving conduction of the semiconductor device 100 .

[0171] The source 50 and the drain 60 are located on a side of the P-type material layer 40 away from the substrate 10 , and are respectively located on two opposite sides of the first sub-portion 21 .

[0172] For example, the source 50 is located on a first portion of the P-type material layer 40 , and the drain 60 is located on a second portion of the P-type material layer 40 .

[0173] like Fig.11 As shown, the gate 70 is located on a side of the barrier layer 30 away from the substrate 10 .

[0174] Exemplarily, when the gate 70 does not provide a voltage, a polarization effect is generated at the interface between the channel layer 20 and the barrier layer 30 due to the presence of a heterojunction, and the polarization effect induces the channel layer 20 to form a two-dimensional electron gas at the interface close to the barrier layer 30. When the gate 70 provides a voltage (for example, the voltage is -5V), the two-dimensional electron gas at the interface between the channel layer 20 and the barrier layer 30 is consumed and holes are generated, and the holes are connected with the holes from the source, the P-type material layer and the drain, so that the semiconductor device 100 is turned on.

[0175] The semiconductor device 100 provided by the embodiment of the present disclosure is provided with a channel layer 20 and a barrier layer 30 on a substrate 10, wherein the channel layer 20 includes a first sub-portion 21 and a second sub-portion 22, wherein a surface of the first sub-portion 21 away from the substrate 10 is higher than a surface of the second sub-portion 22 away from the substrate 10, and the second sub-portion 22 is located on two opposite sides of the first sub-portion 21, and the barrier layer 30 is provided on the first sub-portion 21, and the P-type material layer 40 is provided on the second sub-portion 22, so that the P-type material layer 40 is in contact with the side surface of the first sub-portion 21 and the side surface of the barrier layer 30, and a gate 70 is provided on the barrier layer 30, thereby, under the control of the voltage of the gate 70, the holes provided by the P-type material layer 40 can be conducted through the connection interface between the barrier layer 30 and the first sub-portion 21, so that the semiconductor device 100 is an enhanced power device using hole conduction.

[0176] Moreover, in the semiconductor device 100 provided by the present disclosure, there is no need to prepare grooves with relatively high process difficulty, and there is no need to control the depth of the grooves. It is only necessary to form a barrier layer 30 and a channel layer 20 with simple structures, and the preparation process of the barrier layer 30 and the channel layer 20 is relatively simple, the thickness of the barrier layer 30 and the channel layer 20 is easy to control, and the process controllability and process stability of preparing the barrier layer 30 and the channel layer 20 are high, thereby reducing the difficulty of preparing the semiconductor device 100. It is also possible to make the size accuracy of the prepared barrier layer 30 higher, so that the output current of the semiconductor device 100 can be adjusted according to actual needs, thereby improving the performance of the semiconductor device 100.

[0177] In addition, in the semiconductor device 100 provided by the present invention, the surface of the first sub-portion 21 away from the substrate 10 has not been etched, thereby avoiding etching damage to the surface of the first sub-portion 21 away from the substrate 10, thereby avoiding affecting the hole mobility at the connection interface between the first sub-portion 21 and the barrier layer 30, thereby ensuring that the hole mobility is high, making the channel resistance (the channel resistance here refers to the resistance between the source and the drain) small, which is beneficial to increasing the output current of the semiconductor device 100.

[0178] In some embodiments, the barrier layer 30 has a thickness ranging from 3 nm to 40 nm.

[0179] Further, the thickness of the barrier layer 30 may range from 3 nm to 10 nm, from 10 nm to 21 nm, from 21 nm to 30 nm, from 30 nm to 40 nm, or from 15 nm to 40 nm.

[0180] For example, the thickness of the barrier layer 30 may be 3 nm, 10 nm, 15 nm, 21 nm, 30 nm, or 40 nm.

[0181] By setting the thickness of the barrier layer 30 within the above range, the absolute value of the threshold voltage of the semiconductor device 100 can be made smaller, and the semiconductor device 100 can be turned on by applying a gate voltage with a smaller absolute value, thereby making the switch of the semiconductor device 100 more sensitive and improving the performance of the semiconductor device 100.

[0182] In some examples, the barrier layer 30 may be a single-layer structure or a multi-layer structure. The structure of the barrier layer 30 may refer to the description of some of the above embodiments of the present disclosure, and will not be repeated here.

[0183] In some embodiments, Fig.11 As shown, the orthographic projection of the barrier layer 30 on the substrate 10 coincides with the orthographic projection of the first sub-portion 21 on the substrate 10 .

[0184] For example, the boundary line of the orthographic projection of the barrier layer 30 on the substrate 10 coincides with the boundary line of the orthographic projection of the first sub-portion 21 on the substrate 10. The side surface of the barrier layer 30 is flush with the side surface of the first sub-portion 21.

[0185] Therefore, the same mask pattern (for example, the mask pattern 90 in the above embodiment) can be used as a mask to prepare the barrier layer 30 and the first sub-portion 21, thereby reducing the number of mask patterns used in the preparation process, thereby simplifying the preparation process of the barrier layer 30 and the first sub-portion 21, and simplifying the preparation process of the semiconductor device 100.

[0186] In some embodiments, Fig.11 and Fig.13 As shown, the orthographic projection of the barrier layer 30 on the substrate 10 is located within the orthographic projection range of the gate 70 on the substrate 10 .

[0187] For example, the boundary line of the orthographic projection of the barrier layer 30 on the substrate 10 is located within the boundary line of the orthographic projection of the gate 70 on the substrate 10, and the distance between the boundary line of the orthographic projection of the barrier layer 30 on the substrate 10 and the boundary line of the orthographic projection of the gate 70 on the substrate 10 is greater than or equal to 0.

[0188] The above-mentioned arrangement enables the barrier layer 30 to be completely covered by the gate 70, so that the gate 70 can control the depletion of the two-dimensional electron gas at the interface connecting the barrier layer 30 and the channel layer 20 and control the generation of holes under the action of the gate voltage, thereby achieving conduction between the holes and the holes provided by the P-type material layer 40, thereby ensuring that the semiconductor device 100 is turned on under the control of the gate voltage provided by the gate 70, ensuring the conduction of the semiconductor device 100.

[0189] There are many ways to configure the structure of the source 50 , the drain 60 , the barrier layer 30 and the gate 70 of the semiconductor device 100 , which can be selected and configured according to actual conditions, and the embodiments of the present disclosure are not limited to this.

[0190] In some embodiments, Fig.11 and Fig.12 As shown, the side of the source 50 close to the drain 60 is in the same plane as the side of the barrier layer 30 close to the source 50. The side of the drain 60 close to the source 50 is in the same plane as the side of the barrier layer 30 close to the drain 60.

[0191] Exemplarily, the source 50 has a top surface away from the substrate 10, a bottom surface close to the substrate 10, and a side surface connecting the top surface and the bottom surface. The side surface of the source 50 close to the drain 60 refers to the side surface of the source 50 close to the drain 60.

[0192] Thus, the distance between the source 50 and the drain 60 can be made equal or approximately equal to the size of the first sub-portion 21 in the direction from the source 50 to the drain 60, so that the distance between the source 50 and the drain 60 is smaller, the resistance between the source 50 and the drain 60 is smaller, the output current of the semiconductor device 100 is larger, and the overall size of the semiconductor device 100 can be made smaller, which is conducive to the miniaturization design of the semiconductor device 100 and electronic equipment.

[0193] Exemplarily, the gate 70 also covers a portion of the source 50 and a portion of the drain 60 .

[0194] Thus, the orthographic projection area of ​​the gate 70 on the substrate 10 can be relatively large, thereby ensuring the control of the gate 70 over the channel layer 20 and ensuring that the semiconductor device 100 is an enhancement-mode power device.

[0195] In other embodiments, Fig.13 and Fig.14 As shown, the orthographic projection of the gate 70 on the substrate 10 does not overlap with the orthographic projection of the source 50 on the substrate 10 , and the orthographic projection of the gate 70 on the substrate 10 does not overlap with the orthographic projection of the drain 60 on the substrate 10 .

[0196] Exemplarily, in the thickness direction of the substrate 10 , the gate 70 and the source 50 are staggered, and the gate 70 and the drain 60 are staggered.

[0197] Therefore, breakdown between the gate 70 and the source 50 and the drain 60 can be avoided, so that the breakdown voltage of the semiconductor device 100 is higher, which is beneficial to improving the performance of the semiconductor device 100 .

[0198] In some examples, such as Fig.13 and Fig.14 As shown, along the arrangement direction of the source electrode 50 , the first sub-portion 21 and the drain electrode 60 , there is a gap between the source electrode 50 and the barrier layer 30 , and there is a gap between the drain electrode 60 and the barrier layer 30 .

[0199] Exemplarily, there is a gap between the side of the source 50 close to the drain 60 and the side of the barrier layer 30 close to the source 50. There is a gap between the side of the drain 60 close to the source 50 and the side of the barrier layer 30 close to the drain 60.

[0200] Exemplarily, the gate 70 also covers a portion of the P-type material layer 40 .

[0201] Thus, the distance between the source 50 and the drain 60 can be made larger than the dimension of the first sub-portion 21 in the direction from the source 50 to the drain 60, so that the distance between the source 50 and the drain 60 is larger, and the gate 70 has no overlap with the source 50 and the drain 60 in the thickness direction of the substrate 10, thereby avoiding breakdown between the source 50 and the gate 70, and avoiding breakdown between the drain 60 and the gate 70, so that the formed semiconductor device 100 has a higher breakdown voltage, thereby improving the stability of the semiconductor device 100, and facilitating the integration of the semiconductor device 100 with other semiconductor devices on the same chip.

[0202] In some embodiments, Figure 11 to Figure 14 As shown, the semiconductor device 100 further includes a dielectric layer 80 . The dielectric layer 80 is located between the barrier layer 30 and the gate 70 . For example, the dielectric layer 80 covers the surface of the barrier layer 30 away from the substrate 10 . The dielectric layer 80 also overlaps the source 50 and the drain 60 .

[0203] The dielectric layer 80 is used to achieve isolation and insulation. Fig.11 and Fig.13 As shown, the dielectric layer 80 isolates the barrier layer 30 from the gate 70. The material of the gate 70 can be a metal material, the material of the dielectric layer 80 is an insulating material, and the material of the barrier layer 30 is a semiconductor material. The gate 70, the dielectric layer 80 and the barrier layer 30 form a metal-insulator-semiconductor (MIS) structure.

[0204] For example, the material of the dielectric layer 80 may include: Al2O3, SiN x , SiO2, NiO, Ga x O 1-x N, Al x Si 1-x O or Al x Si 1-x N.

[0205] Exemplarily, the thickness of the dielectric layer 80 ranges from 5 nm to 40 nm.

[0206] For example, the thickness of the dielectric layer 80 may be 5 nm, 11 nm, 21 nm, 31 nm, 38 nm or 40 nm.

[0207] In some embodiments, Fig.12 and Fig.14 As shown, the dielectric layer 80 has an opening 81. The gate 70 is connected to the barrier layer 30 through the opening 81. The gate 70 and the barrier layer 30 may be in Schottky contact or ohmic contact.

[0208] For example, the opening 81 is directly opposite to the barrier layer 30 . The boundary line of the orthographic projection of the opening 81 on the substrate 10 is located within the boundary line of the orthographic projection of the barrier layer 30 on the substrate 10 .

[0209] Therefore, it is easy to realize the control of the gate 70 over the holes at the connection interface between the barrier layer 30 and the channel layer 20 , so that the semiconductor device 100 is opened more sensitively, which is beneficial to improving the performance of the semiconductor device 100 .

[0210] In some examples, the semiconductor device 100 further includes a dielectric insertion layer. The dielectric insertion layer is located between the dielectric layer 80 and the gate 70. The dielectric insertion layer is stacked on the dielectric layer 80, and the orthographic projection of the dielectric insertion layer on the substrate 10 coincides with the orthographic projection of the dielectric layer 80 on the substrate 10.

[0211] Exemplarily, the dielectric insertion layer can adjust the interface state density between the gate 70 and the barrier layer 30 , regulate the charge on the interface, and facilitate the gate 70 to control the conduction of the channel layer 20 , thereby facilitating improving the performance of the semiconductor device 100 .

[0212] The material and thickness of the dielectric insertion layer may refer to the description in some of the above embodiments of the present disclosure.

[0213] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; a channel layer, located at one side of the substrate; the channel layer comprises a first sub-portion and a second sub-portion connected to the first sub-portion, the second sub-portion being located at two opposite sides of the first sub-portion; relative to the substrate, a surface of the first sub-portion away from the substrate is higher than a surface of the second sub-portion away from the substrate; a barrier layer, located at a side of the first sub-portion away from the substrate; A P-type material layer is located on a side of the second sub-section away from the substrate and is respectively located on two opposite sides of the first sub-section; the P-type material layer is in contact with a side surface of the first sub-section and is in contact with at least a portion of a side surface of the barrier layer; a source electrode and a drain electrode, located on a side of the P-type material layer away from the substrate and respectively located on two opposite sides of the first sub-portion; The gate is located on a side of the barrier layer away from the substrate.

2. The semiconductor device according to claim 1, wherein: The thickness of the barrier layer is in the range of 3 nm to 40 nm.

3. The semiconductor device according to claim 1, wherein: The barrier layer at least includes a first sublayer and a second sublayer which are stacked; the material of the first sublayer is different from the material of the second sublayer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The orthographic projection of the barrier layer on the substrate coincides with the orthographic projection of the first sub-portion on the substrate.

5. The semiconductor device according to claim 1, wherein: The orthographic projection of the barrier layer on the substrate is located within the orthographic projection range of the gate on the substrate.

6. The semiconductor device according to claim 5, characterized in that The side surface of the source electrode close to the drain electrode and the side surface of the barrier layer close to the source electrode are in the same plane; the side surface of the drain electrode close to the source electrode and the side surface of the barrier layer close to the drain electrode are in the same plane; The gate also covers a portion of the source and a portion of the drain.

7. The semiconductor device according to claim 5, characterized in that Along the arrangement direction of the source electrode, the first sub-portion and the drain electrode, there is a gap between the source electrode and the barrier layer, and there is a gap between the drain electrode and the barrier layer; The gate also covers a portion of the P-type material layer.

8. The semiconductor device according to claim 6 or 7, characterized in that: The semiconductor device further comprises a dielectric layer; The dielectric layer is located between the barrier layer and the gate, and the dielectric layer is also overlapped on the source and the drain.

9. The semiconductor device according to claim 8, characterized in that The dielectric layer has an opening; the gate is connected to the barrier layer through the opening.

10. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: A channel layer and a barrier layer are formed on a substrate; the channel layer includes a first sub-portion and a second sub-portion connected to the first sub-portion, and the second sub-portion is located on two opposite sides of the first sub-portion; relative to the substrate, a surface of the first sub-portion away from the substrate is higher than a surface of the second sub-portion away from the substrate; the barrier layer is located on a side of the first sub-portion away from the substrate; forming a P-type material layer on the second sub-section; the P-type material layer is respectively located on two opposite sides of the first sub-section; the P-type material layer is in contact with a side surface of the first sub-section and is in contact with at least a portion of a side surface of the barrier layer; forming a source electrode and a drain electrode on the P-type material layer; the source electrode and the drain electrode are respectively located at two opposite sides of the first sub-portion; A gate is formed on the barrier layer.

11. The preparation method according to claim 10, characterized in that: The step of forming a channel layer and a barrier layer on a substrate comprises: forming a channel film and a barrier film in sequence on the substrate; forming a mask pattern on the barrier film, wherein the mask pattern covers the barrier layer to be formed and the first sub-portion to be formed; The portion of the barrier film not covered by the mask pattern is removed, the portion of the channel film covered by the mask pattern is retained, and the portion of the channel film not covered by the mask pattern is thinned to obtain the barrier layer, the first sub-portion and the second sub-portion.

12. The preparation method according to claim 11, characterized in that: The forming of a source and a drain on the P-type material layer comprises: forming a conductive film on the mask pattern and the P-type material layer; The mask pattern and the portion of the conductive film corresponding to the mask pattern are removed, and the portion of the conductive film not corresponding to the mask pattern is retained to form the source and the drain; the side of the source electrode close to the drain electrode and the side of the barrier layer close to the source electrode are in the same plane; the side of the drain electrode close to the source electrode and the side of the barrier layer close to the drain electrode are in the same plane.

13. The preparation method according to claim 11, characterized in that: The forming of a source and a drain on the P-type material layer comprises: forming a conductive film on the mask pattern and the P-type material layer; The conductive film is patterned to form the source electrode and the drain electrode; along the arrangement direction of the source electrode, the first sub-portion and the drain electrode, there is a gap between the source electrode and the barrier layer, and there is a gap between the drain electrode and the barrier layer.

14. The preparation method according to claim 13, characterized in that: Before forming the gate on the barrier layer, the preparation method further includes: removing the mask pattern.

15. The preparation method according to claim 12 or 13, characterized in that: Before forming a gate on the barrier layer, the preparation method further comprises: A dielectric layer is formed on the barrier layer, and a portion of the dielectric layer is also overlapped on the source and the drain.

16. An electronic device, characterized in that: The invention comprises a semiconductor device as claimed in any one of claims 1 to 9, and a circuit board connected to the semiconductor device.

Images