Lateral high-voltage semiconductor device and method of forming lateral high-voltage semiconductor device

Abstract

A lateral high-voltage semiconductor device and a method of forming a lateral high-voltage semiconductor device are disclosed wherein the lateral high-voltage semiconductor device (1) comprises a semiconductor substrate (2) having a front side and a semiconductor element (10). The semiconductor element comprises a first semiconductor region (11) of a first conductivity type formed in the semiconductor substrate, a second semiconductor region (12) formed in the semiconductor substrate and spaced apart from the first semiconductor region (11) in a first lateral direction parallel to the front side, and an extension region (13) adjoining the second semiconductor region (12). A lateral high-voltage semiconductor device (1) is configured to control a load current between a first semiconductor region and a second semiconductor region. The extension region (13) extends along the front side of the semiconductor substrate and comprises at least one mesa (14) protruding at the front side (101) of the semiconductor substrate.

Description

Technical Field

[0001] The present disclosure relates to a lateral high voltage semiconductor device. More specifically, the lateral high voltage semiconductor device may be a lateral power device having a breakdown voltage of at least 80 V or even at least 300 V. Therefore, the present disclosure may relate to a gate driver including a high voltage domain and a low voltage domain. Background Art

[0002] HV (high voltage) semiconductor devices in CMOS (complementary metal oxide semiconductor) technology form or comprise an interface between standard CMOS devices (with input voltages below 5V on the one hand) and industrial or consumer circuits (with operating voltages above 30V on the other hand). Applications of such HV semiconductor devices exist in robotics, the automotive industry and as drivers for MEMS (micro-electromechanical systems). Typically, most signal processing is performed in CMOS components at low operating voltages, and only the output signal interface and / or the input signal interface operate at higher signal levels and / or require higher current drive and absorption capabilities. An example of such an HV semiconductor device is a gate driver circuit that enables a microcontroller or DSP (digital signal processor) to effectively switch on and off a power semiconductor switch. A signal containing information related to the operation of the power semiconductor switch can be fed to the CMOS component from the interface to the power semiconductor switch.

[0003] There is always a need to further improve data exchange between different parts of high voltage semiconductor devices, such as gate driver circuits, with little additional effort. Summary of the invention

[0004] The present invention relates to a lateral high-voltage semiconductor device, which comprises a semiconductor substrate having a front side and a semiconductor device. The semiconductor device comprises: a first semiconductor region of a first conductivity type formed in the semiconductor substrate, a second semiconductor region formed in the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region.

[0005] Embodiments of the present disclosure relate to a lateral high-voltage semiconductor device, the high-voltage semiconductor device comprising a semiconductor substrate having a front side and a semiconductor device region. The semiconductor element comprises: a first semiconductor region of a first conductivity type formed in the semiconductor substrate, a second semiconductor region formed in the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region, and wherein the extension region extends along the front side of the semiconductor substrate and comprises at least one mesa protruding at the front side of the semiconductor substrate.

[0006] Another embodiment of the present disclosure relates to a lateral high-voltage semiconductor device, including a semiconductor substrate having a front side and a semiconductor element. The semiconductor element includes: a first semiconductor region of a first conductivity type formed in the semiconductor substrate, a second semiconductor region spaced apart from the first semiconductor region in a first lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region. The high-voltage semiconductor device also includes: a first field plate structure electrically connected to the first semiconductor region, and a second field plate structure electrically connected to the second semiconductor region, wherein at least one of the first field plate structure and the second field plate structure includes a stack of at least three interconnected field plates on each, wherein at least one of the field plates in the stack includes polysilicon, and at least one of the field plates in the stack includes metal.

[0007] Another embodiment of the present disclosure relates to a lateral high-voltage semiconductor device, comprising: a semiconductor substrate having a front side and a semiconductor element, the semiconductor element comprising: a first semiconductor region of a first conductivity type formed in the semiconductor substrate, a second semiconductor region spaced apart from the first semiconductor region in a first lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region. The high-voltage semiconductor device also includes: a first field plate structure electrically connected to the first semiconductor region, a second field plate structure electrically connected to the second semiconductor region, a third field plate structure electrically connected to a first portion of the extension region, and a fourth field plate structure electrically connected to a second portion of the extension region, wherein the third field plate structure is connected to the first portion of the extension region at a side of the third field plate structure that is closer to the first semiconductor region than the centroid of the third field plate structure along the first lateral direction, and wherein the fourth field plate structure is connected to the second portion of the extension region at a side of the fourth field plate structure that is closer to the fourth semiconductor region than the centroid of the fourth field plate structure along the first lateral direction.

[0008] The at least one mesa protruding from the front side along the extension region and / or a corresponding field plate structure arranged along the extension region allows for improved electrical properties of the lateral high voltage semiconductor device.

[0009] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the figures of the accompanying drawings, the present disclosure is illustrated by way of example and not limitation, in which the same reference numerals denote similar or identical elements. The elements in the accompanying drawings do not necessarily correspond to each other in proportion. The features of the various examples shown may be combined unless they exclude each other.

[0011] Figure 1 A schematic top view of a power semiconductor device is shown.

[0012] Figure 2 A schematic cross section of a power semiconductor device is shown.

[0013] Figure 3 A schematic cross section of a power semiconductor device is shown.

[0014] Figure 4 A schematic cross section of a power semiconductor device is shown, and different examples of field plate structures are shown in more detail.

[0015] Figures 5 to 7 A further schematic cross section of an exemplary power semiconductor device is shown.

[0016] Figures 8 to 11 A more schematic cross-section of an example power semiconductor device in a transistor configuration is shown. DETAILED DESCRIPTION

[0017] Examples described herein provide implementations of lateral high voltage semiconductor devices. The lateral high voltage semiconductor devices may have a breakdown voltage of at least 80V or even at least 300V.

[0018] Embodiments of the present disclosure relate to a lateral high-voltage semiconductor device, the high-voltage semiconductor device comprising a semiconductor substrate having a front side and a semiconductor device region. The semiconductor element comprises a first semiconductor region of a first conductivity type, a second semiconductor region, and an extension region adjacent to the second semiconductor region, the first semiconductor region being formed in the semiconductor substrate, the second semiconductor region being formed in the semiconductor substrate and spaced apart from the first semiconductor region in a first lateral direction parallel to the front side, wherein the semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region, and wherein the extension region extends along the front side of the semiconductor substrate. In a cross section through the device, the lateral load current can flow parallel to the first lateral direction.

[0019] The first semiconductor region may be arranged close to or at the front side of the semiconductor substrate.The second semiconductor region may be arranged close to or at the front side of the semiconductor substrate.

[0020] The extension region may have the same conductivity type as the second semiconductor region, but has a lower doping concentration than the second region. The average doping concentration in the extension region may be at least one order of magnitude or at least two orders of magnitude or even at least three orders of magnitude smaller than that of the second semiconductor region. The extension region may be configured to take over the blocking voltage of the semiconductor element or the blocking voltage of the semiconductor device respectively in the blocking state of the semiconductor element. Therefore, in the blocking state, the breakdown voltage of the semiconductor device may drop by at least 50% at the extension region. The extension region may be configured to weaken the electric field between the first semiconductor region and the second semiconductor region. The extension region may extend mainly in a lateral direction parallel to the front side. Therefore, the main extension direction of the extension region may be parallel to the front side of the substrate. The extension region may be arranged close to or at the front side of the semiconductor substrate.

[0021] The semiconductor element can realize an electronic element or an electronic device. For example, the semiconductor element can be a transistor (e.g., a bipolar junction transistor BJT or a field effect transistor FET or a junction gate field effect transistor JFET), or a diode (e.g., a pn diode or a Zener diode), or an insulated gate bipolar transistor IGBT or a thyristor, etc.

[0022] In the case where the semiconductor element is a transistor, the semiconductor element may also include a body region of a second conductivity type that is laterally adjacent to the first semiconductor region and the extension region, and a gate structure configured to control a lateral load current between the first semiconductor region and the second semiconductor region. The gate region may be insulated from the body region. The gate region may be configured to form an inversion channel in the body region for controlling the lateral load current. The first semiconductor region may be a source or emitter region of a transistor, and the second semiconductor region may be a drain or collector region of a transistor. The first region may be adjacent to the body region. The body region may be adjacent to the extension region. The second semiconductor region may have a first conductivity type. The extension region may also have a first conductivity type.

[0023] In the case where the semiconductor element is a diode, the first semiconductor region may be an anode of the semiconductor element and the second semiconductor region may be a cathode of the semiconductor element. The first semiconductor region and the second semiconductor region may have opposite conductivity types. For example, the first semiconductor region may have a first conductivity type and the second semiconductor region may have a second conductivity type. The extension region may also have the second conductivity type and the first region may be adjacent to the extension region. A pn ​​junction may be formed between the first semiconductor region and the extension region.

[0024] According to some embodiments, a lateral high voltage semiconductor device includes at least one mesa protruding at a front side of a semiconductor substrate.

[0025] As an alternative or supplement to protruding at least one mesa, the lateral high-voltage semiconductor device may include a first field plate structure electrically connected to the first semiconductor region and a second field plate structure electrically connected to the second semiconductor region. The first field plate structure and / or the second field plate structure may include one, two, three or more field plates, wherein the field plates of the same field plate structure partially or completely overlap each other laterally.

[0026] According to some embodiments, at least one of the first field plate structure and the second field plate structure comprises a stack of at least three interconnected field plates on each, wherein at least one of the field plates in the stack comprises polysilicon, and at least one of the field plates in the stack comprises metal. Alternatively or additionally, the lateral high-voltage semiconductor device may further comprise: a third field plate structure electrically connected to the first portion of the extension region, and a fourth field plate structure electrically connected to the second portion of the extension region, wherein the third field plate structure is connected to the first portion of the extension region at a side of the third field plate structure that is closer to the first semiconductor region than the centroid of the third field plate structure along the first lateral direction, and wherein the fourth field plate structure is connected to the second portion of the extension region at a side of the fourth field plate structure that is closer to the fourth semiconductor region than the centroid of the fourth field plate structure along the first lateral direction. In other words, both the third field plate structure and the fourth field plate structure are connected asymmetrically relative to their lateral centers, wherein the protrusion of the corresponding field plate structure on the connection facing the lateral center of the extension region is greater than the protrusion of the corresponding field plate structure on the connection facing away from the lateral center of the extension region.

[0027] The first and second portions of the extension region to which the third field plate structure and the fourth field plate structure are connected may include corresponding mesas protruding at the front side of the semiconductor substrate. Thus, the third field plate structure may be connected to a first mesa of at least one mesa protruding at the front side of the semiconductor substrate. Similarly, the fourth field plate structure may be connected to a second mesa protruding at the front side of the semiconductor substrate. The field plate structure may be at least partially or completely arranged above at least one mesa. Each of the field plate structures may at least partially overlap the corresponding mesa to which it is connected laterally.

[0028] The third field plate structure and the fourth field plate structure may include a stack of at least three interconnected field plates on each. At least one of the field plates in the stack may include polysilicon, and at least one of the field plates in the stack may include metal.

[0029] In one or more of the field plate structures, for example the first field plate structure and the second field plate structure and / or the third field plate structure and the fourth field plate structure, the uppermost field plate of the at least three interconnected field plates may include metal or even consist of metal, and the lowermost field plate of the at least three interconnected field plates includes polysilicon. Each of the field plates of the respective field plate structures may partially or completely laterally overlap with all lower field plates of the same field plate structure. Thus, the uppermost field plate of the at least three interconnected field plates may completely laterally overlap with all field plates of the same field plate structure.

[0030] At least one mesa may be an elevated area compared to the surrounding portion of the extension area. In other words, at the mesa, the substrate may extend higher than the adjacent portion of the mesa. In the mesa area, the substrate may even have a greater thickness than the adjacent portion.

[0031] At least one mesa may be part of a field ring within the semiconductor substrate. In the case of two or more such mesas, each mesa may be part of a respective field ring. The field ring may extend below and / or beside the mesa. The field ring may be part of an extension region. In each field ring, the doping concentration may be higher than the surrounding portion of the extension region. The conductivity type of the doping within the field ring may be the same or opposite to the surrounding portion of the extension region. The field ring may be laterally centered around the respective mesa.

[0032] The lateral high-voltage semiconductor device may further include a first insulating layer laterally adjacent to the at least one mesa on both sides of the at least one mesa. In other words, a portion adjacent to the at least one mesa may be covered by the first insulating layer. The first insulating layer may have the same vertical extension as the at least one mesa and / or the top surface of the insulating layer and the top surface of the mesa form an at least substantially flat surface.

[0033] Portions of the insulating layer may be arranged between the at least one mesa and the first semiconductor region and between the at least one mesa and the second semiconductor region. Alternatively or additionally, portions of the insulating layer may be arranged between at least two separated mesas of the at least one mesa.

[0034] The lateral high voltage semiconductor device may further comprise at least one second insulating layer above the first insulating layer and at least one mesa. The second insulating layer above may comprise the same material or even the same composition as the first insulating layer. The first insulating layer and the second insulating layer may be manufactured in a single or separate manufacturing step. The first layer and / or the second layer may comprise an oxide, such as silicon oxide, or a nitride, such as silicon nitride. The first layer may, for example, comprise a thermally grown oxide, whereas the second layer may comprise a deposited oxide.

[0035] The corresponding electrical connection connecting one of the field plates to the semiconductor portion or semiconductor region can be configured to provide a low-ohmic contact between the field plate structure and the semiconductor portion or semiconductor region, or can include a pn junction or Schottky junction between the field plate structure and the mesa. The electrically connected area can be laterally constructed along the main extension direction of the corresponding mesa associated with the electrical connection. The main extension direction of the mesa can be parallel to the front side of the substrate and perpendicular to the current flowing between the first semiconductor region and the second semiconductor region (or an imaginary line between the first semiconductor region and the second semiconductor region). In a cross section through the device, the main extension direction of the mesa can be parallel to the front side and perpendicular to the first lateral direction. Therefore, in the section, the main extension direction of the mesa can be parallel to the second lateral direction.

[0036] The electrical connection may be configured to provide a low ohmic contact between the third and fourth field plate structures and the respective portion of the extension region.Alternatively or additionally, the electrical connection may include a rectifying junction, such as a pn junction or a Schottky junction, between the field plate structures and the respective portion of the extension region.

[0037] If the third and fourth field plate structures are connected to the respective mesas, the electrical connection may be configured to provide a low ohmic contact between the third and fourth field plate structures and the respective mesas. Alternatively or additionally, the electrical connection may include a rectifying junction, such as a pn junction or a Schottky junction, between the field plate structures and the respective mesas.

[0038] The field plate structures may be embedded in an insulating material, such as a second insulating layer. For example, each field plate structure may be completely surrounded by the insulating material, with only electrical connections being made through the insulating material.

[0039] Each rectifying junction may comprise a first portion and a second portion, the junction being formed at a junction between the portions, wherein the mesas are patterned laterally into the first portion and the second portion. In the case of a pn junction, the first portion may have a first conductivity type and the second portion may have a second conductivity type, wherein the pn junction is formed between the first portion and the second portion.

[0040] For example, the mesas are patterned along a first lateral direction, resulting in the bonding surface extending in a second lateral direction perpendicular to the first lateral direction. For example, the mesas are patterned along a second lateral direction, resulting in the bonding surface extending in the first lateral direction.

[0041] For example, in the case of an ohmic connection, the electrical connection may connect the mesa only asymmetrically, for example close to a lateral edge. For example, in the case of a pn junction, one of the parts of the junction may have a larger lateral extension than the other part. In this case, the smaller part of the junction may extend only close to a lateral edge of the mesa.

[0042] The lateral high voltage semiconductor device may further include a high voltage (HV) wiring layer above the at least one field plate structure. The high voltage wiring layer may be insulated from the at least one field plate structure by an insulating layer (eg, a second insulating layer).

[0043] For example, at least 50% or even at least 70% or even at least 85% of the semiconductor elements may be collectively laterally overlapped by the field plate structure. This may provide effective shielding of the semiconductor elements with respect to the HV wiring layer.

[0044] The semiconductor substrate may include a back side opposite to the front side. The lateral high-voltage semiconductor device may include a back side insulating layer arranged to the back side of the semiconductor substrate. The insulating layer may include an oxide layer. The thickness of the oxide layer may be 0.5 μm to 20 μm, preferably 2 μm to 20 μm. The oxide layer may be deposited on the back side. This allows for great scalability of the voltage level of the semiconductor device because the thickness of the deposited oxide can be easily selected according to the desired breakdown voltage. The combined thickness of the semiconductor substrate and the back side insulating layer may be in the range of 20.5 μm to 100 μm ((semiconductor substrate is 20 μm to 100 μm) + (insulating layer is 0.5 μm to 20 μm)).

[0045] The lateral high voltage semiconductor device may further include an additional silicon layer below the back side of the semiconductor substrate. For example, the additional silicon layer may be directly or indirectly attached to the back insulating layer. For example, one or more adhesion promoting layers may be arranged between the back insulating layer and the additional silicon layer. One or more adhesion promoting layers may include tape, such as DAF tape. For example, as an alternative or in addition to one or more adhesion promoting layers, one or more additional layers may be arranged between the back insulating layer and the additional silicon layer. One or more additional layers may include one or more dielectric layers and / or one or more metal layers.

[0046] The lateral high voltage semiconductor device may also include at least one insulating trench that electrically insulates the semiconductor element from another semiconductor element adjacent to the semiconductor element on the same semiconductor substrate. The insulating trench may include a trench electrode. The trench electrode may include doped or undoped polysilicon. The trench electrode may be floating or connected to any potential. At least one insulating trench may extend from the front side of the substrate to the back side, and at least one insulating trench may abut the back side insulating layer on the back side.

[0047] In the following detailed description, reference is made to the accompanying drawings, which form a part of the detailed description and in which specific embodiments in which the gate driver device can be practiced are shown by way of illustration. Other embodiments may be utilized and structural or logical changes, etc. may be made without departing from the scope of the present disclosure. For example, features shown or described for one embodiment may be used on other embodiments or used in combination with other embodiments to obtain another embodiment. The present disclosure is intended to include such modifications and variations. Examples are described using specific language, which should not be construed as limiting the scope of the appended claims. The drawings are not drawn to scale but are for illustration purposes only. If not otherwise specified, corresponding elements are designated by the same reference numerals in different drawings.

[0048] The terms "having", "containing", "including", "comprising", etc. are open ended, and these terms indicate the presence of stated structures, elements, or features, but do not preclude the presence of additional elements or features. Unless the context clearly indicates otherwise, the articles "a", "an", and "the" are intended to include the plural as well as the singular.

[0049] The term "electrically connected" describes a permanent low resistance ohmic connection between electrically connected elements, such as a direct contact between the relevant elements or a low resistance connection via metal and / or heavily doped semiconductor material.

[0050] The term "power semiconductor device" refers to a semiconductor device having a high voltage blocking capability of at least 30 V (e.g., 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV, or higher) and having a nominal on-state current or forward current of at least 200 mA (e.g., 1 A, 10 A, or greater).

[0051] Semiconductor elements can be configured as diodes, any kind of FET (MOSFET, JFET, etc.), bipolar transistors, IGBTs, etc. MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a voltage-controlled device and includes all types of IGFETs (Insulated Gate Field Effect Transistors) having a gate electrode based on doped semiconductor material and / or metal and having a gate dielectric made of oxide and / or dielectric material other than oxide.

[0052] Ohmic contact refers to a non-rectifying electrical junction between two conductors, such as a semiconductor material and a metal. According to Ohm's law, an ohmic contact has a linear or nearly linear IV curve in the first and third quadrants of a current-voltage (IV) diagram.

[0053] Ranges given for physical dimensions include the boundary values. For example, the range of parameter y from a to b is read as a≤y≤b. The same applies to ranges with a boundary value such as "at most" and "at least".

[0054] The term “on” should not be interpreted as meaning only “directly on.” Rather, if one element is “on” another element (for example, a layer is “on” another layer or is “on” a substrate), additional components (for example, additional layers) may be located between the two elements (for example, if a layer is “on” a substrate, the additional layers may be located between the layer and the substrate).

[0055] Two adjacent doped regions in a semiconductor layer form a semiconductor junction. Two adjacent doped regions of the same conductivity type and having different dopant concentrations form a unipolar junction, such as an n / n+ or p / p+ junction along the boundary surface between the two doped regions. At the unipolar junction, the dopant concentration profile orthogonal to the unipolar junction may show a step or turning point where the dopant concentration profile changes from concave to convex, or vice versa. Two adjacent doped regions with complementary conductivity types form a pn junction.

[0056] The first conductivity type may be n-type and the second conductivity type may be p-type. In this case, the semiconductor region of the first conductivity type may include an excess of a donor-like dopant, and the semiconductor region of the second conductivity type may include an excess of an acceptor-like dopant. Alternatively, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, the semiconductor region of the first conductivity type may include an excess of an acceptor-like dopant, and the semiconductor region of the second conductivity type may include an excess of a donor-like dopant.

[0057] The accompanying drawings illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p". For example, "n-" means a doping concentration that is lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions with the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions can have the same or different absolute doping concentrations.

[0058] Embodiments of the present disclosure relate to a high-voltage semiconductor device, comprising a low-side portion and a high-side portion. The high-voltage semiconductor device may be a gate driver device. The low-side portion outputs a first gate drive signal between a first gate output and a first reference potential VSS. The high-side portion outputs a second gate drive signal between a second gate output and a second reference potential VS. The high-side portion also generates a high-side data signal.

[0059] The low-side portion includes circuits of a low voltage domain. The low voltage domain outputs a first gate drive signal and may also include circuits of a CMOS interface for communicating with a standard CMOS device having an input voltage lower than 5V. The circuits for the CMOS interface and the circuits for driving the first gate drive signal may be isolated from each other or may be part of a one-part voltage domain.

[0060] A first gate drive signal output by the low-side portion can drive the gate of a low-side switch of an electronic half-bridge. A second gate drive signal output by the high-side portion can drive a high-side switch of the same half-bridge. The half-bridge can be part of an H-bridge that switches the polarity of a voltage applied to a load.

[0061] The above-mentioned breakdown voltage of at least 80V or even at least 300V can be applied between the low side and the high side. The breakdown voltage in the corresponding voltage domain of the low side and / or the high side can be smaller, for example less than 80V or less than 50V. However, the breakdown voltage of the semiconductor element can also be at least 80V or even at least 300V. The semiconductor element can establish and / or control the electrical connection between different voltage domains of the high-voltage semiconductor device, for example the high side and the low side in the case of the gate driver device.

[0062] The semiconductor substrate may include a conductive, for example doped semiconductor material. The substrate may be a homogeneous layer or layer stack of two or more sublayers of different compositions and / or internal structures of the semiconductor material. For example, the semiconductor substrate is a silicon, Si or gallium arsenide, GaAS, or gallium nitride, GaN, or silicon carbide, SiC wafer. The thickness of the semiconductor substrate may be in the range of 4 μm to 200 μm, or more specifically in the range of 20 μm to 150 μm.

[0063] Figures 1 to 4 A lateral high-voltage semiconductor device 1 is shown in each case. Figure 1 is a highly schematic top view of the device, while all other figures show lateral cross-sections of the device. A lateral high-voltage semiconductor device 1 comprises a semiconductor substrate 2, for example comprising silicon, Si or silicon carbide, SiC. The lateral high-voltage device 1 comprises at least one semiconductor element 10. The semiconductor element 10 comprises at least a first semiconductor region 11 of a first conductivity type formed in the semiconductor substrate 2 and a second semiconductor region 12 formed in the semiconductor substrate 2. The first semiconductor region 11 and the second semiconductor region 12 are spaced apart from each other along a first lateral direction x parallel to the front side. The substrate 2 may have a first conductivity type or a second conductivity type. Typically, the substrate 2 may have a p-type doping.

[0064] The first semiconductor region 11 and the second semiconductor region 12 may be connected via an extension region 13 adjacent to the second semiconductor region 12. The extension region 13 has a second conductivity type. The extension region 13 may be configured to shield or take over the electric field between the first semiconductor region 11 and the second semiconductor region 12. Therefore, the extension region 13 may be configured to take over the nominal voltage or breakdown voltage of the device 1 between the two regions 11 and 12. The doping degree of the extension region 13 may be lighter than the doping degree of the second semiconductor region 12. The doping concentration of the extension region 13 may be, for example, at least 2 orders of magnitude, at least 3 orders of magnitude, or at least 5 orders of magnitude less than the doping concentration of the second semiconductor region 12. The doping concentration of the extension region 13 may be, for example, at least 2 orders of magnitude, at least 3 orders of magnitude, or at least 5 orders of magnitude less than the doping concentration of the first semiconductor region 11.

[0065] Now refer to Figures 2 to 4 , the lateral high-voltage semiconductor device 1 includes a plurality of mesas 14 protruding at the front side of the semiconductor substrate 2. The mesas 14 are elevated regions compared to the surrounding portions of the extension region 13. In other words, at the mesas 14, the substrate 2 may extend higher than the adjacent portions of the mesas 14 (where the substrate 2 is covered by the insulating layer 16). In the mesa region 14, the substrate 2 may even have a greater thickness than the adjacent portions (where the substrate 2 is covered by the insulating layer 16).

[0066] The main extension direction of the mesa 14 may be parallel to the front side of the substrate and perpendicular to the current flow between the first semiconductor region 11 and the second semiconductor region 12 (or an imaginary line between the first semiconductor region 11 and the second semiconductor region 12). In a cross section through the device, the main extension direction of the mesa 14 extends parallel to the y-axis. The main extension direction of the mesa 14 may be parallel to the front side and perpendicular to the first lateral direction x. Therefore, in the section, the main extension direction of the mesa 14 may be parallel to the second lateral direction y.

[0067] Parts of the insulating layer 16 are arranged between corresponding ones of the mesas 14. One part of the insulating layer 16 is arranged between one mesa 14 and the first semiconductor region 11 because the first semiconductor region 11 includes a raised portion protruding from the front side. Another part of the insulating layer 16 is arranged between one mesa 14 and the second semiconductor region 12 because the second semiconductor region 12 includes a raised portion protruding from the front side.

[0068] The lateral high-voltage semiconductor device also includes a plurality of field plate structures 15 electrically connected to the first semiconductor region 11, the second semiconductor region 12 or the mesa 14, respectively. The first field plate structure 151 is connected to the first semiconductor region 11. The second field plate structure 152 is connected to the second semiconductor region 12. The third field plate structure 153 is connected to the first mesa 14. The fourth field plate structure 154 is connected to the second mesa 14. The field plate structures 15 may each include one, two, three or more field plates, wherein the field plates 154, 155, 156 of the same field plate structure 15 partially overlap each other laterally or completely overlap each other laterally. For example, a larger field plate in the field plate may completely overlap with a smaller field plate of the same field plate structure. Each field plate structure in the field plate structure 15 associated with the mesa 14 at least partially overlaps laterally with the corresponding mesa 14 to which it is connected.

[0069] Figure 4 1. The field plates 154, 155, 156 of the same field plate structure 15 may be interconnected via a connection 159. The lowermost field plate 154 of the respective field plate structure 15 may be connected to one of the mesas 14 or to one of the first semiconductor region 11 and the second semiconductor region 12 via a bottom connection 159. The third field plate structure 153 and the fourth field plate structure 154 are connected to the extension region 13 via the respective associated mesas 14.

[0070] At least one mesa 14 may be part of a field ring within the semiconductor substrate (see Figures 1 to 3). In the case of two or more such mesas 14, each mesa 14 may be part of a respective field ring. The field ring may extend below and / or beside the mesa 14. The field ring may be part of an extension region 13. In each field ring, the doping concentration may be higher than the doping concentration of the surrounding portion of the extension region. The conductivity type of the doping within the field ring may be the same as or opposite to the conductivity type of the surrounding portion of the extension region. The field ring associated with a mesa 14 may be laterally centered around the respective mesa 14. The field rings may each include a field ring doped region 142 having the same or opposite conductivity type as the extension region 13 (see Figure 4 ).

[0071] according to Figure 4 In some embodiments depicted in , the field plate structure 15 includes a stack of at least three interconnected field plates 154, 155, 156 on each other, wherein at least one of the field plates 154 in the stack includes polysilicon and at least one of the field plates 155, 156 of the stack 15 includes metal.

[0072] In one or more of the field plate structures 15, for example, the first field plate structure 151 and the second field plate structure 152 and / or the third field plate structure 153 and the fourth field plate structure 154, the uppermost field plate 156 of the at least three interconnected field plates 154, 155, 156 may include metal or even consist of metal, while the lowermost field plate 154 of the at least three interconnected field plates 154, 155, 156 includes polysilicon. Each of the field plates of the corresponding field plate structure may partially or completely overlap laterally with all lower field plates of the same field plate structure. Therefore, the uppermost field plate of the at least three interconnected field plates may completely overlap laterally with all field plates 154, 155, 156 of the same field plate structure 15.

[0073] Reference Figure 4 , the third field plate structure 153 is connected to the first portion of the extension region 13 at a side of the third field plate structure 153 that is closer to the first semiconductor 11 region along the first lateral direction x than the center of mass of the third field plate structure 153. The fourth field plate structure 154 is connected to the second portion of the extension region 13 at a side of the fourth field plate structure 154 that is closer to the second semiconductor region 12 along the first lateral direction x than the center of mass of the fourth field plate structure 154. In other words, both the third field plate structure 153 and the fourth field plate structure 154 are connected asymmetrically with respect to their lateral centers, wherein the protrusion of the respective field plate structures 153, 154 on the connection 159 facing the lateral center of the extension region 13 is greater than the protrusion of the respective field plate structures 153, 154 on the connection facing away from the lateral center of the extension region 13.

[0074] The respective electrical connections 158, 159 connecting one of the field plates 154 of the field plate structure 15 to the semiconductor portion or semiconductor region may be configured to provide a low-ohmic contact between the field plate structure 15 and the semiconductor portion or semiconductor region, or include a pn junction or Schottky junction between the field plate structure 15 and the mesa 14. Figure 4 In the three lower examples of FIG. 1 , the field plate structure 15 is connected to the mesa 14 / extension region via a doped region 141. The doped region 14 may have the same conductivity type as the extension region 13 with a higher dose to improve the contact resistance. The doped region 14 may have an opposite conductivity type to the extension region 13 with a higher dose to form a rectifying junction. The electrically connected regions may be structured laterally along the main extension direction of the respective mesa associated with the electrical connection.

[0075] The insulating layer 16 may include a first insulating layer 161 that is laterally adjacent to the at least one mesa on both sides of the at least one mesa. In other words, a portion adjacent to the at least one mesa 14 may be covered by the first insulating layer. The first insulating layer 161 may have the same vertical extension as the at least one mesa 14 and / or the top surface of the insulating layer 161 and the top surface of the mesa 14 form an at least substantially flat surface.

[0076] The insulating layer 16 includes a first insulating layer 161, and may further include at least one second insulating layer 162 over the first insulating layer 161 and the at least one mesa 14. The upper second insulating layer 162 may include the same material or even the same composition as the first insulating layer 161. The first layer 161 and the second layer 162 may have different compositions, for example, different materials or different physical properties.

[0077] The first insulating layer 161 and the second insulating layer 162 can be manufactured in a single or separate manufacturing step. The first layer 161 and / or the second layer 162 may include an oxide (e.g., silicon oxide) or a nitride (e.g., silicon nitride). The first layer 161 may, for example, include a thermally grown oxide, while the second layer may, in contrast, include a deposited oxide.

[0078] The semiconductor element 10 can realize an electronic element or an electronic device. For example, the semiconductor element can be a transistor (e.g., a bipolar junction transistor BJT or a field effect transistor FET or a junction gate field effect transistor JFET), or a diode (e.g., a pn diode or a Zener diode), or an insulated gate bipolar transistor IGBT or a thyristor, etc.

[0079] Now refer to Figures 8 to 11In the case where the semiconductor element 10 is a transistor-like device, the semiconductor element 10 may further include a body region 110 of a second conductivity type laterally adjacent to the first semiconductor region 11 and the extension region 13, and a gate structure 113 configured to control a lateral load current between the first semiconductor region 11 and the second semiconductor region 12. The gate region 113 may be insulated from the body region 110. The gate region may be configured to form an inversion channel in the body region for controlling the lateral load current. The first semiconductor region 11 may be a source or emitter region 111 of a transistor, and the second semiconductor region may be a drain or collector region 112 of a transistor. The second semiconductor region 12 or the drain or collector region 112 may have a first conductivity type. The extension region 13 may also have a first conductivity type.

[0080] Reference Fig.10 , some of the mesa regions 14 may be configured as base regions 144. The associated field plate structures are connected to the base regions 144. Fig. 9 , the device 1 comprises an additional extension region of opposite conductivity type compared to the extension region 13 .

[0081] The field plate structure may be embedded in an insulating material, such as the second insulating layer 162 (see Figures 5 to 7 For example, each field plate structure 15 may be completely surrounded by the insulating material 162 , with only the electrical connections 158 , 159 connected via the insulating material 162 .

[0082] For example, the mesas 14 are patterned along a first lateral direction, resulting in the bonding surface extending in a second lateral direction perpendicular to the first lateral direction. For example, the mesas are patterned along a second lateral direction, resulting in the bonding surface extending in the first lateral direction.

[0083] For example, in the case of an ohmic connection, the electrical connections 158, 159 may connect the mesa 14 only asymmetrically, for example close to the lateral edges of the mesa 14. For example, in the case of a pn junction, one part of the junction may have a larger lateral extension than another part. In this case, a smaller part of the junction may extend only close to the lateral edges of the mesa 14.

[0084] The lateral high-voltage semiconductor device 1 may further include a high-voltage (HV) wiring layer 19 (see Figure 3 The high voltage wiring layer 19 may be insulated from the at least one field plate structure 15 by an insulating layer 16 (eg, a second insulating layer 162 ).

[0085] For example, at least 50% or even at least 70% or even at least 85% of the semiconductor element 10 may be collectively laterally overlapped by the field plate structure 15 . This may provide effective shielding of the semiconductor element 10 with respect to the HV wiring layer 19 .

[0086] The semiconductor substrate 2 may include a back side opposite to the front side. The lateral high-voltage semiconductor device may include a back side insulating layer 30 arranged to the back side of the semiconductor substrate 2. The back side insulating layer 30 may include an oxide layer. The thickness of the oxide layer may be 0.5 μm to 20 μm, preferably 2 μm to 20 μm. The oxide layer may be deposited on the back side. This allows for great scalability of the voltage level of the semiconductor device 1 because the thickness of the deposited oxide can be easily selected according to the desired breakdown voltage. The combined thickness of the semiconductor substrate 2 and the back side insulating layer 30 may be in the range of 20.5 μm to 100 μm ((semiconductor substrate is 20 μm to 100 μm) + (insulating layer is 0.5 μm to 20 μm)).

[0087] The lateral high voltage semiconductor device may further include an additional silicon layer below the back side of the semiconductor substrate. For example, the additional silicon layer may be directly or indirectly attached to the back insulating layer. For example, one or more adhesion promoting layers may be arranged between the back insulating layer and the additional silicon layer. One or more adhesion promoting layers may include tape, such as DAF tape. For example, as an alternative or in addition to one or more adhesion promoting layers, one or more additional layers may be arranged between the back insulating layer and the additional silicon layer. One or more additional layers may include one or more dielectric layers and / or one or more metal layers.

[0088] The lateral high-voltage semiconductor device may also include at least one insulating trench 31, which electrically insulates the semiconductor element from another semiconductor element adjacent to the semiconductor element 10 on the same semiconductor substrate 2. The insulating trench 31 may include a trench electrode 33. The trench electrode 33 may include doped or undoped polysilicon. The trench electrode 33 may be floating or connected to any potential (e.g., the potential of the first semiconductor region 11 or the second semiconductor region 12). At least one insulating trench 31 may extend from the front side of the substrate to the back side, and at least one insulating trench 31 on the back side is adjacent to the back side insulating layer 30. The insulating trench 31 may include one or more trench insulating layers 34, for example, including an oxide layer.

[0089] Although specific embodiments have been shown and described herein, it will be appreciated by those skilled in the art that various alternatives and / or equivalent implementations may replace the specific examples shown and described without departing from the scope of the invention. This application is intended to cover any modifications or variations of the specific examples discussed herein. Therefore, the present invention is limited only by the claims and their equivalents.

[0090] It should be noted that the methods and devices including the preferred embodiments thereof outlined herein may be used alone or in combination with other methods and devices disclosed herein. Furthermore, features outlined in the context of a device also apply to the corresponding method, and vice versa. Furthermore, all aspects of the methods and devices outlined in this document may be combined arbitrarily. In particular, the features of the claims may be combined with each other in any manner.

[0091] It should be noted that the description and the accompanying drawings illustrate only the principles of the proposed method and system. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the present invention and are included in its spirit and scope. In addition, all examples and implementations outlined in this document are primarily and explicitly intended to be for illustrative purposes only, to help the reader understand the principles of the proposed method and system. In addition, all statements of the principles, aspects and implementations of the present invention and specific examples thereof provided herein are intended to cover their equivalents.

Claims

1. A lateral high-voltage semiconductor device (1), comprising: A semiconductor substrate (2) having a front side; A semiconductor element (10), comprising: a first semiconductor region (11) of a first conductivity type formed in the semiconductor substrate, a second semiconductor region (12) formed in the semiconductor substrate and spaced apart from the first semiconductor region (11) in a first lateral direction (x) parallel to the front side, and an extension region (13) adjacent to the second semiconductor region (12), Wherein, the lateral high-voltage semiconductor device (1) is configured to control a lateral load current between the first semiconductor region and the second semiconductor region; The extension region (13) extends along the front side of the semiconductor substrate and comprises at least one mesa (14) protruding from the front side (101) of the semiconductor substrate.

2. The lateral high voltage semiconductor device according to claim 1, further comprising: at least one field plate structure (15) at least partially over a corresponding one of the at least one mesa; and an electrical connection connecting the at least one field plate structure to the corresponding mesa.

3. A lateral high-voltage semiconductor device (1), comprising: A semiconductor substrate (2) having a front side; A semiconductor element (10), comprising: a first semiconductor region (11) of a first conductivity type formed in the semiconductor substrate (2), a second semiconductor region (12) spaced apart from the first semiconductor region (11) in a first lateral direction (x) parallel to the front side, and an extension region (13) adjacent to the second semiconductor region (12), Wherein, the lateral high-voltage semiconductor device (1) is configured to control a lateral load current between the first semiconductor region and the second semiconductor region; a first field plate structure (15, 151) electrically connected to the first semiconductor region (11); and A second field plate structure (15, 152) electrically connected to the second semiconductor region (13); wherein at least one of the first field plate structure and the second field plate structure comprises a stack of at least three interconnected field plates (154, 155, 156) on each; Wherein, at least one of the field plates (154, 155, 156) in the stack comprises polysilicon, and at least one of the field plates (154, 155, 156) in the stack comprises metal.

4. A lateral high-voltage semiconductor device (1), comprising: A semiconductor substrate (2) having a front side; A semiconductor element (10), comprising: a first semiconductor region (11) of a first conductivity type formed in the semiconductor substrate, a second semiconductor region (12) spaced apart from the first semiconductor region in a first lateral direction (x) parallel to the front side, and an extension region (13) adjacent to the second semiconductor region, wherein the lateral high-voltage semiconductor device is configured to control a lateral load current between the first semiconductor region and the second semiconductor region; A first field plate structure (15, 151) electrically connected to the first semiconductor region; a second field plate structure (15, 152) electrically connected to the second semiconductor region; a third field plate structure (15, 153) electrically connected to the first portion of the extension region; a fourth field plate structure (15, 154) electrically connected to the second portion of the extension region; wherein the third field plate structure is connected to the first portion of the extension region at a side of the third field plate structure that is closer to the first semiconductor region than the centroid of the third field plate structure along the first lateral direction; The fourth field plate structure is connected to the second portion of the extension region at a side of the fourth field plate structure that is closer to the second semiconductor region than the centroid of the fourth field plate structure along the first lateral direction.

5. The lateral high voltage semiconductor device according to claim 4, wherein: At least one of the first, second, third, and fourth field plate structures comprises a stack of field plates, wherein at least one of the field plates in the stack comprises polysilicon and at least another of the field plates in the stack comprises metal.

6. The lateral high voltage semiconductor device according to any one of claims 3 to 5, wherein: The extension region extends along the front side of the semiconductor substrate and includes at least one mesa protruding at the front side of the semiconductor substrate. 7 . The lateral high voltage semiconductor device according to claim 1 , further comprising a first insulating layer laterally adjacent to the at least one mesa on both sides of the at least one mesa.

8. The lateral high voltage semiconductor device according to claim 7, wherein: The first insulating layer has the same vertical extension as the at least one mesa and / or a top surface of the first insulating layer and a top surface of the at least one mesa form an at least substantially flat surface.

9. The lateral high-voltage semiconductor device according to claim 7 or 8, wherein: The portions of the first insulating layer are arranged as follows: between the at least one mesa and the first semiconductor region and between the at least one mesa and the second semiconductor region, and / or Between at least two separate pieces of the at least one piece. 10 . The lateral high-voltage semiconductor device according to claim 7 , further comprising at least one second insulating layer over the first insulating layer and the at least one mesa.

11. The lateral high voltage semiconductor device according to any one of claims 1, 2 or 6 to 10, further comprising at least one field ring, wherein: The at least one field ring is at least partially arranged within the at least one mesa.

12. The lateral high voltage semiconductor device according to any one of claims 2 to 11, wherein: Each electrical connection is configured to provide a low-ohmic contact between the field plate structure and a corresponding portion of the extension region.

13. The lateral high voltage semiconductor device according to any one of claims 2 to 11, wherein: Each electrical connection includes a rectifying junction between the field plate structure and the mesa.

14. The lateral high voltage semiconductor device according to claim 13, wherein: The rectifying junction includes a first portion, a second portion, and a junction between the first portion and the second portion of the rectifying junction, wherein the mesa is laterally patterned into the first portion and the second portion of the rectifying junction.

15. The lateral high voltage semiconductor device according to claim 14, wherein: The mesas are patterned along the first lateral direction, causing the bonding surface to extend in a second lateral direction perpendicular to the first lateral direction; or The mesas are patterned along the second lateral direction, resulting in the bonding surfaces extending in the first lateral direction. 16 . The lateral high voltage semiconductor device according to claim 2 , further comprising a high voltage wiring layer above the field plate structure.

17. The lateral high voltage semiconductor device according to any one of claims 2 to 15, wherein: At least 50% or even at least 70% of the semiconductor elements are collectively laterally overlapped by the field plate structure.

18. A lateral high-voltage semiconductor device according to any one of the preceding claims, wherein: The semiconductor element further comprises: a body region of the second conductivity type laterally adjoining the first semiconductor region and the extension region, and A gate structure configured to control the lateral load current between the first semiconductor region and the second semiconductor region.

19. A lateral high voltage semiconductor device according to any one of the preceding claims, wherein: The first semiconductor region is arranged close to or at the front side and / or the second semiconductor region is arranged close to or at the front side.

20. A lateral high-voltage semiconductor device according to any one of the preceding claims, wherein: The semiconductor substrate comprises a back side opposite to the front side, wherein the lateral high voltage semiconductor device comprises a back side insulating layer arranged to the back side.

21. The lateral high voltage semiconductor device according to claim 20, wherein: The lateral high-voltage semiconductor device includes at least one insulation trench that electrically insulates the semiconductor element from another semiconductor element adjacent to the semiconductor element on the same semiconductor substrate.

22. The lateral high voltage semiconductor device according to claim 21, wherein: The at least one insulation trench extends from the front side of the substrate to the back side, the at least one insulation trench adjoining the back side insulation layer at the back side.

23. A method for forming a lateral high voltage semiconductor device, the method comprising: providing a semiconductor substrate having a front side; forming a countertop area; A semiconductor element is formed, the semiconductor element comprising: a first semiconductor region of a first conductivity type formed in the semiconductor substrate, a second semiconductor region spaced apart from the first semiconductor region in a lateral direction parallel to the front side, and an extension region adjacent to the second semiconductor region, wherein the semiconductor element is configured to control a lateral load current between the first semiconductor region and the second semiconductor region; The extension region extends along the front side of the semiconductor substrate and includes at least one mesa protruding at the front side of the semiconductor substrate.

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