Semiconductor device
By forming multiple beam-like shielding layers under the trench transistor and deepening the extension depth of the shielding layer by using channel ion implantation technology, the problems of concentrated electric field and high on-resistance of the trench transistor are solved, and the effects of electric field optimization and on-resistance reduction are achieved.
Patent Information
- Application Number
- CN202411625747.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-13
- Publication Date
- 2025-03-28
AI Technical Summary
During use, the electric field is concentrated at the corners of the bottom of the trench, resulting in poor voltage withstand and reliability, and traditional shielding methods will increase the on-resistance.
A plurality of shielding layers with beam-like structures are formed below the trench, and the extension depth of the shielding layer in the semiconductor layer is deepened through channel ion implantation technology, and the electric field distribution at the bottom corner of the trench gate is optimized.
The electric field optimization of the bottom corner of the trench gate is achieved, reducing the on-resistance and improving the short-circuit withstand time.
Smart Images
Figure CN119730322A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and more specifically, to a semiconductor device with a trench gate structure. Background Art
[0002] Compared with the planar transistor structure, the vertical transistor structure is conducive to balancing the blocking voltage and on-resistance in the same area. When multiple discrete devices are used in a power device module or in the same system, the variation in characteristics between transistor devices is also an important consideration for the robustness of the integrated system. During the manufacturing process, transistors need to go through a large number of different process steps, so the device characteristics of the transistors will also vary due to differences in the manufacturing process.
[0003] As a power semiconductor device, there are many ways to improve the Rsp (on-resistance or switching loss) of MOSFET. For trench-type transistors, the electric field will be concentrated at the bottom corner of the trench during use, so the withstand voltage and reliability are poor.
[0004] In order to compensate for this shortcoming, the bottom corners of the trench need to be shielded. However, the shielding method of traditional technology usually leads to an increase in the on-resistance of the semiconductor device, requires a thicker hard mask layer, or leads to an increase in the design size. Summary of the invention
[0005] In view of the above problems, an object of the present invention is to provide a semiconductor device, wherein a shielding layer having a plurality of beam-like structures and extending along a second direction is formed under a trench extending along a first direction, thereby optimizing the electric field at the bottom corner of the trench gate and reducing the on-resistance. In addition, the extension depth of the shielding layer in the semiconductor layer is deepened by channel ion implantation technology, thereby improving the short-circuit withstand time while ensuring low on-resistance.
[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor layer and a trench gate structure, the semiconductor layer having a first surface and a second surface relative to each other, at least a portion of the trench gate structure being located in a trench extending from the first surface to the second surface of the semiconductor layer, wherein the semiconductor layer comprises: a shielding layer, the shielding layer being located between the trench gate structure and the second surface of the semiconductor layer, a preset distance between a bottom surface of the shielding layer in the semiconductor layer and a bottom surface of the trench gate structure being greater than or equal to 1.5 um.
[0007] Optionally, a preset distance between a bottom surface of the shielding layer in the semiconductor layer and a bottom surface of the trench gate structure is greater than or equal to 2 um.
[0008] Optionally, the shielding layer is formed by a channel ion implantation method.
[0009] Optionally, the bottom of the trench gate structure extending along a first direction is spaced adjacent to the shielding layer, the first direction and the second direction are parallel to the first surface of the semiconductor layer, and the first direction and the second direction form an angle that is not zero.
[0010] Optionally, the shielding layer includes a plurality of beam-like structures extending along a second direction, and the plurality of beam-like structures are arranged at intervals along a first direction, and the second direction is parallel to the first surface of the semiconductor layer.
[0011] Optionally, an angle between the first direction and the second direction is greater than 45° and less than 135°.
[0012] Optionally, along the first direction, the transistor region between two adjacent beam-like structures and an adjacent beam-like structure form a cell region, and in the cell region, the width of the transistor region along the first direction is greater than or equal to the width of the beam-like structure.
[0013] Optionally, in the cell region, the ion doping concentration of the shielding layer is increased to reduce the width of the beam-like structure.
[0014] Optionally, a ratio of a width of the beam-like structure to a spacing width of the spacing area is greater than or equal to 1 / 3 and less than or equal to 1.
[0015] Optionally, the semiconductor layer also includes: a source region, located between adjacent trench gate structures, extending from the first surface to the second surface, and adjacent to a side wall of the trench gate structure on one side; a body region, located between adjacent trench gate structures, with both sides of the body region adjacent to the side walls of the adjacent trench gate structures, respectively, and a portion of the upper surface of the body region adjacent to the lower surface of the source region; an epitaxial layer, located between the body region and the second surface of the semiconductor layer, the epitaxial layer separating the adjacent beam-like structures and adjacent to the lower surface of the body region.
[0016] Optionally, the ion doping concentration of the transistor region is greater than the ion doping concentration of the epitaxial layer between the bottom surface of the shielding layer and the second surface.
[0017] Optionally, the shielding layer and the body region are of the second conductivity type, and the epitaxial layer is of the first conductivity type.
[0018] Optionally, the ion doping concentration of the shielding layer is greater than the ion doping concentration of the body region.
[0019] Optionally, a distance between a lower surface of the trench gate structure and the first surface is greater than a distance between a lower surface of the body region and the first surface.
[0020] Optionally, the semiconductor layer includes a SiC semiconductor layer or a Si semiconductor layer.
[0021] The semiconductor device provided by the present invention forms a shielding layer under the trench extending along the first direction, and the shielding layer includes a plurality of beam-like structures extending along the second direction. By controlling the spacing width between adjacent beam-like structures and the width of the beam-like structures along the first direction, the electric field at the bottom corner of the trench gate is optimized, and the on-resistance is reduced. At the same time, the shielding layer is formed by the channel ion implantation method, which can not only increase the extension depth of the shielding layer in the semiconductor layer at the same energy, but also the shielding layer with increased depth can increase the short-circuit withstand time of the semiconductor device.
[0022] Furthermore, the ion concentration of the first conductive type can be increased in the transistor region between two adjacent shielding beams to further reduce the on-resistance of the semiconductor device, so that the semiconductor device not only has a low on-resistance but also has a high short-circuit withstand time.
[0023] Furthermore, in the present application, the beam-shaped structure of the shielding layer extending along the second direction does not form a channel in the partial area in contact with the trench gate, and only forms a channel in the transistor area between adjacent beam-shaped structures. Therefore, the narrower the width of the beam-shaped structure along the first direction, the more helpful it is to reduce the on-resistance. In addition, the shielding layer does not need to be implanted with ultra-high energy ions, so the width of the shielding layer along the first direction can be effectively controlled in the manufacturing process.
[0024] Further, along the first direction, a spacing between adjacent beam-like structures in the shielding layer and an adjacent shielding layer form a cellular region. In a cellular region, controlling the width of the shielding layer along the first direction to be smaller than the spacing between adjacent shielding layers can maintain the withstand voltage and reliability of the semiconductor device at a certain level while improving the Rsp (on-resistance) characteristic. Specifically, in a cellular region, the ratio of the width of the beam-like structure to the spacing between adjacent beam-like structures is less than or equal to 1 but greater than or equal to 1 / 3.
[0025] It should be noted that the above general description and the following detailed description are merely exemplary and explanatory and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0027] Figure 1shows a schematic diagram of the three-dimensional structure of a semiconductor device according to a first embodiment of the present invention;
[0028] Figure 2 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line AA;
[0029] Figure 3 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line BB;
[0030] Figure 4 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line CC;
[0031] Figure 5 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line DD;
[0032] Figure 6 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a first embodiment of the present invention is shown;
[0033] Figure 7 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a second embodiment of the present invention is shown;
[0034] Figure 8 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a third embodiment of the present invention;
[0035] Fig. 9 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a fourth embodiment of the present invention;
[0036] Fig.10 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to a fifth embodiment of the present invention;
[0037] Fig.11 The fifth embodiment of the present invention is shown along Fig.10 Schematic diagram of the cross-section of the semiconductor device taken along line CC. DETAILED DESCRIPTION
[0038] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.
[0039] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.
[0040] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".
[0041] The power device generally includes an active component region, an edge termination region, and a crack-stop or shielding region. The active component region includes an active component array. The present disclosure relates to an active component structure. The size of the active component may vary depending on product requirements, and there may be a body region between active components in the active component region.
[0042] Many specific details of the present application are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to make the present application more clearly understood. However, as those skilled in the art will appreciate, the present application may be implemented without following these specific details.
[0043] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.
[0044] Figure 1 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to a first embodiment of the present invention; Figure 2 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line AA; Figure 3 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line BB; Figure 4 The first embodiment of the present invention is shown along Figure 1 A schematic cross-sectional view of a semiconductor device taken along line CC; Figure 5 The first embodiment of the present invention is shown along Figure 1 The schematic cross-sectional view of the semiconductor device taken along line DD in FIG. Figure 1 The structure above the semiconductor layer and part of the trench gate structure are omitted in order to more clearly express the positional relationship between various structures and regions.
[0045] like Figures 1 to 5As shown, the semiconductor device 10 of the first embodiment of the present application includes a semiconductor layer 100, a plurality of trench gate structures 150 located in the semiconductor layer 100, an interlayer dielectric layer 160 located on the semiconductor layer 100, and a source metal layer 170. The semiconductor layer 100 has a first surface a and a second surface b that are oppositely arranged, and a plurality of trenches 102 extending from the first surface a to the second surface b of the semiconductor layer 100, and the plurality of trench gate structures 150 are located in the corresponding trenches 102.
[0046] In this embodiment, the semiconductor layer 100 is, for example, a SiC substrate, a Si substrate, or a stacked structure of a SiC substrate and an epitaxial layer. However, the present application is not limited thereto, and those skilled in the art may set other materials and layers of the semiconductor layer 100 as needed.
[0047] The semiconductor layer 100 includes a substrate 101, an epitaxial layer 103, a shielding layer 120, a body region 110, a source region 130, a body contact region 140, and a drain contact region 180. Among them, the source region 130, the substrate 101, and the epitaxial layer 103 are of the first conductivity type, the body region 110, the body contact region 140, and the shielding layer 120 are of the second conductivity type, the doping concentration of the body contact region 140 is greater than the doping concentration of the body region 110, and the first conductivity type is opposite to the second conductivity type. The first conductivity type is one of P type and N type, and the second conductivity type is the other of P type and N type. In the embodiment of the present application, for example, the embodiment is described according to the first conductivity type being N type and the second conductivity type being P type.
[0048] The trench gate structure 150 includes a gate dielectric layer 151 and a gate conductor 152. The gate dielectric layer 151 covers the inner surface of the trench 102, the gate conductor 152 is located in the trench 102, and the gate dielectric layer 151 is located between the semiconductor layer 100 and the gate conductor 152, and is used to separate the semiconductor layer 100 from the gate conductor 152. The plurality of trench gate structures 150 extend along a first direction, that is, the first direction is the length direction of the trench gate structure 150, and the plurality of trench gate structures 150 are spaced apart along a second direction, that is, the second direction is the width direction of the trench gate structure 150, and the third direction is the direction from the second surface b of the semiconductor layer 100 to the first surface a. The trench gate structure 150 has two opposite sidewalls 150a and a lower surface 150b, as shown in FIG. Figure 2 As shown. Optionally, the first direction, the second direction and the third direction are respectively represented as the X-axis, the Y-axis and the Z-axis directions, and the first direction, the second direction and the third direction are perpendicular to each other. Optionally, the Y-axis direction is the <11-20> direction or the <1-100> direction, and the plane of the side wall 150a is the (11-20) plane or the (1-100) plane.
[0049] The body region 110 is located between two adjacent trench gate structures 150, and extends along the width direction and the length direction of the trench gate structure. One side of the body region 110 is adjacent to the side wall 150a of one of the trench gate structures 150, and the other side is adjacent to the side wall 150a of the other trench gate structure 150. In addition, the distance between the lower surface of the body region 110 and the first surface a is smaller than the distance between the lower surface 150b of the trench gate structure 150 and the first surface a.
[0050] The source region 130 extends from the first surface a to the second surface b of the semiconductor layer 100 and is adjacent to the body region 110. At the same time, the source region 130 is located between two adjacent trench gate structures 150 and is adjacent to a sidewall 150a of the trench gate structure 150. The body contact region 140 is located between the source regions 130, and divides the source region 130 located between the two adjacent trench gate structures 150 into two parts. The two parts of the source region 130 are respectively adjacent to the sidewall 150a of one of the adjacent trench gate structures 150, that is, in the second direction, the source region 130, the body contact region 140 and the source region 130 are sequentially located between the adjacent trench gate structures 150 on the first surface a of the semiconductor layer 100, and in the third direction, the source region 130 and the body contact region 140 are located above the body region 110. In this embodiment, Figure 1 The figure shows that the body contact region 140 extends along the first direction, thereby separating the source region 130 between two adjacent trench gate structures 150 into two parts. Further, the depth of the body contact region 140 extending from the first surface a to the second surface b in the semiconductor layer 100 is deeper than the depth of the source region 130 extending in the semiconductor layer 100, and is less than the extension depth of the body region 110 in the semiconductor layer 100, and the bottom of the trench of the trench gate structure 150 is located below the bottom of the body region 110, that is, the depth of the trench gate structure 150 extending from the first surface a of the semiconductor layer 100 to the second surface b is greater than the extension depth of the body region 110 in the semiconductor layer 100.
[0051] The substrate 101 is located below the body region 110, i.e., close to the second surface of the semiconductor layer 100. The epitaxial layer 103 is located between the body region 110 and the substrate 101 and between the trench gate structure 150 and the substrate 101. The drain contact region 180 is adjacent to the substrate 101 and is located on a side of the substrate 101 away from the epitaxial layer 103, i.e., the drain contact region 180 extends from the second surface b of the semiconductor layer 100 to the first surface a.
[0052] The shielding layer 120 is located below the body region 110 and the trench gate structure 150, and specifically is adjacent to the lower surface of the body region 110, the lower surface 150b of the trench gate structure 150, and a portion of the sidewall 150a. The shielding layer 120 includes a plurality of beam-like structures extending along the second direction and arranged at intervals along the first direction, and the upper surface of a beam-like structure is alternately adjacent to the lower surfaces of the plurality of body regions 110 and the lower surfaces 150b of the plurality of trench gate structures 150 in sequence. And since the plurality of beam-like structures are distributed at intervals along the first direction, that is, along the first direction, the spacing region between two adjacent beam-like structures exposes the lower surfaces of the body region 110 and the trench gate structure 150, that is, the epitaxial layer 103 separates the adjacent beam-like structures. In addition, along the extension direction of the beam-like structures, the first ends of the plurality of beam-like structures are connected together, and the second ends of the plurality of beam-like structures are also connected together, for example, referring to Figure 6 .
[0053] The interlayer dielectric layer 160 is located on the first surface a of the semiconductor layer 100. The interlayer dielectric layer 160 includes a plurality of layers, and extends along the first direction and is arranged at intervals along the second direction, so that the bottom of the interlayer dielectric layer 160 can cover the portion of the trench gate structure 150 exposed on the first surface of the semiconductor layer 100, and at least expose the source region 130 and the body contact region 140 on the first surface a. The source metal layer 170 is located on the first surface a of the semiconductor layer 100, and contacts at least a portion of the surface of the source region 130 and the body contact region 140 exposed on the first surface a. The interlayer dielectric layer 160 is used to isolate the trench gate structure 150 from the source metal layer 170. The source metal layer 170 and the interlayer dielectric layer 160 can be a multilayer structure of different materials. As an example of a multilayer source metal layer 170, the source metal layer 170 includes a tungsten (W) layer directly covering the body contact region 140 and the source region 130, and an aluminum copper (AlCu) layer directly covering the tungsten layer. Optionally, this embodiment also includes parts not shown in the figure, for example, a gate contact region is opened directly above the gate conductor 152 so that the gate conductor 152 is connected to the gate metal layer, the gate contact region is directly located on the gate conductor 152, and the gate conductor 152 is isolated from the source metal layer 170 by the interlayer dielectric layer 160.
[0054] Further, refer to Figure 2In the cross section of the semiconductor device 10 obtained along the second direction and on a vertical surface of a beam-like structure having a shielding layer 120, the depth of the lower surface of the shielding layer 120 extending in the semiconductor layer 100 is substantially the same, but the upper surface of the shielding layer 120, as described above, is alternately adjacent to the lower surfaces of the plurality of body regions 110 and the lower surfaces of the plurality of trench gate structures 150 in the second direction. In this area, since the shielding layer 120 covers the entire bottom of the trench gate structure 150, and the lower part of the body region 110 is also covered by the shielding layer 120, the current cannot flow through this area and a channel cannot be formed. At the same time, since the shielding layer 120 is in direct contact with the bottom of the trench gate structure 150, the shielding layer 120 in this area can very well protect the bottom corner of the trench gate structure 150 from being broken down.
[0055] In addition, the shielding layer 120 is formed, for example, by a channeling implant method. In channeling ion implantation, ions are implanted along specific lattice directions of the crystal, which are called channeling directions. Because the ions are less hindered by the lattice in these directions, they can penetrate the material more deeply. Compared with the random ion implantation method, channeling ion implantation at the same energy can achieve a steeper and deeper doping profile. In the present application, the shielding layer 120 formed by the channeling ion implantation method has a predetermined distance D between its bottom and the bottom of the trench gate structure 150 greater than or equal to 1.5um, and the shielding layer 120 at this depth can improve the short circuit withstand time (SCWT), thereby improving the safety and reliability of the semiconductor device.
[0056] In a preferred embodiment, the predetermined distance D between the bottom of the shielding layer 120 and the bottom of the trench gate structure 150 is greater than or equal to 2 um.
[0057] refer to Figure 3 In a cross section of the semiconductor device 10 obtained along the second direction and on a vertical surface of a beam-shaped structure without the shielding layer 120, the lower surface of the body region 110 is in direct contact with the epitaxial layer 103. Since there is no shielding layer 120 in the spacing region, the bottom of the trench gate structure 150 is also in direct contact with the epitaxial layer 103, so there is no factor that hinders the flow of current in the spacing region. Therefore, the spacing region is the most ideal structure for reducing the on-resistance, and a transistor can be formed in the spacing region.
[0058] refer to Figure 4In the cross-sectional view of the semiconductor device 10 obtained along the first direction and located in the region of the source region 130, since the cross-sectional view is relatively close to the body contact region 140, there is no interlayer dielectric layer 160 above the source region 130. Of course, if in the region close to the trench gate structure 150, in order to ensure the isolation effect of the interlayer dielectric layer 160, the interlayer dielectric layer 160 can cover part of the upper surface of the source region 130, so in the cross-sectional view of the semiconductor device 10 obtained in the region close to the trench gate structure 150, there can also be an interlayer dielectric layer 160 on the source region 130. For the convenience of subsequent description, the interval region between two adjacent beam-like structures is called a transistor JFET region, indicating that the function of the transistor is completed in this region.
[0059] In this embodiment, further reference is made to Figure 4 river Figure 5 In the first direction, the multiple beam-like structures of the shielding layer 120 are arranged at intervals. In order to enable the beam-like structures to also shield the bottom of the trench gate 150 between adjacent beam-like structures, it is necessary to consider the width Wa of the beam-like structure along the first direction and the width Wb of the spacing area between two adjacent beam-like structures. In this way, it is possible to achieve shielding the bottom of the trench gate structure 150 while manufacturing a semiconductor device with low on-resistance.
[0060] Specifically, for example, a cell region includes a beam-like structure and a transistor JFET region adjacent thereto (W=Wa+Wb) over a width W along a first direction. In this cell region, since the beam-like structure region is a region where no channel is formed, the narrower the width Wa of the beam-like structure, the more helpful it is to reduce the on-resistance Ron. In this embodiment, the width Wa of the beam-like structure is less than or equal to the width Wb of the transistor JFET region. In addition, in this application, there is no need to perform ultra-high energy ion implantation (Ultra-High energy implant, above 2.5 MeV), so it is beneficial to achieve a narrower width Wa of the beam-like structure in terms of process.
[0061] In addition, while ensuring the withstand voltage and reliability of the semiconductor device, the smaller the ratio (Wa / Wb) of the width Wa of the beam-like structure to the width Wb of the transistor JFET region, the better the Rsp (on-resistance) characteristic of the semiconductor device can be improved. Therefore, the width Wa of the beam-like structure can be set smaller than the width Wb of the transistor JFET region between two adjacent beam-like structures. At the same time, by increasing the ion concentration of the shielding layer 120, the width Wa of the beam-like structure in a cell region can be further narrowed, while the width Wb of the transistor JFET region between two adjacent beam-like structures can be widened.
[0062] In this embodiment, a ratio (Wa / Wb) between a width Wa of the beam-like structure and a width Wb of a transistor JFET region between two adjacent beam-like structures is less than or equal to 1 and greater than or equal to 1 / 3.
[0063] Furthermore, when the ratio between the width Wa of the beam-like structure and the width Wb of the transistor JFET region between two adjacent beam-like structures is set, the ion concentration of the transistor JFET region can also be increased, for example, by increasing the concentration of N-type ions in the transistor JFET region through a channel ion implantation method, so as to further reduce the on-resistance of the semiconductor device. Although the transistor JFET region belongs to the epitaxial layer, the ion doping concentration of the transistor JFET region is greater than the ion doping concentration of the epitaxial layer 103 between the bottom of the shielding layer 120 and the second surface. Therefore, the semiconductor device of the present application not only reduces the on-resistance, but also improves the short-circuit withstand time.
[0064] Furthermore, since the beam-like structure already has a portion in contact with the body region 110 in the extending direction thereof, no additional pick-up layer is required to connect the shielding layer 120 and the body region 110 .
[0065] The semiconductor device of this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), and can also be used as an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), for example, the conductivity type of the drain contact region 180 is set to the first conductivity type or the second conductivity type. However, the embodiment of the present application is not limited to this, and those skilled in the art can set the conductivity type of each region in the semiconductor layer 100 in other ways as needed to use the semiconductor device as a MOSFET or an IGBT.
[0066] In this embodiment, when the semiconductor device is in the on state, the body region 110 and the adjacent sidewalls 150a on both sides of the trench gate structure 150 are inverted, thereby forming a channel. Moreover, since the multiple beam-like structures of the shielding layer 120 are spaced apart along the second direction, the channel current can only flow from the transistor JFET region between two adjacent beam-like structures, and by controlling the extension depth of the shielding layer 120 in the semiconductor layer, the short-circuit withstand time of the semiconductor device can be improved; by controlling the ratio of the width of the beam-like structure along the first direction and the width of the transistor JFET region between two adjacent beam-like structures, the bottom corner of the trench gate structure 150 in the channel region can be protected from being broken down by the electric field, thereby reducing the on-resistance of the semiconductor device; further, by increasing the ion concentration of the transistor JFET region, the on-resistance can be reduced. Therefore, the semiconductor device of the present application can improve the overall performance of the device.
[0067] Furthermore, the semiconductor device of this embodiment further includes a drain metal layer (not shown) located on the second surface of the semiconductor layer 100 and connected to the drain contact region 180 .
[0068] Figure 7 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a second embodiment of the present invention is shown.
[0069] like Figure 7 As shown, the similarities between the semiconductor device of the second embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figures 1 to 6 The difference is that, compared with the first embodiment, in the shielding layer 120 in the second embodiment, the first ends of the multiple beam-like structures are not connected together along the extension direction of the beam-like structures, and the second ends of the multiple beam-like structures are not connected together, so that the shielding layer 120 includes multiple parallel and mutually separated beam-like structures, and adjacent beam-like structures are separated by the epitaxial layer.
[0070] In other embodiments, the first ends or the second ends of the plurality of beam-like structures may be connected together, while the other ends are not connected.
[0071] Figure 8 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a third embodiment of the present invention is shown.
[0072] like Figure 8 As shown, the similarities between the semiconductor device of the third embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figures 1 to 6The difference is that, compared with the first embodiment, the angle between the second direction (Y) in which the beam-like structure in the shielding layer 120 extends and the first direction (X) is an obtuse angle. Specifically, the angle between the second direction (Y) in which the beam-like structure in the shielding layer 120 extends and the first direction (X) is in the range of greater than 90° and less than 135°.
[0073] Fig. 9 A diagram showing the positional relationship between a shielding layer and a trench along a horizontal plane of a semiconductor device according to a fourth embodiment of the present invention is shown.
[0074] like Fig. 9 As shown, the similarities between the semiconductor device of the fourth embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figures 1 to 6 The difference is that, compared with the first embodiment, the angle between the second direction (Y) in which the beam-like structure in the shielding layer 120 extends and the first direction (X) is an acute angle. Specifically, the angle between the second direction (Y) in which the beam-like structure in the shielding layer 120 extends and the first direction (X) is in the range of greater than 45° and less than 90°.
[0075] Fig.10 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to a fifth embodiment of the present invention; Fig.11 The fifth embodiment of the present invention is shown along Fig.10 Schematic diagram of the cross-section of the semiconductor device taken along line CC.
[0076] like Fig.10 and Fig.11 As shown, the similarities between the semiconductor device of the fifth embodiment of the present application and the first embodiment are not repeated here, and reference may be made to Figures 1 to 6 The difference is that, compared with the first embodiment, the body contact region 140 in the fifth embodiment includes a plurality of block regions, and the plurality of block regions are arranged at intervals along the first direction, and on the first surface, the body contact region 140 is surrounded by the source region 130 .
[0077] In this embodiment, the angle between the extension direction of the beam-shaped structure and the extension direction of the trench gate structure may be set to be between 45° and 135°.
[0078] The semiconductor device provided by the present invention forms a shielding layer under a trench extending along a first direction, and the shielding layer includes a plurality of beam-like structures extending along a second direction. By controlling the spacing width between adjacent beam-like structures and the width of the beam-like structures along the first direction, the electric field at the bottom corner of the trench gate is optimized, and the on-resistance is reduced. At the same time, the shielding layer is formed by a channel ion implantation method, which can not only increase the extension depth of the shielding layer in the semiconductor layer at the same energy as the random ion implantation method, but also the shielding layer with increased depth can increase the short-circuit withstand time of the semiconductor device.
[0079] Furthermore, the ion concentration of the first conductive type can be increased in the transistor region between two adjacent shielding beams to further reduce the on-resistance of the semiconductor device, so that the semiconductor device not only has a low on-resistance but also has a high short-circuit withstand time.
[0080] Furthermore, in the present application, the beam-shaped structure of the shielding layer extending along the second direction does not form a channel in the partial area in contact with the trench gate, and only forms a channel in the transistor area between adjacent beam-shaped structures. Therefore, the narrower the width of the beam-shaped structure along the first direction, the more helpful it is to reduce the on-resistance. In addition, the shielding layer does not need to be implanted with ultra-high energy ions, but only needs low-energy channel ion implantation. Therefore, the width of the shielding layer along the first direction can be effectively controlled in the manufacturing process.
[0081] Further, along the first direction, a spacing between adjacent beam-like structures in the shielding layer and an adjacent shielding layer form a cellular region. In a cellular region, controlling the width of the shielding layer along the first direction to be smaller than the spacing between adjacent shielding layers can maintain the withstand voltage and reliability of the semiconductor device at a certain level while improving the Rsp (on-resistance) characteristic. Specifically, in a cellular region, the ratio of the width of the beam-like structure to the spacing between adjacent beam-like structures is less than or equal to 1 but greater than or equal to 1 / 3.
[0082] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A semiconductor device, comprising: A semiconductor layer and a trench gate structure, wherein the semiconductor layer has a first surface and a second surface opposite to each other, and at least a portion of the trench gate structure is located in a trench extending from the first surface to the second surface of the semiconductor layer, Wherein, the semiconductor layer comprises: A shielding layer extending along the second direction, the shielding layer is located between the trench gate structure and the second surface of the semiconductor layer, and a preset distance between a bottom surface of the shielding layer in the semiconductor layer and a bottom surface of the trench gate structure is greater than or equal to 1.5 um.
2. The semiconductor device according to claim 1, wherein A preset distance between a bottom surface of the shielding layer in the semiconductor layer and a bottom surface of the trench gate structure is greater than or equal to 2 um.
3. The semiconductor device according to claim 1 or 2, wherein: The shielding layer is formed by a channel ion implantation method.
4. The semiconductor device according to claim 1 or 2, wherein: A portion of the bottom of the trench gate structure extending along a first direction is spaced apart and adjacent to the shielding layer. The first direction and the second direction are parallel to the first surface of the semiconductor layer. The first direction and the second direction form an angle that is not zero.
5. The semiconductor device according to claim 4, wherein: The shielding layer includes a plurality of beam-like structures extending along a second direction, and the plurality of beam-like structures are arranged at intervals along a first direction, and the second direction is parallel to the first surface of the semiconductor layer.
6. The semiconductor device according to claim 5, wherein: An angle between the first direction and the second direction is greater than 45° and less than 135°.
7. The semiconductor device according to claim 5, wherein: Along the first direction, the transistor region between two adjacent beam-like structures and an adjacent beam-like structure form a cell region. In the cell region, a width of the transistor region along a first direction is greater than or equal to a width of the beam-shaped structure.
8. The semiconductor device according to claim 7, wherein: In the cell region, the ion doping concentration of the shielding layer is increased to reduce the width of the beam-like structure.
9. The semiconductor device according to claim 7 or 8, wherein: The ratio of the width of the beam-like structure to the spacing width of the spacing area is greater than or equal to 1 / 3 and less than or equal to 1.
10. The semiconductor device according to claim 9, wherein The semiconductor layer further comprises: A source region, located between adjacent trench gate structures, extending from the first surface to the second surface, with one side adjacent to a sidewall of one of the trench gate structures; A body region, located between adjacent trench gate structures, wherein two sides of the body region are adjacent to side walls of the adjacent trench gate structures respectively, and a portion of an upper surface of the body region is adjacent to a lower surface of the source region; The epitaxial layer is located between the body region and the second surface of the semiconductor layer, wherein the epitaxial layer separates the adjacent beam-shaped structures and is adjacent to the lower surface of the body region.
11. The semiconductor device according to claim 10, wherein: The ion doping concentration of the transistor region is greater than the ion doping concentration of the epitaxial layer between the bottom surface of the shielding layer and the second surface.
12. The semiconductor device according to claim 10, wherein: The shielding layer and the body region are of the second conductivity type, and the epitaxial layer is of the first conductivity type.
13. The semiconductor device according to claim 12, wherein: The ion doping concentration of the shielding layer is greater than the ion doping concentration of the body region.
14. The semiconductor device according to claim 10, wherein: A distance between a lower surface of the trench gate structure and the first surface is greater than a distance between a lower surface of the body region and the first surface.
15. The semiconductor device according to claim 1, wherein The semiconductor layer includes a SiC semiconductor layer or a Si semiconductor layer.