Ultra-steep sub-threshold slope transistor and preparation method thereof

Abstract

The invention discloses an ultra-steep sub-threshold slope transistor and a preparation method thereof, and belongs to the technical field of integrated circuits. An ultra-steep sub-threshold slope transistor is realized by using a superlattice stacked high-kappa gate dielectric, the superlattice stacked high-kappa gate dielectric comprises a plurality of HfO2 / ZrO2 / HfO2 stacking units which are stacked together, and an insertion layer is arranged between every two adjacent stacking units. Growing the superlattice stacked high-kappa gate dielectric by adopting an atomic layer deposition method, performing annealing treatment, and adjusting the gate dielectric interface, the electric leakage characteristic and the proportion of a ferroelectric quadrature phase to an antiferroelectric tetragonal phase by adjusting the type of an insertion layer and / or adjusting an oxygen source and pulse time thereof during growth, so as to obtain the superlattice stacked high-kappa gate dielectric. An ultra-steep sub-threshold slope transistor with a high on-off ratio is achieved. Compared with a traditional transistor, the transistor provided by the invention has higher on-state current, lower sub-threshold swing and smaller electric leakage.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and relates to low-power dynamic random access memory devices and logic devices, and in particular to an ultra-steep subthreshold slope transistor based on a superlattice stacked high-κ gate dielectric and a preparation method thereof. Background Art

[0002] With the development of technology, the demand for integrated circuits continues to increase. In the field of information technology and electronic equipment, the demand for higher performance and lower power consumption is growing, especially in the field of storage and logic. The leakage current of traditional transistors is mainly limited by mechanisms such as the Hall effect and thermal emission, and it is difficult to achieve a relatively small subthreshold swing. Ultra-steep subthreshold slope transistors can reduce the operating voltage required by integrated circuits by introducing new materials, structures and processes to achieve more ideal characteristics, thereby achieving lower power consumption. Traditional ultra-steep subthreshold slope transistors mainly include tunneling transistors and ferroelectric negative capacitance transistors. The on-state current of tunneling transistors is too low, resulting in a slow transmission speed from zero to one. Ferroelectric negative capacitance transistors require the matching of the ferroelectric part and the dielectric part to be adjusted, making it difficult to achieve a uniform threshold voltage and without sufficient κ, it is difficult to achieve faster signal transmission. Summary of the invention

[0003] The purpose of the present invention is to provide an ultra-steep subthreshold slope transistor and a preparation method thereof, which adopts a superlattice stacking high-κ gate dielectric to achieve a steady-state capacitance enhancement effect, thereby realizing a low-power transistor with low subthreshold swing and high on-state current.

[0004] The technical solution of the present invention is as follows:

[0005] A super-steep subthreshold slope transistor, characterized in that the gate dielectric layer of the transistor is a superlattice stacked high-κ gate dielectric, including a plurality of HfO2 / ZrO2 / HfO2 stacked units stacked together, with an insertion layer between two adjacent stacked units; in the HfO2 / ZrO2 / HfO2 stacked units, the upper and lower layers are HfO2, and the middle layer is ZrO2; the insertion layer is selected from one or more of the following materials: aluminum oxide, lanthanum oxide, silicon oxide, beryllium oxide, titanium oxide, tantalum oxide, yttrium oxide, and tungsten oxide.

[0006] Preferably, the HfO2 / ZrO2 / HfO2 stacking unit is grown by atomic layer deposition (ALD), wherein the HfO2 layer is grown for 4 to 6 cycles and has a thickness of 0.4 to 0.6 nm when ALD is used to prepare the HfO2 layer; and the ZrO2 layer is grown for 12 to 17 cycles and has a thickness of 1.2 to 1.7 nm when ALD is used to prepare the ZrO2 layer. The molar ratio of HfO2 to ZrO2 in each stacking unit is preferably 2:3.

[0007] Preferably, the insertion layer is also grown by ALD and has a thickness of 0.1-0.2 nm.

[0008] The ultra-steep subthreshold slope transistor using a superlattice stacked high-κ gate dielectric in the present invention is not limited to a particular structure, and can be a back-gate, top-gate, double-gate, surround-gate, or fin-gate field effect transistor. In one embodiment of the present invention, a double-gate field effect transistor with a back-gate and top-gate structure is prepared, including a substrate and a back-gate electrode, a back-gate dielectric layer, a channel layer, a top-gate dielectric layer, and a top-gate electrode stacked sequentially on the substrate, with source and drain electrodes connected at both ends of the channel; wherein the back-gate dielectric layer and the top-gate dielectric layer are both the superlattice stacked high-κ gate dielectric.

[0009] In the ultra-steep subthreshold slope transistor, the channel layer can be new materials such as silicon, germanium, gallium arsenide, gallium nitride, two-dimensional materials and oxide semiconductors, and the channel layer is prepared by mechanical stripping, chemical vapor deposition, magnetron sputtering, atomic layer deposition laser pulse deposition and other technologies; the gate metal and source and drain metal can be high-temperature resistant metals such as titanium nitride, platinum, tungsten, palladium, etc., and the source and drain metal can also be a series of metals and semiconductors that are not resistant to high temperatures such as nickel, molybdenum, oxides, etc.

[0010] The preparation of the high-κ gate dielectric of the superlattice stack is carried out by atomic layer deposition and rapid thermal annealing. HfO2 and ZrO2 materials are grown in the superlattice stack, and the leakage current and the ratio of the ferroelectric orthorhombic phase to the antiferroelectric tetragonal phase of the gate dielectric are adjusted by the insertion layer. The insertion layer is doped after annealing, and different doping elements and doping contents control the stability of different phases of HfO2 / ZrO2 / HfO2 after annealing, thereby adjusting the ratio of the orthorhombic phase to the tetragonal phase in the mixture. For example, the doping of La elements is conducive to the formation of the ferroelectric orthorhombic phase, and the doping of Al elements can be conducive to the formation of the antiferroelectric tetragonal phase. The ratio of the ferroelectric orthorhombic phase and the antiferroelectric tetragonal phase of the HfO2 / ZrO2 / HfO2 stacking part is adjusted by doping. The interface, leakage current, and the ratio of the orthorhombic phase to the tetragonal phase are adjusted by adjusting the oxygen source and its pulse time, and the formation of the monoclinic phase is controlled. The oxygen source and oxygen source pulse time of HfO2 and ZrO2 in contact with the channel are used to adjust the interface. For example, for the oxide channel, when growing the gate dielectric in contact with the channel, O3 or O plasma oxygen source is used, and the oxygen source pulse time is 0.1s to 30s; when growing the gate dielectric in other parts, H2O is used as the oxygen source, and the oxygen source pulse time is 0.1s to 30s. The oxygen source and oxygen source pulse time of HfO2, ZrO2 and the insertion layer are adjusted to adjust the carbon content and oxygen vacancies in the gate dielectric, thereby adjusting the leakage characteristics and adjusting the ratio of the orthorhombic phase to the tetragonal phase. Different stacking methods are combined to adjust the channel material to achieve the preparation of ultra-steep subthreshold slope transistors. Annealing after the deposition of the high-κ gate dielectric film or annealing after the electrode preparation is completed makes the gate dielectric crystallized.

[0011] The present invention proposes to use superlattice stacked HfO2 and ZrO2 high-κ materials as gate dielectrics, and adjust the threshold, dielectric constant, and leakage characteristics by adjusting the oxygen source and the oxygen source pulse time during ALD growth to achieve an ultra-steep subthreshold slope transistor with a high switching ratio. Compared with traditional transistors, the transistor of the present invention has a higher on-state current, a lower subthreshold swing, and a smaller leakage. The ultra-steep subthreshold slope transistor based on superlattice stacked high-κ gate dielectrics and the preparation method thereof of the present invention have the following advantages:

[0012] (1) Using superlattice to grow gate dielectrics and enhance surface stress, thereby achieving a stable capacitance enhancement effect under the mixing of ferroelectric and antiferroelectric properties;

[0013] (2) Based on the mixing of ferroelectric and antiferroelectric phases, stable capacitance enhancement is achieved within a voltage range, which increases the gate capacitance while reducing the subthreshold swing, and achieves lower operating voltage and larger on-state current;

[0014] (3) Provide multiple adjustment methods, such as adjusting the oxygen source pulse and pulse time, the type of insertion layer, the interface between the channel and the gate dielectric, the capacitance and leakage of the gate dielectric, and have a wide range of applications;

[0015] (4) Superlattice high-κ materials are resistant to high temperatures and can withstand back-end high-temperature processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 Schematic diagram of ALD growth of high-κ gate dielectric in Example 1, wherein: 10 is a HfO2 layer, 9 is a ZrO2 layer, and 8 is an intermediate insertion layer (which may be La2O3, SiO2, Al2O3, BeO, etc.).

[0017] Figure 2 This is a schematic diagram of the structure of the ultra-steep subdomain slope transistor of Example 2, wherein: 1 is a high-resistance silicon substrate, 2 is SiO2, 3 is a back gate superlattice high-κ dielectric, 4 is a channel material, 5 is titanium nitride, 6 is a top gate superlattice high-κ gate dielectric, and 7 is tungsten.

[0018] Figure 3 This is a schematic diagram of the preparation process of the superlattice stacked dual-gate self-aligned transistor in Example 2, which has a total of 14 steps, of which Step 5 and Step 11 are for the preparation of high-κ gate dielectrics, which can be adjusted according to the characteristics of the channel and source and drain metals. DETAILED DESCRIPTION

[0019] In conjunction with the accompanying drawings, the following describes a method for preparing a high-κ gate dielectric of a superlattice stack and a method for preparing an ultra-steep subthreshold slope transistor through an embodiment. In the following description, many details are set forth to facilitate a full understanding of the present invention, but the present invention can be implemented in many other ways different from the description. In summary, the present invention is not limited to the embodiments disclosed below.

[0020] Example 1: Preparation of high-κ gate dielectrics in superlattice stacks

[0021] The gate dielectric is grown in situ by atomic layer deposition (ALD). The hafnium source used is tetrakis(ethylmethylamino)hafnium, the zirconium source is tetrakis(ethylmethylamino)zirconium, the lanthanum source is tri(N,N'-diisopropylformamidinium)lanthanum, the aluminum source is trimethylaluminum, the silicon source is (dimethylamino)silicon, the beryllium source is diethylberyllium, the available oxygen sources include H2O, O3, and O plasma, and the ALD growth temperature is 300°C.

[0022] Figure 1 The specific growth method is shown. First, 4 cycles of HfO2 are grown in the area in contact with the channel. The threshold voltage and leakage characteristics of the device are adjusted by adjusting the oxygen source and / or oxygen source pulse time of the first 4 cycles or the first multiple cycles. For oxide channels (such as IGZO, ITO, InO, ITWO, IZO, etc.), oxygen vacancies can be introduced or filled by adjusting the pulse time of O3 or O plasma oxygen source, thereby achieving the effect of adjusting the threshold; for silicon channels, H2O is used as the oxygen source to obtain a thinner interface SiO2 to achieve a higher EOT, and O3 or oxygen plasma is used as the oxygen source to obtain a better interface with better dielectric properties.

[0023] Then 12 cycles of ZrO2 are grown, in which the oxygen source and pulse time can be adjusted to adjust the channel threshold and interface in the first few cycles.

[0024] Then, 4 more cycles of HfO2 were grown. The cycle of HfO2:ZrO2:HfO2 of 4:12:4 is a single superlattice cycle, in which the molar ratio of Hf to Zr is 4 to 6.

[0025] Then, a cycle of insertion layers is grown as needed. If you want to have smaller leakage, choose Al2O3, SiO2 or BeO as the insertion layer. The insertion layer has a higher bandgap width, which can reduce leakage, and can increase the tetragonal phase ratio, adjust the term ratio in the gate dielectric to achieve better ferroelectric and antiferroelectric mixed interweaving, and realize the function of steady-state negative capacitance; La2O3 insertion layer can increase the orthorhombic phase ratio, reduce the monoclinic phase ratio of low dielectric constant, and at the same time increase the gate dielectric bandgap width, reduce leakage, and increase reliability. The high κ and leakage characteristics of the overall gate dielectric stack can be achieved through the combination of different insertion layers.

[0026] ALD repeatedly grows HfO2 / ZrO2 / HfO2, insertion layer, HfO2 / ZrO2 / HfO2, insertion layer, ..., until the desired thickness is reached to achieve the desired high κ and required leakage characteristics, wherein the insertion layer can be combined, and the oxygen source and its pulse time can also be selected according to the needs of the gate dielectric. By adjusting the type of insertion layer, the oxygen source and the pulse time, the ratio of the ferroelectric orthorhombic phase to the antiferroelectric tetragonal phase can be adjusted to achieve a stable capacitance enhancement effect near the transistor operating voltage. With a steady-state negative capacitance, an ultra-steep subthreshold slope transistor is realized.

[0027] After the gate dielectric or gate metal is grown by ALD, rapid thermal annealing is performed, and annealing is performed at 500° C. for 60 seconds in a forming gas or nitrogen to form a stable ferroelectric antiferroelectric mixed high-κ gate dielectric.

[0028] Example 2: Transistor Preparation

[0029] Figure 2 The transistor structure of the double-gate superlattice stacked high-κ gate dielectric is shown, which includes high-resistance silicon substrate 1, SiO2 layer, back gate electrode, back gate superlattice high-κ dielectric 3, channel material 4, top gate superlattice high-κ dielectric 6, top gate electrode, and source and drain electrodes at both ends of the channel. The preparation process of the transistor of the double-gate superlattice stacked high-κ gate dielectric is as follows: Figure 3 As shown, including:

[0030] Step 1: Substrate Cleaning

[0031] The high-resistance single-crystal silicon substrate with a SiO2 layer on the surface is ultrasonically cleaned with RCA1 solution, acetone, isopropanol, and deionized water to clean organic matter and particles on the surface of the substrate, and then blown dry with high-purity nitrogen.

[0032] Step 2: Back gate etching

[0033] Through the photoresist mask, this step can use photolithography, electron beam lithography and other methods to define the pattern, ICP SF6 / O2 etches out the groove, and the groove depth is no greater than the thickness of the SiO2 layer.

[0034] Step 3: Back Gate Metal Deposition

[0035] In this example, magnetron TiN / W with a thickness of 10nm / 20nm is used as the back gate metal.

[0036] Step 4: CMP polishing, annealing, and removal of metal outside the grooves to make the surface smooth.

[0037] Step 5: Back-gate superlattice high-κ gate dielectric deposition

[0038] In this example, ALD is used to grow the back gate dielectric, growing HfO2 / ZrO2 / HfO2 / Al2O3 / HfO2 / ZrO2 / HfO2 / HfO2 / ZrO2 / HfO2, wherein the first cycle is grown using H2O low oxygen source pulse time, and the last 4 cycles are grown using O3 medium-length oxygen source pulse time.

[0039] Step 6: Deposit channel material

[0040] In this example, 3nm indium tin oxide is used as the channel by magnetron sputtering. In practice, the channel layer can also be made of new materials such as silicon, germanium, gallium arsenide, gallium nitride, two-dimensional materials, oxide semiconductors, etc. The channel layer is prepared by mechanical stripping, chemical vapor deposition, magnetron sputtering, atomic layer deposition, etc. If the channel is resistant to high temperatures, annealing is performed after the complete transistor preparation. If the transistor is not resistant to high temperatures, N2 rapid thermal annealing for 60s is performed after the fifth step is completed to crystallize, and then the channel material is deposited or transferred.

[0041] Step 7: Deposit source and drain metal.

[0042] In this example, magnetron sputtered TiN is used as the source and drain contact metal.

[0043] Step 8: Spin-coat HSQ for masking.

[0044] Step 9: Expose and develop HSQ to form a top gate region.

[0045] Step 10: Top gate metal etching, using Cl2 / AlCl3 to etch the TiN in the top gate area to expose the channel.

[0046] Step 11: Top-gate superlattice high-κ gate dielectric deposition

[0047] In this example, ALD is used to grow the back gate dielectric, growing HfO2 / ZrO2 / HfO2 / Al2O3 / HfO2 / ZrO2 / HfO2 / Al2O3 / HfO2 / ZrO2 / HfO2. The first group of HfO2 is prepared by long pulse O3 growth, and the subsequent cycles are prepared by short pulse H2O growth.

[0048] Step 12: Source and drain via etching

[0049] The top superlattice stacked high-κ gate dielectric is etched by ICP SF6 / O2 and etched to the source and drain TiN regions to form self-alignment.

[0050] Step 13: Top gate deposition TiN / W forms top gate metal and source-drain metal contacts, and W deposition prevents TiN from oxidation.

[0051] Step 14: CMP top gate flattening removes excess metal on the top, isolates the source and drain from the gate, and forms a complete dual-gate transistor. After preparation, rapid annealing is performed at 500°C in N2 atmosphere for 60s to crystallize the gate and fill the damage to the channel and metal during the preparation process.

[0052] If the channel material or gate metal is not resistant to high temperature, annealing can be performed after depositing the gate dielectric film in step 5, and annealing in step 14 can be omitted. In this case, step 11 can achieve crystallization without annealing by adjusting the gate dielectric thickness, oxygen source and pulse time, or directly utilize the high κ characteristics of HfO2 / ZrO2 mixed gate dielectric.

Claims

1. An ultra-steep subthreshold slope transistor, characterized in that: The gate dielectric layer of the transistor is a superlattice stacked high-κ gate dielectric, including a plurality of HfO2 / ZrO2 / HfO2 stacking units stacked together, with an insertion layer between two adjacent stacking units; in the HfO2 / ZrO2 / HfO2 stacking unit, the upper and lower layers are HfO2, and the middle layer is ZrO2; the insertion layer is selected from one or more of the following materials: aluminum oxide, lanthanum oxide, silicon oxide, beryllium oxide, titanium oxide, tantalum oxide, yttrium oxide and tungsten oxide.

2. The ultra-steep subthreshold slope transistor according to claim 1, characterized in that: In the HfO2 / ZrO2 / HfO2 stacking unit, the thickness of each HfO2 layer is 0.4-0.6 nm, the thickness of the ZrO2 layer is 1.2-1.7 nm; and the thickness of the insertion layer is 0.1-0.2 nm.

3. The ultra-steep subthreshold slope transistor according to claim 2, characterized in that: The molar ratio of HfO2 to ZrO2 in each HfO2 / ZrO2 / HfO2 stacking unit is 2:

3.

4. The ultra-steep subthreshold slope transistor according to claim 1, characterized in that: The transistor is a back-gate, top-gate, double-gate, wrap-gate or fin-gate field effect transistor.

5. The ultra-steep subthreshold slope transistor according to claim 1, characterized in that: The transistor is a double-gate field effect transistor with a back-gate and top-gate structure, comprising a substrate and a back-gate electrode, a back-gate dielectric layer, a channel layer, a top-gate dielectric layer, and a top-gate electrode stacked in sequence on the substrate, with source and drain electrodes connected at both ends of the channel; The back gate dielectric layer and the top gate dielectric layer are both the superlattice stacked high-κ gate dielectrics.

6. The ultra-steep subthreshold slope transistor according to claim 1, characterized in that: The HfO2 / ZrO2 / HfO2 stacking unit is grown by an atomic layer deposition method, wherein the HfO2 layer is grown for 4 to 6 cycles, and the ZrO2 layer is grown for 12 to 17 cycles.

7. The method for preparing the ultra-steep subthreshold slope transistor according to any one of claims 1 to 6, characterized in that: The superlattice stacked high-κ gate dielectric is grown by an atomic layer deposition method and annealed. The ratio of the ferroelectric orthorhombic phase to the antiferroelectric tetragonal phase and the leakage characteristics in the gate dielectric are adjusted by adjusting the type of the insertion layer and / or by adjusting the oxygen source and its pulse time during growth, so as to realize the function of steady-state negative capacitance.

8. The preparation method according to claim 7, characterized in that: When the gate dielectric is grown in situ using atomic layer deposition, the hafnium source is tetrakis(ethylmethylamino)hafnium, the zirconium source is tetrakis(ethylmethylamino)zirconium, the lanthanum source is tri(N,N'-diisopropylformamidinium)lanthanum, the aluminum source is trimethylaluminum, the silicon source is (dimethylamino)silicon, the beryllium source is diethylberyllium, and the oxygen source is selected from H2O, O3 and O plasma.

9. The preparation method according to claim 7, characterized in that: When growing the gate dielectric in contact with the channel, the interface is adjusted by adjusting the oxygen source and its pulse time.

10. The preparation method according to claim 9, characterized in that: For the oxide channel, when growing the gate dielectric in contact with the channel, O3 or O plasma oxygen source is used, and the oxygen source pulse time is 0.1s to 30s; when growing the gate dielectric in other parts, H2O is used as the oxygen source, and the oxygen source pulse time is 0.1s to 30s.

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