Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. According to one embodiment, a semiconductor device includes a first electrode, a second electrode separated from the first electrode, and a semiconductor portion provided between the first electrode and the second electrode. The semiconductor section has a first region, a second region, and a third region provided between the first region and the second region in a second direction perpendicular to a first direction from the first electrode toward the second electrode. The third region includes a tenth semiconductor region of the first conductivity type provided on the first electrode, and a current blocking region provided on the tenth semiconductor region and between the sixth semiconductor region and the ninth semiconductor region in the second direction.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Japanese Patent Application No. 2023-159965 (filing date: September 25, 2023) as a basic application. The present application incorporates the entire contents of the basic application by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] There is known a semiconductor device in which an IGBT and a diode connected in parallel to each other are provided on a single semiconductor substrate.

[0005] There is a semiconductor device that is provided with two regions that perform different actions. This semiconductor device is called, for example, an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor). The RC-IGBT has an IGBT region that performs the action of the IGBT and a diode region that performs the action of the diode. Sometimes a specified region is provided between the IGBT region and the diode region so that the action of the IGBT and the action of the diode do not affect the action of the other. By providing this region, for example, it is possible to suppress the current flowing from the IGBT region to the diode region, so that it does not affect the action of the semiconductor device. However, in order to fully suppress the current, it is necessary to increase the size of the region. If the size is increased, the size of the semiconductor device will also increase. Summary of the invention

[0006] According to an embodiment, a semiconductor device includes a first electrode, a second electrode separated from the first electrode, and a semiconductor portion. The semiconductor portion is provided between the first electrode and the second electrode. The semiconductor portion includes a first region, a second region, and a third region provided between the first region and the second region in a second direction perpendicular to the first direction from the first electrode toward the second electrode. The semiconductor portion is provided on the first electrode. The semiconductor portion is provided below the second electrode. The first region includes: a first semiconductor region of the first conductivity type; a second semiconductor region of the second conductivity type, arranged on the first semiconductor region; a third semiconductor region, arranged on the second semiconductor region, and having a lower impurity concentration of the first conductivity type than the first semiconductor region; a gate electrode, which is opposite to the third semiconductor region in the second direction via a gate insulating layer; a fourth semiconductor region of the second conductivity type, arranged on the third semiconductor region, and having a higher impurity concentration of the second conductivity type than the second semiconductor region; and a sixth semiconductor region of the second conductivity type, arranged between the first semiconductor region and the second semiconductor region in the first direction. The second region includes: a seventh semiconductor region of the second conductivity type having a higher second conductivity type impurity concentration than the second semiconductor region; the second semiconductor region is disposed on the seventh semiconductor region; an eighth semiconductor region of the first conductivity type is disposed on the second semiconductor region and is electrically connected to the second electrode; a ninth semiconductor region of the second conductivity type is disposed between the second semiconductor region and the seventh semiconductor region in the first direction and has a second conductivity type impurity concentration higher than the second semiconductor region and lower than the seventh semiconductor region; and a conductive portion electrically connected to the second electrode, a portion of which is opposed to the eighth semiconductor region via an insulating layer in the second direction. The third region includes: a tenth semiconductor region of the first conductivity type disposed on the first electrode; and a current blocking region disposed on the tenth semiconductor region and disposed between the sixth semiconductor region and the ninth semiconductor region in the second direction.

[0007] According to the embodiment of the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device which can suppress an increase in size and suppress a current flowing from one operating region to another operating region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a plan view showing an example of a semiconductor device according to an embodiment.

[0009] Figure 2 yes Figure 1B1-B2 section view.

[0010] Figure 3 This is a flowchart showing an example of a method for manufacturing a semiconductor device according to an embodiment.

[0011] Figure 4 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment.

[0012] Figure 5 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment.

[0013] Figure 6 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment.

[0014] Figure 7 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment.

[0015] Figure 8 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment.

[0016] Fig. 9 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment.

[0017] Fig.10 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment.

[0018] Fig.11 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment.

[0019] Fig.12 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment.

[0020] Fig.13 The diagram shows a semiconductor portion manufactured through the manufacturing process of the semiconductor device according to the embodiment. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0022] The drawings are schematic or conceptual drawings, and the relationship between the thickness and width of each part, the ratio of the size between the parts, etc. are not necessarily the same as in reality. Even when the same part is shown, the sizes and ratios of each other may be shown differently depending on the drawings.

[0023] In the present specification and each drawing, the same elements as those already described are denoted by the same reference numerals, and detailed description thereof will be appropriately omitted.

[0024] In the following description, n + 、n、n － and p + The symbols n and p indicate the relative high and low impurity concentrations in each conductivity type. + Compared with n, the impurity concentration of n-type is relatively high. － Indicates that the impurity concentration of n-type is relatively low compared to n. + Indicates that the p-type impurity concentration is relatively high compared to the p-type. － Indicates that the p-type impurity concentration is relatively lower than that of p.

[0025] Each embodiment described below may be implemented by inverting the p-type and n-type of each semiconductor region.

[0026] Figure 1 It is a top view of a semiconductor device according to an embodiment.

[0027] Figure 2 yes Figure 1 B1-B2 section view.

[0028] The semiconductor device involved in the embodiment is an RC-IGBT. Figure 1 and Figure 2 As shown in FIG. 1 , the semiconductor device 100 according to the embodiment includes a collector electrode 31 (first electrode), an emitter electrode 32 (second electrode), a gate pad 33, and a semiconductor portion 34. The semiconductor portion 34 includes a p + type (first conductivity type) collector region 1A (first semiconductor region), p + Type (first conductivity type) collector region 1B (tenth semiconductor region), n － type (second conductivity type) base region 2 (second semiconductor region), p-type base region 3 (third semiconductor region), n + type emitter region 4 (fourth semiconductor region), p + type contact region 5 (fifth semiconductor region), n + type cathode region 7 (seventh semiconductor region), p-type anode region 8 (eighth semiconductor region), p + type anode region 9, n-type buffer region 10A (sixth semiconductor region), n-type buffer region 10B (ninth semiconductor region), n-type barrier region 11, oxygen implanted region 12 (current blocking region), gate electrode 20 and conductive portion 21.

[0029] In the description of the embodiment, an XYZ orthogonal coordinate system is used. The direction from the collector electrode 31 toward the emitter electrode 32 is set as the Z direction (first direction). Two directions perpendicular to the Z direction and orthogonal to each other are set as the X direction (second direction) and the Y direction (third direction). In addition, for the sake of description, the direction from the collector electrode 31 toward the emitter electrode 32 is called "up", and the opposite direction is called "down". These directions are based on the relative positional relationship between the collector electrode 31 and the emitter electrode 32, and have nothing to do with the direction of gravity.

[0030] like Figure 1 As shown, an emitter electrode 32 and a gate pad 33 are provided on the upper surface of the semiconductor device 100. The emitter electrode 32 and the gate pad 33 are separated from each other. For example, a plurality of emitter electrodes 32 are provided in the Y direction. A gate wiring 33a is provided around each emitter electrode 32. The gate wiring 33a is electrically connected to the gate pad 33.

[0031] like Figure 2 As shown, the semiconductor portion 34 of the semiconductor device 100 includes an IGBT region R1, a diode region R2, and a separation region R3 provided between the IGBT region R1 and the diode region R2 in the X direction perpendicular to the Z direction from the collector electrode 31 toward the emitter electrode 32. Figure 1 In the example shown, a plurality of IGBT regions R1, diode regions R2, and separation regions R3 are provided in the X direction and the Y direction, respectively. The IGBT regions R1 and the diode regions R2 are alternately provided in the X direction. The separation region R3 is provided between the IGBT region R1 and the diode region R2.

[0032] like Figure 2 As shown, a collector electrode 31 is provided on the lower surface of the semiconductor device 100 . The collector electrode 31 and the emitter electrode 32 are separated from each other. A plurality of IGBT regions R1 , a plurality of diode regions R2 , and a separation region R3 are located between the collector electrode 31 and the emitter electrode 32 .

[0033] like Figure 2 As shown, each IGBT region R1 is provided with a p + Type collector region 1A, n － A portion of the p-type base region 2, the p-type base region 3, the p-type contact region 5a, and the n + Type emitter region 4, p + type contact region 5 , n-type buffer region 10A, n-type barrier region 11 and gate electrode 20 .

[0034] p + The collector region 1A is provided on a portion of the collector electrode 31 and is electrically connected to the collector electrode 31.－ A portion of the base region 2 is provided on the p + The p-type collector region 1A is provided on the p-type base region 3. － The portion of the base region 2 is located above the p + The gate electrode 20 is opposed to the p-type base region 3 via a gate insulating layer 20a in the X direction.

[0035] In p + Type collector region 1A and n － The n-type buffer region 10A is provided between parts of the n-type base region 2. The n-type impurity concentration of the n-type buffer region 10A is lower than that of the n-type base region 2. + The n-type impurity concentration of the cathode region 7 is higher than that of n － The n-type impurity concentration of the n-type base region 2 is reduced. By providing the n-type buffer region 10A, the n-type buffer region 10A can more reliably suppress the n-type impurity concentration of the n-type base region 2. － Extension of the depletion layer in the type base region 2.

[0036] like Figure 2 As shown, n + The p-type emitter region 4 is provided on the p-type base region 3. The emitter electrode 32 is provided on the collector electrode 31. + An emitter electrode 32 is provided on the emitter region 4. + The emitter region 4 is connected to the p + Type contact areas 5 are arranged side by side. + The p-type contact region 5 may be a p-type contact region. In the Z direction, a p-type contact region 5a is provided between the p-type base region 3 and the emitter electrode 32. + The p-type contact region 5 is disposed on the p-type base region 3 and is connected to the n-type base region 3 in the X direction. + The emitter region 4 is arranged side by side. + The p-type impurity concentration of the p-type contact region 5 is higher than the p-type impurity concentration of the p-type base region 3 .

[0037] The end portion of the gate electrode 20 in the Y direction is electrically connected to the gate wiring 33 a .

[0038] like Figure 2 As shown, the p-type base region 3 and n + Type emitter region 4, p + A plurality of p-type contact regions 5 and gate electrodes 20 are provided in the X direction. A plurality of p-type base regions 3 and a plurality of gate electrodes 20 are provided in stripe shapes and extend in the Y direction.

[0039] Each diode region R2 is provided with n + Type cathode region 7, n－ another part of the p-type base region 2, the p-type anode region 8, the p + n-type anode region 9, n-type buffer region 10B and conductive portion 21. + The cathode region 7 is disposed on another portion of the collector electrode 31 and is electrically connected to the collector electrode 31. － Another part of the type base region 2 is arranged at n + The p-type cathode region 7 is disposed on the p-type anode region 8. － The other part of the type base region 2 is located on n + type cathode region 7.

[0040] In n + Type cathode region 7 and n － The n-type buffer region 10B is provided between the other part of the n-type base region 2. The n-type impurity concentration of the n-type buffer region 10B is lower than that of the n-type base region 2. + The n-type impurity concentration of the cathode region 7 is higher than that of n － The n-type impurity concentration of the n-type base region 2 is reduced. By providing the n-type buffer region 10B, the n-type buffer region 10B can more reliably suppress the n-type impurity concentration of the n-type base region 2. － Extension of the depletion layer in another part of the type base region 2.

[0041] The conductive portion 21 faces the p-type anode region 8 via the insulating layer 21a in the X direction. + The p-type anode region 9 is disposed on the p-type anode region 8. + The p-type impurity concentration of the p-type anode region 9 is higher than the p-type impurity concentration of the p-type anode region 8. + The type anode region 9 and the conductive portion 21 are electrically connected to the emitter electrode 32 .

[0042] p-type anode region 8, p + The plurality of p-type anode regions 9 and the plurality of conductive portions 21 are provided in the X direction. + The anode region 9 and the plurality of conductive portions 21 are each provided in a strip shape and extend in the Y direction.

[0043] In each separation region R3, a p + p-type collector region 1B, p-type contact region 5a, p-type anode region 8, p + Type anode region 9, n － The other part of the type base region 2, the conductive portion 21 and the oxygen implantation region 12. + The p-type collector region 1B is provided on another portion of the collector electrode 31 and is electrically connected to the collector electrode 31. The oxygen implantation region 12 is provided on the p-type collector region 1B. +Type collector region 1B. － Another part of the p-type base region 2 is provided on the oxygen implanted region 12. The p-type anode region 8, the p-type contact region 5a, and the conductive portion 21 are provided in the same manner as in each diode region R2.

[0044] The oxygen-implanted region 12 is provided between the n-type buffer region 10A and the n-type buffer region 10B in the X direction. In the Z direction, the thickness of the oxygen-implanted region 12 is thicker than the thickness of each of the n-type buffer region 10A and the n-type buffer region 10B. In the present embodiment, the case where oxygen is injected into the oxygen-implanted region 12 is described, but other materials may be included instead of oxygen. That is, for example, in the case where the n-type buffer region 10A is mainly made of silicon, a material that reacts with silicon and exhibits insulating properties may be injected. The material may be, for example, any one of carbon, nitrogen, and silicon nitride.

[0045] P + Type collector region 1A, 1B, n － Type base area 2, n + An example of the impurity concentrations in the n-type cathode region 7 , the n-type buffer region 10A, the n-type buffer region 10B, and the oxygen implanted region 12 will be described.

[0046] p + The impurity concentration of the first conductivity type in the collector regions 1A and 1B is 1×10 17 cm 3 ~1×10 18 cm 3 .n － The second conductivity type impurity concentration in the base region 2 is 1×10 14 cm 3 .n + The impurity concentration of the second conductivity type in the cathode region 7 is 1×10 18 cm 3 ~2×10 20 cm 3 The second conductivity type impurity concentration in the n-type buffer region 10A and the n-type buffer region 10B is 1×10 16 cm 3 The oxygen implanted region 12 contains the second conductivity type impurity concentration and oxygen as impurities. The concentration in the oxygen implanted region 12 related to the second conductivity type impurity is 1×10 16 cm 3 , for oxygen, the concentration can be 3×10 17 cm 3 ~3×10 19 cm 3 , but it is preferably set to 1×10 18 cm3 above.

[0047] The operation of the semiconductor device 100 will be described.

[0048] In a state where a positive voltage is applied to the collector electrode 31 relative to the emitter electrode 32, a voltage equal to or higher than the threshold is applied to the gate electrode 20. As a result, a channel (inversion layer) is formed in the p-type base region 3. Electrons pass through the channel from the n + Type emitter region 4 to n － type base region 2 flows, holes flow from p + The collector region 1A is n － Type base area 2 flows. － The carrier density accumulated in the type base region 2 increases, and conductivity modulation occurs. － The resistance of the p-type base region 2 is greatly reduced, and the IGBT region R1 is turned on. Then, when the voltage applied to the gate electrode 20 becomes lower than the threshold, the channel in the p-type base region 3 disappears, and the IGBT region R1 is switched to the off state.

[0049] After the IGBT region R1 is switched to the off state, － The electrons accumulated in the base region 2 pass through the p + The holes are discharged from the p-type collector region 1 to the collector electrode 31 . The holes are discharged from the p-type base region 3 to the emitter electrode 32 .

[0050] For example, a bridge circuit is formed by a plurality of semiconductor devices 100. When one semiconductor device 100 is switched from an on state to an off state, an induced electromotive force is applied to the emitter electrode 32 of another semiconductor device 100 through the inductance component of the bridge circuit. As a result, in the other semiconductor device 100, the diode region R2 operates. Holes flow from the p-type anode region 8 to the n-type anode region 8. － type base region 2 flows, and electrons flow from n + Type cathode region 7 to n － The diode region R2 functions as a freewheeling diode (FWD).

[0051] In the semiconductor device 100, the concentration of oxygen in the oxygen-implanted region 12 in the separation region R3 is higher than that in the n-type buffer regions 10A and 10B. Therefore, the resistivity and crystal defect density of the oxygen-implanted region 12 become larger. As a result, the carrier lifetime (Life time) can be reduced. The crystal defect density can be defined, for example, by the number of defects generated in the manufacturing process or the number of foreign matter per unit area that is the cause thereof. The crystal defect density can be investigated, for example, by observing the cross section of the semiconductor device 100 using a TEM (transmitted electron microscope). In the TEM, the object of observation is, for example, at least one of a black spot at the cross section, a deep arrangement such as DLTS (Deep Level Transient Spectroscopy), a lattice defect, and a point defect.

[0052] In addition, when the semiconductor device 100 performs the above-described operation, the current flowing from the n-type buffer region 10A to the n-type buffer region 10B in the X direction can be greatly suppressed by the oxygen implantation region 12, for example. － The IGBT region R1 and the diode region R2 can be electrically separated from each other under the type base region 2.

[0053] For example, when the semiconductor device 100 performs IGBT operation, when the p + Before the built-in potential of n-type collector region 10 reaches a certain value, the current flowing from n-type buffer region 10A to n-type buffer region 10B can be suppressed by oxygen implanted region 12. Therefore, in semiconductor device 100, occurrence of unipolar operation can be suppressed.

[0054] In n － An n-type barrier region 11 may be provided between the p-type base region 2 and the p-type base region 3. By providing the n-type barrier region 11, when the IGBT region R1 is in the on state, the n-type barrier region 11 can be suppressed. － The discharge of holes accumulated in the type base region 2 can increase the n － The carrier density in the type base region 2 is reduced. Thus, the resistance when the IGBT region R1 is in the on state can be further reduced.

[0055] In the IGBT region R1, part of the plurality of gate electrodes 20 may be replaced by the conductive portion 21. By replacing part of the gate electrodes 20 by the conductive portion 21, when the IGBT region R1 is in the on state, n can be increased. － The carrier density in the type base region 2 is increased, thereby further reducing the resistance of the semiconductor device 100.

[0056] An example of the material of each component of the semiconductor device 100 is described.

[0057] p + Type collector region 1A, 1B, n － type base region 2, p-type base region 3, n + Type emitter region 4, p + Type contact area 5, n + type cathode region 7, p-type anode region 8, p + The n-type anode region 9, the n-type buffer regions 10A and 10B, and the n-type barrier region 11 include silicon, silicon carbide, gallium nitride, or gallium arsenide as semiconductor materials. When silicon is used as the semiconductor material, arsenic, phosphorus, or antimony can be used as the n-type impurity. Boron can be used as the p-type impurity.

[0058] The gate electrode 20 and the conductive portion 21 include conductive materials such as polysilicon. The gate insulating layer 20a and the insulating layer 21a include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The collector electrode 31, the emitter electrode 32, the gate pad 33, and the gate wiring 33a include metals such as aluminum.

[0059] Next, Figure 1 A method for manufacturing the semiconductor device 100 shown will be described.

[0060] Figure 3 1 is a flowchart showing an example of a manufacturing process of the semiconductor device 100 .

[0061] Figures 4 to 13 The diagrams show examples of cross sections of the semiconductor portions 100A to 100J in each manufacturing process.

[0062] First, the pre-process (ST101) is performed. The pre-process is to form n － The front process is a process for forming the IGBT region R1, the diode region R2, and the isolation region R3 on the type base region 2. In other words, the front process is a process before the back process of the RC-IGBT is performed. Figure 4 FIG. 2 shows an example of a cross section of a semiconductor unit 100A manufactured by a previous process. Figure 4 As shown, in the semiconductor portion 100A, the p-type base region 3 and the n + Type emitter region 4, p + type contact region 5, p-type anode region 8, p + The type anode region 9, the gate electrode 20, the conductive portion 21 and the emitter electrode 32 are formed on the n － type substrate area 2a.

[0063] Next, n ions are injected (ST102). N ions are impurities of the second conductivity type (n type in this embodiment), and are formed by ionizing phosphorus, for example. N ions are injected from the bottom of the semiconductor portion 100A in the Z direction. As a result, n ions are injected into the semiconductor portion 100A. － A portion of the n-type base region 2a forms the n-type buffer region 10a. The region of the n-type base region 2a where the n-type buffer region 10a is not formed is set as the n-type base region 2b. Figure 5 As shown, in the semiconductor unit 100B, n － An n-type buffer region 10a is provided below the n-type base region 2b. The second conductivity type impurity concentration of the n-type buffer region 10a is, for example, 1×10 16 cm 3 The second conductivity type impurity is implanted, for example, by three-step implantation to form an n-type buffer region 10a of a desired thickness. Here, three-step implantation is a method of performing ion implantation three times by changing the conditions of ion implantation. Thus, n ions can be implanted at three different depths in the Z direction.

[0064] Next, a resist is applied (ST103) and exposed (ST104). The resist is applied to the entire lower surface of the n-type buffer region 10a. Next, for example, the resist in the separation region R3 is exposed through a predetermined mask and then developed and removed. As a result, the resist applied to the lower surface of the semiconductor portion 100B disappears in the separation region R3. Figure 6 As shown, in the semiconductor portion 100C, the resist 41 is formed in the IGBT region R1, and the resist 42 is formed in the diode region R2. In other words, the resist provided on the lower surface of the semiconductor portion 100C forms an opening in the isolation region R3.

[0065] Next, oxygen ions are implanted (ST105). Oxygen ions are implanted into the opening of the semiconductor portion 100C in the isolation region R3. The implantation conditions of oxygen ions are, for example, 1500 kev at room temperature, 0°C, and 1×10 13 ~1×10 15 cm 2 , an injection angle (Tilt) of 7° and an injection rotation angle (Twist) of 23°. The dose of oxygen ions is set so that the peak concentration of oxygen ions is at least equal to or greater than the impurity concentration of the second conductivity type in the n-type buffer regions 10A and 10B. The oxygen ions are preferably injected in the Z direction in a manner thicker than the thickness of each of the n-type buffer regions 10A and 10B. Thus, in the separation region R3, as Figure 7 As shown, in the semiconductor portion 100D, the oxygen implantation region 12a is formed at n － type base region 2a and the n-type buffer region 10a.

[0066] In addition, before the oxygen ion implantation, boron ions may be implanted. The implantation of boron ions is performed at, for example, 750kev, 3.4×10 11 cm 3 , injection angle (Tilt) 7° and injection rotation angle (Twist) 23°, or, 1400kev, 1.5×10 11 cm 3 , injection angle (Tilt) 7° and injection rotation angle (Twist) 23°.

[0067] Next, the resist is peeled off (ST106). Thus, the resists 41 and 42 are peeled off from the semiconductor portion 100D, and a semiconductor device 100D is manufactured. Figure 8 The semiconductor portion 100E is shown.

[0068] Next, inject p + ions (ST107). p + The ions are impurities of the first conductivity type (p-type in this embodiment), and are obtained by ionizing boron, for example. Figure 8 The lower surface of the semiconductor portion 100E shown in FIG. 1 is implanted with p + As a result, p-type ions are formed in a part of the n-type buffer region 10a of the semiconductor portion 100E. + Type collector region. + The p-type collector region is formed to be connected to the oxygen implantation region 12a in the isolation region R3. + The region of the n-type buffer region 10a in the collector region is set as the n-type buffer region 10b. Fig. 9 As shown, in the semiconductor portion 100F, p + The n-type collector region 1a is provided below the n-type buffer region 10b.

[0069] Next, a resist is applied (ST108) and exposure is performed (ST109). + Next, for example, the resist is exposed to light through a predetermined mask to open the diode region R2 portion of the resist, and then developed. As a result, the resist applied to the diode region R2 on the lower surface of the semiconductor portion 100F disappears. Fig.10 As shown, in the semiconductor portion 100G, the resist 51 is formed in the IGBT region R1 and the isolation region R3. In other words, in the diode region R2, the resist provided on the lower surface of the semiconductor portion 100G is opened.

[0070] Next, inject n + Ion (ST110). +The ions are impurities of the second conductivity type (n-type in this embodiment), and are formed by ionizing phosphorus, for example. + The amount of ion implantation is greater than that of the n ion implantation described above. Fig.10 In the semiconductor portion 100G shown in FIG. 1 , n is implanted into the lower surface of the diode region R2. + ions. As a result, the concentration of the second conductivity type impurity in a part of the n-type buffer region 10b becomes higher. The region where the concentration of the second conductivity type impurity in the n-type buffer region 10b becomes higher forms an n-type buffer region 10b. + In the diode region R2, the n-type buffer region 10b is not formed with n + The area of ​​the n-type cathode region 7a is set as the n-type buffer region 10c. Fig.11 As shown, in the semiconductor portion 100H, an n-type buffer region 10c and an n-type buffer region 10c are provided in the diode region R2. + n-type cathode region 7a is provided under the n-type buffer region 10c. + Type cathode region 7a.

[0071] Next, the resist is peeled off (ST111). Fig.11 The semiconductor part 100H shown in the figure is manufactured by peeling off the resist 51. Fig.12 The semiconductor portion 100I is shown.

[0072] Next, annealing is performed (ST112). + type collector region 10a, n-type buffer region 10b, n-type buffer region 10c, n + The cathode region 7a and the oxygen implantation region 12a are activated. + type collector region 10a, n-type buffer region 10b, n-type buffer region 10c, n + The cathode region 7a and the oxygen implantation region 12a are respectively set to p + n-type collector regions 1A, 1B, n-type buffer regions 10A, n-type buffer regions 10B, n + The cathode region 7 and the oxygen injection region 12 are shown in FIG. Fig.13 As shown, the semiconductor portion 100J after the annealing process is provided with p + n-type collector regions 1A, 1B, n-type buffer regions 10A, 10B, n + type cathode region 7 and oxygen injection region 12.

[0073] Next, a collector electrode is formed (ST113). Fig.13 The collector electrode 31 is formed below the semiconductor portion 100J shown in FIG. Figure 1 A semiconductor device 100 is shown.

[0074] According to the manufacturing method, a semiconductor device 100 can be manufactured. The semiconductor device 100 includes a semiconductor device 100 provided on a p + Oxygen implantation region 12 is provided on n-type collector region 10B and between n-type buffer region 10A and n-type buffer region 10B in the X direction.

[0075] The embodiments include the following aspects.

[0076] (Note 1)

[0077] A semiconductor device, comprising:

[0078] 1st electrode;

[0079] a second electrode separated from the first electrode; and

[0080] a semiconductor portion provided between the first electrode and the second electrode,

[0081] The semiconductor portion includes a first region, a second region, and a third region disposed between the first region and the second region in a second direction perpendicular to the first direction from the first electrode toward the second electrode, and the semiconductor portion is disposed on the first electrode and below the second electrode.

[0082] The first area includes:

[0083] a first semiconductor region of a first conductivity type;

[0084] a second semiconductor region of a second conductivity type, disposed on the first semiconductor region;

[0085] a third semiconductor region, provided on the second semiconductor region, having a lower impurity concentration of the first conductivity type than that of the first semiconductor region;

[0086] a gate electrode, in the second direction, facing the third semiconductor region via a gate insulating layer;

[0087] The fourth semiconductor region of the second conductivity type is provided on the third semiconductor region and has a higher impurity concentration of the second conductivity type than that of the second semiconductor region; and

[0088] The sixth semiconductor region of the second conductivity type is provided between the first semiconductor region and the second semiconductor region in the first direction.

[0089] The second area includes:

[0090] The seventh semiconductor region of the second conductivity type has a higher impurity concentration of the second conductivity type than the second semiconductor region;

[0091] The second semiconductor region is disposed on the seventh semiconductor region;

[0092] The eighth semiconductor region of the first conductivity type is disposed on the second semiconductor region and is electrically connected to the second electrode;

[0093] The ninth semiconductor region of the second conductivity type is provided between the second semiconductor region and the seventh semiconductor region in the first direction, and has a second conductivity type impurity concentration higher than that of the second semiconductor region and lower than that of the seventh semiconductor region; and

[0094] a conductive portion electrically connected to the second electrode, a portion of which is opposed to the eighth semiconductor region via an insulating layer in the second direction,

[0095] The third area includes:

[0096] The tenth semiconductor region of the first conductivity type is disposed on the first electrode; and

[0097] The current blocking region is disposed on the tenth semiconductor region and between the sixth semiconductor region and the ninth semiconductor region in the second direction.

[0098] (Note 2)

[0099] The semiconductor device according to Supplementary Note 1, wherein:

[0100] There is also a fifth semiconductor region of the first conductivity type, which is provided on the third semiconductor region and has a higher impurity concentration of the first conductivity type than that of the third semiconductor region.

[0101] (Note 3)

[0102] The semiconductor device according to Supplement 1 or 2, wherein:

[0103] The current blocking region includes at least any one of oxygen, nitrogen, silicon dioxide, and carbon.

[0104] (Note 4)

[0105] The semiconductor device according to any one of appendices 1 to 3, wherein:

[0106] The concentration of any one of oxygen, nitrogen, silicon dioxide, and carbon contained in the current blocking region is higher than the concentration of the second conductivity type impurity in the sixth semiconductor region and the ninth semiconductor region.

[0107] (Note 5)

[0108] The semiconductor device according to Supplementary Note 4, wherein:

[0109] The concentration of any one of oxygen, nitrogen, silicon dioxide and carbon is 1×10 18 cm 3 above.

[0110] (Note 6)

[0111] The semiconductor device according to any one of Supplementary Notes 1 to 5, wherein:

[0112] The resistivity of the current blocking region is higher than the resistivity of each of the sixth semiconductor region and the ninth semiconductor region.

[0113] (Note 7)

[0114] The semiconductor device according to any one of Supplementary Notes 1 to 6, wherein:

[0115] A crystal defect density of the current blocking region is higher than crystal defect densities of the sixth semiconductor region and the ninth semiconductor region.

[0116] (Note 8)

[0117] A method for manufacturing a semiconductor device, wherein:

[0118] forming a semiconductor portion having a first region, a second region, and a third region disposed between the first region and the second region, a first electrode being disposed on the first region, the second region, and the third region, and a first semiconductor layer of a second conductivity type being disposed in the first region, the second region, and the third region,

[0119] forming a second semiconductor layer of the second conductivity type having an impurity concentration of the second conductivity type higher than the impurity concentration of the second conductivity type in the first semiconductor layer on the surface of the semiconductor portion opposite to the surface on which the first electrode is provided,

[0120] In the first region, the second region, and the third region, a resist is applied below the second semiconductor layer.

[0121] The resist in the third region is removed to open the third region,

[0122] injecting any one of oxygen, nitrogen, silicon dioxide and carbon from below the second semiconductor layer through the opening of the third region by ion implantation;

[0123] The resist applied to the first region and the second region is removed.

[0124] (Note 9)

[0125] The method for manufacturing a semiconductor device according to Supplementary Note 8, wherein:

[0126] Under the second semiconductor layer after the resist is removed, the first conductivity type impurity is implanted from below the second semiconductor layer by ion implantation.

[0127] (Note 10)

[0128] The method for manufacturing a semiconductor device according to Supplementary Note 9, wherein:

[0129] After the first conductivity type impurities are implanted, a resist is applied below the second semiconductor layer in the first region, the second region, and the third region.

[0130] The resist in the second region is removed to open the second region,

[0131] The second conductivity type impurity is injected from below the second semiconductor layer by ion implantation.

[0132] The resist is removed from the second semiconductor layer.

[0133] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the main purpose of the invention. These embodiments and their variations are included in the scope and main purpose of the invention, and are included in the invention described in the claims and their equivalents. In addition, the aforementioned embodiments can be implemented in combination with each other.

[0134] Description of Reference Numerals

[0135] 1A, 1B…p + Type collector area, 2…n － type base region, 3…p type base region, 4…n + Type emitter region, 5a…p type contact region, 5…p + Type contact area, 7…n + type cathode region, 8…p type anode region, 9…p +n-type anode region, 10A, 10B…n-type buffer region, 11…n-type barrier region, 12…oxygen implantation region, 20…gate electrode, 20a…gate insulating layer, 21…conductive portion, 21a…insulating layer, 31…collector electrode, 31, 32…emitter electrode, 33…gate pad, 33a…gate wiring, 34…semiconductor portion, 41, 42, 51…resist, 100…semiconductor device, 100A to 100J…semiconductor portion, R1…IGBT region, R2…diode region, R3…isolation region

Claims

1. A semiconductor device, wherein: have: 1st electrode; a second electrode separated from the first electrode; and a semiconductor portion disposed between the first electrode and the second electrode, the semiconductor portion having a first region, a second region, and a third region disposed between the first region and the second region in a second direction perpendicular to the first direction from the first electrode toward the second electrode, the semiconductor portion being disposed above the first electrode and below the second electrode, The first area includes: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type, disposed on the first semiconductor region; a third semiconductor region, provided on the second semiconductor region, having a lower impurity concentration of the first conductivity type than that of the first semiconductor region; a gate electrode facing the third semiconductor region via a gate insulating layer in the second direction; The fourth semiconductor region of the second conductivity type is provided on the third semiconductor region and has a higher impurity concentration of the second conductivity type than that of the second semiconductor region; and The sixth semiconductor region of the second conductivity type is provided between the first semiconductor region and the second semiconductor region in the first direction. The second area includes: The seventh semiconductor region of the second conductivity type has a higher impurity concentration of the second conductivity type than the second semiconductor region; The second semiconductor region is disposed on the seventh semiconductor region; The eighth semiconductor region of the first conductivity type is disposed on the second semiconductor region and is electrically connected to the second electrode; The ninth semiconductor region of the second conductivity type is provided between the second semiconductor region and the seventh semiconductor region in the first direction, and has a second conductivity type impurity concentration higher than that of the second semiconductor region and lower than that of the seventh semiconductor region; and a conductive portion electrically connected to the second electrode, a portion of which is opposed to the eighth semiconductor region via an insulating layer in the second direction, The third area includes: The tenth semiconductor region of the first conductivity type is disposed on the first electrode; and The current blocking region is disposed on the tenth semiconductor region and between the sixth semiconductor region and the ninth semiconductor region in the second direction.

2. The semiconductor device according to claim 1, wherein: There is also a fifth semiconductor region of the first conductivity type, which is provided on the third semiconductor region and has a higher impurity concentration of the first conductivity type than that of the third semiconductor region.

3. The semiconductor device according to claim 1, wherein: The current blocking region includes at least any one of oxygen, nitrogen, silicon dioxide, and carbon.

4. The semiconductor device according to claim 1, wherein: The concentration of any one of oxygen, nitrogen, silicon dioxide, and carbon contained in the current blocking region is higher than the concentration of the second conductivity type impurity in the sixth semiconductor region and the ninth semiconductor region.

5. The semiconductor device according to claim 4, wherein: The concentration of any one of oxygen, nitrogen, silicon dioxide and carbon is 1×10 18 cm 3 above.

6. The semiconductor device according to claim 1, wherein: The resistivity of the current blocking region is higher than the resistivity of each of the sixth semiconductor region and the ninth semiconductor region.

7. The semiconductor device according to claim 1, wherein: A crystal defect density of the current blocking region is higher than crystal defect densities of the sixth semiconductor region and the ninth semiconductor region.

8. A method for manufacturing a semiconductor device, wherein: forming a semiconductor portion having a first region, a second region, and a third region disposed between the first region and the second region, a first electrode being disposed on the first region, the second region, and the third region, and a first semiconductor layer of a second conductivity type being disposed in the first region, the second region, and the third region, forming a second semiconductor layer of the second conductivity type having an impurity concentration of the second conductivity type higher than the impurity concentration of the second conductivity type in the first semiconductor layer on the surface of the semiconductor portion opposite to the surface on which the first electrode is provided, In the first region, the second region, and the third region, a resist is applied below the second semiconductor layer. The resist in the third region is removed to open the third region, injecting any one of oxygen, nitrogen, silicon dioxide and carbon from below the second semiconductor layer through the opening of the third region by ion implantation; The resist applied to the first region and the second region is removed.

9. The manufacturing method according to claim 8, wherein: Under the second semiconductor layer after the resist is removed, the first conductivity type impurity is implanted from below the second semiconductor layer by ion implantation.

10. The manufacturing method according to claim 9, wherein: After the first conductivity type impurities are implanted, a resist is applied below the second semiconductor layer in the first region, the second region, and the third region. The resist in the second region is removed to open the second region, The second conductivity type impurity is injected from below the second semiconductor layer by ion implantation. The resist is removed from the second semiconductor layer.

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