Gate preparation method and semiconductor device
By depositing and planarizing the conductive material layer in the trench gate semiconductor device, the polysilicon surface recession problem is solved, and the device performance and productivity are improved.
Patent Information
- Application Number
- CN202411979435.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-30
- Publication Date
- 2025-03-28
AI Technical Summary
During the preparation of a trench gate semiconductor device, the polysilicon surface is concave and the region of the trench is formed, resulting in a height difference between the polysilicon surface in the trench and the semiconductor substrate surface, affecting device performance and production yield.
By depositing a layer of conductive material, multiple trenches in the semiconductor substrate are filled and covered with the upper surface of the substrate, followed by a planarization process to eliminate recesses on the upper surface of the conductive material layer, and a gate electrode is formed by a patterning process.
The depression on the upper surface of the conductive material layer is eliminated, so that the depression is further expanded during the patterning process, and the performance and productivity of the semiconductor device are improved.
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Figure CN119730348A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a gate preparation method and a semiconductor device. Background Art
[0002] Semiconductor devices can be divided into two categories according to the location and structure of the gate: planar gate type and trench gate type. Among them, trench gate semiconductor devices can increase the cell density by setting the gate in the trench of the semiconductor substrate, which is conducive to improving the utilization rate of the wafer. At the same time, trench gate semiconductor devices eliminate the JFET effect and effectively reduce the on-resistance of semiconductor devices. Thanks to these advantages, as electronic devices develop towards higher performance, lower power consumption and smaller size, trench gate semiconductor devices have also been increasingly widely used.
[0003] refer to Figure 1A and Figure 1B In the process of preparing trench gate semiconductor devices, it is necessary to deposit a conductive material in the trench of the semiconductor substrate to form a gate, wherein the semiconductor substrate is, for example, a silicon carbide (SiC) substrate, and the conductive material is usually polysilicon (Polysilicon, Poly). However, due to limitations of the deposition process and other reasons, the area on the polysilicon surface corresponding to the trench is concave to form a depression. During subsequent back etching, the depression is further enlarged, causing a height difference between the polysilicon surface in the trench and the semiconductor substrate surface. In addition, there is a large difference in the thickness of polysilicon in different areas of the trench. The closer to the center of the trench, the greater the height difference between the polysilicon surface and the silicon carbide substrate surface. For example, in Figure 1A In the figure, the distance between the upper surface of the polysilicon near the sidewall of the trench and the upper surface of the semiconductor substrate is h1, and the distance between the upper surface of the polysilicon in the center of the trench and the upper surface of the polysilicon near the sidewall of the trench is h2. This greatly affects the performance and production yield of semiconductor devices.
[0004] Therefore, a new gate preparation method is needed. Summary of the invention
[0005] In view of the above problems, the purpose of the present application is to provide a gate preparation method and a semiconductor device, which can improve the performance and production yield of trench gate semiconductor devices.
[0006] According to one aspect of the present application, a gate preparation method is provided, which includes: depositing a conductive material layer, the conductive material layer filling a plurality of grooves in a semiconductor substrate and covering the upper surface of the semiconductor substrate; planarizing the upper surface of the conductive material layer; and patterning the conductive material layer to form a gate; wherein the gate includes a first gate filling the grooves, and a second gate electrically connected to at least a portion of the first gate.
[0007] Optionally, the planarization includes: forming a first material layer, wherein the first material layer covers an upper surface of the conductive material layer; and etching back the first material layer and the conductive material layer to planarize the upper surface of the conductive material layer.
[0008] Optionally, after the back etching, the thickness of the conductive material layer is greater than or equal to a preset thickness.
[0009] Optionally, after the etching back, the method further includes: removing the remaining first material layer.
[0010] Optionally, the patterning includes: forming a second material layer, the second material layer covering a preset area of the conductive material layer; etching the conductive material layer to remove the conductive material layer outside the preset area to form the first gate and the second gate; and removing the second material layer; wherein the conductive material layer in the preset area forms the second gate.
[0011] Optionally, the first material layer and / or the second material layer comprises a photolithography material.
[0012] Optionally, before depositing the conductive material layer, the method further includes: forming a plurality of the grooves in the semiconductor substrate.
[0013] Optionally, the method further includes: forming a dielectric layer, wherein the dielectric layer covers inner walls of each of the trenches and an upper surface of the semiconductor substrate, and the dielectric layer is used to isolate the conductive material layer from the semiconductor substrate.
[0014] Optionally, the semiconductor substrate includes a silicon carbide substrate, and the conductive material layer includes a polysilicon material layer.
[0015] According to another aspect of the present application, a semiconductor device is provided, comprising: a semiconductor substrate having a plurality of grooves, wherein the grooves extend from the upper surface of the semiconductor substrate into the semiconductor substrate; and a gate, comprising a first gate filling each of the grooves and a second gate located on the upper surface of the semiconductor substrate, wherein the second gate is electrically connected to at least a portion of the first gate, wherein the gate is prepared by any of the gate preparation methods described above.
[0016] According to the gate preparation method and semiconductor device disclosed in the present application, before the gate is formed by patterning, the upper surface of the conductive material layer forming the gate is flattened to eliminate the depression on the upper surface of the conductive material layer, thereby preventing the depression on the upper surface of the conductive material layer from being further enlarged during the patterning process, thereby improving the performance and product yield of the semiconductor device.
[0017] Furthermore, during the planarization process, the conductive material layer is thinned to eliminate the depression or at least reduce the depression degree of the depression, thereby forming a double guarantee for the planarization process with the first material layer filled in the depression, which is more conducive to improving the effect of the planarization process. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:
[0019] Figure 1A and Figure 1B An example diagram of a gate electrode prepared according to a prior art preparation method is shown;
[0020] Figure 2 A schematic structural diagram showing a trench gate semiconductor device;
[0021] Figure 3 A schematic flow chart showing a gate preparation method disclosed in the present application;
[0022] Figure 4 A schematic flow chart of flattening is shown;
[0023] Figure 5 A schematic flow chart showing patterning;
[0024] Figure 6 A schematic flow chart showing the formation of a second material layer;
[0025] 7A to 7H Multiple cross-sectional views showing different stages of the gate preparation method according to the present application;
[0026] Figures 8A to 8D Schematic multi-sectional cross-sectional views of some stages of the gate manufacturing method of the present application are shown when the recess is not completely eliminated. DETAILED DESCRIPTION
[0027] Various embodiments of the present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements, components and regions are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. The fill patterns of the same area in different drawings may also be different.
[0028] At the same time, certain words are used in this specification and claims to refer to specific components. It should be understood by those skilled in the art that manufacturers may use different terms to refer to the same component. This specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.
[0029] In addition, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations, nor do they represent the number of entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.
[0030] It should also be noted that, in the various methods and processes of the present application, the size of the step numbers does not mean the order of execution, nor does it constitute any limitation on the implementation process of the embodiments of the present application.
[0031] In order to facilitate a better understanding of the present application, a trench gate semiconductor device is first briefly described.
[0032] Figure 2 A schematic structural diagram of a trench gate semiconductor device is shown. In order to highlight the main idea of the present application, Figure 2 The complete semiconductor device is not shown. Figure 2 The trench gate semiconductor device 100 includes a semiconductor substrate 110 and a gate 120, wherein the gate 120 includes a first gate 121 and a second gate 122. Specifically, the semiconductor substrate 110 includes a plurality of trenches, which are filled with the first gate 121, and the second gate 122 is located on the upper surface of the semiconductor substrate 110 and electrically connected to at least a portion of the first gate 121, and the second gate 122 is used to form a conductive connection with an external electrical connection contact.
[0033] As an example, in Figure 2 Only two trenches and corresponding first gates 121 are shown, and the two first gates 121 are electrically connected by the second gate 122 .
[0034] In order to improve the performance and production yield of trench gate semiconductor devices, the present application also discloses a gate preparation method. Figure 3 A schematic flow chart showing a gate preparation method disclosed in an embodiment of the present application; Figure 4 A schematic flow chart of flattening is shown; Figure 5 A schematic flow chart showing patterning; Figure 6 7A to 7B show a schematic flow chart of forming a second material layer; Figure 7HMultiple cross-sectional views at different stages of the gate manufacturing method according to the present application are shown.
[0035] In order to facilitate understanding of the present application, in the following text, the direction between the upper surface and the lower surface of the semiconductor substrate is referred to as the first direction. Figure 2 The first direction is the Z direction or the reverse direction of the Z direction, and the first direction is also the depth direction of the groove. The arrangement direction of the grooves in the semiconductor substrate is the second direction, that is, Figure 2 The direction of the trench in the semiconductor is the third direction, i.e. Figure 2 The first direction, the second direction and the third direction are not parallel to each other and intersect each other. In a preferred embodiment, the first direction, the second direction and the third direction are perpendicular to each other. Figure 2 The cross-sectional views taken along the AA' line, the BB' line, and the CC' line are exemplified as cross-sectional views at different angles.
[0036] The gate preparation method disclosed in the embodiments of the present application will be described in detail below with reference to the accompanying drawings.
[0037] refer to Figure 3 The gate preparation method disclosed in the embodiment of the present application includes the following steps S11-S14:
[0038] In step S11, Fig. 7A , a plurality of trenches Ⅰ are formed in the semiconductor substrate 110 .
[0039] The semiconductor substrate 110 is, for example, a semiconductor substrate known to those skilled in the art, such as a silicon carbide (SiC) substrate, gallium nitride (GaN), silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP).
[0040] In some embodiments, each groove I may be formed by etching. In some other embodiments, the groove I may be formed by other methods in the prior art, and this application does not make too many restrictions and explanations on this.
[0041] It should be understood that, based on different types of semiconductor devices, before forming the trench I, doped regions of different doping types are usually formed in the semiconductor substrate 110. For example, for MOSFET (Metal-Oxide-SemiconductorField-Effect Transistor), well regions, source regions and other doped regions are formed in the semiconductor substrate 110. For IGBT (Insulated Gate Bipolar Transistor), collector regions, buffer regions and other doped regions are formed in the semiconductor substrate 110. This application does not make too many restrictions or explanations on this, that is, the preparation method of this application is applicable to any type of trench gate semiconductor device. Preferably, this application is applicable to trench gate power semiconductor devices.
[0042] After forming a plurality of trenches, a dielectric layer is usually deposited to cover the inner wall of each trench I and the upper surface of the semiconductor substrate 110, so as to electrically isolate the semiconductor substrate 110 from the subsequently deposited conductive material layer.
[0043] In step S12, combined Figure 7B , a conductive material layer 10 is deposited, and the conductive material layer 10 fills the plurality of trenches I in the semiconductor substrate 110 and covers the upper surface of the semiconductor substrate 110 .
[0044] The conductive material layer 10 is, for example, polysilicon (Poly) or other gate materials known to those skilled in the art. Figure 7B In the figure, the thickness of the conductive material layer 10 on the upper surface of the semiconductor substrate 110 is d1.
[0045] Ideally, the conductive material layer 10 should have a flat upper surface. However, during the deposition of the conductive material layer 10, due to limitations of the deposition process and other reasons, the surface of the conductive material layer 10 corresponding to the groove I is concave to form a depression II.
[0046] In step S13 , the upper surface of the conductive material layer 10 is planarized.
[0047] In some embodiments, the depression II can be removed by chemical-mechanical polishing (CMP). There may also be some disadvantages in using the CMP process. For example, the use of the CMP process requires the introduction of corresponding equipment, which is not conducive to controlling production costs; for example, the use of the CMP process may still leave new scratches on the surface of the conductive material layer during the polishing process, and these scratches will still be enlarged in the subsequent preparation process; in addition, in actual operation, since the degree of depression of each depression II is not exactly the same, if the same degree of polishing and thinning is performed on different areas on the surface of the conductive material layer, it is difficult to ensure that all depressions II can be eliminated while the conductive material layer still has a certain thickness, and too low a thickness of the conductive material layer will affect the quality of the device.
[0048] In some other embodiments, the upper surface of the conductive material layer 10 may be planarized by filling the recess II.
[0049] Specifically, refer to Figure 4 The planarization process using the method of filling the recess II includes the following steps S21-S23:
[0050] In step S21, Figure 7C , forming a first material layer 20 , wherein the first material layer 20 covers the upper surface of the conductive material layer 10 .
[0051] The first material layer 20 includes a first portion 21 and a second portion 22. The first portion 21 fills the recess II on the upper surface of the conductive material layer 10, and the second portion 22 covers the upper surface of the conductive material layer 10. Figure 7C In the embodiment, the thickness of the second portion 22 is d2.
[0052] The first material layer 20 is, for example, an etchable material such as a photolithographic material, for example, common photolithographic materials such as photoresist (PR) and spin-on glass (SOG) can be selected. In some embodiments, the first material layer 20 is made of the same material as the second material layer used in the subsequent process, so that the introduction of new raw materials and preparation processes in the preparation process can be avoided, thereby further saving costs. The second material layer will be specifically introduced below and will not be repeated here.
[0053] In the present application, the specific formation process of the first material layer 20 is not described and limited in detail, and those skilled in the art can select a corresponding preparation process according to the material of the first material layer 20. For example, in some embodiments, the first material layer 20 uses a photolithography material such as PR or SOG, and the first material layer 20 can be formed by subsequent processes such as spin coating and baking.
[0054] In step S22 , the first material layer 20 and the conductive material layer 10 are etched back to planarize the upper surface of the conductive material layer 10 .
[0055] In some embodiments, in combination Fig.7D In the back etching process of this step, the first material layer 20 is completely removed, and the thickness of the conductive material layer 10 on the surface of the semiconductor substrate 110 is also reduced. The thickness of the semiconductor substrate 110 after thinning is greater than or equal to the preset thickness d3. The preset thickness d3 is also the minimum thickness of the second gate 122 formed in the end, where d3<d1, d1 is the deposition thickness of the conductive material layer 10. Fig.7D In the embodiment, the conductive material layer 10 is thinned to a preset thickness d3 as an example.
[0056] like Fig.7D As shown, when the semiconductor substrate 110 is thinned to a preset thickness d3, the depression II of the conductive material layer 10 is completely eliminated. That is, by completely removing the first material layer 20 and thinning the conductive material layer 10, the depression II of the conductive material layer 10 is completely eliminated after planarization, thereby avoiding the negative impact of the depression II in subsequent steps.
[0057] In step S23 , the first material layer 20 remaining on the upper surface of the conductive material layer 10 is removed.
[0058] In this step, the first material layer 20 remaining on the upper surface of the conductive material layer 10 after planarization can be removed by an ashing process to avoid the influence of the remaining first material layer 20 on subsequent processes.
[0059] The ashing process may be to use plasma of O2, CF4 or a mixed gas thereof to remove the remaining first material layer 20. In some embodiments, the ashing process may also be to use other plasma to remove the remaining first material layer 20.
[0060] In some embodiments, step S23 may not be performed, but step S23 can completely remove the first material layer 20 on the upper surface of the conductive material layer 10, which is conducive to obtaining a better planarization effect.
[0061] In step S14 , the conductive material layer 10 is patterned to form a gate 120 , wherein the gate 120 includes a first gate 121 filling the trench and a second gate 122 electrically connected to at least a portion of the first gate 121 .
[0062] Specifically, combined Figure 5 The graphical steps include the following steps S31-S33:
[0063] In step S31, a second material layer 30 is formed, and the second material layer 30 covers a predetermined area of the conductive material layer 10. Figure 2 The preset area is the area of the conductive material layer 10 at the position corresponding to the second gate 122, and the conductive material layer 10 in the preset area is the second gate 122 formed subsequently; the area outside the preset area is the non-preset area.
[0064] In some embodiments, the second material layer 30 is also an etchable material. In a preferred embodiment, as described above, the second material layer 30 is made of the same material as the first material layer 20. For example, common photolithography materials such as photoresist (PR) and spin-on glass (SOG) can be used.
[0065] In this embodiment, the second material layer 30 covering the preset area of the conductive material layer 10 can be realized by the following steps:
[0066] Step S311, combining Fig. 7E , a second material layer 30 is coated on the conductive material layer 10 .
[0067] In this step, the second material layer 30 completely covers the upper surface of the conductive material layer 10 , that is, the second material layer 30 covers the conductive material layer in the preset area and the non-preset area.
[0068] Step S312, combining Figure 7F , the second material layer 30 covering the non-preset area is exposed to remove the second material layer 30 in the non-preset area. The unexposed second material layer 30 is the second material layer 30 covering the preset area of the conductive material layer 10, that is, the second material layer 30 finally formed only covers the preset area of the conductive material layer 10.
[0069] In step S32, combined Figure 7G , the conductive material layer 10 is etched to remove the conductive material layer 10 in the non-preset area on the upper surface of the semiconductor substrate 110, and the remaining conductive material layer 10' forms a gate 120. Specifically, the conductive material layer 10' remaining in the groove I forms a first gate 121, and the conductive material layer 10' remaining in the preset area forms a second gate 122. Figure 7G The embodiment is as follows: in the BB' cross-sectional view and the CC' cross-sectional view, the conductive material layer 10' located between the second material layer 30 and the semiconductor substrate 110, that is, Figure 2 The second gate 122 in.
[0070] In step S33, Figure 7H , remove the second material layer 30.
[0071] In this step, the second material layer 30 is removed by a process such as ashing.
[0072] In some embodiments, the ashing process may be to use plasma of O2, CF4 or a mixture thereof to remove the remaining second material layer 30. In other embodiments, the ashing process may be to use other plasma to remove the remaining second material layer 30.
[0073] According to the gate preparation method disclosed in the present application, before the gate is formed by patterning, the upper surface of the conductive material layer forming the gate is flattened to eliminate the depressions on the upper surface of the conductive material layer, thereby preventing the depressions on the upper surface of the conductive material layer from being further enlarged during the patterning process, thereby affecting the performance and product yield of the semiconductor device.
[0074] Furthermore, the thickness of the conductive material layer is reduced to completely eliminate the depression on the upper surface of the conductive material layer, thereby further improving the planarization effect.
[0075] In the above-mentioned embodiment, when the conductive material layer 10 is thinned to a preset thickness d3, the depression II is completely eliminated. However, it should be understood that in some embodiments, when the conductive material layer 10 is thinned to a preset thickness d3, at least part of the depression II may not be eliminated. That is, there may be the following two situations: first, the depression II on the upper surface of the conductive material layer 10 is partially eliminated, but because the conductive material layer 10 is thinned, the depression II that is not eliminated will also be reduced in degree; second, the depression II on the upper surface of the conductive material layer 10 is still completely retained, but because the conductive material layer 10 is thinned, the degree of concavity of each depression II is completely reduced.
[0076] Figures 8A to 8D Schematic multi-section cross-sectional view of the gate preparation method of the present application at some stages when the recess is not completely eliminated. It should be understood that Figures 8A to 8D The situation shown is still included in the gate preparation method disclosed in this application, so Figures 8A to 8D Only some stages with significant differences are described.
[0077] Fig. 8A FIG. 4 is a schematic diagram showing a situation in which the depression is not completely eliminated after the above step S22. Fig. 8A In the example, two depressions are fully preserved, and in Fig. 8A In the figure, the recess that is not completely eliminated is marked as II' to distinguish it from the recess II formed when the conductive material layer 10 is formed.
[0078] refer to Fig. 8AIn the process of thinning the conductive material layer 10 to the preset thickness d3, the width and degree of the two recesses II' are reduced. At the same time, the first portion 21 of the first material layer 20 filled in the recess II' is also retained, and the upper surface of the conductive material layer 10 can still be planarized, and the negative effects of the recess II' in subsequent steps can be avoided.
[0079] It should be further explained that in these embodiments where recess II' is not completely eliminated, the first portion 21 retained in recess II' will affect the etching speed of the conductive material layer 10 in the subsequent step of patterning to form a gate, thereby causing the first gate 121 filled in the corresponding groove I to be slightly higher than the upper surface of the semiconductor layer 110.
[0080] Figure 8B FIG. 4 shows a multi-section cross-sectional view after etching the conductive material layer, that is, a multi-section cross-sectional view after the above step S32. Figure 8B , a local enlarged view of region III is shown. Referring to the enlarged region III, it can be specifically shown that the first gate 121 is higher than the upper surface of the semiconductor substrate 110 by a distance d4.
[0081] Figure 8C The multi-section cross-sectional view after removing the second material layer, that is, the multi-section cross-sectional view after the above step S33 is shown. Since the first portion 21 filling the recess II' is retained after planarization, the first portion 21 in the recess II' is still retained after step S33, so that the second gate 122 has a flat upper surface.
[0082] However, in some other embodiments, reference Fig.8D , the first part 21 of the recess II' is also removed in step S33. Accordingly, the recess II' in the preset area is still retained and exposed, that is, the recess II' on the upper surface of the second gate 122 is still retained and exposed. However, since the degree of the recess II' has been effectively reduced during the planarization process, and in the subsequent process of semiconductor device preparation, these recesses are filled with a gate dielectric layer or other structures, the impact of these recess II' on the performance and yield of the semiconductor device can be ignored.
[0083] The filling of the first material layer 20 and the thinning of the thickness of the conductive material layer 10 provide a double guarantee for eliminating the depression II. Therefore, even when the thickness of the conductive material layer 10 is thinned to a preset thickness, there are still some depressions II that have not been eliminated. These depressions II will also be reduced in width and depression degree and filled with the first portion 21 of the first material layer 20, so that they will not have a negative impact in the subsequent patterning.
[0084] In summary, according to the gate preparation method provided in the present application, before the gate is formed by patterning, the upper surface of the conductive material layer forming the gate is planarized, and the depressions on the upper surface of the conductive material layer are eliminated, thereby avoiding further expansion of the depressions on the upper surface of the conductive material layer during the patterning process, which is beneficial to improving the performance of semiconductor devices and product yield.
[0085] Furthermore, during the planarization process, the conductive material layer is thinned to reduce the concave degree of the depression, thereby forming a double guarantee for the planarization process with the first material layer filled in the depression, which is more conducive to improving the effect of the planarization process.
[0086] In addition, the present application also provides a semiconductor device, wherein the semiconductor substrate has a plurality of grooves and a gate. Each groove extends from the upper surface of the semiconductor substrate into the semiconductor substrate. The gate includes a first gate filling each groove and a second gate located on the upper surface of the semiconductor substrate, and the second gate is electrically connected to at least a portion of the first gate. The gate of the semiconductor device is prepared according to the gate preparation method disclosed in the present application, so that the corresponding beneficial effects can also be achieved, which will not be repeated here.
[0087] According to the embodiments of the present application as above, these embodiments do not describe all the details in detail, nor do they limit the present application to specific embodiments only. Obviously, according to the above description, many modifications and changes can be made. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The scope of protection of the present application shall be based on the scope defined by the claims of the present application.
Claims
1. A method for preparing a gate, wherein: include: Depositing a conductive material layer, wherein the conductive material layer fills a plurality of trenches in the semiconductor substrate and covers an upper surface of the semiconductor substrate; planarizing the upper surface of the conductive material layer; as well as Patterning the conductive material layer to form a gate; The gate includes a first gate filling the trench and a second gate electrically connected to at least a portion of the first gate.
2. The gate preparation method according to claim 1, wherein: The planarization includes: forming a first material layer, wherein the first material layer covers an upper surface of the conductive material layer; and The first material layer and the conductive material layer are etched back to planarize the upper surface of the conductive material layer.
3. The gate preparation method according to claim 2, wherein: After the etching back, the thickness of the conductive material layer is greater than or equal to a preset thickness.
4. The gate preparation method according to claim 2, wherein: After the etching back, the method further includes: removing the remaining first material layer.
5. The gate preparation method according to any one of claims 2 to 4, wherein: The graphics include: forming a second material layer, wherein the second material layer covers a preset area of the conductive material layer; etching the conductive material layer to remove the conductive material layer outside the preset area to form the first gate and the second gate; and removing the second material layer; Wherein, the conductive material layer in the preset area forms the second gate.
6. The gate preparation method according to claim 5, wherein: The first material layer and / or the second material layer includes a photolithography material.
7. The gate preparation method according to claim 1, wherein: Before depositing the conductive material layer, the method further includes: forming a plurality of the grooves in the semiconductor substrate.
8. The gate preparation method according to claim 7, wherein: Also includes: A dielectric layer is formed, the dielectric layer covers the inner walls of each of the trenches and the upper surface of the semiconductor substrate, and the dielectric layer is used to isolate the conductive material layer from the semiconductor substrate.
9. The gate preparation method according to claim 1, wherein: The semiconductor substrate includes a silicon carbide substrate, and the conductive material layer includes a polysilicon material layer.
10. A semiconductor device, wherein: include: A semiconductor substrate having a plurality of grooves, wherein the grooves extend from the upper surface of the semiconductor substrate into the semiconductor substrate; as well as a gate, comprising a first gate filling each of the trenches and a second gate located on the upper surface of the semiconductor substrate, wherein the second gate is electrically connected to at least a portion of the first gate, Wherein, the gate is prepared by the gate preparation method according to any one of claims 1-9.