Semiconductor device with super junction structure
By setting grooves and trench gates in the body region of the superjunction structure semiconductor device to form a plurality of L-shaped second channels, the problem of decreasing current capability in the prior art is solved, and a higher current capability and a smaller cell area are achieved.
Patent Information
- Application Number
- CN202411146772.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-20
- Publication Date
- 2025-03-28
AI Technical Summary
When existing superjunction structure semiconductor devices add P-type or N-type layers to reduce specific on-resistance, the effective channel becomes narrower, resulting in a decrease in the current capability of the device and an increase in the cell area.
By providing a plurality of grooves arranged spaced in the width direction of the device and a groove gate fitted with the grooves in the body region, the source region is formed in the gap between the plurality of grooves, thereby forming a plurality of L-shaped second channels, thereby increasing the effective width and current capability of the device.
This increases the number of channels inside the device, enhances the current capability, increases the effective width of the device, reduces the cell area, and thus improves the performance of the device.
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Figure CN119730350A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a super junction structure semiconductor device. Background Art
[0002] Integrated superjunction devices are widely used in high-voltage power integrated circuits because of their low on-resistance and high withstand voltage. Superjunction devices usually form a superjunction structure in the epitaxial region to reduce the specific on-resistance without losing the withstand voltage. The superjunction structure is composed of alternating N-type doped strips and P-type doped strips.
[0003] Figure 1 A schematic diagram of the three-dimensional structure of a super junction semiconductor device in the prior art is shown. Figure 1 As shown, the super junction structure semiconductor device includes: a substrate 1, a drift layer 2 located on the upper surface of the substrate 1, a body region 3 and a lateral super junction structure 4 located on the upper surface of the drift layer 2 and arranged side by side, a source region 5 located in the body region 3 and spaced from the lateral super junction structure 4, and a drain region 6 located on the side of the lateral super junction structure 4 away from the body region 3. And, a body contact region 7 located in the body region 3 and a gate dielectric structure 8 located on the upper surface of the body region 3. The body contact region 7 and the source region 5 are connected to the gate electrode S, the drain region 6 is connected to the drain electrode D, and the gate dielectric structure 8 leads the gate electrode G through the gate. The lateral super junction structure 4 is composed of alternately arranged N-type doped strips Ntop and P-type doped strips Ptop, which transforms the conventional two-dimensional voltage-resistant layer into a three-dimensional junction voltage-resistant layer composed of N-type strips and P-type strips along the width direction of the device. For N(P) type devices, the P(N) type doping strips will assist the depletion of the N(P) type doping strips and the N(P) type drift region, so that the epitaxial region can have a higher doping concentration under the same withstand voltage state, thereby reducing the device's specific on-resistance. That is, by adding a P-type layer or an N-type layer in the width direction of the device, the concentration of the device epitaxial layer can be greatly increased, thereby reducing the device's on-resistance. In addition, the PN junction in the superjunction structure can adjust the electric field distribution, which makes the electric field distribution more uniform, thereby also improving the device's withstand voltage. However, since the P-type layer or the N-type layer is added to the epitaxial layer, the effective channel becomes narrower, which will also reduce the effective width of the device, reduce the current capacity of the device, and increase the cell area of the device under the same current capacity. Summary of the invention
[0004] In view of the above problems, an object of the present invention is to provide a super junction structure semiconductor device to solve the problems in the prior art.
[0005] According to one aspect of the present invention, there is provided a super junction structure semiconductor device, comprising: a drift layer stacked above a substrate layer; a drain region and a body region, respectively located on a first side and a second side above the drift layer; a super junction structure, located between the drain region and the body region, comprising a plurality of alternatingly arranged N-type strips and P-type strips; a gate oxide layer, comprising a groove group, wherein the groove group comprises a plurality of grooves penetrating the body region and arranged at intervals from each other; a gate layer, comprising a plurality of trench gates respectively embedded in the plurality of grooves; and a source region, at least located in gaps formed between the plurality of grooves, wherein the arrangement direction of the plurality of grooves is the same as the arrangement direction of the N-type strips and the P-type strips.
[0006] Optionally, the gate oxide layer also includes a planar layer, which is located above the body region between the groove group and the super junction structure. The gate layer also includes a planar gate located above the planar layer, and the source region is also located in the body region below the planar gate.
[0007] Optionally, the source region includes: a first source region, located in the body region on a side of the groove group close to the super junction structure, adjacent to the groove group; and a second source region, located between the gaps between the plurality of grooves; a third source region, located in the body region on a side of the groove group away from the super junction structure, adjacent to the groove group, and the second source region connects the first source region and the third source region.
[0008] Optionally, when the super junction structure semiconductor device is in operation, a first lateral channel is formed along the surface of the device between the first source region and the drain region, and an L-shaped second channel is formed along the inside of the device between the first source region to the third source region and the drain region respectively.
[0009] Optionally, the super junction structure semiconductor device further includes: a field oxide layer distributed above the super junction structure, the planar layer partially covers the surface of the super junction structure, the field oxide layer is connected to the planar layer, and the planar gate partially covers the surface of the field oxide layer.
[0010] Optionally, the P-type strips and the N-type strips extend along a first direction, and the P-type strips and the N-type strips are alternately arranged along a second direction, the first direction is perpendicular to the second direction, a plurality of groove groups are distributed in the body region, and the plurality of groove groups are arranged at intervals along the first direction, a plurality of trench gates are correspondingly embedded in the plurality of grooves of each groove group, and each groove is surrounded by the source region.
[0011] Optionally, the groove comprises a square groove, a hollow cylindrical groove or a hollow prismatic groove, and the shape of the groove grid matches the shape of the groove.
[0012] Optionally, the planar layer is connected to the adjacent groove groups as a whole, and the planar gate is connected to the adjacent plurality of trench gates as a whole.
[0013] Optionally, all of the gate layers are connected to the same gate electrode through conductive material, all of the source regions are connected to the same source electrode through conductive material, all of the body regions are connected to the same body region electrode through conductive material, and the drain regions are connected to the drain electrode through conductive material.
[0014] Optionally, the body region has a first doping type, the drift layer and the source region have a second doping type, the first doping type is one of N-type doping and P-type doping, and the second doping type is the other of N-type doping and P-type doping.
[0015] The super junction structure semiconductor device provided by the present invention provides a plurality of grooves arranged at intervals along the width direction of the device and a trench gate embedded in the groove in the body region, so that the source region can be formed in the gap between the plurality of grooves. Thus, the source region around each trench gate can form a current flow path along the extension direction of the trench gate inside the device, thereby forming a plurality of L-shaped second channels from the source region to the drain region. The number of channels inside the device increases, the current increases, thereby increasing the effective width of the device, improving the current capacity of the device, and reducing the cell area of the device under the same current capacity.
[0016] Furthermore, a planar gate and a trench gate are simultaneously provided in the superjunction structure semiconductor device. The source region below the planar gate can form a first channel leading to the drain region on the device surface, and the source region around the trench gate can form a second channel passing through the drain region inside the device. By combining the trench gate and the planar gate, the number of channels in the device is increased, the current capacity is enhanced, the effective width of the device is increased, and the effective width of the device that is reduced due to the presence of the P-type strip is compensated. Thus, the device performance is improved.
[0017] Furthermore, by providing a plurality of groove groups spaced apart from each other along the first direction in the body region, a second channel can be formed between the source region around each groove and the drain region, which significantly increases the number of second channels and improves the current capacity of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0019] Figure 1 A schematic diagram of the three-dimensional structure of a super junction structure semiconductor device in the prior art is shown;
[0020] Figure 2 and Figure 3 A schematic diagram of a three-dimensional structure and a schematic diagram of a three-dimensional structure decomposition of a super junction structure semiconductor device according to a first embodiment of the present invention are respectively shown;
[0021] Figure 4 Shows Figure 2 A schematic cross-sectional view of a superjunction structure semiconductor device taken along line AA';
[0022] Figure 5 Shows the corresponding Figure 2 A top view of a superjunction structure semiconductor device;
[0023] Figure 6 and Figure 7 A schematic diagram of a three-dimensional structure and a schematic diagram of a three-dimensional structure decomposition of a super junction structure semiconductor device according to a second embodiment of the present invention are respectively shown;
[0024] Figure 8 Shows Figure 6 A schematic cross-sectional view of a superjunction structure semiconductor device taken along line AA';
[0025] Fig. 9 Shows the corresponding Figure 6 Top view of a superjunction semiconductor device. DETAILED DESCRIPTION
[0026] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.
[0027] When describing the structure of a device, when a layer or a region is referred to as being "on" or "above" another layer or another region, it may mean being directly above the other layer or another region, or having other layers or regions between it and the other layer or another region. Furthermore, if the device is turned over, the layer or the region will be "below" or "beneath" the other layer or another region. In this application, the term "semiconductor structure" refers to the collective term for the entire semiconductor structure formed in the various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
[0028] Unless otherwise specified below, the various layers or regions of the semiconductor device may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC, and IV semiconductors, such as Si and Ge. The gate conductor and electrode layer may be formed of various conductive materials, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of the various conductive materials.
[0029] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.
[0030] Figure 2 and Figure 3 A schematic three-dimensional structure diagram and a schematic three-dimensional structure decomposition diagram of a super junction structure semiconductor device according to a first embodiment of the present invention are respectively shown. Figure 4 Shows Figure 2 Schematic diagram of the cross section of the super junction structure semiconductor device taken along line AA'. Figure 5 Shows the corresponding Figure 2 Top view of a superjunction semiconductor device.
[0031] Combination Figure 2-Figure 5 The superjunction structure semiconductor device of the first embodiment of the present invention is described by taking LDMOS (laterally-diffused metal-oxide semiconductor) as an example, and of course it can also be applied to superjunction LIGBT (lateral insulated-gate bipolar transistor). The superjunction structure semiconductor device 100 includes: a substrate 110, a drift layer 120 located above the substrate 110, a drain region 130 and a body region 150 located on a first side and a second side above the drift layer 120, respectively, and a superjunction structure 140 located between the drain region 130 and the body region 150, wherein a portion of the superjunction structure 140 is located in the drift region 120. Generally, in a semiconductor structure, it is a common operation to form another layer structure in a layer structure by a process such as implantation or doping, so Figure 3 The exploded view is given for clarity only. Figure 2 The shapes and positions of the layers in the three-dimensional diagram do not imply that the actual product can be decomposed in this way.
[0032] In this embodiment, the super junction structure 140 includes a plurality of alternately arranged N-type strips 142 and P-type strips 141, both of which extend along a first direction, and the P-type strips 141 and the N-type strips 142 are alternately arranged along a second direction, and the first direction is perpendicular to the second direction. Figure 2 It can be seen that the first direction can be regarded as the length direction of the device, that is, the direction from the first side to the second side, and the second direction can be regarded as the width direction of the device. The first ends of the P-type strips 141 and the N-type strips 142 of the super junction structure 140 are adjacent to the drain region 130, and the second ends are adjacent to the body region 150. The height of the super junction structure 140 in the device can be greater than, less than or equal to the body region 150. Taking N-type LDMOS as an example, the substrate 110 is P-type doped, the drift layer 120 is N-type doped, and the drain region 130 is an N+ injection region. The P-type doping here can be regarded as the first doping type, and the N-type doping can be regarded as the second doping type. Of course, based on the type of device, N-type doping and P-type doping can also be interchanged.
[0033] The super junction structure semiconductor device 100 of this embodiment further includes a gate oxide layer, the gate oxide layer includes a groove group that penetrates the body region 150 to reach the drift layer 120, and the groove group includes a plurality of grooves 171 arranged at intervals along the second direction, and the grooves 171 are oxide layers and also insulating layers. That is, the arrangement direction of the plurality of grooves 171 of the groove group is the same as the arrangement direction of the N-type strips 141 and the P-type strips 142 in the super junction structure 140. A groove gate 181 is also formed correspondingly in each groove 171, and the shape of the groove gate 181 matches the shape of the groove 171. The plurality of groove gates 181 can be regarded as part of the gate layer in this embodiment. The groove 171 can include a square groove, a hollow cylindrical groove or a hollow prismatic groove, etc., and the figure takes a square groove as an example. The groove group is located in the body region 150, that is, there is a part of the body region 150 between the groove group and the super junction structure 140, and there is also a part of the body region 150 on the other side of the groove group. The super junction structure semiconductor device 100 also includes a source region, which is at least located in the gap formed between the multiple grooves 171. When the semiconductor device is working, due to the effect of the channel gate 181, the source region between the grooves 171 first forms a current downward, and then converges to the drain region 130 to the right, forming an L-shaped second channel L2 located inside the device. Since the source region between each two adjacent grooves 171 can form such a second channel L2, the number of channels of the overall device is increased, the effective channel width of the device is increased, and the current capacity is improved.
[0034] Further, the gate oxide layer also includes a planar layer 172, and the planar layer 172 is located above the body region 150 between the groove group and the super junction structure 140, corresponding to covering the body region 150 of this part. Then correspondingly, the gate layer also includes a planar gate 182 located above the planar layer 172, and the planar gate 182 and the trench gate 181 can both be regarded as the gate of the device, and the planar layer 172 and the groove 171 can both be regarded as the gate oxide layer of the device. In this embodiment, the planar layer 172 is connected to the adjacent groove group as a whole, and the planar gate 182 is connected to the adjacent multiple trench gates 181 as a whole. Corresponding to the semiconductor structure with the planar gate 182, the source region is also located in the body region 150 below the planar gate 182, so that when the super junction structure semiconductor device 100 is in operation, a first channel L1 can be formed between the source region and the drain region 130 below the planar gate 182 along the surface of the device in the horizontal direction. Through the combination of trench gate and planar gate, the number of channels in the device is increased, the current capacity is enhanced, the effective width of the device is increased, and the effective width of the device is reduced due to the existence of P-type strips, thereby improving device performance.
[0035] Further, the source region includes a first source region 161, a second source region 162 and a third source region 163, and the first source region 161 is located in the body region 150 on the side of the groove group close to the super junction structure 140, and is adjacent to the groove group. The second source region 162 is located between the gaps of the plurality of grooves 171. The third source region 163 is located in the body region 150 on the side of the groove group away from the super junction structure 140, and is adjacent to the groove group. Therefore, the second source region 162 connects the first source region 161 and the third source region 163. The first source region 161, the third source region 163 and the drain region 130 all extend along the second direction. There is also a body contact region 151 in the body region 150 on the side of the groove group away from the super junction structure 140, and the body contact region 151 is adjacent to the third source region 163 and also extends along the second direction. The first source region 161 not only participates in the formation of the first channel L1, but also participates in the formation of the second channel L2, increasing the number of channels and improving the current capacity. Moreover, the source region around each groove 171 can form a second channel L2, which increases the effective width of the device and improves the device capability. In this embodiment, all gate layers (including the trench gate 181 and the planar gate 182) are connected to the same gate electrode G through a conductive material, all source regions (the first source region 161 to the third source region 163) are connected to the same source electrode S through a conductive material, all body regions 150 are connected to the same body region electrode P through a conductive material, and the drain region 130 is connected to the drain electrode D through a conductive material. The conductive material may be, for example, a metal.
[0036] The super junction structure semiconductor device 100 of this embodiment may further include a field oxide layer 190, which is distributed above the super junction structure 140. The plate layer 172 may partially cover the surface of the super junction structure 140, and the field oxide layer 190 is connected to the plate layer 172, and the planar gate 182 partially covers the surface of the field oxide layer 190. In order to clearly show the structure of the super junction structure 140, Figure 2 and Figure 5 The field oxide layer 190 is omitted.
[0037] The above structure is described by taking LDMOS as an example. Of course, this embodiment can also be applied to LIGBT devices. The difference between LIGBT and LDMOS is that the doping types of the drain region are opposite. Regardless of LDMOS or LIGBT, except for the substrate, all the above P-type doping and all the N-type doping types can be interchanged.
[0038] Figure 6 and Figure 7 A schematic diagram of a three-dimensional structure and a schematic diagram of a three-dimensional structure decomposition of a super junction structure semiconductor device according to a second embodiment of the present invention are respectively shown; Figure 8 Shows Figure 6 A schematic cross-sectional view of a superjunction structure semiconductor device taken along line AA'; Fig. 9 Shows the corresponding Figure 6 Top view of a superjunction semiconductor device.
[0039] Combination Figure 6-Figure 9 , a super junction structure semiconductor device 200 of the second embodiment of the present invention is provided, which adds some structures on the basis of the super junction structure semiconductor device 100 of the first embodiment. The super junction structure semiconductor device 200 of this embodiment also includes a substrate 210, a drift layer 220 located above the substrate 210, a drain region 230 and a body region 250 located on the first side and the second side above the drift layer 220, respectively, and a super junction structure 240 located between the drain region 230 and the body region 250, wherein the super junction structure 240 is partially located in the drift region 220 and includes alternately arranged P-type strips 241 and N-type strips 242. It also includes a source region (a first source region 261, a second source region 262, and a third source region 263), a gate oxide layer (including a groove group and a plate layer 272, wherein the groove group includes a plurality of grooves 271), a gate layer (including a trench gate 281 and a plane gate 282), and a field oxide layer 290. The shape, position, performance, doping type, and working principle of these layer structures are the same as those of the first embodiment.
[0040] The difference between this embodiment and the first embodiment is that, in this embodiment, there are multiple groove groups, that is, multiple groove groups are distributed in the body region 260, and the multiple groove groups are arranged at intervals along the first direction. Multiple grooves 271 of each groove group are correspondingly embedded with multiple trench gates 281, and each groove 271 is also surrounded by an active region. Figure 6-Figure 9 In the figure, from the second side to the first side, there are 3 groups of groove groups, and each groove group has a corresponding groove gate, namely, the groove gates GT1, GT2 and GT3. The groove gate GT1 can form a whole with the plane gate 282. Except for the groove group closest to the super junction structure 140, the third source region 263 is distributed on both sides of the other two groove groups, and the second source region 262 is distributed between each groove 271. A body contact region 251 is also distributed on the side of the body region 250 farthest from the super junction structure 240. In this embodiment, all gate layers (including the groove gates GT1-GT3 and the plane gate 182) are connected to the same gate electrode G through a conductive material, all source regions (the first source region 261 to the third source region 263) are connected to the same source electrode S through a conductive material, all body regions 250 are connected to the same body region electrode P through a conductive material, and the drain region 230 is connected to the drain electrode D through a conductive material. The conductive material may include a metal.
[0041] Therefore, compared with the first embodiment, this embodiment provides a plurality of groove groups spaced apart from each other along the first direction in the body region, so that the source region around each groove can form a second channel with the drain region, thereby significantly increasing the number of second channels and improving the current capacity of the device.
[0042] In summary, the super junction structure semiconductor device of the embodiment of the present invention is adopted, by providing a plurality of grooves arranged at intervals along the width direction of the device and a trench gate embedded with the groove in the body region, so that the source region can be formed in the gap between the plurality of grooves. Thus, the source region around each trench gate can form a current flow path along the extension direction of the trench gate inside the device, thereby forming a plurality of L-shaped second channels from the source region to the drain region. Moreover, a planar gate and a trench gate are provided at the same time, and the source region under the planar gate can form a first channel leading to the drain region on the surface of the device, and the source region around the trench gate can form a second channel passing through the drain region inside the device. Through the combination of the trench gate and the planar gate, the number of channels in the device is increased, the current capacity is enhanced, and the effective width of the device is increased. Under the same current capacity, the cell area of the device can be reduced, thereby improving the device performance.
[0043] Furthermore, by providing a plurality of groove groups spaced apart from each other along the first direction in the body region, a second channel can be formed between the source region around each groove and the drain region, which significantly increases the number of second channels and improves the current capacity of the device.
[0044] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A superjunction semiconductor device, comprising: a drift layer, stacked above the substrate layer; a drain region and a body region, respectively located on a first side and a second side above the drift layer; A super junction structure, located between the drain region and the body region, comprising a plurality of alternately arranged N-type strips and P-type strips; The gate oxide layer includes a groove group, wherein the groove group includes a plurality of grooves penetrating the body region and arranged at intervals from each other; A gate layer, comprising a plurality of trench gates respectively embedded in the plurality of grooves; The source region is at least located in the gaps formed between the plurality of grooves. Wherein, the arrangement direction of the plurality of grooves is the same as the arrangement direction of the N-type strips and the P-type strips.
2. The super junction structure semiconductor device according to claim 1, wherein: The gate oxide layer also includes a planar layer, which is located above the body region between the groove group and the super junction structure. The gate layer also includes a planar gate located above the planar layer. The source region is also located in the body region below the planar gate.
3. The super junction structure semiconductor device according to claim 2, wherein: The source region comprises: A first source region is located in the body region on a side of the groove group close to the super junction structure and is adjacent to the groove group; and A second source region is located between the gaps of the plurality of grooves; The third source region is located in the body region on a side of the groove group away from the super junction structure and is adjacent to the groove group. The second source region is connected to the first source region and the third source region.
4. The super junction structure semiconductor device according to claim 3, wherein: When the super junction structure semiconductor device is in operation, a first lateral channel is formed along the device surface between the first source region and the drain region, and an L-shaped second channel is formed along the inside of the device between the first source region to the third source region and the drain region respectively.
5. The super junction structure semiconductor device according to claim 2, further comprising: A field oxide layer is distributed above the super junction structure, the planar layer partially covers the surface of the super junction structure, the field oxide layer is connected to the planar layer, and the planar gate partially covers the surface of the field oxide layer.
6. The super junction structure semiconductor device according to claim 1, wherein: The P-type strips and the N-type strips extend along a first direction, and the P-type strips and the N-type strips are alternately arranged along a second direction, wherein the first direction is perpendicular to the second direction. A plurality of groove groups are distributed in the body region, and the plurality of groove groups are arranged at intervals along the first direction. A plurality of trench gates are correspondingly embedded in the plurality of grooves of each groove group, and each groove is surrounded by the source region.
7. The super junction structure semiconductor device according to claim 1, wherein: The groove includes a square groove, a hollow cylindrical groove or a hollow prism groove, and the shape of the groove grid matches the shape of the groove.
8. The super junction structure semiconductor device according to claim 2, wherein: The flat plate layer is connected to the adjacent groove groups as a whole, and the plane gate is connected to the adjacent plurality of groove gates as a whole.
9. The super junction structure semiconductor device according to claim 6, wherein: All of the gate layers are connected to the same gate electrode through conductive material, all of the source regions are connected to the same source electrode through conductive material, all of the body regions are connected to the same body region electrode through conductive material, and the drain region is connected to the drain electrode through conductive material.
10. The super junction structure semiconductor device according to claim 1, wherein: The body region has a first doping type, the drift layer and the source region have a second doping type, the first doping type is one of N-type doping and P-type doping, and the second doping type is the other of N-type doping and P-type doping.