Semiconductor device

Abstract

The invention provides a semiconductor device. The semiconductor device comprises a drift region of a first conductivity type; the body region of the second conduction type is arranged in the drift region; a plurality of closed regular hexagonal grooves; the cross section of each regular hexagonal groove is a closed regular hexagonal profile; the regular hexagonal groove is filled with a conductive material and is electrically isolated from other structures of the semiconductor device; the regular hexagonal grooves are adjacently arranged, and the adjacent edges of the adjacent regular hexagonal grooves are parallel to each other; the highly-doped source region of the first conduction type is embedded into the body region, and the source region is located between adjacent edges of the adjacent regular hexagonal grooves; and the contact region is arranged in the source region, and the contact region is connected with the source electrode or the emitter electrode. According to the semiconductor device, the gate trenches are arranged in the form of the closed hexagonal units, and the active regions are located between the adjacent hexagonal units, so that the power density can be improved, the switch controllability can be improved, and the design adjustability can be enhanced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a semiconductor device. Background Art

[0002] Semiconductor power devices with trench gate structures include trench metal oxide semiconductor field effect transistors (MOSFETs) and trench insulated gate bipolar transistors (IGBTs). These devices have a gate contact, which is electrically isolated from the rest of the transistor by a suitable insulating material (such as silicon dioxide) and is used to control the device and switch it from a blocking state to a conducting state, or vice versa. The gate is formed in a trench region formed by a process such as etching. A highly conductive region, usually called the source, is surrounded by the gate trench and contacts the main top metallization layer of the device. This allows the formation of a channel region in which carriers can flow, thereby conducting current. The main performance indicators of such power devices include the power loss generated when switching from a blocking state to a conducting state (or vice versa) under load and the power loss generated during the conduction phase. However, there are many other design considerations, such as controllability of the switching phase, dynamic overvoltage, and robustness of the device to harsh switching events or short circuit events. In order to achieve appropriate performance in a given application, the device must be optimized within a wide design space.

[0003] Such as MOSFET, IGBT or similar devices with an active region containing multiple trench structures. The device includes a semiconductor substrate of the first conductivity type, in which there is a region of the second conductivity type (body region), and a highly doped region of the first conductivity type (source region) is formed in the body region. In some embodiments of the device, another layer of the first conductivity type (enhancement region) may be included below the body region. Deep trenches are formed on either side of the body region and are electrically isolated from the rest of the semiconductor material by a layer of insulating material (such as silicon dioxide). These trenches are then filled with conductive material and connected to the gate electrode. In the body region, contacts can also be formed and connected to the emitter or source potential of the device. By adjusting the voltage on the gate electrode, the device can be switched from a conducting state to a blocking state, and vice versa. In the prior art, the grooves form stripes (such as the US patent document with publication number US8633510B2 and the Chinese patent document with publication number CN102044565A) or a grid layout, in which a stripe or a square can be called a unit. Examples of stripe layouts in the prior art are as follows Figure 1 As shown in a and b, the grid unit layout example is as follows Figure 1As shown in c. The stripe layout is the simplest possible way to combine a series of active units to form the active area of ​​the device, but there are some problems with this concept in terms of manufacturability and device performance. First, because the wafer is usually made very thin, the wafer is very sensitive to mechanical stress. When etching the deep trenches of the stripe layout in the wafer, all the long trenches extend in the same direction on the device and the wafer. When the trench density is too high, the wafer may begin to warp (or bend, deform), which brings challenges to wafer processing. At the same time, there is a certain limit on the density of the trenches, which also limits the channel density on the wafer. Secondly, the signal is transmitted through the relatively thin and resistive material in the trench, which may reduce the switching performance of the device, and two adjacent trenches may not be tightly coupled, resulting in an asymmetric channel region. Thirdly, a contact area must be formed between the two gate trenches of the active mesa, which is a limitation on the mesa boundary size. As shown in Figure 1 Although the grid layout shown in c solves some of the problems, especially achieving better coupling between two adjacent trenches, the manufacturability problem still exists. In addition, since the adjacent trenches are connected to each other, it is not easy to add a dummy trench for emitter bias in the grid layout, which requires considerable additional design effort. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a semiconductor device, in which gate trenches are arranged in the form of closed hexagonal units, and the active area is located between adjacent hexagonal units. This layout can increase power density and improve switch controllability, and enhance design adjustability.

[0005] In order to solve the above problems, the present invention provides a semiconductor device, comprising: a drift region of a first conductivity type; A body region of a second conductivity type, disposed in the drift region; A plurality of closed first regular hexagonal grooves, wherein the first regular hexagonal grooves extend from the upper surface of the semiconductor device to the body region; the cross section of each of the first regular hexagonal grooves is a closed regular hexagonal outline; the first regular hexagonal grooves are filled with a conductive material, and the conductive material is electrically isolated from other structures of the semiconductor device by a dielectric layer; the conductive material is connected to a gate electrode; the first regular hexagonal grooves are arranged adjacent to each other, and adjacent sides of adjacent first regular hexagonal grooves are parallel to each other; A highly doped source region of the first conductivity type is embedded in the body region, and the source region is located between adjacent sides of adjacent first regular hexagonal trenches; A contact region is provided in the source region, and the contact region is connected to a source electrode or an emitter electrode.

[0006] Preferably, it further comprises: an enhancement region of the first conductivity type, arranged below the body region; and the first regular hexagonal trench extends from the upper surface of the semiconductor device to the body region and the enhancement region.

[0007] Preferably, the spacing between adjacent first regular hexagonal grooves includes a first spacing and a second spacing, the second spacing is larger than the first spacing, and the contact area is only provided between adjacent first regular hexagonal grooves having a spacing of the second spacing.

[0008] Preferably, in the area between adjacent first regular hexagonal grooves with a spacing of the second spacing, the source region does not extend to the adjacent first regular hexagonal grooves on both sides in the width direction; or no source region is provided in the area between adjacent first regular hexagonal grooves with a spacing of the second spacing, and only a contact region is provided, and the contact region is connected to the source region between adjacent first regular hexagonal grooves with a spacing of the first spacing.

[0009] Preferably, adjacent first regular hexagonal grooves are interconnected by an additional conductive layer, an orthogonal groove, or a combination of the two to transmit gate signals; the conductive layer is arranged above the main semiconductor material; the orthogonal grooves extend from the upper surface of the semiconductor device to the body region, and there are one or more orthogonal grooves; in the area where the conductive layer is set, the contact area is interrupted; in the area where the orthogonal grooves are set, the source region is interrupted and no contact area is set.

[0010] Preferably, at least one first regular hexagonal trench surrounds a highly doped first floating p-well region of the second conductivity type, the depth of the first floating p-well region is greater than the depth of the first regular hexagonal trench, and the first floating p-well region is not electrically connected to the electrode.

[0011] Preferably, an emitter contact or a source contact is provided inside the at least one first regular hexagonal trench.

[0012] Preferably, the source region is interrupted in any proportion. Figure 1 As shown in b, a plurality of interruption regions are provided in the middle of the source region to control injection and reduce short-circuit current, and the ratio of the length of the interruption region to the length of the source region can be adjusted arbitrarily.

[0013] Preferably, at least one of the first regular hexagonal grooves is provided with a second regular hexagonal groove inside; the cross-section of the second regular hexagonal groove is a closed regular hexagonal outline; the second regular hexagonal groove is concentric with the first regular hexagonal groove, and the side length is smaller than the first regular hexagonal groove, and the side of the second regular hexagonal groove is parallel to the side of the first regular hexagonal groove; the second regular hexagonal groove extends from the upper surface of the semiconductor device to the body region and the enhancement region.

[0014] Preferably, in at least one of the first regular hexagonal trenches, a second floating P-well region is further provided in a region between the first regular hexagonal trench and the second regular hexagonal trench or in a region surrounded by the second regular hexagonal trench.

[0015] Preferably, in at least one of the first regular hexagonal trenches, an emitter contact or a source contact is provided in an area between the first regular hexagonal trench and the second regular hexagonal trench where the second floating P-well region is not provided, or in an area surrounded by the second regular hexagonal trench where the second floating P-well region is not provided.

[0016] Preferably, at least one of the second regular hexagonal trenches in the first regular hexagonal trenches is connected to an emitter or source potential.

[0017] Preferably, the second regular hexagonal groove is in a floating state.

[0018] Preferably, the side lengths of the first regular hexagonal grooves are the same.

[0019] Compared with the prior art, the present invention has the following beneficial effects: The semiconductor device of the present invention, wherein the gate trenches are arranged not in a stripe or grid pattern, but in a closed hexagonal unit form, and the active area is located between adjacent hexagonal units. The hexagonal units can be closely arranged in the required area so as to be able to conduct a specific current. Compared with the gate trenches arranged in stripes, the gate trenches arranged in regular hexagons greatly reduce the total length of a single trench, and under given geometric constraints, the hexagonal layout can achieve the highest channel density. The gate trenches are arranged in regular hexagons compared with the stripe arrangement. In the case of the same active and inactive table sizes, the hexagonal layout has more active areas per unit area.

[0020] Since wafers are usually made very thin, they are very sensitive to mechanical stress. When etching deep grooves in a wafer, when the groove density is too high, the wafer may begin to warp (or bend, deform), which is its limitation. In the semiconductor device of the present invention, a plurality of regular hexagonal grooves are uniformly etched into the semiconductor material in different directions, which greatly relieves the stress in the material.

[0021] The semiconductor device of the present invention adopts regular hexagonal gate trenches, so that gate signals can be distributed more evenly, and by using a proper layout, all trenches can be better coupled together, which has obvious advantages for very fast switch designs. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 11 is a top view of a conventional trench device with a stripe layout in the prior art, wherein a is a top view of a conventional trench device with a stripe layout including a floating P-well region in the prior art; b is a top view of a conventional trench device with a stripe layout including a floating P-well region and an interrupt source region in the prior art; c is a top view of a conventional trench device with a stripe layout including a floating P-well region, an interrupt source region and a dummy trench in the prior art; Figure 2 is a schematic diagram of a semiconductor device according to Embodiment 1 of the present invention, wherein a is a top view of the semiconductor device according to Embodiment 1 of the present invention; b is a longitudinal cross-sectional view obtained along a drawn tangent line (not drawn according to the relative proportion of the structure in a); Figure 3 is a top view of a semiconductor device according to a second embodiment of the present invention, wherein a is a top view of an example of the semiconductor device according to the second embodiment of the present invention; b is a top view of another example of the semiconductor device according to the second embodiment of the present invention; Figure 4 is a top view of a semiconductor device according to a fourth embodiment of the present invention, wherein a is a top view of an example of the semiconductor device according to the fourth embodiment of the present invention; b is a top view of another example of the semiconductor device according to the fourth embodiment of the present invention; Figure 5 is a schematic diagram of a semiconductor device according to Embodiment 3 of the present invention, wherein a is a top view of an exemplary structure of the semiconductor device according to Embodiment 3 of the present invention; b and c are longitudinal cross-sectional views obtained along the tangent lines drawn in a; Figure 6 Schematic diagram of another example of a semiconductor device according to Embodiment 3 of the present invention, wherein a is a top view of another example structure of a semiconductor device according to Embodiment 3 of the present invention; b is a top view of an example structure of an orthogonal groove having a higher ratio according to Embodiment 3; Figure 7 Schematic diagram of a third example of the semiconductor device of Embodiment 3 of the present invention, wherein a is a top view of the third example structure of the semiconductor device of Embodiment 3 of the present invention; b is a longitudinal cross-sectional view along the tangent line shown in a; Figure 8 Schematic diagram of an example structure of Embodiment 5 of the present invention, wherein a is a top view of an example structure of Embodiment 5 of the present invention; b is a longitudinal cross-sectional view obtained along the tangent line drawn in a; Fig. 9 Schematic diagram of an example structure of embodiment 6 of the present invention, wherein a is a top view of an example structure of embodiment 6 of the present invention; b is a longitudinal cross-sectional view obtained along the tangent line drawn in a; Fig.10is a top view of a semiconductor device according to a seventh embodiment of the present invention, wherein a is a top view of an example of the semiconductor device according to the seventh embodiment of the present invention, and b is a top view of another example of the semiconductor device according to the seventh embodiment of the present invention; Fig.11 is a schematic diagram of another structural example of Embodiment 7 of the present invention, wherein a is a top view of another structural example of Embodiment 7 of the present invention, and b is a longitudinal cross-sectional view obtained along the tangent line drawn in a; Fig.12 A comparison diagram of the gate trenches arranged in a regular hexagon and in a stripe arrangement; Fig.13 1 and 2 are top views of two exemplary semiconductor devices in Embodiment 2 of the present invention, wherein a is a top view of one exemplary semiconductor device in Embodiment 2 of the present invention, and b is a top view of another exemplary semiconductor device in Embodiment 2 of the present invention.

[0023] Among them: 1-body region; 2-enhancement region; 3-first regular hexagonal trench; 4-source region; 5-contact region; 6-active region; 7-conductive layer; 8-orthogonal trench; 9-first floating p-well region; 10-emitter contact or source contact; 11-second regular hexagonal trench; 12-second floating P-well region; 13-emitter contact or source contact; 14-emitter / source contact; 15-emitter contact; 16-inactive region. DETAILED DESCRIPTION

[0024] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solution of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Example 1

[0025] like Figure 2 a is a top view of the semiconductor device of this embodiment. Figure 2 b is Figure 2 The longitudinal section view obtained along the tangent line in a (not in accordance with Figure 2 The relative scale of the structure in a is shown).

[0026] A semiconductor device according to this embodiment includes: a drift region of a first conductivity type; A body region 1 of a second conductivity type, arranged in the drift region; An enhancement region 2 of the first conductivity type, arranged below the body region 1; A plurality of closed first regular hexagonal trenches 3 of the same size, the first regular hexagonal trenches 3 extending from the upper surface of the semiconductor device to the body region 1 and the enhancement region 2; the cross section of each first regular hexagonal trench 3 is a closed regular hexagonal outline; the first regular hexagonal trenches 3 are filled with a conductive material, and the conductive material is electrically isolated from other structures of the semiconductor device by a dielectric layer; the conductive material is connected to the gate electrode; the first regular hexagonal trenches 3 are arranged adjacent to each other, and adjacent sides of adjacent first regular hexagonal trenches 3 are parallel to each other; A highly doped source region 4 of the first conductivity type is embedded in the body region 1, and the source region 4 is located between adjacent sides of adjacent first regular hexagonal trenches 3; The contact region 5 is provided in the source region 4 and is connected to the source or emitter electrode.

[0027] In the semiconductor device of this embodiment, the gate trenches are not arranged in a stripe or grid pattern, but in a closed hexagonal unit, and the active area 6 is located between adjacent hexagonal units. The hexagonal units can be closely arranged in the required area so as to be able to conduct a specific current. Compared with the gate trenches arranged in stripes, the gate trenches arranged in regular hexagons greatly reduce the total length of a single trench. Under given geometric constraints, the hexagonal layout can achieve the highest channel density. Fig.12 As shown, the gate trenches are arranged in a regular hexagonal pattern compared with the stripe pattern. With the same active and inactive mesa sizes, the hexagonal pattern has more active areas per unit area.

[0028] Since wafers are usually made very thin, they are very sensitive to mechanical stress. When etching deep grooves in a wafer, when the groove density is too high, the wafer may begin to warp (or bend, deform), which is its limitation. In the semiconductor device of this embodiment, a number of regular hexagonal grooves are uniformly etched into the semiconductor material in different directions, which greatly relieves the stress in the material.

[0029] The semiconductor device of this embodiment adopts a regular hexagonal gate trench, and the gate signal can be distributed more evenly. The gate signal is input into the gate trench through the gate wiring structure. Usually, not too many gate wiring structures are arranged on the chip because this will reduce the effective area. In the classic strip layout, the coupling between adjacent trenches is very weak because the gate signal has to propagate a long way to reach this point. In the regular hexagonal layout of this embodiment, by using an appropriate layout, all trenches can be better coupled together. For very fast switch designs, this is an obvious advantage. Example 2

[0030] The semiconductor device of this embodiment is a further improvement based on Embodiment 1. Among the arrangements of multiple first regular hexagonal grooves, the adjacent first regular hexagonal grooves are separated by two different spacings (the spacing between adjacent first regular hexagonal grooves refers to the distance between adjacent sides of adjacent regular hexagonal grooves), a first spacing and a second spacing, with the first spacing < the second spacing. The contact region 5 is provided only between adjacent first regular hexagonal grooves with a spacing of the second spacing.

[0031] As Figure 3 shown in a, it is a top view of a structural example of the semiconductor device of this embodiment. Among them, each hexagonal groove is separated by two different distances d1 and d2, and the ratio of the area of the region with a distance of d1 to the area of the region with a distance of d2 is 2:1. d1 < d2, and the contact region 5 is formed only at d2.

[0032] Figure 3 Shown in b, it is a top view of another structural example of the semiconductor device of this embodiment. Each hexagonal groove is separated by two different distances d1 and d2, and the ratio of the area of the region with a distance of d1 to the area of the region with a distance of d2 is 1:2. d1 < d2, and the contact region 5 is formed only at d2.

[0033] The semiconductor device of this embodiment overcomes the critical dimension problem of the mesa caused by contact formation. The spacing between two adjacent hexagonal grooves can be changed as Figure 3 shown in a and b. The contact region can be formed only in the larger spacing region d2, while channel modulation mainly occurs in the narrower region d1. The different spacings can be arranged in various ways and ratios to optimize the channel density.

[0034] A further improvement is that, as Fig.13 shown in a, in the region between adjacent first regular hexagonal grooves with a spacing of the second spacing, the source region does not extend to the adjacent first regular hexagonal grooves on both sides in the width direction, or as Figure 4 shown in b, there is no source region in the region between adjacent first regular hexagonal grooves with a spacing of the second spacing, and only a contact region is provided. The contact region is connected to the source region between adjacent first regular hexagonal grooves with a spacing of the first spacing. That is, the source region is formed only on the small mesa, because otherwise, there would be active parts of two different mesas, which is not ideal. The contact region is only connected to the region where the small mesa and the large mesa meet, that is, connected to the source region. Embodiment 3

[0035] The semiconductor device of this embodiment is further improved on the basis of embodiment 1 in that adjacent first regular hexagonal grooves 3 are interconnected by one or a combination of an additional conductive layer 7 and orthogonal grooves 8 to transmit gate signals; the conductive layer 7 is arranged above the main semiconductor material; the orthogonal grooves 8 extend from the upper surface of the semiconductor device to the body region 1 and the enhancement region 2, and there are one or more orthogonal grooves 8; in the area where the conductive layer 7 is arranged, the contact area 5 is interrupted; in the area where the orthogonal grooves 8 are arranged, the source area 4 is interrupted and the contact area 5 is not arranged. In these areas, the source contact is disconnected. However, a channel area can still be formed under the polysilicon gate wiring, and the current is conducted through the source layer. The conductive layer can be doped polysilicon above the main semiconductor material.

[0036] like Figure 5 A in the figure is a top view of an exemplary structure of the semiconductor device of this embodiment, wherein adjacent first regular hexagonal trenches 3 are connected to each other through an additional conductive layer 7 to transmit gate signals. Figure 5 b and c are Figure 5 A conductive layer 7 is provided above the bulk semiconductor material, and in the active region extending in the x-direction, the contact region 5 is interrupted to accommodate conductive connections between the regular hexagonal trenches so as to connect them to the gate potential.

[0037] like Figure 6 Figure a is a top view of the second example structure of the semiconductor device of this embodiment, wherein adjacent first regular hexagonal grooves 3 are connected to each other through two grooves parallel to each other and perpendicular to the sides of the regular hexagonal grooves to transmit gate signals. In the area where the orthogonal grooves 8 are set, the source region 4 is interrupted and the contact region 5 is not set. This connection plays the role of source interruption and gate connection. Figure 6 Figure b is an example of a method with a higher ratio of orthogonal trenches 8. The use of double trenches also forms a source interruption region that can be used to control the minority carrier injection efficiency in the device.

[0038] like Figure 7 In a, a is a top view of the third exemplary structure of the semiconductor device of this embodiment, wherein adjacent first regular hexagonal trenches 3 are connected to each other via an orthogonal trench to transmit gate signals. Figure 7 b is along Figure 7 The longitudinal cross-sectional view obtained by drawing the tangent line shown in a. In the area where the orthogonal trench 8 is provided, the source region 4 is interrupted and the contact region 5 is not provided.

[0039] Further, each hexagonal trench can be connected to 0-6 adjacent hexagonal trenches through any one or a combination of the three connections mentioned above. This allows flexibility in designing devices to achieve the desired switch symmetry, source-to-source ratio, channel density, and contact area. Example 4

[0040] The semiconductor device of this embodiment is further improved on the basis of Embodiment 1 in that at least one first regular hexagonal trench 3 is surrounded by a highly doped first floating p-well region 9 of the second conductivity type, the depth of the first floating p-well region 9 is greater than the depth of the first regular hexagonal trench 3, and the first floating p-well region 9 is not electrically connected to the electrode. Figure 4 As shown in a.

[0041] In another embodiment, a further improvement on the basis of embodiment 1 is that an emitter contact or a source contact 10 is provided inside at least one first regular hexagonal trench. Figure 4 As shown in b.

[0042] The interior of the regular hexagonal trench can contain a floating P-well region for additional trench protection or an emitter shorting structure to improve switching controllability. These additional design elements can also be selectively applied only to certain hexagonal trenches. Example 5

[0043] The semiconductor device of this embodiment is further improved on the basis of Embodiment 1 in that at least one first regular hexagonal trench 3 is provided with a closed second regular hexagonal trench 11 inside; the cross section of the second regular hexagonal trench 11 is a closed regular hexagonal profile, the second regular hexagonal trench 11 is concentric with the first regular hexagonal trench 3, and the side length is smaller than the first regular hexagonal trench 3, and the side of the second regular hexagonal trench 11 is parallel to the side of the first regular hexagonal trench 3; the second regular hexagonal trench 11 extends from the upper surface of the semiconductor device to the body region 1 and the enhancement region 2. A second floating P-well region 12 is also provided in the area between the first regular hexagonal trench 3 and the second regular hexagonal trench 11 or in the area surrounded by the second regular hexagonal trench 11.

[0044] Figure 8 Figure a is a structural example of the present embodiment, in which a second floating P-well region 12 is provided in the region surrounded by the second regular hexagonal trench 11 inside. Figure 8 b is Figure 8 A longitudinal cross-sectional view of the device along the tangent line shown in a. The outer trench includes the active (gate) trench, and the inner hexagon is a dummy trench. The inner trench can be connected to the gate or emitter / source potential, which affects the switching behavior of the device. In addition, a floating P-well region is filled inside the inner regular hexagonal trench. Example 6

[0045] The semiconductor device of this embodiment is further improved on the basis of Embodiment 5 in that, in at least one first regular hexagonal trench 3, an emitter contact or a source contact 13 is provided in the area between the first regular hexagonal trench where the second floating P-well region 12 is not provided and the second regular hexagonal trench, or in the area surrounded by the second regular hexagonal trench where the second floating P-well region 12 is not provided.

[0046] like Fig. 9 Figure a is a structural example of this embodiment, using concentric hexagonal trench units, with the outer regular hexagon as an active trench and the inner regular hexagon as a virtual trench. No second floating P-well region 12 is provided between the concentric trench pairs, but a contact 13 is formed as a conductive path for majority carriers. The inner hexagon is filled with the second floating P-well region 12. Fig. 9 b is Fig. 9 A is a longitudinal section view obtained by drawing the tangent line shown in FIG. Example 7

[0047] The semiconductor device of this embodiment is further improved on the basis of embodiment 1 in that at least one first regular hexagonal trench 3 is provided with a closed second regular hexagonal trench 11 inside; and a second floating P-well region 12 is also provided in the region between the first regular hexagonal trench 3 and the second regular hexagonal trench 11. The outer hexagon serves as an active trench, and the inner hexagon serves as a virtual trench. Adjacent first regular hexagonal trenches 3 are connected to each other through an additional conductive layer 7 to transmit gate signals. In the active region extending along the x-direction, the contact region is interrupted to accommodate the conductive connection between the hexagonal trenches so as to connect them to the gate potential.

[0048] Fig.10 Figure a is a structural example of this embodiment, in which a floating P-well region is formed between concentric hexagons.

[0049] Fig.10 b is another structural example of this embodiment, and Fig.10 The difference in a is that the emitter / source contact 14 is located inside the inner hexagon.

[0050] Fig.11 In a and b, another structural example of this embodiment is shown. Fig.10 Based on the structure of b, an emitter contact 15 is also provided in the inner hexagonal trench to bias the virtual trench to the emitter / source potential.

[0051] In the solutions in the above-mentioned embodiments disclosed in the present invention, the above-mentioned design elements can be freely combined with each other, and any type of hexagonal units disclosed can be combined and arranged in the same semiconductor device in any proportion or pattern.

[0052] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A semiconductor device, characterized in that: include: a drift region of a first conductivity type; A body region of a second conductivity type, disposed in the drift region; A plurality of closed first regular hexagonal grooves, wherein the first regular hexagonal grooves extend from the upper surface of the semiconductor device to the body region; the cross section of each of the first regular hexagonal grooves is a closed regular hexagonal outline; the first regular hexagonal grooves are filled with a conductive material, and the conductive material is electrically isolated from other structures of the semiconductor device by a dielectric layer; the conductive material is connected to a gate electrode; the first regular hexagonal grooves are arranged adjacent to each other, and adjacent sides of adjacent first regular hexagonal grooves are parallel to each other; A highly doped source region of the first conductivity type is embedded in the body region, and the source region is located between adjacent sides of adjacent first regular hexagonal trenches; A contact region is provided in the source region, and the contact region is connected to a source electrode or an emitter electrode.

2. The semiconductor device according to claim 1, wherein: Also includes: An enhancement region of a first conductivity type, disposed below the body region; The first regular hexagonal trench extends from the upper surface of the semiconductor device into the body region and the enhancement region.

3. The semiconductor device according to claim 1, wherein: The spacing between adjacent first regular hexagonal grooves includes a first spacing and a second spacing, the second spacing is greater than the first spacing, and the contact area is only provided between adjacent first regular hexagonal grooves having a spacing of the second spacing.

4. The semiconductor device according to claim 3, wherein: In a region between adjacent first regular hexagonal trenches having a spacing of a second spacing, both sides of the source region in the width direction do not extend to the adjacent first regular hexagonal trenches; Or, no source region is provided in the region between adjacent first regular hexagonal trenches having a pitch of the second pitch, and only a contact region is provided, and the contact region is connected to the source region between adjacent first regular hexagonal trenches having a pitch of the first pitch.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: Adjacent first regular hexagonal grooves are interconnected through an additional conductive layer, an orthogonal groove, or a combination of the two to transmit gate signals; the conductive layer is arranged above the main semiconductor material; the orthogonal grooves extend from the upper surface of the semiconductor device to the body region, and there are one or more orthogonal grooves; in the area where the conductive layer is arranged, the contact area is interrupted; in the area where the orthogonal grooves are arranged, the source area is interrupted and no contact area is arranged.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that: A highly doped first floating p-well region of the second conductivity type is surrounded by at least one first regular hexagonal trench, the depth of the first floating p-well region is greater than the depth of the first regular hexagonal trench, and the first floating p-well region is not electrically connected to the electrode.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that: An emitter contact or a source contact is disposed inside the at least one first regular hexagonal trench.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that: The source region is interrupted in arbitrary proportions.

9. The semiconductor device according to any one of claims 1 to 4, characterized in that: A closed second regular hexagonal groove is provided inside at least one of the first regular hexagonal grooves; the cross section of the second regular hexagonal groove is a closed regular hexagonal profile, the second regular hexagonal groove is concentric with the first regular hexagonal groove, and the side length of the second regular hexagonal groove is smaller than that of the first regular hexagonal groove, and the side of the second regular hexagonal groove is parallel to the side of the first regular hexagonal groove; The second regular hexagonal trench extends from the upper surface of the semiconductor device into the body region and the enhancement region.

10. The semiconductor device according to claim 9, wherein: In at least one of the first regular hexagonal trenches, a second floating P-well region is further provided in a region between the first regular hexagonal trench and the second regular hexagonal trench or in a region surrounded by the second regular hexagonal trench.

11. The semiconductor device according to claim 10, characterized in that: In at least one of the first regular hexagonal trenches, an emitter contact or a source contact is provided in an area between the first regular hexagonal trench and the second regular hexagonal trench where the second floating P-well region is not provided, or in an area surrounded by the second regular hexagonal trench where the second floating P-well region is not provided.

12. The semiconductor device according to claim 9, wherein: The second regular hexagonal trench in at least one of the first regular hexagonal trenches is connected to an emitter or source potential.

13. The semiconductor device according to claim 9, wherein: The second regular hexagonal groove is in a floating state.

14. The semiconductor device according to any one of claims 1 to 4, characterized in that: The side lengths of the first regular hexagonal grooves are the same.

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