Method of manufacturing a semiconductor device

Abstract

The application provides a manufacturing method of a semiconductor device, which uses n-type ions with atomic weight greater than Ge to replace phosphorus ions in source-drain injection of an nMOS region and pre-amorphous injection ions in the prior art, so that an n-type source-drain injection region in an amorphous silicon state can be formed, the pre-amorphous injection in the prior art is omitted, and thus the process is simplified and the process cost is reduced. The injection of the n-type ions with atomic weight greater than Ge is more helpful to increase multiple grain cross points than the pre-amorphous injection of Ge, C and other ions in the prior art, can reduce the cobalt silicide crystal phase transition temperature of the nMOS region, on the basis of not sacrificing the thermal stability of the pMOS region, compatible with the requirement difference of the nMOS region and the pMOS region on the formation of cobalt silicide and the heat treatment temperature of the cobalt silicide from the high resistance phase to the low resistance phase, avoids the problems caused by the requirement difference, and can improve the device resistance. And the annealing activation process after the subsequent source-drain ion injection is performed after the formation of the cobalt silicide, and the device performance can be further improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device manufacturing, and particularly relates to a manufacturing method of a semiconductor device. BACKGROUND

[0002] When the feature size of integrated circuit manufacturing process is reduced to deep submicron, the feature size of transistor gate, source and drain active region and contact hole is continuously reduced, which results in the continuously increased series resistance of active region and contact resistance of contact hole, thereby affecting the speed of circuit.

[0003] In order to reduce the sheet resistance of polysilicon gate and active region and the contact resistance of contact hole, metal silicide process technology is developed and widely applied in integrated circuit manufacturing process.

[0004] Cobalt silicide (Co-Salicide, also known as cobalt silicide, which can be abbreviated as CoSi) has the advantages of good thermal stability and low resistance, and is the best choice for products requiring high temperature process, and the process node of CoSi is generally 0.25 μm-65 nm. With the further reduction of the feature size of devices, the difficulty of converting CoSi from high resistance phase to low resistance phase is also gradually increased. Therefore, in the current CoSi process, the industry usually further increases the process of pre-amorphous ion implantation (PAI) before depositing metal Co to improve the above-mentioned difficulty of converting CoSi from high resistance phase to low resistance phase with the reduction of size. The process flow is as follows:

[0005] First, please refer to (A) in Figure 1 After the pMOS region and the nMOS region are defined by the device isolation structure 301 on the substrate 300, the gate oxide layer 302 and the gate 303 are formed by the gate process, and the side wall 304 is further formed by the side wall process;

[0006] Then, please refer to (A) in Figure 1 The S / D IMP process is performed, that is, the pMOS region is masked and n-type ions such as phosphorus P are used to perform source and drain ion implantation on the nMOS region to form n-type source and drain implantation region 305n, and the nMOS region is masked and p-type ions such as boron B are used to perform source and drain ion implantation on the pMOS region to form p-type source and drain implantation region 305p;

[0007] Next, please refer to Figure 1(B) of FIG. 1, spike and laser spike anneal (LSA) are performed to anneal and activate the implanted ions in the n-type source / drain implant region 305n and the p-type source / drain implant region 305p, which will have lateral and vertical diffusion, so as to optimize the profile and doping uniformity of the n-type source / drain implant region 305n and the p-type source / drain implant region 305p;

[0008] Next, please refer to Figure 1 (B) of FIG. 1, the silicide barrier layer 306 required by the nMOS region and the pMOS region is formed by material deposition, photolithography, etching and other processes;

[0009] Then, please refer to Figure 1 (B) of FIG. 1, under the masking effect of the silicide barrier layer, a pre-amorphization ion implantation (PAI implantation) is performed on the nMOS region and the pMOS region. The PAI implantation ions are usually Ge, C and other elements. By using the PAI implantation ions, the atoms in the crystal lattice are displaced, so that the crystal is transformed into amorphous, and the CoSi crystal phase transition temperature can be reduced;

[0010] Next, please refer to Figure 1 (C) of FIG. 1, metal Co is deposited and two rapid thermal processes (RTP) are performed in sequence. During the thermal process, the amorphous layer generated by the PAI implantation can reduce the CoSi crystal phase transition temperature. Thus, after further removing the unreacted Co, a lower-resistance CoSi is formed in the region exposed by the silicide barrier layer 306;

[0011] After that, a contact hole etching stop layer (not shown in Figure 1 ) can be deposited, and subsequent metal connection (contact plug and metal interconnection line) and other processes are continued.

[0012] The above process has the following disadvantages:

[0013] (1) due to the existence of Ge, C and other elements injected by PAI, when the nMOS region and the pMOS region are simultaneously formed by two times of rapid thermal processing (RTP) to form CoSi, the nMOS region and the pMOS region actually have different requirements for the process temperature of RTP, generally, the nMOS region requires a higher RTP temperature (i.e. the temperature for high-to-low resistance phase transition) than the pMOS region, when the requirement of the nMOS region is met, the pMOS region is prone to have defects such as Co clustering due to the excessively high temperature, thereby destroying the uniformity and profile of CoSi formed on the substrate and increasing the resistance (Rs) of CoSi formed in the pMOS region, because Ge / C elements are also injected along with phosphorus P during source-drain ion implantation for the nMOS region, the PAI injection causes the increase of Ge / C elements again, and the existence of a large amount of Ge / C elements causes the high temperature to easily cause Co clustering; when the requirement of the pMOS region is met, the nMOS region is prone to have defects such as insufficient high-to-low resistance phase transition of CoSi due to the excessively low temperature, which also destroys the uniformity and profile of CoSi formed on the substrate and increases the resistance (Rs) of CoSi formed in the nMOS region, thereby limiting the improvement of device performance.

[0014] (2) because NiSi is prone to have defects such as clustering under high temperature conditions, the process temperature of subsequent metal connection processes and the like is generally limited to not exceeding 650℃, thereby failing to meet the requirements of some products which still need some high-temperature processes after the formation of metal silicide, and the application range is narrow.

[0015] (3) because the PAI injection process is additionally added, the process complexity and cost are increased.

[0016] (4) the ions implanted in the S / D of the pMOS region and the nMOS region have been activated by annealing before the deposition of the silicide barrier layer, when they are subjected to the two times of RTP for forming CoSi again, the ions in the n-type source-drain implantation region 305n and the p-type source-drain implantation region 305p which have been activated before will diffuse again, thereby causing the degradation of device performance. SUMMARY

[0017] The present application aims to provide a manufacturing method of a semiconductor device, which can simplify the process, improve the uniformity and profile of CoSi as a whole, and reduce the resistance of CoSi.

[0018] To achieve the above-mentioned purpose, the present application provides a manufacturing method of a semiconductor device, which comprises:

[0019] providing a substrate with an nMOS region and a pMOS region, and forming a gate on the nMOS region and the pMOS region;

[0020] masking the pMOS region and performing n-type ion implantation, wherein the n-type ion implantation includes n-type ions with atomic weight greater than Ge, to form n-type source-drain implant regions in the substrate on both sides of the gate of the nMOS region in amorphous silicon state, and masking the nMOS region and performing p-type ion implantation to form p-type source-drain implant regions in the substrate on both sides of the gate of the pMOS region;

[0021] forming a silicide blocking layer on the substrate of the nMOS region and the pMOS region, wherein the silicide blocking layer exposes at least part of the surface of the n-type source-drain implant regions, at least part of the surface of the p-type source-drain implant regions, and at least part of the surface of the top of each gate;

[0022] depositing cobalt and performing two different rapid thermal processes in sequence to form cobalt silicide on the exposed surfaces of the n-type source-drain implant regions, the p-type source-drain implant regions, and the gates, and to convert the high-resistance phase of the cobalt silicide into a low-resistance phase;

[0023] conformally depositing a contact hole etching stop layer on the cobalt silicide;

[0024] respectively performing a spike thermal annealing process and a laser spike annealing process to activate the n-type ions in the n-type source-drain implant regions and the p-type ions in the p-type source-drain implant regions.

[0025] Optionally, the n-type ions with atomic weight greater than Ge include at least one of As and Sb.

[0026] Optionally, the n-type ions with atomic weight greater than Ge have an implantation energy of 12 keV to 16 keV and a doping concentration of 2e+15 cm -2 to 3e+15 cm -2 .

[0027] Optionally, the spike thermal annealing process has a temperature range of 1040°C to 1060°C, and the laser spike annealing process has a temperature range of 1100°C to 1200°C.

[0028] Optionally, the contact hole etching stop layer has a thickness of 5 nm to 20 nm.

[0029] Optionally, the manufacturing method further includes forming at least one contact plug and at least one metal interconnection line through a metal connection process, wherein each contact plug penetrates the contact hole etching stop layer from top to bottom, and the bottom is in electrical contact with the cobalt silicide of the corresponding region, and the top is in electrical contact with the corresponding metal interconnection line.

[0030] Optionally, the metal connection process has a temperature higher than 650°C.

[0031] Optionally, when the n-type ion implantation is performed, at least one of Ge, C, F, N is implanted into the substrate on both sides of the gate of the nMOS region as impurity ions together with the n-type ion with atomic weight greater than Ge by means of co-ion implantation.

[0032] Optionally, the p-type ion comprises at least one of B, BF2, Ga, In.

[0033] Optionally, when the p-type ion implantation is performed, at least one of Ge, C, F, N, P is implanted into the substrate on both sides of the gate of the pMOS region as impurity ions together with the p-type ion by means of co-ion implantation.

[0034] Optionally, after the gate is formed on the nMOS region and the pMOS region and before the n-type ion implantation and the p-type ion implantation are performed, the method further comprises: forming a sidewall on the sidewall of each gate; or, after the high-resistance phase of the cobalt silicide is converted into a low-resistance phase and before the contact hole etching stop layer is conformally deposited on the cobalt silicide, the method further comprises: removing the unreacted metal and further removing the silicide barrier layer.

[0035] Compared with the prior art, the technical scheme of the present application has at least one of the following beneficial effects:

[0036] 1. The source and drain implantation of the nMOS region is performed by means of the n-type ion with atomic weight greater than Ge instead of phosphorus P in the prior art, which not only forms the n-type source and drain implantation region in the nMOS region in the state of amorphous silicon (i.e. α-Si), but also eliminates the pre-amorphization implantation (PAI) before the deposition of Co in the prior art, without increasing the mask, simplifying the process and reducing the process cost.

[0037] 2. The implantation of n-type ions (e.g. As, Sb, etc.) with atomic weight greater than Ge not only forms amorphous silicon in the n-type source / drain implantation region, but also helps to increase the number of multiple grain cross points in the n-type source / drain implantation region (because of the greater atomic weight), making the process of reaction between silicon (Si) and cobalt (Co) to form CoSi easier, i.e. the temperature required for the formation of CoSi is lower, and the phase transition temperature of the formed CoSi is lower. In addition, the process of pre-amorphous implantation of ions such as Ge and C in the pMOS region is also eliminated, so that the phase transition temperature in the process of conversion of CoSi in the nMOS region from the high resistance phase to the low resistance phase can be reduced without sacrificing the thermal stability of CoSi in the pMOS region, and the heat treatment temperature for the formation of CoSi and the phase transition of the formed CoSi in the pMOS region and the nMOS region can be adjusted to be substantially the same, and Co clusters are not easily generated. The demand gap for the heat treatment temperature for the formation of CoSi and the conversion of CoSi from the high resistance phase to the low resistance phase in the nMOS region and the pMOS region is compatible, and the problems of CoSi consistency and morphology difference and CoSi resistance in the prior art caused by the demand gap are avoided, and the device resistance can be improved at the same heat treatment temperature.

[0038] 3. The annealing activation process after the source / drain ion implantation is adjusted to be after the deposition of the contact hole etching stop layer, which not only activates the source / drain ion implantation ions in the nMOS region and the pMOS region at the same time, but also performs more annealing processes on CoSi at the same time. In addition, the spike heat annealing (spike) process and the laser spike annealing (LSA) process do not cause Co clusters and do not increase the damage to the consistency and profile of CoSi because of the short heating time, and further improve the conversion of CoSi from the high resistance phase to the low resistance phase without causing Co clusters and without increasing the damage to the consistency and profile of CoSi. Therefore, compared with the prior art, the resistance (Rs) of the formed CoSi can be further reduced, and the device performance can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0039] Those skilled in the art will understand that the provided drawings are for a better understanding of the present application, and do not constitute any limitation on the scope of the present application. Among them:

[0040] Figure 1 is a device structure cross-sectional schematic diagram in a prior semiconductor device manufacturing method.

[0041] Figure 2 is a flowchart of a semiconductor device manufacturing method according to an embodiment of the present application.

[0042] Figure 3 is a device structure cross-sectional view in a manufacturing method of a semiconductor device according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application. It should be understood that the present application can be practiced with modification and alteration, and that the present application is not limited to the embodiments described. Rather, the embodiments are provided as examples to fully and entirely disclose the present application, and to fully and entirely convey the scope of the present application to those skilled in the art. Like reference numerals refer to like elements throughout the specification. It should be understood that when an element is referred to as being "connected to" another element, it can be directly connected to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements present. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0044] The technical solutions of the present application are further described in detail below in conjunction with the drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description. It should be noted that the drawings are very simplified and use non-precise proportions, only for the purpose of conveniently and clearly assisting the description of the embodiments of the present application.

[0045] Referring to Figure 2 , an embodiment of the present application provides a manufacturing method of a semiconductor device, comprising the following steps:

[0046] S1, providing a substrate with an nMOS region and a pMOS region, and forming a gate on the nMOS region and the pMOS region;

[0047] S2, masking the pMOS region and performing n-type ion implantation, wherein the n-type ions include n-type ions with atomic weight greater than Ge, to form n-type source-drain implantation regions in amorphous silicon state in the substrate on both sides of the gate of the nMOS region, and masking the nMOS region and performing p-type ion implantation to form p-type source-drain implantation regions in the substrate on both sides of the gate of the pMOS region;

[0048] S3, forming a silicide barrier layer on the substrate of the nMOS region and the pMOS region, the silicide barrier layer exposing at least part of the surface of the n-type source-drain implantation region, at least part of the surface of the p-type source-drain implantation region and at least part of the surface of each of the gate tops;

[0049] S4, depositing metal cobalt and performing two different rapid thermal processes in succession to form cobalt silicide on the exposed surfaces of the n-type source-drain implantation region, the p-type source-drain implantation region and each of the gates, while converting the high-resistance phase of the cobalt silicide into a low-resistance phase;

[0050] S5, conformally depositing a contact hole etching stop layer on the cobalt silicide and the silicide barrier layer;

[0051] S6, performing heat treatment by a spike thermal annealing process and a laser spike annealing process respectively to activate the n-type ions in the n-type source-drain implantation region and the p-type ions in the p-type source-drain implantation region.

[0052] Please refer to (A) in Figure 3 , in step S1, first, a substrate 100 is provided, the material of the substrate 100 can be any suitable semiconductor material such as silicon (Si), silicon germanium (GeSi), silicon carbide (SiC) or silicon on insulator (SOI), a device isolation structure 101 can be formed in the substrate 100 by any suitable device isolation process such as a shallow trench isolation process or a local field oxide isolation process, thereby defining the corresponding nMOS region and pMOS region, and before or after forming the device isolation structure 101, a corresponding n-type well (not shown) or p-type well (not shown) can also be formed in the substrate 100 of the nMOS region or pMOS region by a corresponding ion implantation process; then, a gate oxide layer 102 is synchronously formed on the substrate 100 of the nMOS region and the pMOS region by any suitable process such as thermal oxidation or chemical vapor deposition, and further, polycrystalline silicon is deposited on the gate oxide layer 102 and gate lithography and etching are performed, thereby synchronously forming corresponding polycrystalline silicon gates 103 on the nMOS region and the pMOS region; then, a side wall 104 is formed on the side wall of the polycrystalline silicon gate 103 by a side wall process.

[0053] Please refer to (A) and (B) in Figure 3 , in step S2, the pMOS region can be masked first and n-type ion implantation is performed, and then the nMOS region is masked and p-type ion implantation is performed; or the nMOS region can be masked first and p-type ion implantation is performed, and then the pMOS region is masked and n-type ion implantation is performed.

[0054] As an example, the process in step S2 is as follows:

[0055] First, please refer to Figure 3(A) in FIG. 1, a photoresist is coated and developed by using a mask for forming the source / drain of the nMOS device (i.e. nMOS S / D mask) to form a patterned photoresist 200.

[0056] Then, the substrate 100 of the nMOS region is implanted with n-type ions to form n-type source / drain implant regions 105n in the substrate 100 on both sides of the polysilicon gate 103 of the nMOS region, with the patterned photoresist 200, the polysilicon gate 103 and the sidewall 104 of the nMOS region as masks (i.e. n-type ion implantation is performed on the nMOS region). The n-type ions for the source / drain ion implantation include n-type ions with atomic weight greater than Ge, and are usually heavily doped, thus destroying the crystal lattice of the substrate 100 at the implantation site, and making the n-type source / drain implant regions 105n in amorphous silicon (a-Si) state. The n-type ions with atomic weight greater than Ge are actually used to replace the conventional phosphorus (P) ions for nMOS source / drain implantation in the prior art, and Ge, C, etc. ions for pre-amorphization implantation between Co deposition in the prior art. Since the atomic weight of the n-type ions is greater than Ge, the implantation energy can help to increase the number of multiple grain cross points in the n-type source / drain implant regions 105n, and improve the amorphization degree and uniformity, which is beneficial to reduce the CoSi phase transition temperature in the subsequent step S3. Optionally, the n-type ions with atomic weight greater than Ge include at least one of arsenic (As) and antimony (Sb). For example, the n-type ions with atomic weight greater than Ge are As.

[0057] Optionally, when the substrate 100 of the nMOS region is implanted with n-type ions to form n-type source / drain implant regions 105n in the substrate 100 on both sides of the polysilicon gate 103 of the nMOS region, with the patterned photoresist 200, the polysilicon gate 103 and the sidewall 104 of the nMOS region as masks, at least one of Ge (germanium), C (carbon), F (fluorine), N (nitrogen) impurity ions is implanted into the substrate 100 on both sides of the polysilicon gate 103 of the nMOS region by using a common ion implantation method together with the n-type ions with atomic weight greater than Ge. The implantation of these at least one of Ge, C, F, N impurity ions can play a role in inhibiting the diffusion of doping elements during annealing, improving the activation rate of doping elements, reducing the drain-induced barrier lowering (DIBL) effect, adjusting the final depth, profile of the junction at the n-type source / drain implant regions 105n, and improving device reliability and extending device service life, etc.

[0058] Then, the patterned photoresist 200 is removed by a suitable photoresist removal process, and a photoresist is coated and developed by using a mask for forming the source / drain of the pMOS device (i.e. pMOS S / D mask) to form a patterned photoresist 201.

[0059] Then, the p-type ions are used to perform source-drain ion implantation on the substrate 100 of the pMOS region with the patterned photoresist 201, the polysilicon gate 103 and the sidewall 104 of the pMOS region as masks, so as to form a p-type source-drain implantation region 105p in the substrate 100 on both sides of the polysilicon gate 103 of the pMOS region. The p-type ions of the source-drain ion implantation include at least one of B (boron), BF2 (boron fluoride), Ga (gallium) and In (indium). By controlling the process parameters such as the implantation dose and the implantation energy of the p-type ions, the p-type ions can cause the substrate 100 to be amorphized to a sufficient degree after being implanted into the substrate 100, so as to meet the requirements of CoSi formation and phase transition on the pMOS region. Alternatively, when the p-type ions are used to perform source-drain ion implantation on the substrate 100 of the pMOS region with the patterned photoresist 201, the polysilicon gate 103 and the sidewall 104 of the pMOS region as masks, the impurity ions of at least one of Ge, C, F, N and P (phosphorus) are also implanted into the substrate 100 on both sides of the gate of the pMOS region by means of common ion implantation. The implantation of the impurity ions of at least one of Ge, C, F, N and P can play a role in inhibiting the diffusion of doping elements during the subsequent annealing process, improving the activation rate of the doping elements, reducing the effect of barrier reduction (DIBL) introduced by the drain, adjusting the final depth, profile and the like of the junction of the p-type source-drain implantation region 105p, and improving the reliability and prolonging the service life of the device.

[0060] It should be understood that in this step, the implantation of the n-type ions with an atomic mass greater than Ge actually replaces the phosphorus P ions commonly used as the source-drain implantation of the nMOS region in the prior art and the Ge, C and the like ions used in the pre-amorphization implantation before the deposition of Co in the prior art, so that the implantation dose, the implantation energy and the implantation type and the like process parameters of the n-type ions with an atomic mass greater than Ge can be controlled to meet the requirements of the source-drain performance of the original nMOS region and the amorphization degree achieved by the pre-amorphization implantation. The n-type ions with an atomic mass greater than Ge can be heavily doped, and the implantation dose and the like parameters of the other ions implanted at the same time can be unchanged relative to the prior art. Alternatively, the implantation energy of the n-type ions with an atomic mass greater than Ge is 12 keV to 16 keV, the doping concentration is 2e+15 cm -2 ~ 3e+15 cm -2The n-type ions with atomic weight greater than Ge will destroy the lattice of the substrate 100 at the injection site, which will help to increase the multi-grain cross points in the n-type source / drain implantation region 105n, and make the n-type source / drain implantation region 105n present in a sufficient amorphous silicon (a-Si) state, which is beneficial to reduce the CoSi phase transition temperature on the n-type source / drain implantation region 105n in the subsequent step S4.

[0061] Please refer to (C) in Figure 3 In step S3, a silicide area block (SAB) layer 106 is formed by deposition, photolithography and etching of a SAB material, which exposes at least part of the top surface of each polysilicon gate 103, and at least part of the top surface of the n-type source / drain implantation region 105n and the p-type source / drain implantation region 105p. Specifically, first, the SAB layer 106 (e.g., a material such as silicon oxide, silicon nitride or silicon oxynitride) can be deposited by any suitable process such as chemical vapor deposition; then, a patterned photoresist layer (not shown) is formed on the SAB layer 106 by a photolithography process, which aims to define the area where the SAB layer 106 needs to be reserved (i.e., the area where cobalt silicide is not needed to be formed); then, the SAB layer 106 is etched by any suitable etching process such as dry etching, with the patterned photoresist layer as a mask, so that the remaining SAB layer 106 can expose at least part of the top surface of each polysilicon gate 103, and at least part of the top surface of the n-type source / drain implantation region 105n and the p-type source / drain implantation region 105p, and mask the sidewall of each sidewall 104 and other surfaces, in preparation for the formation of cobalt silicide in the next step; then, the patterned photoresist layer is removed by any suitable stripping process such as wet etching. Thus, when cobalt silicide is formed on the n-type source / drain implantation region 105n and the p-type source / drain implantation region 105p subsequently, cobalt silicide will also be formed on the top surface of each polysilicon gate 103.

[0062] In other embodiments of the present application, according to the device performance and design requirements, the SAB layer 106 remaining after etching not only masks the sidewall of each sidewall 104 and other surfaces, but also masks the top surface of each polysilicon gate 103, so that when cobalt silicide is formed on the n-type source / drain implantation region 105n and the p-type source / drain implantation region 105p subsequently, cobalt silicide will not be formed on the top surface of each polysilicon gate 103.

[0063] In step S4, first, please refer to Figure 3(D) in FIG. 1 1, the metal Co 107 is deposited by any suitable process such as sputtering deposition, and the surfaces of the n-type source / drain implant regions 105n, the p-type source / drain implant regions 105p and the polysilicon gates 103 exposed by the silicide blocking layer 106 are in direct contact with the metal Co 107; then, please refer to Figure 3 (E) in FIG. 1 1, the metal Co 107 reacts with the silicon in the surfaces of the n-type source / drain implant regions 105n, the p-type source / drain implant regions 105p and the polysilicon gates 103 exposed by the silicide blocking layer 106 to form the high-resistance phase of cobalt silicide (CoSi) 108 by a first rapid thermal process (RTP) such as rapid thermal annealing, which consumes less silicon in the n-type source / drain implant regions 105n, the p-type source / drain implant regions 105p and the polysilicon gates 103 and does not degrade the device performance; then, please refer to Figure 3 (E) in FIG. 1 1, the high-resistance phase of cobalt silicide in the cobalt silicide 108 layer is converted to the low-resistance phase of cobalt silicide (for example, from the high-resistance CoSi2phase to the low-resistance CoSi phase or Co2Si phase) by a second rapid thermal process (RTP) such as sub-rapid thermal annealing, which has a higher temperature than the first rapid thermal process (RTP).

[0064] In this step S4, the n-type source / drain implant regions 105n and the polysilicon gates 103 in the nMOS region have multiple grain cross points due to the presence of n-type ions with atomic weight greater than Ge, so that the phase transition temperature of the cobalt silicide 108 on the top surface of the n-type source / drain implant regions 105n and the polysilicon gates 103 in the nMOS region is lowered when the high-resistance phase of cobalt silicide 108 is converted to the low-resistance phase (for example, from the high-resistance CoSi2phase to the low-resistance CoSi phase or Co2Si phase), and at the same phase transition temperature as the pMOS region, more low-resistance cobalt silicide phases are formed, thereby reducing the resistance Rs of the cobalt silicide 108 on the n-type source / drain implant regions 105n and the polysilicon gates 103 in the nMOS region.

[0065] Furthermore, in the two rapid thermal processes for forming the cobalt silicide 108, the n-type ions with atomic weight greater than Ge (for example, As, Sb, etc.) replace the pre-amorphous ions of Ge, C, etc. in the prior art, so that the nMOS region does not easily cause clustering of Co due to the presence of excess ions of Ge, C, etc. during the conversion of the CoSi in the nMOS region from the high-resistance phase to the low-resistance phase, and thus the uniformity and profile of the cobalt silicide 108 formed in the nMOS region are better than in the prior art, i.e. the resistance (Rs) of the cobalt silicide 108 formed in the nMOS region is further reduced, thereby facilitating the improvement of the performance of the nMOS device.

[0066] In addition, the p-type ion implantation of the pMOS region is different from the n-type ion implantation of the nMOS region, and without the subsequent annealing activation of S6, the pMOS region does not need to introduce additional Ge / C for pre-amorphization as in the prior art, but utilizes the characteristic that the implanted p-type ions can cause amorphization of the substrate and the characteristic that the cobalt silicide 108 required in the pMOS region in the prior art has a low phase transition temperature from the high resistance phase to the low resistance phase, so that in step S4, the formation of CoSi and the heat treatment temperature for the phase transition of CoSi from the high resistance phase to the low resistance phase of the nMOS region and the pMOS region can be adjusted to be substantially the same, and on the basis of not sacrificing the thermal stability of the cobalt silicide 108 of the pMOS region, the nMOS region and the pMOS region can form the required cobalt silicide 108 together, and at this heat treatment temperature, Co clusters are not easily generated in the pMOS region, so that the uniformity and profile of the cobalt silicide 108 formed in the pMOS region are not damaged, and compared with the prior art, the resistance (Rs) of the cobalt silicide 108 formed in the pMOS region is reduced, and the performance of the pMOS device is improved.

[0067] In summary, since the nMOS region uses n-type ions (such as As, Sb, etc.) with an atomic weight greater than Ge for source and drain implantation, the process of simultaneously performing PAI implantation in the nMOS region and the pMOS region in the prior art is omitted, and the difference in the requirements for the heat treatment temperature for the formation of CoSi and the phase transition of CoSi from the high resistance phase to the low resistance phase of the nMOS region and the pMOS region is compatible, the problems of poor uniformity and profile of CoSi and high resistance of CoSi caused by the difference in the requirements in the prior art are avoided, and the device resistance is improved at the same heat treatment temperature.

[0068] As an example, in this step S4, due to the presence of n-type ions (such as As, Sb, etc.) with an atomic weight greater than Ge, the temperature range of the two rapid heat treatment processes is 400-800°C, among which, the cobalt silicide is particularly suitable for products requiring high-temperature processes, has the advantages of good thermal stability and low resistance, and is formed after treatment with n-type ions with an atomic weight greater than Ge, and is particularly suitable for products requiring high-temperature processes and can be further applied to the manufacture of small-size products.

[0069] Further, please refer to (E) in Figure 3 After the formation of the cobalt silicide 108, the metal Co 107 that has not reacted with silicon can be removed by wet etching to prevent the remaining metal Co 107 from bridging to cause a short circuit of the circuit.

[0070] Please refer to Figure 3In (F) of FIG. 1, in step S5, the silicide blocking layer 106 can be removed first by any suitable process such as wet etching, and then a contact hole etching stop layer 109 is deposited by a process such as chemical vapor deposition, which is thin and conformally covers the device surface previously covered by the silicide blocking layer 106 and the cobalt silicide 108. The material of the contact hole etching stop layer 109 can be any suitable material such as silicon oxide, silicon nitride or silicon oxynitride, and can be a single layer or a multi-layer structure.

[0071] As an example, the thickness of the contact hole etching stop layer 109 is 5-50 nm.

[0072] In other embodiments of the present application, the silicide blocking layer 106 can be retained before the deposition of the contact hole etching stop layer 109, according to the device performance and design requirements, so that the contact hole etching stop layer 109 is deposited on the silicide blocking layer 106 and the cobalt silicide 108.

[0073] Please refer to Figure 3 In (F) of FIG. 1, in step S6, the n-type ions and the p-type ions implanted in the n-type source / drain implant region 105n and the p-type source / drain implant region 105p, respectively, are activated by annealing, so as to form the source / drain regions 105n' and 105p' required by the nMOS and pMOS transistors, respectively, on both sides of the polysilicon gate 103 in the nMOS region and the pMOS region, by using a spike anneal process followed by a laser anneal process.

[0074] In the present embodiment, since the n-type ions with a larger atomic weight such as As are used to replace the phosphorus P ions in the prior art for the source / drain implant in the nMOS region in step S2, a shallower junction depth can be formed under the same implantation energy, which is beneficial to improve the device performance.

[0075] As an example, the temperature range of the spike anneal process is 1040-1060°C, and the temperature range of the laser anneal process is 1100-1200°C, which can activate the n-type ions and the p-type ions, reduce the diffusion of the corresponding doping ions in the n-type source / drain implant region 105n and the p-type source / drain implant region 105p, eliminate the amorphization and lattice damage in the n-type source / drain implant region 105n and the p-type source / drain implant region 105p, and also re-anneal the cobalt silicide 108 on the nMOS region and the pMOS region to increase the effect of the phase transition of the cobalt silicide 108 from a high resistance phase to a low resistance phase, so that the resistance (Rs) of the formed cobalt silicide 108 can be reduced more than the prior art, which is beneficial to improve the device performance.

[0076] In addition, compared with the prior art, the step S6 for activating the n-type ions and the p-type ions for source-drain implantation is performed after the two rapid thermal processing steps (i.e. step S4) for forming the cobalt silicide 108, which can effectively solve the problem of the performance degradation of the device caused by the re-diffusion of the MOS region at the source and drain when the MOS region at the source and drain undergoes the two rapid thermal processing steps for forming the cobalt silicide 108, thereby ensuring the performance of the device.

[0077] In this step, the contact hole etching stop layer 109 can prevent the oxidation of the cobalt silicide 108.

[0078] After the step S6, subsequent processes can be performed, such as a metal gate replacement process and a metal connection process, and the like, to complete the manufacturing of the semiconductor device. These subsequent processes can allow the process temperature to be higher than 650°C, which will not be limited by the Co cluster problem as in the prior art, and can meet the needs of some products that still require some high-temperature processes after the formation of CoSi, and have a wider range of applications.

[0079] As an example, after the step S6 (i.e. after the annealing activates the n-type ions implanted in the n-type source-drain implantation region 105n and the p-type source-drain implantation region 105p), the manufacturing method further comprises depositing an interlayer dielectric layer (not shown) and further forming at least one contact plug (not shown) and at least one metal interconnection line (not shown) through a metal connection process (including a contact hole process, a metal interconnection process, etc.), wherein each of the contact plugs penetrates the interlayer dielectric layer and the contact hole etching stop layer from top to bottom, and the bottom is in electrical contact with the cobalt silicide 108 in the corresponding region, and the top is in electrical contact with the corresponding metal interconnection line. The process of depositing the interlayer dielectric layer and the temperature of the metal connection process are both allowed to be higher than 650°C. In addition, the process of depositing the interlayer dielectric layer and the metal connection process described above are both conventional techniques in the art, and will not be described here.

[0080] It is found through tests that, under the condition that other conditions remain unchanged, the n-type ions with an atomic weight greater than Ge such as As are used to replace the phosphorus P ions in the nMOS region source-drain ion implantation stage in the prior art, and the process of annealing to activate the n-type ions implanted in the nMOS region and the p-type ions implanted in the pMOS region is adjusted to be after the formation and phase transition of the cobalt silicide 108, which not only effectively activates the implanted n-type ions and p-type ions, but also reduces the resistance Rs of the source and drain by 18% to 34% (the activation degree is inversely proportional to the resistance value, and the diffusion degree is proportional to the resistance value, so it can be seen that the use of the present application makes the activation effect better and the diffusion degree less).

[0081] In addition, the resistance of cobalt silicide can be effectively reduced. Through testing, the resistance Rs of cobalt silicide of the most difficult phase transition test key is reduced by 35% to 42%, which shows that the technical scheme of the application can break through the limitation of the existing cobalt silicide process node of 0.25 μm to 65 nm, and can make the Co silicidation process still have application value in a smaller process node.

[0082] In summary, the manufacturing method of the semiconductor device provided by the application can replace the phosphorus P in the prior art with the n-type ion with an atomic weight greater than Ge to perform source-drain implantation in the nMOS region, without changing other doping elements (such as Ge and C used to improve DBIL in NMOS and PMOS) required to be implanted in one pass when source-drain implantation is performed and used to improve device performance. Not only can the n-type source-drain implantation region in the nMOS region be formed in an amorphous silicon (i.e., α-Si) state, but also the pre-amorphization implantation before deposition of Co in the prior art can be omitted, without increasing a mask (also referred to as a mask), simplifying the process, and reducing the process cost. In addition, the implantation of the n-type ion (for example, As and Sb) with an atomic weight greater than Ge not only forms amorphous silicon in the n-type source-drain implantation region, but also is more conducive to increasing the multiple grain cross points in the n-type source-drain implantation region (because the atomic weight is greater), making the reaction of silicon Si and cobalt Co to generate CoSi easier, i.e., the temperature required for the formation of CoSi is lower, the crystal phase transition temperature of the formed CoSi is lower, and the process of pre-amorphization implantation of the ions such as Ge and C in the pMOS region is also omitted. Therefore, the crystal phase transition temperature in the process of conversion of CoSi in the nMOS region from a high-resistance phase to a low-resistance phase can be reduced without sacrificing the thermal stability of CoSi in the pMOS region, and Co clusters are not easily generated. The demand gap for the formation of CoSi and the heat treatment temperature in the phase of conversion of CoSi from a high-resistance phase to a low-resistance phase in the nMOS region and the pMOS region is compatible, the problems of CoSi consistency and morphology difference and CoSi resistance in the prior art caused by the demand gap are avoided, and the device resistance can be improved under the same heat treatment temperature. In addition, the annealing activation process after source-drain ion implantation is performed after the formation of cobalt silicide. Not only can the cobalt silicide be annealed again to improve the effect of conversion of cobalt silicide from a high-resistance phase to a low-resistance phase, but also the problem of deterioration of device performance caused by the re-diffusion of the activated source-drain ion due to the heat treatment process of the formation of cobalt silicide can be avoided compared with the scheme in which the source-drain ion heat annealing is performed to complete activation before the formation of metal silicide in the prior art.

[0083] The above description is only a description of the preferred embodiments of the present application, and is not any limitation on the scope of the present application. Any modification or change made by those skilled in the art according to the above disclosure is within the protection scope of the technical scheme of the present application.

Claims

1. A method of manufacturing a semiconductor device, characterized by, The application comprises: providing a substrate with nMOS region and pMOS region, and forming gate on the nMOS region and the pMOS region; masking the pMOS region and performing n-type ion implantation, and n-type ions with atomic weight greater than Ge are included in the n-type ions to form n-type source-drain implantation region in the substrate on both sides of the gate of the nMOS region in amorphous silicon state, and masking the nMOS region and performing p-type ion implantation to form p-type source-drain implantation region in the substrate on both sides of the gate of the pMOS region; forming silicide barrier layer on the substrate of the nMOS region and the pMOS region, the silicide barrier layer exposes at least part of the surface of the n-type source-drain implantation region, at least part of the surface of the p-type source-drain implantation region and at least part of the surface of each of the gate top; depositing metal cobalt and performing two different rapid thermal processes in sequence to form cobalt silicide on the exposed surface of the n-type source-drain implantation region, the p-type source-drain implantation region and each of the gate, and to convert the high resistance phase of the cobalt silicide into the low resistance phase; conformally depositing contact hole etching stop layer on the cobalt silicide; respectively using spike thermal annealing process and laser spike annealing process for heat treatment to activate the n-type ions in the n-type source-drain implantation region and the p-type ions in the p-type source-drain implantation region.

2. The production method according to claim 1, wherein The n-type ions with atomic weight greater than Ge include at least one of As and Sb.

3. The production method according to claim 1, wherein The n-type ion with atomic weight greater than Ge is implanted at an energy of 12 keV to 16 keV and a doping concentration of 2e+15 cm -2 to 3e+15 cm -2 .

4. The production method according to claim 1, wherein The temperature range of the spike thermal annealing process is 1040-1060℃, and the temperature range of the laser spike annealing process is 1100-1200℃.

5. The production method according to claim 1, wherein The thickness of the contact hole etching stop layer is 6. The production method according to claim 1, wherein It also comprises forming at least one contact plug and at least one metal interconnection line through metal connection process, wherein each of the contact plugs penetrates the contact hole etching stop layer from top to bottom, and the bottom is in electrical contact with the cobalt silicide of the corresponding region, and the top is in electrical contact with the corresponding metal interconnection line; The temperature of the metal connection process is higher than 650℃.

7. The production method according to claim 1, wherein When performing n-type ion implantation, at least one of Ge, C, F, N is implanted into the substrate on both sides of the gate of the nMOS region as impurity ions together with the n-type ions with atomic weight greater than Ge.

8. The production method according to claim 1, wherein The p-type ions include at least one of B, BF2, Ga, In.

9. The production method according to claim 8, wherein When performing p-type ion implantation, at least one of Ge, C, F, N, P is implanted into the substrate on both sides of the gate of the pMOS region as impurity ions together with the p-type ions.

10. The production method according to any one of claims 1 to 9, wherein After forming gate on the nMOS region and the pMOS region and before performing n-type ion implantation and performing p-type ion implantation, it also comprises forming sidewall on the sidewall of each of the gates; or, after converting the high resistance phase of the cobalt silicide into the low resistance phase and before conformally depositing contact hole etching stop layer on the cobalt silicide, it also comprises removing unreacted metal and further removing the silicide barrier layer.

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