Method for manufacturing semiconductor device, and semiconductor device

Abstract

The embodiment of the invention relates to a semiconductor device manufacturing method and a semiconductor device. In a method of manufacturing a semiconductor device according to one embodiment, a semiconductor portion having a transistor region and a diode region is formed, and a first lifetime control region is formed in a lower portion of the semiconductor portion in the diode region by ions irradiated from above the semiconductor portion. A second lifetime control region is formed at the upper part of the semiconductor part at the same time as the first lifetime control region by ions irradiated through the mask from above the semiconductor part so as not to overlap the first lifetime control region.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2023 — 158959 (filing date: September 22, 2023). This application incorporates the entire contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0004] As one of semiconductor devices, RC (Reverse Conductive) - IGBT (Insulated Gate Bipolar Transistor) is known. In an RC-IGBT, a transistor region where an IGBT is provided and a diode region where an FWD (Free Wheeling Diode) connected in anti-parallel with the IGBT is provided are formed on the same substrate. That is, the IGBT and the FWD are formed on one semiconductor chip.

[0005] The above-described semiconductor device has the following technical problems: due to the tail current (Japanese: テール電流) caused by the accumulated carriers in the diode region during the recovery operation of the FWD, and the parasitic diode operation that causes hole injection from the transistor region to the diode region during the conduction operation of the FWD, the recovery loss deteriorates.

[0006] Therefore, in order to solve the above technical problems, a technique is known in which lattice defects are generated by ions irradiated to the transistor region and the diode region to provide a lifetime control region.

[0007] In order to reduce the tail current, it is effective to form a lifetime control region below the diode region. On the other hand, in order to suppress the parasitic diode operation, it is effective to form a lifetime control region above the boundary portion between the transistor region and the diode region. Thus, when a plurality of lifetime control regions are locally formed at different positions, multiple ion irradiations are required. Therefore, the formation of the lifetime control region takes a long time. Summary of the Invention

[0008] In one embodiment of a method for manufacturing a semiconductor device, a semiconductor portion having a transistor region and a diode region is formed, a first lifetime control region is formed in a lower portion of the semiconductor portion in the diode region by irradiating ions from above the semiconductor portion, and a second lifetime control region is formed simultaneously with the first lifetime control region in an upper portion of the semiconductor portion by irradiating ions through a mask from above the semiconductor portion in a manner that does not overlap with the first lifetime control region.

[0009] According to the present embodiment, it is possible to provide a method for manufacturing a semiconductor device and a semiconductor device capable of shortening the time required for forming a lifetime controlled region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a cross-sectional view of the semiconductor device according to the first embodiment cut along the vertical direction.

[0011] Figure 2 It is a diagram showing the process flow before and after the lifetime control region forming process of the semiconductor device according to the first embodiment.

[0012] Figure 3 This is a cross-sectional view for explaining the process of forming the surface element structure.

[0013] Figure 4 It is a cross-sectional view for explaining the resist pattern forming process.

[0014] Figure 5 This is a cross-sectional view for explaining the metal mask mounting process.

[0015] Figure 6 This is a cross-sectional view for explaining the ion irradiation process.

[0016] Figure 7 This is a cross-sectional view for explaining the back grinding process.

[0017] Figure 8 This is a cross-sectional view for explaining a back diffusion layer forming step.

[0018] Fig. 9 This is a cross-sectional view for explaining the first electrode process.

[0019] Fig.10 It is a cross-sectional view of a semiconductor device of a comparative example cut along a vertical direction.

[0020] Fig.11 It is a cross-sectional view for explaining the first metal mask mounting step and the first ion irradiation step.

[0021] Fig.12It is a cross-sectional view for explaining the second metal mask mounting step and the second ion irradiation step.

[0022] Fig.13 This is a cross-sectional view of the semiconductor device according to the second embodiment cut along the vertical direction. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention.

[0024] (First Embodiment)

[0025] Figure 1 It is a cross-sectional view of the semiconductor device of the first embodiment cut along the vertical direction. In the following description, the X-axis, Y-axis and Z-axis shown in each figure are sometimes used to describe the configuration and structure of each part of the semiconductor device. The X-axis, Y-axis and Z-axis are orthogonal to each other, and represent the X direction, Y direction and Z direction respectively. In addition, sometimes the Z direction is regarded as the upper direction and the opposite direction is regarded as the lower direction for description. In this embodiment, the X direction and the Y direction are respectively equivalent to the second direction and the third direction, indicating the in-plane direction parallel to the surface (or back side) of the semiconductor device 1. The Z direction is equivalent to the first direction, indicating the out-of-plane direction orthogonal to the surface (or back side) of the semiconductor device 1.

[0026] In addition, p, p + The expression refers to the p-type impurity concentration in terms of p, p + The order of is increasing. Then, n - 、n、n + The expression refers to the n-type impurity concentration in terms of n - 、n、n + The order is ascending.

[0027] The impurity concentration can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry). In addition, the relative level of the impurity concentration can also be determined, for example, based on the level of the carrier concentration obtained by SCM (Scanning Capacitance Microscopy). In addition, the depth and distance of the semiconductor region can be obtained, for example, by SIMS.

[0028] Figure 1The semiconductor device 1 shown is an RC-IGBT. The semiconductor device 1 includes a first electrode 10, a second electrode 20, and a semiconductor portion 30. In addition, the semiconductor portion 30 has a transistor region 30a in which a transistor element such as an IGBT is provided and a diode region 30b in which a diode element such as a FWD is provided. The transistor region 30a and the diode region 30b are alternately arranged along the x direction. In addition, a separation region in which no transistor element and diode element are provided may be provided between the transistor region 30a and the diode region 30b.

[0029] The first electrode 10 is provided on the back surface of the semiconductor portion 30. The first electrode 10 can be formed using, for example, a metal such as aluminum. The first electrode 10 functions as a collector electrode in the transistor region 30a and functions as a cathode electrode in the diode region 30b.

[0030] The second electrode 20 faces the first electrode in the Z direction via the semiconductor portion 30. The second electrode 20 can be formed using a metal such as aluminum, for example. The second electrode 20 functions as an emitter electrode in the transistor region 30a and as an anode electrode in the diode region 30b.

[0031] The semiconductor portion 30 has p + Collector region 31, n + Cathode region 32, n buffer region 33, n - Base region 34, p base region 35, p anode region 36, n + The emitter region 37, the gate electrode 38 and the gate insulating film 39. + The collector region 31 corresponds to a p-type third semiconductor region. + The cathode region 32 corresponds to the n-type fourth semiconductor region. The n-buffer region 33 corresponds to the n-type second semiconductor region. - The base region 34 corresponds to the n-type first semiconductor region.

[0032] p + The collector region 31 is provided on the first electrode 10 in the transistor region 30a. + The cathode region 32 is provided on the first electrode 10 in the diode region 30b. + The thickness of the cathode region 32 is related to p + The thickness of the collector region 31 is substantially the same. + The cathode region 32 and p + The collector regions 31 are formed in layers having the same depth from the surface of the semiconductor portion 30. + The thickness of the cathode region 32 need not be equal to + The thickness of the collector region 31 may be the same or different.

[0033] n buffer area 33 is provided at p + The collector region 31 and n + The cathode region 32 is provided with an n buffer region 33. - Base region 34 .

[0034] In n - The base region 34 is provided with a first lifetime controlled region 41 and a second lifetime controlled region 42. Lattice defects functioning as life time killers are formed in the first lifetime controlled region 41 and the second lifetime controlled region 42, respectively.

[0035] The first lifetime control region 41 is set at n - The lower part of the base region 34, in other words, is provided at the boundary portion with the n buffer region 33. On the other hand, the second lifetime control region 42 is provided at the n - The upper part of the base region 34 is the boundary between the transistor region 30a and the diode region 30b.

[0036] The first lifetime control region 41 and the second lifetime control region 42 are formed by irradiating hydrogen ions, helium ions, etc. At this time, in order to simultaneously form the first lifetime control region 41 and the second lifetime control region 42, the two lifetime control regions are formed so as not to overlap in the Z direction. In other words, the first lifetime control region 41 and the second lifetime control region 42 are formed so as to be offset from each other in the X direction.

[0037] In the n located in the transistor region 30a - A p base region 35 is provided on the base region 34. - A p-type anode region 36 is provided on the base region 34. In the present embodiment, the p-type impurity concentration contained in the p-base region 35 is the same as the p-type impurity concentration contained in the p-anode region 36. However, the p-type impurity concentration does not need to be the same between the p-base region 35 and the p-anode region 36, and may be different. The p-base region 35 and the p-anode region 36 having different p-type impurity concentrations can be formed by, for example, separate ion implantation.

[0038] In addition, in the present embodiment, the thickness of the p base region 35 is greater than the thickness of the p anode region 36. In other words, the p base region 35 is formed to a position deeper from the surface of the semiconductor portion 30 than the p anode region 36. However, the thickness of the p base region 35 does not need to be greater than the thickness of the p anode region 36, and may be the same as or smaller than the thickness of the p anode region 36.

[0039] n +The emitter region 37 is in contact with the p base region 35. + The emitter region 37 is in contact with the second electrode 20. When the voltage between the gate electrode 38 and the second electrode 20 (emitter electrode) becomes equal to or higher than the threshold voltage, an n-channel is formed in the p-base region 35. Thus, a voltage from p to n is generated in the transistor region 30a. + The collector region 31 is connected to the n + Current path in emitter region 37 .

[0040] The gate electrode 38 is connected to the p base region 35 and the n + The emitter regions 37 are opposed to each other. The gate electrode 38 can be formed using, for example, polysilicon. In addition, the gate insulating film 39 is, for example, a silicon oxide film (SiO2).

[0041] In addition, in this embodiment, the gate electrode 38 and the gate insulating film 39 are provided not only in the transistor region 30a but also in the diode region 30b. However, it is also possible not to provide the gate electrode 38 and the gate insulating film 39 in the diode region 30b. + The emitter region 37. Therefore, the gate electrode 38 provided in the diode region 30b is a dummy gate electrode.

[0042] In the semiconductor device 1, when the tail current caused by the accumulated carriers in the diode region 30b is large during the recovery operation of the FWD, the recovery loss of the FWD becomes large. - A first lifetime control region 41 is formed at the lower portion of the base region 34. Lattice defects, which are lifetime suppressing factors, are formed in the first lifetime control region 41, so that tail current can be reduced. Thus, recovery loss can be reduced.

[0043] In the semiconductor device 1, when the FWD is turned on, the p base region 35 of the transistor region 30a and the n base region 35 of the diode region 30b are connected. + When the cathode region 32 operates as a parasitic diode, holes are injected from the transistor region 30a to the diode region 30b. As a result, the recovery loss of the FWD may be deteriorated. Therefore, in this embodiment, the n -A second lifetime control region 42 is formed on the upper portion of the base region 34. Lattice defects that serve as lifetime suppressing factors are also formed in the second lifetime control region 42, so that the operation of the parasitic diode can be suppressed. Thus, the recovery loss can be reduced. In addition, when the second lifetime control region 42 is formed on the surface of the transistor region 30a, the conduction characteristics of the IGBT may deteriorate. Furthermore, when the second lifetime control region 42 is formed, the gate threshold voltage (Vth) may vary due to damage to the gate insulating film 39. Therefore, in the present embodiment, the formation area of ​​the second lifetime control region 42 is limited to the surface of the boundary between the transistor region 30a and the diode region 30b. Thus, the parasitic diode operation can be suppressed while suppressing the disadvantages of deteriorating the conduction characteristics of the IGBT and varying the gate threshold voltage (Vth).

[0044] Here, refer to Figure 2 to Figure 9 A method for manufacturing the semiconductor device 1 of the present embodiment will be described. Here, the lifetime controlled region forming step of forming the first lifetime controlled region 41 and the second lifetime controlled region 42 and the manufacturing steps before and after the lifetime controlled region forming step will be mainly described.

[0045] Figure 2 1 is a diagram showing the process flow before and after the lifetime control region forming process of the semiconductor device 1 of the present embodiment. Figure 2 As shown, there is a surface element structure forming step (step S1) before the lifetime control region forming step (step S2). In addition, there is a back element structure forming step (step S3) after the lifetime control region forming step. Furthermore, there is a cutting step (step S4) after the back element structure forming step (step S3).

[0046] Figure 3 FIG. 1 is a cross-sectional view for explaining the surface element structure forming process. In the surface element structure forming process, first, n is formed on the semiconductor wafer 11. - Base region 34 .

[0047] Next, in the transistor region 30a, at n - The p base region 35, n base region 36 and n base region 37 are sequentially formed on the base region 34. + The emitter region 37, the gate electrode 38 and the gate insulating film 39. On the other hand, in the diode region 30b, - A p-type anode region 36, a gate electrode 38, and a gate insulating film 39 are sequentially formed on the base region 34. However, the gate electrode 38 formed in the diode region 30b is a dummy gate electrode.

[0048] Finally, the second electrode 20 is formed. The p base region 35 to the gate insulating film 39 and the second electrode 20 can be formed by a generally used manufacturing method, and therefore detailed descriptions thereof are omitted.

[0049] Next, the lifetime control region forming step will be described. The lifetime control region forming step is composed of a resist pattern forming step, a metal mask mounting step, and an ion irradiation step.

[0050] Figure 4 2 is a cross-sectional view for explaining the resist pattern forming process. In the resist pattern forming process, first, the resist 40 is applied to the entire upper surface of the second electrode 20. Next, the resist 40 applied to the region opposite to the boundary between the transistor region 30a and the diode region 30b and the resist 40 applied to the region opposite to the diode region 30b on the upper surface of the second electrode 20 are removed by exposure and development. As a result, Figure 4 As shown, the pattern of the resist 40 is formed so that a region facing the boundary portion between the transistor region 30 a and the diode region 30 b and a region facing the diode region 30 b are exposed.

[0051] Figure 5 2 is a cross-sectional view for explaining a metal mask mounting process. In the metal mask mounting process, a metal mask 50 is disposed above the resist 40. The metal mask 50 is made of, for example, aluminum or nickel.

[0052] The metal mask 50 shields the formation position of the second lifetime control region 42, and is patterned to expose the formation position of the first lifetime control region 41. In addition, the thickness of the metal mask 50 is designed to be a value that allows the ions irradiated in the subsequent ion irradiation step to stay at the formation position of the second lifetime control region 42.

[0053] Figure 6 2 is a cross-sectional view for explaining the ion irradiation process. In the ion irradiation process, the metal mask 50 is irradiated from the top to the n direction. - The base region 34 is irradiated with ions containing hydrogen or helium. - In the exposed portion shielded by the metal mask 50, the irradiated ions reach n - A position of a predetermined depth in the base region 34. As a result, a first lifetime controlled region 41 is formed.

[0054] In addition, the irradiated ions reach the n-base region 34 in the portion that is shielded only by the metal mask 50, that is, the boundary between the transistor region 30a and the diode region 30b. -As a result, the second lifetime controlled region 42 is formed simultaneously with the first lifetime controlled region 41 .

[0055] In addition, in n - In the base region 34, the irradiated ions do not reach the region shielded by both the resist 40 and the metal mask 50. After the ion irradiation step, the resist 40 is peeled off. Thus, the lifetime control region forming step is completed.

[0056] Next, the back surface element structure forming step is described. The back surface element structure forming step includes a back surface grinding step, a back surface diffusion layer forming step, and a first electrode step.

[0057] Figure 7 This is a cross-sectional view for explaining the back grinding process. In the back grinding process, the back side of the n - The base region 34 is polished. As a result, the first lifetime control region 41 is located at n - The lower portion of the base region 34 .

[0058] Figure 8 FIG. 1 is a cross-sectional view for explaining the back diffusion layer forming step. - The n-type buffer region 33 is formed under the base region 34. Next, in the transistor region 30a, the p-type buffer region 33 is formed under the n-type buffer region 33. + On the other hand, in the diode region 30b, an n buffer region 33 is formed below the n buffer region 33. + Cathode region 32. p + Collector region 31, n + The cathode region 32 and the n buffer region 33 can be formed by a commonly used manufacturing method, and thus detailed descriptions thereof are omitted.

[0059] Fig. 9 FIG. 1 is a cross-sectional view for explaining the first electrode process. In the first electrode process, the first electrode 10 is formed at p + Under the collector region 31 and n + The cathode region 32 is formed below. Thus, the back element structure forming step is completed.

[0060] In the final cutting process, the blade is used to Fig. 9 The semiconductor wafer 11 shown is cut into a lattice shape. As a result, the semiconductor wafer 11 is divided into a plurality of semiconductor chips.

[0061] Here, a comparative example to be compared with the present embodiment will be described.

[0062] Fig.10FIG. 2 is a cross-sectional view of a semiconductor device of a comparative example cut along a vertical direction. Fig.10 In the present invention, the same components as those of the semiconductor device 1 are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0063] In the semiconductor device 100 of this comparative example, Fig.10 As shown, the first lifetime controlled region 41 and the second lifetime controlled region 42 overlap in the Z direction. Therefore, the first lifetime controlled region 41 and the second lifetime controlled region 42 of the comparative example cannot be formed simultaneously. The lifetime controlled region forming process of the comparative example will be described below.

[0064] The lifetime control region forming step of the comparative example includes a first metal mask mounting step, a first ion irradiation step, a second metal mask mounting step, and a second ion irradiation step.

[0065] Fig.11 It is a cross-sectional view for explaining the first metal mask mounting step and the first ion irradiation step.

[0066] In the first metal mask mounting step, the first metal mask 51 is disposed above the second electrode 20. The first metal mask 51 shields the transistor region 30a, while exposing the diode region 30b. In addition, the thickness of the first metal mask 51 is designed to be a value that prevents the ions irradiated in the subsequent first ion irradiation step from passing through.

[0067] In the first ion irradiation step, the first metal mask 51 is irradiated from the upper direction n. - The base region 34 is irradiated with ions containing hydrogen or helium. - The irradiated ions reach the exposed portion of the base region 34 that is not blocked by the metal mask 50, that is, the diode region 30b. - A position of a predetermined depth in the base region 34. As a result, a first lifetime controlled region 41 of the comparative example is formed.

[0068] Fig.12 It is a cross-sectional view for explaining the second metal mask mounting step and the second ion irradiation step.

[0069] In the second metal mask installation process, the second metal mask 52 is arranged above the second electrode 20. The second metal mask 52 shields the portion other than the boundary portion between the transistor region 30a and the diode region 30b. In addition, the thickness of the second metal mask 52 is designed to be a value that prevents the ions irradiated in the subsequent second ion irradiation process from passing through.

[0070] In the second ion irradiation step, the second metal mask 52 is irradiated from the upper direction n. -The base region 34 is irradiated with ions containing hydrogen or helium. - The exposed portion of the base region 34 not shielded by the second metal mask 52, that is, the upper portion of the boundary between the transistor region 30a and the diode region 30b, is irradiated with ions. As a result, the second lifetime control region 42 of the comparative example is formed.

[0071] In the lifetime control region forming process of this comparative example, two metal masks consisting of the first metal mask 51 and the second metal mask 52 and two ion irradiation processes consisting of the first ion irradiation process and the second ion irradiation process are required. Therefore, it takes a lot of time to form the first lifetime control region 41 and the second lifetime control region 42. As a result, the process cost becomes high.

[0072] In contrast, in this embodiment, a metal mask 50 and a resist 40 are used together, and the metal mask 50 is thinned and the shielding ability is intentionally reduced to allow ions to pass through. Thus, the first lifetime control region 41 and the second lifetime control region 42 can be formed simultaneously by one metal mask 50 and one ion irradiation. Thus, the lifetime control region formation process time can be shortened, and as a result, the process cost can be reduced.

[0073] (Second Embodiment)

[0074] Fig.13 FIG. 2 is a cross-sectional view of the semiconductor device according to the second embodiment cut along the vertical direction. Fig.13 In the present invention, the same components as those of the semiconductor device 1 according to the first embodiment are denoted by the same reference numerals, and duplicate descriptions are omitted.

[0075] exist Fig.13 In the semiconductor portion 30 of the semiconductor device 2 shown in FIG. 1 , a separation region 30c is provided between the transistor region 30a and the diode region 30b. In the separation region 30c, n buffer regions 33 and n - The base region 34 and the p-anode region 36 are sequentially stacked between the first electrode 10 and the second electrode 20 .

[0076] In addition, in the separation region 30c, n - The base region 34 and the p-anode region 36 are provided with a gate electrode 38 and a gate insulating film 39. However, the gate electrode 38 is a dummy gate electrode similar to the gate electrode 38 provided in the diode region 30b.

[0077] Furthermore, in the semiconductor device 2 of the present embodiment, the first lifetime controlled region 41 is provided in n of the diode region 30b. -The first lifetime controlled region 41 can reduce the tail current caused by the accumulated carriers in the diode region 30 b during the recovery operation of the FWD.

[0078] On the other hand, the second lifetime control region 42 is provided to separate n in the region 30c. - The upper portion of the base region 34 extends to the boundary portion between the separation region 30c and the transistor region 30a. - The second lifetime controlled region 42 can suppress the operation of the parasitic diode when the FWD is turned on.

[0079] In this embodiment, as in the first embodiment, the first lifetime controlled region 41 and the second lifetime controlled region 42 are arranged to be offset from each other in the X direction, and therefore do not overlap in the Z direction. Therefore, as in the first embodiment, by using the metal mask 50 and the resist 40 together, the first lifetime controlled region 41 and the second lifetime controlled region 42 can be formed simultaneously using one metal mask 50 and primary ion irradiation.

[0080] Therefore, according to the present embodiment, the lifetime control region forming process time can be shortened, and as a result, the process cost can be reduced.

[0081] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions and changes can be made without departing from the scope of the subject matter of the invention. These embodiments and their variations are also included in the invention described in the scope of the claims and their equivalents as well as the contents included in the scope and subject matter of the invention.

[0082] Description of Reference Numerals

[0083] 1: Semiconductor devices

[0084] 10: First electrode

[0085] 20: Second electrode

[0086] 30: Semiconductor Division

[0087] 30a: Transistor area

[0088] 30b: diode area

[0089] 30c: Separation area

[0090] 31: p + Collector region (third semiconductor region)

[0091] 32:n +Cathode region (fourth semiconductor region)

[0092] 33: n buffer region (second semiconductor region)

[0093] 34:n - Base region (first semiconductor region)

[0094] 40: Resist

[0095] 41: First life control area

[0096] 42: Second life control area

[0097] 50: Metal mask.

Claims

1. A method for manufacturing a semiconductor device, wherein: forming a semiconductor portion having a transistor region and a diode region, A first lifetime control region is formed in a lower portion of the semiconductor portion in the diode region by ion irradiation from above the semiconductor portion, A second lifetime controlled region is formed simultaneously with the first lifetime controlled region in an upper portion of the semiconductor portion so as not to overlap with the first lifetime controlled region due to ions irradiated from above the semiconductor portion through a mask.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The second lifetime control region is formed at an upper portion of a boundary portion between the transistor region and the diode region.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: forming a separation region between the transistor region and the diode region, The second lifetime control region is formed at an upper portion of a boundary portion between the transistor region and the separation region.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The first lifetime controlled region and the second lifetime controlled region are formed in a state where a resist that prevents the ions from passing therethrough is disposed between the transistor region and the mask.

5. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The mask is a metal mask including aluminum or nickel.

6. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The ions are hydrogen ions or helium ions.

7. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: The first lifetime controlled region and the second lifetime controlled region are formed in the n-type first semiconductor region of the semiconductor portion.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: After forming the first lifetime control region and the second lifetime control region, forming an n-type second semiconductor region under the first semiconductor region, forming a p-type third semiconductor region below the second semiconductor region in the transistor region, forming an n-type fourth semiconductor region below the second semiconductor region in the diode region, A first electrode is formed under the third semiconductor region and under the fourth semiconductor region.

9. The method for manufacturing a semiconductor device according to claim 8, wherein The first lifetime controlled region and the second lifetime controlled region are formed in a state where the second electrode is formed on the semiconductor portion.

10. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: An IGBT is formed in the transistor region, and a FWD is formed in the diode region.

11. A semiconductor device, wherein: have: a first electrode; a second electrode, opposite to the first electrode in a first direction; A semiconductor portion, disposed between the first electrode and the second electrode, having a transistor region and a diode region; A first lifetime control region is disposed at a lower portion of the diode region; as well as The second lifetime controlled region is provided on an upper portion of the semiconductor portion so as not to overlap with the first lifetime controlled region in the first direction.

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