Semiconductor device, preparation method of semiconductor device and chip

Abstract

The invention relates to the field of semiconductors, and provides a semiconductor device, a preparation method of the semiconductor device and a chip. The semiconductor device comprises a substrate layer, at least one fin field effect transistor, at least one connection structure and an additional metal layer, the additional metal layer is arranged above a gate structure and is connected with at least part of the at least one connection structure, the height of the upper surface of the additional metal layer is smaller than or equal to that of the upper surface of the connecting structure, and the height of the lower surface of the additional metal layer is larger than or equal to that of the upper surface of the gate structure. According to the semiconductor device, the additional metal layer is introduced by utilizing the height difference between the M0 and the MG in the FinFET process and is used for providing the winding resources, so that the number of the winding resources provided in the standard unit is increased, the height of the standard unit is reduced under the condition that the number of the winding resources required by the standard unit is not changed, and the integration level of a chip is further improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and more specifically, to a semiconductor device, a method for preparing a semiconductor device, and a chip. Background Art

[0002] In the semiconductor field, the integration of chips is mainly affected by the size of standard cells. Among them, the metal spacing and the gate spacing of the field effect transistor (FET) that constitutes the standard cell are two key factors that affect the size of the standard cell in two different directions. The gate spacing limits the number of FETs that can be accommodated per unit size in the width direction of the standard cell. As the progress of the reduction of FET device size gradually slows down along the development of Moore's Law, the reduction of gate spacing has also encountered a bottleneck.

[0003] Metal pitch is the minimum spacing between the winding resources connecting the standard cells without interfering with each other, which limits the number of FETs that can be accommodated per unit size in the height direction of the standard cell. Therefore, if more winding resources can be provided in a unit space while meeting the metal pitch limitation, the height of the standard cell can be reduced. Therefore, how to increase the number of winding resources provided inside the standard cell has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The embodiments of the present application provide a semiconductor device, a method for preparing the semiconductor device, and a chip. By utilizing the height difference between the metal interconnect layer M0 and the metal gate MG in a fin field effect transistor (FinFET) process, an additional metal layer can be introduced between M0 and MG, and a power line M0G is arranged therein, thereby saving winding resources in other metal layers that were originally required to arrange the power lines, and increasing the number of winding resources provided inside the standard unit.

[0005] In a first aspect, a semiconductor device is provided, characterized in that it includes: a substrate layer, at least one fin field effect transistor, at least one connection structure and an additional metal layer; at least one fin field effect transistor includes at least one fin structure and at least one gate structure arranged on the upper surface of the substrate layer; at least one connection structure spans at least part of the fin structure in at least one fin structure and covers at least part of the surface of at least part of the fin structure; the additional metal layer is arranged above the gate structure and connected to at least part of the connection structure in at least one connection structure, the height of the upper surface of the additional metal layer relative to the upper surface of the substrate layer is less than or equal to a first height, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is greater than or equal to a second height, the first height is the height of the upper surface of the at least one connection structure relative to the upper surface of the substrate layer, and the second height is the height of the upper surface of the at least one gate structure relative to the upper surface of the substrate layer.

[0006] Optionally, the additional metal layer comprises a conductive material.

[0007] Optionally, the conductive material includes at least one of the following: copper, cobalt.

[0008] According to the technical solution provided in the present application, by utilizing the height difference between the metal interconnect layer M0 and the metal gate MG in the fin field effect transistor (FinFET) process, an additional metal layer is inserted between the height of M0 and the height of MG to provide winding resources, thereby increasing the number of winding resources provided inside the standard cell, compressing and reducing the height of the standard cell while keeping the number of winding resources required for the standard cell unchanged, thereby improving the integration of the chip.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the semiconductor device also includes: a first metal layer, wherein the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer is greater than a first height; a dielectric layer, used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer; the first metal layer includes at least one winding resource extending in a direction parallel to the upper surface of the substrate layer, and the projection of the at least one winding resource on the upper surface of the substrate layer at least partially overlaps with the projection of at least one connecting structure and / or at least one gate structure on the upper surface of the substrate layer; the dielectric layer includes at least one first contact hole along the second direction, used to connect the at least one winding resource with the at least one connecting structure and / or at least one gate structure.

[0010] According to the above technical solution, the addition of the additional metal layer does not affect the original M1 being connected to M0 or MG through the first contact hole V0, so that all the original winding resources M1 on the first metal layer can be normally provided to the standard unit for use, thereby compressing and reducing the height of the standard unit while keeping the number of winding resources required by the standard unit unchanged, thereby improving the integration of the chip.

[0011] In combination with the first aspect, in certain implementations of the first aspect, at least one power line is arranged in the additional metal layer, at least one power line is electrically connected to at least part of the at least one connection structure, and at least one power line is used to supply power to at least one fin field effect transistor.

[0012] According to the above technical solution, the power line M0G is laid out so that other original metal layers can save the winding resources originally needed to lay out the power line, thereby increasing the number of winding resources provided inside the standard unit.

[0013] In combination with the first aspect, in some implementations of the first aspect, at least one power line extends in a direction parallel to the upper surface of the substrate layer and passes through the semiconductor device in the extending direction.

[0014] According to the above technical solution, the arrangement of MOG in the additional metal layer can facilitate the access of each standard unit, thereby saving space inside the standard unit.

[0015] In combination with the first aspect, in certain implementations of the first aspect, the extension direction of at least one power line is the same as the extension direction of at least one winding resource, and the projection of at least one winding resource on the upper surface of the substrate layer and the projection of at least one power line on the upper surface of the substrate layer at least partially overlap; the dielectric layer also includes at least one second contact hole along the second direction, which is used to connect at least one winding resource with at least one power line.

[0016] According to the above technical solution, by making the projections of M0G and M1 overlap in the vertical direction, M0G can also be connected to M1 through the contact hole V0, so that the idle part of the winding resources on the first metal layer can be provided to the power line, thereby reducing the overall equivalent resistance of the power line and further reducing the power consumption of the chip.

[0017] In combination with the first aspect, in certain implementations of the first aspect, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to the second height; at least one gate structure includes at least one first gate structure and at least one second gate structure; at least one first gate structure is not in contact with the first power line; and the upper surface of at least one second gate structure is at least partially in contact with at least one power line.

[0018] According to the above technical solution, by making the lower surface height of M0G level with MG, the height of MG can contact M0G, so that whether the gate structure is connected to the power supply can be controlled by the size and position of the gate structure, and then whether the gate fails can be controlled, thereby achieving single diffusion break (SDB) without introducing additional processes or sacrificing the available area of ​​​​the standard unit.

[0019] In a second aspect, a method for preparing a semiconductor device is provided, comprising: forming a substrate layer; forming at least one fin field effect transistor on the upper surface of the substrate layer, the at least one fin field effect transistor comprising at least one fin structure and at least one gate structure arranged on the upper surface of the substrate layer; forming at least one connecting structure, the at least one connecting structure spanning at least part of the fin structure in the at least one fin structure and covering at least part of the surface of at least part of the fin structure; forming an additional metal layer, the additional metal layer being arranged above the gate structure and connected to at least part of the connecting structure in the at least one connecting structure, the height of the upper surface of the additional metal layer relative to the upper surface of the substrate layer being less than or equal to a first height, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer being greater than or equal to a second height, the first height being the height of the upper surface of the at least one connecting structure relative to the upper surface of the substrate layer, and the second height being the height of the upper surface of the at least one gate structure relative to the upper surface of the substrate layer.

[0020] In combination with the second aspect, in certain implementations of the second aspect, the preparation method also includes: forming a dielectric layer and a first metal layer, the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer is greater than a first height, and the dielectric layer is used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer; wherein the first metal layer includes at least one winding resource extending in a direction parallel to the upper surface of the substrate layer, and the projection of at least one winding resource on the upper surface of the substrate layer at least partially overlaps with the projection of at least one connecting structure and / or at least one gate structure on the upper surface of the substrate layer; the dielectric layer includes at least one first contact hole along the second direction, which is used to connect at least one winding resource with at least one connecting structure and / or at least one gate structure.

[0021] In combination with the second aspect, in certain implementations of the second aspect, at least one power line is arranged in the additional metal layer, at least one power line is electrically connected to at least part of the at least one connection structure, and at least one power line is used to supply power to at least one fin field effect transistor.

[0022] In combination with the second aspect, in some implementations of the second aspect, at least one power line extends in a direction parallel to the upper surface of the substrate layer and passes through the semiconductor device in the extending direction.

[0023] In combination with the second aspect, in certain implementations of the second aspect, the extension direction of at least one power line is the same as the extension direction of at least one winding resource, and the projection of at least one winding resource on the upper surface of the substrate layer and the projection of at least one power line on the upper surface of the substrate layer at least partially overlap; the dielectric layer also includes at least one second contact hole along the second direction, which is used to connect at least one winding resource with at least one power line.

[0024] In combination with the second aspect, in certain implementations of the second aspect, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to the second height; at least one gate structure includes at least one first gate structure and at least one second gate structure; at least one first gate structure is not electrically connected to at least one first power line; and the upper surface of at least one second gate structure is at least partially electrically connected to at least one power line.

[0025] In a third aspect, a chip is provided, comprising a semiconductor device as in the first aspect or any possible implementation of the first aspect.

[0026] In a fourth aspect, an electronic device is provided, comprising the chip in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a schematic structural diagram of a semiconductor device 100 composed of a single FinFET.

[0028] Figure 2 FIG. 2 is a top view of a semiconductor device 200 composed of a plurality of FinFETs.

[0029] Figure 3 is a cross-sectional view of a semiconductor device 300 composed of a plurality of FinFETs.

[0030] Figure 4 is a top view of the first metal layer.

[0031] Figure 5 It is a schematic structural diagram of a semiconductor device 500 provided in an embodiment of the present application.

[0032] Figure 6 It is a perspective view from above of a semiconductor device 500 provided in an embodiment of the present application.

[0033] Figure 7 It is a perspective view from a top view of a semiconductor device 700 provided in an embodiment of the present application.

[0034] Figure 8 It is a schematic diagram of the principle of the second gate structure cutting off the diffusion region in the embodiment of the present application.

[0035] Fig. 9It is a perspective view from a top view of a semiconductor device 900 provided in an embodiment of the present application.

[0036] Fig.10 It is a schematic flowchart of a method for preparing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0038] The present application will present various aspects, embodiments or features around a system including multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all devices, components, modules, etc. discussed in conjunction with the figures. In addition, combinations of these schemes may also be used.

[0039] In addition, in the embodiments of the present application, words such as "exemplary" and "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" in the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0040] In the embodiments of the present application, "corresponding (corresponding, relevant)" and "corresponding (corresponding)" can sometimes be used interchangeably. It should be pointed out that when the distinction between them is not emphasized, the meanings they intend to express are consistent.

[0041] The network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are equally applicable to similar technical problems.

[0042] References to "one embodiment" or "some embodiments" etc. described in this specification mean that a particular feature, structure or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, the phrases "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0043] In the present application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: including the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0044] The technical solution in the embodiment of the present application can be applied to a semiconductor device including a fin field-effect transistor (FinFET). The semiconductor device in the embodiment of the present application can include at least one FET, and the embodiment of the present application does not limit the type, position relationship or connection relationship of the at least one FET.

[0045] Figure 1 is a schematic diagram of the structure of a semiconductor device 100 composed of a single FinFET. Figure 1 As shown, the FinFET is arranged on the upper surface of the substrate layer 110. In the embodiment of the present application, the type or composition of the substrate layer is not specifically limited. For example, the substrate layer 110 may be a silicon substrate, or the substrate layer 110 may be made of single crystal silicon, gallium arsenide, gallium nitride, silicon carbide, silicon germanium or other semiconductor materials.

[0046] Specifically, the FinFET is composed of a fin structure 120 and a gate structure 130. The fin structure 120 is a protruding structure grown from the upper surface of the substrate layer 110. The fin structure 120 extends in a direction parallel to the upper surface of the substrate layer 110 and is connected to the upper surface of the substrate layer 110. The gate structure 130 spans the fin structure 120 and covers at least a portion of the surface of the fin structure. In other words, the fin structure 120 passes through the gate structure 130 in its extension direction. The gate structure 130 extends in another direction parallel to the upper surface of the substrate layer 110. Optionally, the fin structure 120 and the gate structure 130 are perpendicular to the extension direction of the upper surface of the substrate layer 110, for example, Figure 1 The fin structure 120 extends along the Y direction, and the gate structure 130 extends along the X direction, wherein the X direction and the Y direction are perpendicular to each other and parallel to the upper surface of the substrate layer 110 , and the Z direction is perpendicular to the upper surface of the substrate layer 110 .

[0047] In the FinFET, the gate structure 130 constitutes a gate, and the fin structure 120 can respectively constitute a source and a drain in the extending direction with the gate structure 130 as a dividing line. Figure 1 The position of the fin structure 120 located on the first side of the gate structure along the Y direction close to the screen can be the source of the FinFET, and the position of the fin structure 120 located on the second side of the gate structure along the Y direction away from the screen can be the drain of the FinFET. Alternatively, the position of the fin structure 120 located on the first side of the gate structure along the Y direction close to the screen can be the drain of the FinFET, and the position of the fin structure 120 located on the second side of the gate structure along the Y direction away from the screen can be the source of the FinFET.

[0048] Optionally, the upper surface of the substrate layer 110 may also be covered with an oxide layer 140. The lower surface of the oxide layer 140 contacts the upper surface of the substrate layer 110, and the upper surface of the oxide layer 140 contacts the lower surface of the gate structure. In the embodiment of the present application, the type or composition of the insulating layer is not specifically limited. For example, the oxide layer 140 may be silicon dioxide, or the oxide layer 140 may also be made of other metal oxides.

[0049] A standard cell is a semiconductor device that implements the smallest function in a chip, including but not limited to inverter gates, AND gates, registers, selectors, and other basic units. Each standard cell includes at least one FinFET, where multiple FinFETs can be connected along the Figure 1 Arranged in the X direction and / or Y direction.

[0050] For example, a plurality of gate structures 130 of wide fin structures 120 may be included in the Y direction where the fin structure 120 extends, thereby forming a plurality of FinFETs arranged in parallel along the Y direction. In a standard cell, the Y direction is generally referred to as the length direction of the standard cell, and the size of the standard cell along the Y direction is generally referred to as the length of the standard cell.

[0051] For another example, a plurality of parallel fin structures 120 may be arranged in the X direction, and the gate structure 130 simultaneously crosses the plurality of fin structures 120, thereby forming a plurality of FinFETs arranged in parallel along the X direction. In a standard cell, the X direction is generally referred to as the height direction of the standard cell, and the size of the standard cell along the Y direction is generally referred to as the height of the standard cell.

[0052] In order for the standard cell to work properly, it is necessary to connect the source, drain and / or gate of a specific FinFET to a power source or other standard cells through wires according to the circuit design diagram. However, with the development of the FinFET manufacturing process, the width of the fin structure 120 in the X direction gradually decreases, which is not conducive to direct connection with the wire. Therefore, in the existing FinFET advanced manufacturing process, the semiconductor device also includes a connection structure. The connection structure spans at least one of the fin structures of the semiconductor device and covers at least a portion of the surface of the fin structure spanned.

[0053] Figure 2 A top view of a semiconductor device 200 composed of a plurality of FinFETs is shown. Figure 2 The X and Y directions shown in Figure 1 Corresponding in.

[0054] like Figure 2 As shown, the gate structure 130 extends along the X direction across six fin structures 120. The six fin structures extend in parallel along the Y direction, with each three fin structures being grouped together. For example, one group of fin structures 120 may be the fins of an N-type FinFET, and another group of fin structures 120 may be the fins of a P-type FinFET. Each connecting structure 150 diffracts along the X direction, spanning a source portion or a drain portion of a group of three fin structures 120. The height of the upper surfaces of the gate structure 130 and the connecting structure 150 relative to the upper surface of the substrate layer 110 in the Z direction perpendicular to the X and Y directions is higher than the height of the upper surfaces of the fin structures 120 relative to the upper surface of the substrate layer 110 in the Z direction. Therefore, Figure 2 In the top view, the gate structure 130 and the connection structure 150 both cover at least a portion of the upper surface of the fin structure 120 .

[0055] In the conventional scheme, the wires are distributed in a metal layer located at a higher position than the gate structure and the connection structure in the Z direction. Wires extending in the X direction or in the Y direction can be arranged in the metal layer. An insulating dielectric layer is filled between metal layers at different heights in the Z direction, and the wires of different layers can be connected through through holes penetrating in the Z direction in the dielectric layer at overlapping positions projected in the Z-axis direction. The through holes are filled with conductive materials so that the circuits between different metal layers can be connected. According to the height of the metal layer in the Z direction, they can be named the first metal layer, the second metal layer, the third metal layer, etc. in sequence, and the positions where the wires can be arranged are referred to as M1, M2 and M3. The through hole connecting M1 and M2 can be named the first through hole V1, the through hole connecting M2 and M3 can be named the second through hole V2, and so on.

[0056] The first metal layer is the metal layer closest to the standard cell in the Z direction. The height of the lower surface of the first metal layer relative to the upper surface of the substrate layer 110 in the Z direction is greater than the height of the upper surface of the gate structure 130 and the connection structure 150 relative to the upper surface of the substrate layer 110 in the Z direction. Therefore, the gap between the lower surface of the first metal layer and the upper surface of the substrate layer 110 is also filled with a dielectric layer. The dielectric layer includes a first contact hole that penetrates along the Z direction, which is used to connect the gate structure 130 and / or the connection structure 150 to M1 of the first metal layer at the overlapping position projected along the Z axis direction.

[0057] Figure 3 A cross-sectional view of a semiconductor device 300 is shown. Figure 3 It is a cross-sectional view after the fin structure 120 of the semiconductor device 300 is cut along a plane formed by the Y direction and the Z direction, wherein the Y direction and the Z direction correspond to the coordinate system mentioned above.

[0058] The connection structure 150 may be made of a conductive material, such as a metal material. Therefore, the position in the Z direction occupied by the conductive material constituting the connection structure 150, starting from the height of the upper surface of the fin structure 120 in the Z direction to the height of the upper surface of the connection structure 150 in the Z direction, is also called the metal interconnection layer M0. Figure 3 M0 shown in .

[0059] The portion of the gate structure 130 that contacts the fin structure 120 may be made of a high-k dielectric material (HK), such as hafnium dioxide; the rest of the portion including the upper surface may be made of a conductive material, such as a metal material. Therefore, the position of the conductive material constituting the gate structure 130 in the Z direction, starting from the height of the upper surface of the fin structure 120 in the Z direction to the height of the upper surface of the gate structure 130 in the Z direction, is also called a metal gate (MG). Figure 3 MG shown in .

[0060] like Figure 3 As shown, in the current advanced process for preparing FinFET, the height of M0 in the Z direction is higher than MG. That is, the height of the upper surface of the connection structure 150 relative to the upper surface of the substrate layer 110 in the Z direction is greater than the height of the upper surface of the gate structure 130 relative to the upper surface of the substrate layer 110 in the Z direction. For simplicity, in the following embodiments, the height of the upper surface of the connection structure 150 relative to the upper surface of the substrate layer 110 in the Z direction is collectively referred to as the first height h1, and the height of the upper surface of the gate structure 130 relative to the upper surface of the substrate layer 110 in the Z direction is collectively referred to as the second height h2, wherein the first height is greater than the second height.

[0061] like Figure 3 As shown, M1 is located above the FinFET in the standard cell in the Z direction, that is, the height of the lower surface of M1 is greater than the first height. M0 and MG can be connected to M1 through a first contact hole (V0 or V0G), wherein the contact hole for connecting M1 to M0 is called V0, and the contact hole for connecting M1 to MG is called V0G.

[0062] Metal pitch is the minimum distance between wires that can work normally without interfering with each other. Due to the limitation of metal pitch, the locations where wires can be laid per unit area in each metal layer are limited, and the locations where wires can be laid in a metal layer are called winding resources provided by the metal layer.

[0063] Figure 4 A top view of the first metal layer is shown. Figure 4 As shown, for example, in the first metal layer, at most 4 winding resources M1 can be provided in the unit size along the X direction, each winding resource extends along the Y direction, and the distance between each winding resource is set according to the metal spacing. In this case, if the standard cell needs to lay out a total of 6 wires extending along the Y direction (including a power line and a ground line), a first metal layer with a size greater than 1 unit (for example, 1.5 unit sizes) is required in the X direction, so the minimum height of the standard cell in the height direction (X direction) is limited to not less than 1.5 unit sizes.

[0064] It should be understood that the above example is only based on the use of M1 wiring. In the case of multi-layer metal layer wiring, when the metal spacing and the number of metal layers are fixed, the winding resources that can be provided by the metal layer per unit area are fixed and limited. The number of winding resources limits the further improvement of chip integration, so how to increase the number of winding resources provided inside the standard cell has become a technical problem that needs to be solved urgently.

[0065] The wires connecting the standard cells can be divided into power lines and signal lines according to their functions. Among them, the signal line connects the standard cell and other standard cells and is used to transmit electrical signals between the standard cells; the power line connects the standard cell and the power supply to supply power to the standard cell. Since each standard cell needs to be powered, the traditional solution of laying the power line on the metal layer generally requires an entire winding resource. Therefore, if the power line can be laid in a position other than the winding resources provided by the existing metal layer within the space occupied by the existing semiconductor device, the winding resources of the metal layer can be saved.

[0066] In view of this, an embodiment of the present application provides a semiconductor device, which utilizes the height difference between the metal interconnect layer M0 and the metal gate MG in the existing FinFET production process, introduces an additional metal layer located between M0 and MG in the mid-stage process of semiconductor device preparation, and lays a power line M0G in the additional metal layer, thereby saving winding resources that were originally required to lay the power line in other metal layers, and increasing the number of winding resources provided inside the standard unit.

[0067] Figure 5 A schematic structural diagram of a semiconductor device 500 provided in an embodiment of the present application is shown. The semiconductor device 500 includes a substrate layer 510, a fin structure 520 of at least one FinFET, a gate structure 530 of at least one FinFET, at least one connection structure 540 and an additional metal layer 550. Figure 5 It is a cross-sectional view after the fin structure 520 of the semiconductor device 500 is cut along a plane formed by the Y direction and the Z direction, wherein the Y direction and the Z direction correspond to the coordinate system mentioned above.

[0068] At least one FinFET composed of a fin structure 520 and a gate structure 530 is disposed on the upper surface of the substrate layer 510, and at least one connection structure 540 spans over at least a portion of the fin structure 520 in at least one fin structure 520 and covers at least a portion of the surface of the at least portion of the fin structure 520. Optionally, the substrate layer 510, the fin structure 520, the gate structure 530, and the connection structure 540 correspond to the substrate layer 110, the fin structure 120, the gate structure 130, and the connection structure 150 described above, respectively, and have the same structure and position relationship. For specific structure and position relationship, reference may be made to Figures 1 to 4 As well as the related descriptions in the previous article, I will not repeat them here.

[0069] The height of the upper surface of the additional metal layer 550 relative to the upper surface of the substrate layer 510 is less than or equal to a first height h1, the additional metal layer is disposed above the gate structure and connected to at least part of the at least one connection structure, and the height of the lower surface of the additional metal layer 550 relative to the upper surface of the substrate layer 510 is greater than or equal to a second height h2. The first height is the height of the upper surface of the connection structure 540 relative to the upper surface of the substrate layer 510, and the second height is the height of the upper surface of the gate structure 530 relative to the upper surface of the substrate layer.

[0070] At least one power line M0G extending in a direction parallel to the upper surface of the substrate layer is arranged in the additional metal layer 550. The power line is electrically connected to at least part of the connection structure 540 of at least one connection structure 540 of the standard cell, and is used to power the FinFET in the standard cell. The power line can be divided into a positive power line Vdd and a negative power line Vss. Vdd provides a drain power supply voltage, which is generally connected to the connection structure 540 to which the drain of a P-type metal-oxide semiconductor field effect transistor (MOS) is connected. Vss provides a source power supply voltage, which is generally connected to the connection structure 540 to which the source of an N-type MOS is connected. In the case of a single power supply, Vss provides zero voltage or grounding, so Vss is also called a ground line in some embodiments.

[0071] Optionally, the additional metal layer includes a conductive material, including but not limited to at least one of the following: copper and cobalt.

[0072] Optionally, the semiconductor device 500 further includes at least one metal layer including a first metal layer. The height of the lower surface of M1 in the first metal layer relative to the upper surface of the substrate layer 510 is greater than the first height. M1 is connected to at least part of the connection structure 540 in at least one connection structure 540 through V0 in the dielectric layer, and / or is connected to at least part of the gate structure 530 in at least one gate structure 530 through V0G in the dielectric layer.

[0073] according to Figure 6 It can be seen that M0G and M1 are located in two parallel planes with different heights. In addition, since the height of M0G in the Z direction is lower than the height of M0 in the Z direction, the minimum distance of M0G relative to M1 in the Z direction is greater than the minimum distance of M0 relative to M1 in the Z direction. Therefore, in the case where M0 does not interfere with M1, M0G will not interfere with M1. The position of M0G on the plane formed by the X direction and the Y direction can also ignore the position of M1 on the plane formed by the X direction and the Y direction, so that the projections of M0G and M1 on the plane formed by the X direction and the Y direction can partially overlap or even completely overlap. That is, the addition of M0G does not affect the design of the original metal layer, so that all winding resources M1 can still be normally provided to the standard unit without changing the existing first metal layer structure.

[0074] It should be understood that Figure 5The cross-sectional view shown is only for illustrating the height relationship of MOG relative to M0 and MG in the Z direction, and does not limit the shape and position of the projection of MOG on the plane formed by the X direction and the Y direction. The shape and position of the projection of MOG on the plane formed by the X direction and the Y direction can be adjusted according to the extension direction and position of the power line. A schematic diagram of the power line layout is given below.

[0075] Figure 6 A perspective view of a semiconductor device 500 provided in an embodiment of the present application is shown in a top view. Figure 6 The figure shows the superposition of projections of related elements in multiple planes located at different heights in the Z direction, such as the first metal layer, the additional metal layer, and the standard unit, on the plane formed by the X and Y directions. For the sake of simplicity, elements not related to the description are omitted in the figure.

[0076] like Figure 6 As shown, since there is a height difference between M0G and M1 in the Z direction perpendicular to the X direction and the Y direction, the distance between the projections of M0G and M1 on the plane formed by the X direction and the Y direction can be smaller than the metal spacing limit or even overlap.

[0077] For example, suppose the constraints are Figure 4 The example shown is the same, that is, the first metal layer can accommodate 4 M1s in the unit size along the X direction, and the standard cell still needs to lay out 6 wires extending along the Y direction. Figure 6 As shown on the left, since two power lines among the six wires can use M0G in the additional metal layer, only four M1s provided by the first metal layer of one unit size need to be used as other wires in the X direction, so that the minimum height in the standard unit height direction (X direction) can be reduced to one unit size, which is less than the limit of 1.5 unit sizes in the traditional solution.

[0078] For example, Figure 6 As shown on the right, the size of the standard cell in the height direction (X direction) remains unchanged, and is still 1.5 unit sizes. In this case, the M1 that can be provided in the first metal layer is more than 4, for example, 5 or more, and the two M0Gs provided by the additional metal layer make the winding resources available to the standard cell exceed 6. And there is no additional height in the Z direction compared to the traditional solution, so it is equivalent to providing more winding resources in the unit space of the semiconductor device, so that more FinFETs can be accommodated in the standard cell.

[0079] To summarize, the technical solution provided in the embodiment of the present application utilizes the height difference between the metal interconnect layer M0 and the metal gate MG in the FinFET process of the fin field effect transistor, and inserts an additional metal layer between the height of M0 and the height of MG for laying out the power line M0G, so that other original metal layers can save the winding resources originally required for laying out the power line, thereby increasing the number of winding resources provided inside the standard unit, compressing and reducing the height of the standard unit while keeping the number of winding resources required for the standard unit unchanged, thereby improving the integration of the chip.

[0080] When planning the arrangement of FinFETs in standard cells, in order to save space, multiple gate structures whose extension direction is perpendicular to the extension direction of the fin structure are usually arranged in parallel in the extension direction of the active area composed of a group of parallel fin structures, thereby dividing multiple FinFETs. In order for the multiple FinFETs formed in the above manner to work normally, the active areas of different FinFETs need to be isolated. The technology in which two FinFETs are isolated by a dummy gate structure is called single diffusion break (SDB). Existing methods of implementing SBD generally require the design of a special isolation structure under the dummy gate structure, which requires the addition of additional processes in the semiconductor device preparation process and the sacrifice of part of the standard cell area.

[0081] In view of this, the embodiments of the present application are Figure 5 Based on the semiconductor device shown, the effect of SBD can be achieved without introducing additional processes or sacrificing area.

[0082] In some possible embodiments, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to the second height, and the second height is equal to the height of the upper surface of the gate structure relative to the upper surface of the substrate layer, that is, the lower surface of MOG can contact the upper surface of MG.

[0083] In this case, Figure 7 1 shows a perspective view of a semiconductor device 700 provided in an embodiment of the present application from a top view. Figure 7 Also, only the projection of the part related to the content to be explained on the plane formed by the X direction and the Y direction is shown, and other irrelevant parts are omitted.

[0084] like Figure 7 As shown, OD represents the active region of the FinFET, that is, the region where the source and drain of the FinFET are formed. Figure 7 The two ODs extend along the Y direction, and each OD may include a fin structure extending along the Y direction, or may include a group of mutually parallel fin structures extending along the Y direction. For simplicity, the specific number of fin structures is not shown in the figure.

[0085] M0G represents two power rails extending along the Y direction provided on the additional metal layer. Optionally, the two M0Gs may be composed of a power rail providing Vdd and a ground rail providing Vss. For example, Figure 7 The upper M0G in the middle can be a power rail, and the lower M0G can be a ground rail.

[0086] M0 represents a metal interconnect layer, which crosses the fin structure included in OD, and the upper surface of M0 is higher than the height of the fin structure in OD in the Z direction, that is, M0 covers part of the surface of OD in the top view. M0 extends along the X direction, and at least part of M0 extends to contact with M0G, so as to power the FinFET in the standard cell through M0G.

[0087] MG represents the metal gate portion of the gate structure. The gate structure spans over part of the upper surface of the fin structure, so Figure 7 In the figure, MG is shown to extend along the X direction and cover part of OD. In addition, since the lower surface of MOG and the upper surface of MG are at the same height in the Z direction in this embodiment, Figure 7 The MG that crosses the MOG in the top view can actually contact the MG. Therefore, the gate structure can be divided into a first gate structure and a second gate structure according to whether it contacts the MOG.

[0088] The first gate structure is not electrically connected to the MOG, for example, the two MGs spanning the two ODs in the figure. The upper surface of the second gate structure is electrically connected to the MOG, for example Figure 7 The two MGs are located in the middle of the Y direction. Since the first gate structure is not in contact with the power line, the potential of the gate structure can be controlled by other wires, thereby controlling the switching state of the MOS. Therefore, the source and drain on the left and right sides of the first gate structure constitute a MOS that can work normally. Since the second gate structure is directly connected to the power line, the potential on the second gate structure is equal to the source potential or the drain potential. Therefore, the carrier channel between the source and the drain separated by the second gate structure is always in a closed state, so that no current flows, and the function of separating two adjacent MOSs in the Y direction by a single second gate structure is achieved.

[0089] Figure 8 The principle of the second gate structure cutting off the diffusion region in the embodiment of the present application is shown. Figure 8As shown in the figure, for P-type MOS (PMOS), when the gate is connected to the power rail, the gate always has the same high potential as the drain, which is equivalent to a PMOS that is always in the off state, thereby achieving the cutting off of carrier diffusion. Similarly, for N-type MOS (NMOS), when the gate is connected to the ground rail, the gate always has the same low potential as the source, which is equivalent to an NMOS that is always in the off state, thereby achieving the cutting off of carrier diffusion.

[0090] Through the above solution, the height of MG can contact MOG, so that whether the gate structure is connected to the power supply can be controlled only by the size and position of the gate structure, and then whether the gate fails can be controlled, thereby achieving the SDB effect without introducing additional processes or sacrificing the available area of ​​the standard unit.

[0091] The resistance of the power line is one of the factors that affect the power consumption of the semiconductor device. By reducing the resistance of the power line, the power consumption of the semiconductor device can be reduced.

[0092] In some possible implementations, the projection of M0G of the semiconductor device provided in the embodiment of the present application on the upper surface of the substrate layer may at least partially overlap with the projection of M1 on the upper surface, so that M0G can be connected to M1 through a second contact hole V0 that runs through the dielectric layer from top to bottom, thereby allowing the idle M1 and M0G in the first metal layer that are not used for laying wires to be used together as power lines to reduce the equivalent resistance of the power lines.

[0093] In this case, Fig. 9 A perspective view of a semiconductor device 900 provided in an embodiment of the present application is shown in a top view. Fig. 9 The two sections of M1 drawn in the figure represent the idle parts of M1 used as power lines. The projection of the idle part of M1 on the plane formed by the X direction and the Y direction falls within the projection range of M0G on the plane formed by the X direction and the Y direction, and the shaded rectangle represents the position where M1 is connected to M0G through the second contact hole V0.

[0094] It should be understood that Fig. 9 The M1 shown in the figure is only an idle winding resource used as a power line, and does not represent all the winding resources in the first metal layer. The winding resource M1 in the first metal layer not shown in the figure can still be connected to M0 or MG through the first contact hole for laying signal lines. That is, the idle M1 used as a power line does not affect the normal use of other winding resources.

[0095] exist Fig. 9The position between the two second contact holes is equivalent to M0G and M1 being used together as a power line. The connection mode of this part is that the fin structure is connected to M0, M0 is connected to M0G, M0G is connected to V0, and V0 is connected to M1. The equivalent resistance of this part of the power line is equivalent to the sum of the resistance of M1 in this part and the resistance of V0 in parallel on the basis of the resistance of this part of M0G. Compared with the case where only the additional metal layer is used, this part of the resistance is the resistance of M0G in this part, which reduces the resistance of the power line.

[0096] Through the above solution, M0G can also be connected to M1 through the contact hole V0, so that the idle part of the winding resources on the first metal layer can be provided to the power line, thereby reducing the overall equivalent resistance of the power line and further reducing the power consumption of the chip.

[0097] Fig.10 is a schematic flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application. Fig.10 As shown, the method includes the following steps.

[0098] S1010: forming a substrate layer.

[0099] For example, in step S1010, a substrate layer for preparing a FinFET structure may be provided. The substrate may be a substrate in various forms, such as a silicon substrate, a bulk semiconductor material substrate, a semiconductor-on-insulator substrate, a compound semiconductor substrate, etc., which is not limited in the present embodiment. Figure 5 The substrate layer 510 in is similar.

[0100] S1020: forming at least one fin field effect transistor on the upper surface of the substrate layer.

[0101] For example, in step S1020, a FinFET structure may be prepared on the substrate layer. The FinFET includes at least one fin structure and at least one gate structure disposed on the upper surface of the substrate layer. The specific preparation process of the FinFET may refer to the existing process flow, and the present application does not specifically limit the formation method of the FinFET. The at least one fin structure may be connected to the substrate layer. Figure 5 Similar to the fin structure 520 in FIG. 1 , at least one gate structure may be Figure 5 The gate structure 530 in is similar.

[0102] S1030: Form at least one connection structure.

[0103] For example, in step S1030, a connection structure may be prepared at the source and drain portions of the FinFET. At least one connection structure crosses at least a portion of the fin structure in at least one fin structure and covers at least a portion of the surface of at least the portion of the fin structure that it crosses. The preparation process of the connection structure may refer to the existing process flow, and the present application does not make specific limitations on this, but the height of the upper surface of the connection structure relative to the upper surface of the substrate layer should be greater than the height of the upper surface of the gate structure relative to the upper surface of the substrate layer. At least one connection structure may be connected to Figure 5 The connection structure 540 in is similar.

[0104] S1040: forming an additional metal layer.

[0105] For example, in step S1040, an additional metal layer for providing a power line MOG may be provided. The additional metal layer is disposed above the gate structure and connected to at least part of the at least one connection structure, the height of the upper surface of the additional metal layer relative to the upper surface of the substrate layer is less than or equal to a first height, and the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is greater than or equal to a second height. The first height is the height of the upper surface of the connection structure relative to the upper surface of the substrate layer, and the second height is the height of the upper surface of the gate structure relative to the upper surface of the substrate layer. The specific structure of the additional metal layer can be referred to Figure 5 An additional metal layer 550 is provided in the embodiment of the present invention.

[0106] Optionally, at least one power line MOG is arranged in the additional metal layer. MOG is electrically connected to at least part of the at least one connection structure, and is used to supply power to the FinFET. Optionally, MOG extends in a direction parallel to the upper surface of the substrate layer.

[0107] In some possible implementations, MOG may be formed by MO epitaxy. Optionally, epitaxial growth methods (or deposition methods) include but are not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), and metal organic chemical vapor deposition (MOCVD).

[0108] Optionally, MOG can be made of a conductive material, including but not limited to at least one of the following: copper, cobalt.

[0109] In some possible embodiments, the method may further include: forming a dielectric layer and a first metal layer, wherein the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer is greater than a first height, and the dielectric layer is used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer; wherein the first metal layer includes at least one winding resource extending in a direction parallel to the upper surface of the substrate layer, and the projection of the at least one winding resource on the upper surface of the substrate layer at least partially overlaps with the projection of at least one connecting structure and / or at least one gate structure on the upper surface of the substrate layer; and the dielectric layer includes at least one first contact hole along the second direction, which is used to connect the at least one winding resource with the at least one connecting structure and / or at least one gate structure.

[0110] Optionally, the extension direction of at least one power line is the same as the extension direction of at least one winding resource, and the projection of at least one winding resource on the upper surface of the substrate layer and the projection of at least one power line on the upper surface of the substrate layer at least partially overlap; the dielectric layer also includes at least one second contact hole along the second direction, which is used to connect at least one winding resource with at least one power line.

[0111] Optionally, the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to a second height; at least one gate structure includes at least one first gate structure and at least one second gate structure; at least one first gate structure is not electrically connected to at least one first power line; and the upper surface of at least one second gate structure is at least partially electrically connected to at least one power line.

[0112] The present application also provides a chip. The chip includes: Figure 5 The semiconductor device shown, or the semiconductor device in the chip is composed of Fig.10 Prepared as shown.

[0113] The embodiment of the present application also provides an electronic device, which includes the above chip.

[0114] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the protection scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: A substrate layer (510), at least one fin field effect transistor, at least one connection structure (540), and an additional metal layer (550); The at least one fin field effect transistor comprises at least one fin structure (520) and at least one gate structure (530) disposed on the upper surface of the substrate layer (510); The at least one connection structure (540) spans over at least a portion of the fin structure (520) of the at least one fin structure (520) and covers at least a portion of the surface of the at least portion of the fin structure (520); The additional metal layer (550) is arranged above the gate structure (530) and is connected to at least part of the connection structures (540) in the at least one connection structure (540); the height of the upper surface of the additional metal layer (550) relative to the upper surface of the substrate layer (510) is less than or equal to a first height; the height of the lower surface of the additional metal layer (550) relative to the upper surface of the substrate layer (510) is greater than or equal to a second height; the first height is the height of the upper surface of the at least one connection structure (540) relative to the upper surface of the substrate layer (510); and the second height is the height of the upper surface of the at least one gate structure (530) relative to the upper surface of the substrate layer (510).

2. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: a first metal layer, wherein the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer (510) is greater than the first height; A dielectric layer, used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer (510); The first metal layer comprises at least one winding resource extending in a direction parallel to the upper surface of the substrate layer (510), and a projection of the at least one winding resource on the upper surface of the substrate layer (510) at least partially overlaps with a projection of the at least one connection structure (540) and / or the at least one gate structure (530) on the upper surface of the substrate layer (510); The dielectric layer comprises at least one first contact hole along the second direction, which is used to connect the at least one winding resource with the at least one connection structure (540) and / or at least one gate structure (530).

3. The semiconductor device according to claim 2, characterized in that At least one power line is arranged in the additional metal layer (550), the at least one power line is electrically connected to at least part of the connection structure (540) in the at least one connection structure (540), and the at least one power line is used to supply power to the at least one fin field effect transistor.

4. The semiconductor device according to claim 3, characterized in that The at least one power line extends in a direction parallel to the upper surface of the substrate layer (510) and passes through the semiconductor device in the extending direction.

5. The semiconductor device according to claim 4, characterized in that The extension direction of the at least one power line is the same as the extension direction of the at least one winding resource, and the projection of the at least one winding resource on the upper surface of the substrate layer (510) and the projection of the at least one power line on the upper surface of the substrate layer (510) at least partially overlap; The dielectric layer also includes at least one second contact hole along the second direction, which is used to connect the at least one winding resource and the at least one power line.

6. The semiconductor device according to any one of claims 3 to 5, characterized in that: The height of the lower surface of the additional metal layer (550) relative to the upper surface of the substrate layer (510) is equal to the second height; The at least one gate structure (530) includes at least one first gate structure (530) and at least one second gate structure (530); The at least one first gate structure (530) is not electrically connected to the at least one first power line; An upper surface of the at least one second gate structure (530) is at least partially electrically connected to the at least one power line.

7. A method for preparing a semiconductor device, characterized in that: include: forming a substrate layer; forming at least one fin field effect transistor on the upper surface of the substrate layer, wherein the at least one fin field effect transistor comprises at least one fin structure and at least one gate structure disposed on the upper surface of the substrate layer; forming at least one connection structure, the at least one connection structure spanning over at least a portion of the at least one fin structure and covering at least a portion of a surface of the at least portion of the fin structure; An additional metal layer is formed, wherein the additional metal layer is arranged above the gate structure and connected to at least part of the at least one connecting structure, the height of the upper surface of the additional metal layer relative to the upper surface of the substrate layer is less than or equal to a first height, and the height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is greater than or equal to a second height, the first height is the height of the upper surface of the at least one connecting structure relative to the upper surface of the substrate layer, and the second height is the height of the upper surface of the at least one gate structure relative to the upper surface of the substrate layer.

8. The preparation method according to claim 7, characterized in that: The preparation method further comprises: forming a dielectric layer and a first metal layer, wherein the height of the lower surface of the first metal layer relative to the upper surface of the substrate layer is greater than the first height, and the dielectric layer is used to fill the gap between the lower surface of the first metal layer and the upper surface of the substrate layer; The first metal layer includes at least one winding resource extending in a direction parallel to the upper surface of the substrate layer, and a projection of the at least one winding resource on the upper surface of the substrate layer at least partially overlaps with a projection of the at least one connection structure and / or at least one gate structure on the upper surface of the substrate layer; The dielectric layer includes at least one first contact hole along the second direction, which is used to connect the at least one winding resource with the at least one connection structure and / or at least one gate structure.

9. The preparation method according to claim 8, characterized in that: At least one power line is arranged in the additional metal layer, the at least one power line is electrically connected to at least part of the at least one connection structure, and the at least one power line is used to supply power to the at least one fin field effect transistor.

10. The preparation method according to claim 9, characterized in that: The at least one power line extends in a direction parallel to the upper surface of the substrate layer and passes through the semiconductor device in the extending direction.

11. The preparation method according to claim 10, characterized in that: The extension direction of the at least one power line is the same as the extension direction of the at least one winding resource, and the projection of the at least one winding resource on the upper surface of the substrate layer and the projection of the at least one power line on the upper surface of the substrate layer at least partially overlap; The dielectric layer also includes at least one second contact hole along the second direction, which is used to connect the at least one winding resource and the at least one power line.

12. The preparation method according to any one of claims 9 to 11, characterized in that: The height of the lower surface of the additional metal layer relative to the upper surface of the substrate layer is equal to the second height; The at least one gate structure includes at least one first gate structure and at least one second gate structure; The at least one first gate structure is not electrically connected to the at least one first power line; An upper surface of the at least one second gate structure is at least partially electrically connected to the at least one power line.

13. A chip, characterized in that: A semiconductor device comprising the semiconductor device as claimed in any one of claims 1 to 6.

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