Dielectric isolation between epitaxial region and sub-fin region

Abstract

Dielectric isolation between the epitaxial region and the sub-fin region is provided. Techniques are provided herein for forming an integrated circuit having a dielectric material formed in a cavity below a source or drain region. A cavity may be formed within the sub-fin portion of the semiconductor device. In one such example, a FET (Field Effect Transistor) includes a gate structure extending around fins of semiconductor material or any number of nanowires. The semiconductor material may extend in a first direction between the source and drain regions, while the gate structure extends on the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric filler may be formed in the recess beneath the source or drain region, or a dielectric liner may be formed on sidewalls of the recess to prevent epitaxial growth of the source or drain region from the sub-fin. Removal of the semiconductor sub-fins from the backside may then be performed without causing damage to the source or drain region.

Description

Background Art

[0001] As integrated circuits continue to shrink in size, many challenges arise. For example, reducing the size of memory and logic cells within the interconnect structure is becoming increasingly difficult, as is reducing the device spacing at the device level. Maintaining a certain level of quality between the various transistor elements can be a challenge, as the various transistor elements may undergo many different manufacturing processes. Therefore, many important challenges remain with regard to forming such semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1A and 1B are different cross-sectional views of an integrated circuit including a dielectric material in a cavity below a source and / or drain region according to an embodiment of the present disclosure.

[0003] Figure 1C According to the embodiment of the present disclosure Figure 1A and 1B A plan view of an integrated circuit.

[0004] Figure 2A and 2B is a cross-sectional view illustrating a stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0005] Figure 3A and 3B is a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0006] Figure 4A and 4B is a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0007] Figure 5A and 5B is a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0008] Fig. 6A and Figure 6Bis a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0009] Fig. 7A and 7B is a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0010] Fig. 8A and 8B is a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0011] Fig.9A and 9B is a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0012] Fig. 10A and 10B is a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0013] Fig.11A and 11B is a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0014] Fig. 12A and 12B is a cross-sectional view illustrating another stage in a first example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0015] Fig.13A and 13B is a cross-sectional view illustrating a stage in a second example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0016] Fig.14A and 14Bis a cross-sectional view illustrating another stage in a second example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0017] Fig.15A and 15B is a cross-sectional view illustrating another stage in a second example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0018] Fig.16A and 16B is a cross-sectional view illustrating another stage in a second example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0019] Fig.17A and 17B is a cross-sectional view illustrating another stage in a second example process for forming an integrated circuit configured with dielectric material in a cavity below source and / or drain regions according to an embodiment of the present disclosure.

[0020] Fig.18 A cross-sectional view of a chip package including one or more semiconductor dies according to some embodiments of the present disclosure is shown.

[0021] Fig.19 is a flow chart of a process for fabricating a semiconductor device having a dielectric material in a cavity below a source and / or drain region according to an embodiment of the present disclosure.

[0022] Fig. 20 A computing system including one or more integrated circuits as variously described herein is shown according to an embodiment of the present disclosure.

[0023] Although the following detailed description will be made with reference to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent in light of the present disclosure. As will be further understood, the drawings are not necessarily drawn to scale or intended to limit the present disclosure to the specific configurations shown. For example, although some of the drawings generally indicate perfectly straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have less than perfect straight lines, right angles (e.g., some features may have tapered sidewalls and / or rounded corners), and some features may have surface topology or otherwise be non-smooth, given the real-world limitations of the processing equipment and techniques used. DETAILED DESCRIPTION

[0024] Provided herein is a technique for forming an integrated circuit having a dielectric material formed in a cavity beneath a source and / or drain region. The cavity may be formed within a sub-fin portion of a semiconductor device. The technique may be used in any number of integrated circuit applications and is particularly useful for logic and memory cells, such as those using finFETs or full gate transistors (e.g., ribbonFETs and nanowire FETs) or fork-sheet transistors (e.g., nanosheet FETs). In one such example, a FET (field effect transistor) includes a gate structure having a gate electrode on a gate dielectric. The gate structure extends around a fin or any number of nanowires (or nanoribbons or nanosheets, as the case may be) of semiconductor material. The semiconductor material may extend in a first direction between the source and drain regions, and the gate structure extends on the semiconductor material in a second direction substantially orthogonal to the first direction. A dielectric fill material may be formed beneath the source and / or drain regions to prevent epitaxial growth of the source or drain regions from any portion of the sub-fin. In another example, one or more dielectric layers can be deposited within the cavity below the source or drain region such that an air gap exists below the source and / or drain region and is surrounded by the one or more deposited dielectric layers. In either case, removal of the semiconductor sub-fin from the back side can be subsequently performed without causing damage to the source or drain region due to the presence of dielectric material below the source or drain region. In this way, the source and drain regions are decoupled from the sub-fin processing. Many variations and embodiments will be apparent in light of the present disclosure.

[0025] Overview

[0026] As previously described above, there remain many important challenges for integrated circuit manufacturing. In more detail, as devices become smaller and more densely packed, semiconductor sub-fins below the semiconductor region of the device may form parasitic junctions between source or drain regions because at least a portion of the source or drain region may be adjacent to the sub-fin. In some cases, via epitaxial growth on the sub-fin, the source or drain region may be undesirably formed on the exposed portion of the sub-fin below the device. In addition, attempts to remove the sub-fin from the back side of the structure may damage the bottom side of the source or drain region. In operation, these effects may, for example, reduce the switching speed of the transistor and reduce overall performance.

[0027] Therefore and in accordance with an embodiment of the present disclosure, a technique for isolating or otherwise decoupling a source or drain region from an underlying sub-fin is provided herein. The technique can be used, for example, to protect a source or drain region and / or eliminate undesired junction formation between a source or drain region and a sub-fin during a backside etching process for removing a sub-fin. In an example, an etching process (e.g., a reactive ion etching (RIE) process) is performed to remove a portion of a semiconductor fin and to form a source / drain trench at a location where the source and drain regions will be. The etching process also etches at least partially into the sub-fin region below the semiconductor fin, thereby forming a groove in the sub-fin region, with dielectric fillers on both sides of the groove. The dielectric filler can act as a shallow trench isolation (STI) between devices. One or more dielectric materials can be formed in the sub-fin groove before forming a source or drain region in the source / drain trench. In one example, one or more dielectric materials substantially fill the volume of the sub-fin groove, and a source or drain region is formed on the filled groove. In another example, one or more dielectric layers are formed within the recess to cover any exposed portions of the sub-fin, and a source or drain region is formed on the one or more dielectric layers. According to some embodiments, the one or more dielectric layers do not fill the volume of the recess, so that an air gap can exist within a given recess below the source or drain region. In any such case, the dielectric material deposited within the sub-fin recess protects the source or drain region from various backside processes (e.g., backside removal of the semiconductor sub-fin).

[0028] According to an embodiment, an integrated circuit includes a semiconductor device having one or more semiconductor bodies extending from a source or drain region in a first direction and a gate structure extending on the one or more semiconductor bodies in a second direction different from the first direction, a dielectric layer under the gate structure, and a dielectric filler under the source or drain region. A top surface of the dielectric filler is above a top surface of the dielectric layer.

[0029] According to another embodiment, an integrated circuit includes one or more semiconductor bodies extending in a first direction from a source or drain region, a gate structure extending on the one or more semiconductor bodies in a second direction different from the first direction, a dielectric layer below the gate structure, and a dielectric liner below the source or drain region. The dielectric liner is located within a cavity in the dielectric layer such that an air gap exists between a bottom surface of the source or drain region and the dielectric liner within the cavity.

[0030] According to another embodiment, a method of forming an integrated circuit includes: forming a multilayer fin extending in a first direction on a substrate, the substrate having a first material layer alternating with a second material layer, and a sub-fin below the alternating material layer; forming a first dielectric layer adjacent to the sub-fin; forming a sacrificial gate and a spacer on the sidewall of the sacrificial gate, the sacrificial gate extending in a second direction on the multilayer fin, the second direction being different from the first direction; removing an exposed portion of the multilayer fin adjacent to the sacrificial gate and at least a portion of the sub-fin below the exposed portion of the multilayer fin so that a groove is formed in the sub-fin; forming a dielectric material in the groove so that a top surface of the dielectric material is above a top surface of the sub-fin; forming a source or drain region on the dielectric material, and the source or drain region is coupled to an end of the second material layer; removing the sacrificial gate and forming a gate structure on the first material layer; removing the sub-fin from the back side of the integrated circuit; and forming a second dielectric layer to replace the sub-fin. Another example may use a body fin (e.g., finFET) instead of a multilayer fin (e.g., ribbonFET), where the source or drain region is formed on the dielectric material and coupled to the end of the fin.

[0031] The technology can be used with any type of planar or non-planar transistor, including finFETs (sometimes called dual-gate transistors or tri-gate transistors), or nanowire and nanoribbon transistors (sometimes called full-gate transistors), or fork-piece transistors, to name a few examples. More generally, the technology described herein can benefit any transistor architecture with a gate dielectric layer that undergoes relatively high temperature annealing (e.g., 500°C to 700°C). The source and drain regions can be, for example, epitaxial regions deposited during etching and replacement source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the corresponding transistor. The gate structure can be implemented with a gate-first process or a gate-last process (sometimes called a replacement metal gate or RMG process) or any other gate formation process. Any number of semiconductor materials can be used to form transistors, such as Group IV materials (e.g., silicon, germanium, silicon germanium) or Group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0032] The use of the techniques and structures provided herein can be detectable using tools, such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM), to name a few suitable example analytical tools; composition mapping; x-ray crystallography or diffraction (XRD); energy dispersive x-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe (LEAP) technology; 3D tomography; or high-resolution physical or chemical analysis. For example, in some example embodiments, such a tool can indicate the presence of a dielectric region below a source or drain region that is different from any surrounding backside dielectric layer (e.g., STI). The dielectric region can include a different dielectric material than the backside dielectric layer, or there can be a visible seam between the dielectric region and the backside dielectric layer. In some examples, air gaps may be observed within the dielectric region beneath the source or drain region.

[0033] It should be readily understood that the meaning of "above" and "on" in the present disclosure should be interpreted in the broadest manner, so that "above" and "on" not only mean "directly on" something, but also include the meaning of being on something with intermediate features or layers therebetween. In addition, for ease of description, spatially relative terms such as "below", "below", "lower", "above", "upper", "top", "bottom", etc. may be used herein to describe the relationship of one element or feature to another element or feature shown in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative descriptors used herein may also be interpreted accordingly.

[0034] As used herein, the term "layer" refers to a portion of a material including a region having a thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entire underlying or superstructure, or may have an extent less than the extent of the underlying or superstructure. In addition, a layer may be a region of a uniform or non-uniform continuous structure, the layer having a thickness less than the thickness of the continuous structure. For example, a layer may be located between or between any pair of horizontal planes between the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A layer may be conformal to a given surface (whether flat or curved), having a relatively uniform thickness across the entire layer.

[0035] As used herein, "compositionally different" or "compositionally unique" materials refer to two materials having different chemical compositions. This compositional difference can be, for example, due to an element in one material that is not in the other (e.g., SiGe is compositionally different from silicon), or due to one material having all of the same elements as a second material, but at least one of those elements is intentionally provided in a different concentration in one material relative to the other material (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this diversity of chemical compositions, materials can also have unique dopants (e.g., gallium and magnesium) or the same dopants but in different concentrations. In yet other embodiments, compositionally unique materials can also refer to two materials having different crystal orientations. For example, (110) silicon is compositionally unique or different from (100) silicon. Stacks that produce different orientations can be achieved, for example, by blanket wafer layer transfer. If two materials are elementally different, then one of the materials has an element that is not present in the other material.

[0036] Architecture

[0037] Figure 1A is a cross-sectional view taken through various semiconductor devices along a “fin” direction according to an embodiment of the present disclosure, showing a semiconductor body extending between source or drain regions of each semiconductor device. Figure 1B shows a parallel to the Figure 1A A cross-sectional view of a gate structure extending across the semiconductor body of the transistor and into the page (or out of the page, as the case may be) such that it moves away from the semiconductor body of the transistor but still straddles the gate structure extending over the semiconductor body. Figure 1C It is cross Figure 1A and Figure 1B A top-down cross-sectional view of adjacent semiconductor devices taken along the dashed line 1C-1C depicted in FIG. Figure 1A Shows a cross Figure 1C A cross section taken along the dashed line 1A-1A depicted in FIG. 1A , and Figure 1B Shown along Figure 1C A cross section taken along the dashed line 1B-1B depicted in FIG.

[0038] Each semiconductor device can be, for example, a non-planar metal oxide semiconductor (MOS) transistor, such as a tri-gate (e.g., finFET) or a gate-all-around (GAA) transistor, although other transistor topologies and types can also benefit from the techniques provided herein. Examples herein show semiconductor devices having a GAA structure (e.g., having nanoribbons, nanowires, or nanosheets extending between source and drain regions). Other examples can have a fork-sheet structure having a p-type device and an n-type device separated by a dielectric ridge or structure.

[0039] The semiconductor material used in each semiconductor device can be formed by a semiconductor substrate. One or more semiconductor regions of the device may include fins, which may be, for example, intrinsic to the substrate (formed by the substrate itself), such as silicon fins etched from a bulk silicon substrate. Alternatively, the fins may be formed by materials deposited onto the substrate. In one such example case, a blanket layer of SiGe may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In yet other embodiments, the fins include alternating material layers (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanobelts and nanosheets during the gate formation process, wherein one type of alternating layer is selectively etched away to release another type of alternating layer within the channel region so that a full gate process or a fork-sheet gate process may then be performed. Likewise, in some examples, the alternating layers may be blanket deposited and then etched into fins or deposited into fin-shaped grooves.

[0040] In some embodiments, the substrate is removed and replaced with one or more backside dielectric layers represented by dielectric base layer 102. Thus, dielectric base layer 102 may represent STI regions and any number of backside interconnect layers. According to some embodiments, the dielectric layers of dielectric base layer 102 include any suitable dielectric material, such as silicon dioxide.

[0041] Each semiconductor device includes one or more semiconductor regions (also referred to as channel regions), such as one or more nanoribbons 104 extending in a first direction between epitaxial source or drain regions 106. The term nanoribbon may also encompass other similar shapes, such as nanowires or nanosheets. A gate structure 108 extends over one or more semiconductor regions (e.g., nanoribbons 104) of a given semiconductor device in a second direction (e.g., into and out of the page) to form a transistor gate.

[0042] Depending on the application and dopant distribution, any source or drain region 106 can act as a source region or a drain region. Any semiconductor material suitable for source and drain regions (e.g., Group IV and Group III-V semiconductor materials) can be used for any of the source or drain regions 106 shown. In any such case, the composition and doping of the source or drain region 106 can be the same or different, depending on the polarity of the transistor. For example, any semiconductor device that is a p-channel transistor has a high concentration of p-type dopants in the associated source or drain region 106, and any semiconductor device that is an n-channel transistor has a high concentration of n-type dopants in the associated source or drain region 106. Example p-type dopants include boron, and example n-type dopants include phosphorus. Any number of source and drain configurations and materials can be used. In some examples, the n-type source or drain region includes silicon doped with phosphorus, and the p-type source or drain region includes silicon germanium doped with boron.

[0043] The gate structure 108 includes a gate dielectric and a gate electrode. The gate dielectric refers to any number of dielectric layers present between the nanoribbon 104 and the gate electrode. The gate dielectric may also be present on the surface of other structures within the gate trench, such as the surface of the dielectric base layer 102. The gate dielectric may include any suitable gate dielectric material. In some embodiments, the gate dielectric includes a layer of native oxide material (e.g., silicon dioxide) on the nanoribbon or other semiconductor region that constitutes the channel region of the device, and a layer of high-k dielectric material (e.g., hafnium oxide) on the native oxide.

[0044] The gate electrode may represent any number of conductive layers on the gate dielectric, such as any metal, metal alloy, or doped polysilicon layer. In some embodiments, the gate electrode includes one or more work function metals around the nanoribbons 104. In some embodiments, one of the semiconductor devices is a p-channel device including a work function metal having titanium around its nanoribbons, and the other semiconductor device is an n-channel device including a work function metal having tungsten around its nanoribbons. The gate electrode may also include a fill metal or other conductive material around the work function metal to provide an overall gate electrode structure.

[0045] According to some embodiments, spacer structures 110 and internal spacers 112 are present along sidewalls of gate structure 108. Spacer structures 110 and internal spacers 112 may be any suitable dielectric material, such as silicon nitride, and provide separation between a given gate structure 108 and an adjacent source or drain region 106. Internal spacers 112 may separate adjacent nanoribbons 104 from each other along a third direction (e.g., a vertical direction).

[0046] According to some embodiments, dielectric cap layer 114 may be present on a gate electrode within a gate trench of a semiconductor device. A top surface of dielectric cap layer 114 may be substantially coplanar with a top surface of spacer structure 110. In some examples, dielectric cap layer 114 may include the same dielectric material as spacer structure 110.

[0047] According to some embodiments, a conductive contact 116 is provided on the source or drain region 106. The conductive contact 116 may include any suitable conductive material, such as tungsten, molybdenum, ruthenium, cobalt, or other metals. The conductive contacts 116 may be formed together so that they all include the same conductive material. In some examples, the conductive contact 116 includes a silicide layer (e.g., a layer having titanium and silicon) directly on the top surface of the source or drain region 106.

[0048] According to some embodiments, dielectric region 118 is provided below source or drain region 106 including one or more dielectric materials. In some examples, a bottom portion of dielectric region 118 includes a bottom dielectric layer 120. According to some embodiments, bottom dielectric layer 120 may be formed during the same process of forming inner spacer 112, and thus bottom dielectric layer 120 may be the same dielectric material as inner spacer 112. According to some embodiments, the remaining volume of dielectric region 118 is filled or substantially filled with dielectric filler 122. Dielectric filler 122 may be any suitable dielectric material having a high etch selectivity to the dielectric material of bottom dielectric layer 120 and inner spacer 112. In one example, dielectric filler 122 includes silicon dioxide, while bottom dielectric layer 120 and inner spacer 112 include silicon nitride. According to some embodiments, a top surface of dielectric region 118 (e.g., a top surface of dielectric filler 122) is above a top surface of base dielectric layer 102 and below a bottom surface of bottommost nanoribbon 104. Thus, growth of source or drain 106 is confined to a region above dielectric region 118 and is prevented from growing from any pre-existing sub-fin portion.

[0049] According to some embodiments, the formation of the dielectric region 118 may have the additional benefit of masking the gate footer region 124 , which may extend partially into the source / drain trenches adjacent to the source or drain region 106 . Figure 1B 1 shows how a dielectric fill 122 covers a gate footer region 124 that may extend below the bottom of the spacer structure 110. This may protect the source or drain region 106 from damage during the gate formation process, which will be discussed in more detail herein. According to some embodiments, Figure 1B Also shown in FIG. 1 is a dielectric plug 126 that fills the source / drain trench portions between different source or drain regions. The dielectric plug 126 may be any suitable dielectric material, such as silicon dioxide. Figure 1C As shown, Figure 1B The cross section is parallel to Figure 1A and in the second direction Figure 1A The source or drain region 106 is closely adjacent to each other.

[0050] Manufacturing method

[0051] Figure 2A-12A 2B-12B include cross-sectional views that collectively illustrate a first example process for forming an integrated circuit configured with a dielectric material in a cavity below a source or drain region according to an embodiment of the present disclosure. Figures 13A-17A13B-17B include cross-sectional views that collectively illustrate a second example process for forming an integrated circuit configured with a dielectric material in a cavity below a source or drain region according to an embodiment of the present disclosure. Figure 2A-17A Representation and Figure 1A A similar cross-sectional view across a series of semiconductor devices, while Figure 2B-17B Representation and Figure 1B Similar to Figure 2A-17A Each group of figures sharing the same letter shows an example structure resulting from the process flow up to that point in time, so the depicted structure evolves as the process flow continues, ultimately forming Figures 12A-12B The first example structure shown in Figure 1A and 1B ), and Fig.17A and 17B . Such an example structure may be part of an entire integrated circuit (e.g., such as a processor or memory chip) that includes, for example, digital logic cells and / or memory cells and analog mixed signal circuits. Thus, the integrated circuit structure shown may be part of a larger integrated circuit that includes other integrated circuits not depicted. Example materials and process parameters are given, but it will be understood in light of the present disclosure that other materials and process parameters may also be used.

[0052] Figure 2A and 2B Each shows a cross-sectional view taken through a substrate 201 having a series of material layers formed on the substrate according to an embodiment of the present disclosure. Alternating material layers can be deposited on the substrate 201, including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form a GAA transistor structure. Any number of alternating sacrificial layers 202 and semiconductor layers 204 can be deposited on the substrate 201.

[0053] Substrate 201 may be, for example, a bulk substrate including a Group IV semiconductor material (e.g., silicon, germanium, or SiGe), a Group III-V semiconductor material (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors may be formed. Alternatively, substrate 201 may be a semiconductor-on-insulator substrate having a desired semiconductor layer on a buried insulator layer (e.g., silicon on silicon dioxide). Alternatively, substrate 201 may be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates may be used.

[0054] According to some embodiments, semiconductor layer 204 has a different material composition than sacrificial layer 202. In some embodiments, semiconductor layer 204 includes a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a III-V material such as indium phosphide (InP) or gallium arsenide (GaAs). Sacrificial layer 202 includes a material that can be selectively removed relative to semiconductor layer 204. For example, in some examples, semiconductor layer 204 is silicon and sacrificial layer 202 is SiGe, or vice versa. In some other examples where SiGe is used in each of semiconductor layer 204 and sacrificial layer 202, the germanium concentration between semiconductor layer 204 and sacrificial layer 202 is different to allow for etching selectivity. For example, semiconductor layer 204 can include a higher germanium content than sacrificial layer 202.

[0055] Although the dimensions may vary from one exemplary embodiment to the next, in some examples, the thickness of each semiconductor layer 204 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each semiconductor layer 204 is substantially the same (e.g., within 1-2 nm). The thickness of each sacrificial layer 202 may be approximately the same as the thickness of each semiconductor layer 204 (e.g., about 5-20 nm). In some embodiments, the bottommost sacrificial layer 202 (e.g., formed directly on the substrate 201) is thicker than the other sacrificial layers 202. For example, the bottom sacrificial layer 202 may be 25%, 50%, 75%, or 100% thicker than the thickness of the remaining sacrificial layers 202. Each of the semiconductor layer 204 and the sacrificial layer 202 may be deposited using any material deposition technique, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) or epitaxial growth.

[0056] Figure 3A and 3B 3 and 4 respectively depict that, according to an embodiment, after forming the cap layer 302 and subsequently forming the fins under the cap layer 302, Figure 2A and 2B . The capping layer 302 may be any suitable hard mask material, such as a carbon hard mask (CHM) or silicon nitride. The capping layer 302 is patterned into rows to form corresponding rows of fins from alternating layers of the sacrificial layer 202 and the semiconductor layer 204. Figure 3A As seen in FIG. 3 , the capping layer 302 extends along the top of each fin in a first direction.

[0057] According to some embodiments, the anisotropic etching process through the layer stack continues into at least a portion of substrate 201. The portion of substrate 201 below cap layer 302 and the fin is not etched and produces a sub-fin region 304, such as Figure 3AThe etched portion of the substrate 201 that is not below the fin may be filled with a dielectric filler 306 that acts as a STI between adjacent fins, such as Figure 3B As shown in . Dielectric filler 306 may be any suitable dielectric material, such as silicon dioxide. According to some embodiments, sub-fin region 304 indicates that both sides of substrate 201 are the remaining portions of dielectric filler 306 .

[0058] Figure 4A and 4B Depicted is a diagram showing, according to some embodiments, after forming sacrificial gate 402 and spacer structure 404. Figure 3A and 3B . A gate mask layer may first be patterned into strips extending orthogonally (e.g., in the second direction) across each fin so as to form corresponding sacrificial gates 402 in the strips below the gate mask layer. Thereafter, the gate mask layer may be removed or may remain as a capping layer over each sacrificial gate 402. According to some embodiments, the sacrificial gate material is removed in all areas not protected by the gate mask layer. Figure 4B As seen in FIG. 4 , the bottom of sacrificial gate 402 can flare outward due to the proximity of the semiconductor fins. This manufacturing effect creates a gate footer region 406 that extends toward the middle of the source / drain trenches between adjacent gate trenches. Sacrificial gate 402 can be any suitable material that can be selectively removed without damaging the semiconductor material of the fins. In some examples, sacrificial gate 402 includes polysilicon.

[0059] According to some embodiments, a spacer structure 404 is formed along the sidewalls of the sacrificial gate 402. The spacer structure 404 may be conformally deposited (e.g., CVD or ALD) and then etched back or otherwise removed (e.g., by anisotropic or directional etching) from the horizontal surface so that the spacer structure 404 remains mostly only on the sidewalls of any exposed structure. The width (along the first direction) of the spacer structure 404 may vary from one example to the next, but in some cases is in the range of 3nm to 20nm. According to some embodiments, the spacer structure 404 may be any suitable dielectric material, such as silicon nitride, silicon carbonitride, or silicon carbon nitride oxide. In one such embodiment, the spacer structure 404 includes a nitride and the dielectric fill 306 includes an oxide to provide a degree of etch selectivity during final gate processing. Other etch selective dielectric schemes (e.g., oxide / carbide, carbide / nitride) may also be used for the spacer structure 404 and the dielectric fill 306. In other embodiments, the spacer structure 404 and the dielectric fill 306 are identical or otherwise similar in composition, where etch selectivity is not employed.

[0060] According to some embodiments, the spacer structure 404 extends to the top surface of the gate footer region 406 in a third direction (e.g., vertical direction), but does not cover the entire gate footer region 406. During the etch-back process, the dielectric material of the spacer structure 404 may be removed from a more horizontal portion of the gate footer region 406. Therefore, a portion of the sacrificial gate 402 may be exposed at the bottom of the source / drain trench.

[0061] Figure 5A and 5B depicts, after removing the exposed portions of the fin not protected by the sacrificial gate 402 and the spacer structure 404, according to some embodiments, Figure 4A and 4B 406. A cross-sectional view of the structure shown in . The exposed fin portions may be removed using any anisotropic etching process, such as reactive ion etching (RIE) or other directional etching process. In accordance with some embodiments, the exposed fin portions are removed from source / drain trenches that alternate with gate trenches (currently filled with sacrificial gate 402) along a first direction. In some embodiments, at least a portion of the sub-fin region 304 is also removed during the etching process, thereby forming a sub-fin recess. Due to the high aspect ratio of the trench, the sub-fin recess may have a tapered profile. During the etching process for removing portions of the semiconductor fin, some exposed portions of the gate foot region 406 may also be removed.

[0062] Fig. 6A and 6B FIG. 2 depicts an embodiment of the present disclosure, after removing a portion of the sacrificial layer 202 . Figure 5A and 5B An isotropic etching process may be used to selectively recess the exposed end of each sacrificial layer 202 (eg, while etching relatively few semiconductor layers 204).

[0063] Fig. 7A and 7B FIG. 7 depicts an embodiment of the present disclosure, after forming the inner spacer 702. Fig. 6A and 6B, which is a cross-sectional view of the structure shown in . The inner spacer 702 can have a material composition similar or identical to that of the spacer structure 404. Thus, the inner spacer 702 can be any suitable dielectric material that exhibits a high etch selectivity to semiconductor materials such as silicon and / or silicon germanium. The inner spacer 702 can be conformally deposited on the sides of the fin structure, for example using a conformal deposition process such as CVD or ALD, and then etched back using an isotropic etching process to expose the ends of the semiconductor layer 204. According to some embodiments, after the etch back process, a portion of the dielectric material at the bottom of the sub-fin groove remains and forms a bottom dielectric layer 704. Thus, the bottom dielectric layer 704 can be the same dielectric material as the inner spacer 702. According to some embodiments, the inner spacer 702 has a width similar to that of the spacer structure 404 (e.g., along the first direction). Note that according to some embodiments, the inner spacer 702 can be formed around the ends of the semiconductor layer 204 and not along other edges of the gate trench away from the semiconductor layer 204 (e.g., Figure 7B ).

[0064] Fig. 8A and 8B 8 and 9 respectively depict that after forming a dielectric filler 802 in at least a remaining volume of the sub-fin recess according to some embodiments, Fig. 7A and 7B . A dielectric filler 802 may be formed within the source / drain trenches and subsequently recessed to a final height that places the top surface of the dielectric filler 802 at least above the top surface of the adjacent sub-fin region 304. According to some embodiments, the top surface of the dielectric filler 802 is lower than the bottom surface of the bottommost semiconductor layer 204 in the fin. Figure 8B As shown in , dielectric filler 802 is also formed within the bottom of the source / drain trenches and can therefore cover the gate footer region 406. The dielectric filler 802 can be any suitable dielectric material that exhibits good selective etching to the spacer structure 404 and the inner spacer 702. In some examples, the dielectric filler 802 includes silicon dioxide, and the spacer structure 404 and the inner spacer 702 include silicon nitride.

[0065] Fig.9A and 9B 1 and 2 respectively depict that after forming a source or drain region 902 in a source / drain trench according to some embodiments, Fig. 8A and 8B. A source or drain region 902 may be formed in an area previously occupied by the exposed fin between the spacer structures 404. According to some embodiments, the source or drain region 902 is epitaxially grown from the exposed semiconductor material at the end of the semiconductor layer 204. In some example embodiments, the source or drain region 902 is an n-channel source or drain region (e.g., epitaxial silicon with an n-type dopant) or a p-channel source or drain region (e.g., epitaxial SiGe with a p-type dopant). A contact 904 may be formed on a top surface of the source or drain region 902. The contact 904 may include any suitable conductive material, such as tungsten, cobalt, molybdenum, or ruthenium, for making electrical contact with the underlying source or drain region 902. In some embodiments, the region above the source or drain region 902 is filled with a dielectric, which is replaced with the contact 904 after the sacrificial gate 402 is replaced with the gate structure. According to some embodiments, due to the presence of dielectric filler 802 , no portion of source or drain region 902 grows from sub-fin region 304 .

[0066] According to some embodiments, along a given source / drain trench running in the second direction, a dielectric filler 906 is provided between adjacent source or drain regions 902. In some examples, the dielectric filler 906 occupies the remaining volume within the source / drain trench, which is around and possibly on a portion of the source or drain region 902. The dielectric filler 906 can be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler 906 extends up to and is coplanar with the top surface of the spacer structure 404 (e.g., after a polishing process).

[0067] Fig. 10A and 10B 4 and 40, respectively, after removing the sacrificial gate 402 and the sacrificial layer 202 according to some embodiments. Fig.9A and 9B 4. In examples where gate mask layers are still present, they may be removed at this time. Once sacrificial gate 402 is removed, the fins extending between spacer structures 404 are exposed.

[0068] In the example where the fin includes alternating sacrificial layers 202 and semiconductor layers 204, the sacrificial layers 202 are selectively removed to leave nanoribbons 1002 extending between corresponding source or drain regions 902. Each set of perpendicular nanoribbons 1002 represents a semiconductor region (also referred to as a channel region) of a different semiconductor device. It should be understood that the nanoribbons 1002 may also be nanowires or nanosheets. The sacrificial gate 402 and the sacrificial layer 202 may be removed using the same isotropic etching process or different isotropic etching processes.

[0069] Fig.11A and11B 1 and 2 respectively depict that after forming a gate structure 1102 around the nanoribbon 1002 in the gate trench according to some embodiments, Fig. 10A and 10B . As described above, the gate structure 1102 includes a gate dielectric and a gate electrode on the gate dielectric. The gate dielectric can be conformally deposited around the nanoribbon 1002 using any suitable deposition process, such as atomic layer deposition (ALD). The gate dielectric can include any suitable dielectric (e.g., silicon dioxide and / or a high-k dielectric material). For example, examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. According to some embodiments, the gate dielectric is hafnium oxide with a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric includes one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some examples, the gate dielectric can be a multilayer structure. For example, the gate dielectric may include a first layer on the nanoribbon 1002 and a second layer on the first layer. The first layer may be, for example, an oxide of a semiconductor layer (e.g., silicon dioxide), and the second layer may be a high-k dielectric material (e.g., hafnium oxide). In some embodiments, when a high-k dielectric material is used, an annealing process may be performed on the gate dielectric to improve its quality. In some embodiments, the high-k material may be nitrided to improve its aging resistance.

[0070] The gate electrode can be deposited on the gate dielectric and can be any conductive structure. In some embodiments, the gate electrode includes doped polysilicon, a metal or a metal alloy. Examples of suitable metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper and their carbides and nitrides. The gate electrode can include, for example, one or more work function layers, a resistance reduction layer and / or a barrier layer. The work function layer can include, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate, or an n-type work function material (e.g., titanium aluminum carbide) for an NMOS gate.

[0071] According to some embodiments, the gate cap 1104 can be formed by first recessing the gate electrode and filling the recess with a dielectric material. The dielectric material can then be polished so that its top surface is substantially coplanar with any adjacent spacer structures or materials within the source / drain trenches. The gate cap 1104 can be any suitable dielectric material, such as silicon nitride.

[0072] Fig. 12A and 12B and respectively depict, according to some embodiments, after removing the semiconductor material from the back side and replacing it with a dielectric material. Fig.11A and 11B . Once all front-side processes have been performed across the integrated circuit, the substrate 201 may be removed by any arrangement of grinding, polishing, and / or chemical etching processes. According to some embodiments, all material is removed from the back side until at least the bottom surface of the dielectric filler 306 is exposed, which may also expose the bottom surface of the adjacent sub-fin region 304. According to some embodiments, the sub-fin region 304 is also removed from the back side and replaced by the dielectric material 1202, which may include any number of dielectric layers. In some examples, the dielectric material 1202 also covers the dielectric filler 306 and may be the same or similar dielectric material as the dielectric filler 306. In some examples, the dielectric filler 306 is also removed from the back side, and the dielectric material 1202 represents a newly deposited dielectric material on the back side of the integrated circuit. According to some embodiments, in any case, the dielectric region consisting of the bottom dielectric layer 704 and the dielectric filler 802 extends into the dielectric material 1202.

[0073] Fig.13A and 13B 1 and 2 respectively depict, according to some embodiments, after forming a dielectric liner 1302 along all exposed surfaces within the source / drain trenches, Fig. 7A and 7B . The dielectric liner 1302 may have a thickness between about 3 nm and about 7 nm and may be any suitable dielectric material that exhibits a high etch selectivity to the material of the spacer structure 404 and the inner spacer 702. In one example, the dielectric liner 1302 includes aluminum oxide. The dielectric liner 1302 may also be formed on the top surface of the bottom dielectric layer 704 within the sub-fin recess. Fig. 14B As seen in FIG. 4 , the dielectric liner 1302 covers the gate foot region 406 .

[0074] Fig.14A and 14B 1 and 2 respectively depict, according to some embodiments, after forming sacrificial material 1402 in source / drain trenches and subsequently trimming dielectric liner 1302, Fig.13A and 13B . In some examples, sacrificial material 1402 includes a carbon hard mask (CHM), which can be deposited within the source / drain trenches and recessed to a final height. According to some embodiments, the top surface of sacrificial material 1402 above the sub-fin recess is at least above the top surface of the adjacent sub-fin region 304. According to some embodiments, the top surface of sacrificial material 1402 is lower than the bottom surface of the bottommost semiconductor layer 204 in the fin. Fig. 14BAs shown in , sacrificial material 1402 also remains along the bottom of other portions of the source / drain trenches.

[0075] According to some embodiments, all portions of dielectric liner 1302 not protected by sacrificial material 1402 are removed. In some examples, an isotropic ammonia-based etch may be used to remove dielectric liner 1302. According to some embodiments, dielectric liner 1302 remains on all surfaces of sub-fin region 304 at least within the sub-fin recess.

[0076] Fig.15A and 15B 1 and 2 respectively depict, according to some embodiments, after removing the sacrificial material 1402 and forming a source or drain region 1502 in the source / drain trench, Fig.14A and 14B . The sacrificial material 1402 may be removed using an ashing process or any other suitable isotropic etching process. A source or drain region 1502 may be formed in the area previously occupied by the exposed fins between the spacer structures 404. According to some embodiments, the source or drain region 1502 is epitaxially grown from the exposed semiconductor material at the end of the semiconductor layer 204. In some example embodiments, the source or drain region 1502 is an n-channel source or drain region (e.g., epitaxial silicon with an n-type dopant) or a p-channel source or drain region (e.g., epitaxial SiGe with a p-type dopant). According to some embodiments, due to the presence of the dielectric liner 1302, no portion of the source or drain region 1502 grows from the sub-fin region 304. In some examples, a cavity 1504 is formed below the source or drain region 1502 in the area that was previously the sub-fin recess. The cavity 1504 may be closed at the top (due to the growth of the source or drain region 1502), or may have openings on either side of the top along the second direction.

[0077] Fig.16A and 16B and respectively depicting, according to some embodiments, after forming additional dielectric material in the source / drain trenches; Fig.15A and 15B1504. A cross-sectional view of the structure shown in . One or more other dielectric materials are formed within the source / drain trenches to protect the source or drain regions 1502 from certain process operations and to fill any dead space between the source or drain regions 1502 within the source / drain trenches. Thus, one or more dielectric layers 1602 may be deposited on the surface of the source or drain regions 1502 and may also be deposited on the surface within the cavity 1504. In some examples, the one or more dielectric layers 1602 include at least one layer of silicon nitride. Along a given source / drain trench running in the second direction, a dielectric filler 1604 is provided between adjacent source or drain regions 1502. In some examples, the dielectric filler 1604 occupies the remaining volume within the source / drain trench around and on a portion of the source or drain region 1502. The dielectric filler 1604 may be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler 1604 extends up to and is coplanar with the top surface of the spacer structure 404 (eg, after a polishing process). The dielectric filler 1604 may be provided on one or more dielectric layers 1602 within the source / drain trenches.

[0078] According to some embodiments, the formation of one or more dielectric layers 1602 and / or dielectric filler 1604 closes any gaps or openings at the top of cavity 1504, leaving an air gap 1606 within a central portion of cavity 1504. Air gap 1606 may be filled with an inert gas (e.g., argon) or may be substantially free of appreciable gas at vacuum pressure.

[0079] Fig.17A and 17B 1702, gate structure 1704, gate cap 1706, and backside dielectric material 1708. Fig.16A and 16B These structures are similar to those in the above reference. Figures 9A-12A 9b - 12B are formed in the same manner as discussed above. According to some embodiments, the dielectric region including at least the bottom dielectric layer 704 and the dielectric liner 1302 extends into the dielectric material 1708.

[0080] Fig.18 An example embodiment of a chip package 1800 according to an embodiment of the present disclosure is shown. It can be seen that the chip package 1800 includes one or more dies 1802. The one or more dies 1802 may include at least one integrated circuit having a semiconductor device, such as any semiconductor device disclosed herein. In some example configurations, the one or more dies 1802 may include any other circuits for interfacing with other devices formed on the die or other devices connected to the chip package 1800.

[0081] It can also be seen that the chip package 1800 includes a housing 1804 bonded to a package substrate 1806. The housing 1804 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for the components of the chip package 1800. One or more dies 1802 can be conductively coupled to the package substrate 1806 using connections 1808, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGA), pins, or wire bonding, just to name a few examples. The package substrate 1806 can be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive paths (e.g., including conductive vias and lines) that extend through the dielectric material between faces of the package substrate 1806 or between different locations on each face. In some embodiments, the package substrate 1806 can have a thickness of less than 1 mm (e.g., between 0.1 mm and 0.5 mm), although any number of package geometries can be used. Additional conductive contacts 1812 may be provided on the opposite side of the package substrate 1806 for conductively contacting, for example, a printed circuit board (PCB). One or more through-holes 1810 extend through the thickness of the package substrate 1806 to provide a conductive path between one or more connections 1808 and one or more contacts 1812. For ease of illustration, the through-hole 1810 is shown as a single straight column passing through the package substrate 1806, although other configurations may be used (e.g., inlays, dual inlays, through-silicon vias, or interconnect structures that meander through the thickness of the substrate 1806 to contact one or more intermediate locations therein). In still other embodiments, the through-hole 1810 is made of multiple smaller stacked through-holes, or is staggered at different locations across the package substrate 1806. In the illustrated embodiment, the contact 1812 is a solder ball (e.g., for a bump-based connection or a ball grid array arrangement), but any suitable package bonding mechanism may be used (e.g., a pin in a pin grid array arrangement or a contact in a contact grid array arrangement). In some embodiments, solder resist is provided between the contacts 1812 to inhibit short circuits.

[0082] In some embodiments, molding material 1814 may be disposed around one or more dies 1802 included within housing 1804 (e.g., as an underfill material between die 1802 and package substrate 1806, and as an overfill material between die 1802 and housing 1804). Although the size and quality of molding material 1814 may vary from one embodiment to the next, in some embodiments, molding material 1814 is less than 1 millimeter thick. Example materials that may be used for molding material 1814 include epoxy molding materials, as appropriate. In some cases, molding material 1814, in addition to being electrically insulating, is also thermally conductive.

[0083] method

[0084] Fig.19 is a flow chart of a method 1900 for forming at least a portion of an integrated circuit according to one embodiment. The various operations of the method 1900 may be performed in Figure 2A-17A 2B-17B. However, the correlation of various operations of method 1900 with specific components shown in the aforementioned figures is not intended to imply any structural and / or use limitations. Instead, the aforementioned figures provide example embodiments of method 1900. Other operations may be performed before, during, or after any operation of method 1900. For example, method 1900 does not explicitly describe various standard processes that are typically performed to form transistor structures. Some operations of method 1900 may be performed in an order different from the order shown.

[0085] According to some embodiments, method 1900 begins at operation 1902, where a plurality of parallel semiconductor fins are formed. The semiconductor material in the fins may be formed from a substrate such that the fins are an integral part of the substrate (e.g., etched from a bulk silicon substrate). Alternatively, the fins may be formed from a material deposited onto an underlying substrate. In one such example case, a blanket layer of SiGe may be deposited onto a silicon substrate and then patterned and etched to form a plurality of SiGe fins extending from the substrate. In another such example, non-intrinsic fins may be formed in a so-called aspect ratio-based capture process, in which the intrinsic fins are etched away to leave fin-shaped trenches that may then be filled with alternative semiconductor materials (e.g., group IV or group III-V materials). In yet other embodiments, the fins include alternating layers of material (e.g., alternating layers of silicon and SiGe) that facilitate the formation of nanowires and nanoribbons during a gate formation process, wherein one type of alternating layer is selectively etched away to release another type of alternating layer within the channel region so that a full gate-all-around (GAA) process may then be performed. Likewise, according to some examples, the alternating layers may be blanket deposited and then etched into fins, or deposited into fin-shaped trenches. The fins may also include a cap structure on each fin that is used to define the position of the fin during, for example, an RIE process. The cap structure may be a dielectric material, such as silicon nitride.

[0086] According to some embodiments, a dielectric filler is formed around a sub-fin of one or more fins. In some embodiments, the dielectric filler extends between each pair of adjacent parallel fins and travels longitudinally in the same direction as the fins. In some embodiments, the anisotropic etching process that forms the fins also etches into a portion of the substrate, and the dielectric filler can be formed within a recessed portion of the substrate. Thus, the dielectric filler acts as a shallow trench isolation (STI) between adjacent fins. The dielectric filler can be any suitable dielectric material, such as silicon dioxide. The lower portion of the fin adjacent to the dielectric filler can be identified as a sub-fin.

[0087] The method 1900 continues with operation 1904, where a sacrificial gate is formed on the fin. The sacrificial gate can be patterned in strips running orthogonally and parallel to each other on the fin using a gate mask layer (e.g., forming a cross-hatched pattern). The gate mask layer can be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate itself can be formed of any suitable material that can be selectively removed later without damaging the semiconductor material of the fin. In one example, the sacrificial gate includes polysilicon.

[0088] According to some embodiments, the spacer structure is also formed on at least the sidewalls of the sacrificial gate. The spacer structure can be deposited and then etched back so that the spacer structure mostly remains only on the sidewalls of any exposed structure. In some cases, the spacer structure can also be formed along the sidewalls of the exposed fins running orthogonally between the strips of the sacrificial gate. According to some embodiments, the spacer structure can be any suitable dielectric material, such as silicon nitride or silicon oxynitride.

[0089] Method 1900 continues with operation 1906, where exposed portions of the fin are removed to form source / drain trenches. Any exposed portions of the fin not covered by a sacrificial gate or spacer structure may be removed using any anisotropic etching process, such as reactive ion etching (RIE). In accordance with some embodiments, the etching process continues through the fin and removes portions of the sub-fins between the dielectric fillers. The removed sub-fin portions create sub-fin recesses that extend below the top surface of the adjacent dielectric filler within the source / drain trenches. In accordance with some embodiments, as described above, the sacrificial layer of the fin may be recessed (e.g., by an isotropic etching process) followed by deposition of internal spacers (e.g., silicon nitride).

[0090] Method 1900 continues with operation 1908 where a dielectric material is formed within the sub-fin recess. According to some embodiments, the dielectric material deposited during the formation of the inner spacer as discussed above is also deposited at the bottom of the sub-fin recess and remains after the formation of the inner spacer. Thus, the bottom dielectric layer can have the same dielectric material as the inner spacer.

[0091] In one example, a dielectric filler is formed within the remaining volume of the sub-fin recess on the bottom dielectric layer. The dielectric filler can be formed within the source / drain trench and then recessed to a final height that places the top surface of the dielectric filler at least above the top surface of the adjacent sub-fin or the top surface of the adjacent STI. According to some embodiments, the top surface of the dielectric filler is lower than the bottom surface of the bottommost semiconductor layer in the fin. The dielectric filler can be any suitable dielectric material that exhibits good selective etching of the spacer structure and the internal spacer. In some examples, the dielectric filler includes silicon dioxide, and the spacer structure and the internal spacer include silicon nitride.

[0092] In another example, a dielectric liner is formed along the surface of the source / drain trench and on the bottom dielectric layer within the sub-fin recess. Thus, the dielectric liner can be formed on at least all exposed semiconductor surfaces within the sub-fin recess. The dielectric liner can have a thickness between about 3 nm and about 7 nm and can be any suitable dielectric material that exhibits high etch selectivity to the material of the spacer structure and the internal spacer. In one example, the dielectric liner includes aluminum oxide.

[0093] According to some embodiments, a sacrificial material is formed on the lower portion of the source / drain trenches to protect the lower portion of the dielectric liner, while the exposed top portion of the dielectric liner is removed. The dielectric liner may be removed using any suitable isotropic etching process (e.g., an ammonia-based etching process). After removing the sacrificial material, the dielectric liner remains along the lower surface of the source / drain trenches and at least along all surfaces within the sub-fin recess.

[0094] Method 1900 continues with operation 1910, where source or drain regions are formed at opposite ends of the fins within the source / drain trenches. The source or drain region may be formed in an area previously occupied by the exposed fins between the spacer structures. According to some embodiments, the source or drain region is epitaxially grown from the exposed semiconductor material (or nanoribbon, nanowire, or nanosheet, as the case may be) of the fin along the outer wall of the spacer structure. In some example embodiments, the source or drain region is an NMOS source or drain region (e.g., epitaxial silicon with an n-type dopant) or a PMOS source or drain region (e.g., epitaxial SiGe with a p-type dopant). A dielectric filler may be formed between and on the source or drain region along a given source / drain trench. The dielectric filler may be any suitable dielectric material, such as silicon dioxide. In some examples, the dielectric filler extends over the source or drain region until and coplanar with the top surface of the spacer structure. The dielectric filler also acts as an electrical insulator between adjacent source or drain regions, although some adjacent source or drain regions may have merged together during their growth. According to some embodiments, no portion of the source or drain region grows from the sub-fin due to the presence of the dielectric filler in the sub-fin recess or the dielectric liner in the sub-fin recess.

[0095] Method 1900 continues with operation 1912, where the sacrificial gate is replaced with a gate structure. According to some embodiments, the sacrificial gate may be removed together with any sacrificial layer in the exposed fin between the spacer structures (in the case of a GAA structure). A gate structure may then be formed to replace the sacrificial gate. The gate structure may include both a gate dielectric and a gate electrode. According to some embodiments, a gate dielectric is first formed on the exposed semiconductor region between the spacer structures, and then a gate electrode is formed in the remaining portion of the gate trench between the spacer structures. The gate dielectric may include any number of dielectric layers deposited using a CVD process (e.g., ALD). The gate electrode may include any conductive material, such as a metal, a metal alloy, or polysilicon. To name just a few examples, the gate electrode may be deposited using electroplating, chemical plating, CVD, ALD, PECVD, or PVD.

[0096] According to some embodiments, a contact is also formed on the source or drain region. The contact may include any suitable conductive material, such as tungsten, molybdenum, ruthenium, or cobalt. Prior to forming the contact in the recessed area, the dielectric fill on the source or drain region may be recessed to expose the source or drain region. The contact may include any number of different conductive materials and may extend over the top surface of any number of source or drain regions within the source / drain trench.

[0097] Method 1900 continues with operation 1914, where the substrate and sub-fins are replaced from the back side with one or more dielectric layers. Once all front side processes have been performed across the integrated circuit, the substrate may be removed by any arrangement of grinding, polishing, and / or chemical etching processes. In accordance with some embodiments, all material is removed from the back side until at least the bottom surface of the dielectric filler between the sub-fins is exposed. In accordance with some embodiments, the exposed sub-fins are also removed from the back side and replaced with dielectric material, which may include any number of dielectric layers. Ultimately, various dielectric materials are formed on the back side of the integrated circuit, surrounding the dielectric region formed within the sub-fin recesses.

[0098] Example System

[0099] Fig. 20 2000 is an example computing system implemented with one or more integrated circuit structures disclosed herein according to some embodiments of the present disclosure. It can be seen that the computing system 2000 houses a motherboard 2002. The motherboard 2002 may include a plurality of components, including but not limited to a processor 2004 and at least one communication chip 2006, each of which may be physically and electrically coupled to the motherboard 2002, or otherwise integrated therein. As will be appreciated, the motherboard 2002 may be, for example, any printed circuit board (PCB), whether a motherboard, a daughterboard mounted on a motherboard, or a sole board of the system 2000, etc.

[0100] Depending on its application, the computing system 2000 may include one or more other components that may or may not be physically or electrically coupled to the motherboard 2002. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptographic processor, a chipset, an antenna, a display, a touch screen display, a touch screen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (e.g., a hard drive, a compact disk (CD), a digital versatile disk (DVD), etc.). Any component included in the computing system 2000 may include one or more integrated circuit structures or devices configured according to example embodiments (e.g., a module including an integrated circuit device on a substrate having one or more semiconductor devices including a dielectric material in a cavity below a source or drain region, as variously provided herein). In some embodiments, multiple functions may be integrated into one or more chips (eg, by way of example, note that communication chip 2006 may be part of or otherwise integrated into processor 2004).

[0101] The communication chip 2006 enables wireless communication for transmitting data to and from the computing system 2000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which can transmit data via non-solid media using modulated electromagnetic radiation. The term does not imply that the associated device does not contain any lines, although in some embodiments they may not contain any lines. The communication chip 2006 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols designated as 3G, 4G, 5G and higher levels. The computing system 2000 can include multiple communication chips 2006. For example, the first communication chip 2006 may be dedicated to short-range wireless communications such as Wi-Fi and Bluetooth, and the second communication chip 2006 may be dedicated to long-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0102] The processor 2004 of the computing system 2000 includes an integrated circuit die packaged within the processor 2004. In some embodiments, the integrated circuit die of the processor includes on-board circuits implemented with one or more semiconductor devices as variously described herein. The term "processor" may refer to any device or portion of a device that processes electronic data, such as from registers and / or memory, to transform the electronic data into other electronic data that may be stored in registers and / or memory.

[0103] The communication chip 2006 may also include an integrated circuit die packaged within the communication chip 2006. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as variously described herein. As will be understood in light of the present disclosure, note that multi-standard wireless capabilities may be integrated directly into the processor 2004 (e.g., where the functionality of any chip 2006 is integrated into the processor 2004, rather than having a separate communication chip). Further note that the processor 2004 may be a chipset with such wireless capabilities. In short, any number of processors 2004 and / or communication chips 2006 may be used. Likewise, any one chip or chipset may have multiple functions integrated therein.

[0104] In various implementations, the computing system 2000 may be a laptop computer, a netbook, a notebook, a smart phone, a tablet computer, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, a digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the disclosed techniques (as variously described herein).

[0105] It will be appreciated that in some embodiments, the various components of computing system 2000 may be combined or integrated in a system-on-chip (SoC) architecture. In some embodiments, a component may be a hardware component, a firmware component, a software component, or any suitable combination of hardware, firmware, or software.

[0106] Further example embodiments

[0107] The following examples relate to further embodiments, from which numerous permutations and configurations will be apparent.

[0108] Example 1 is an integrated circuit comprising: a semiconductor device having one or more semiconductor bodies extending from a source or drain region in a first direction and a gate structure extending on the one or more semiconductor bodies in a second direction different from the first direction; a dielectric layer under the gate structure; and a dielectric filler under the source or drain region. A top surface of the dielectric filler is above a top surface of the dielectric layer.

[0109] Example 2 includes the integrated circuit of Example 1, wherein the one or more semiconductor bodies are nanoribbons, nanosheets, or nanowires comprising germanium, silicon, or any combination thereof.

[0110] Example 3 includes the integrated circuit of Example 2, wherein a top surface of the dielectric fill is lower than a bottom surface of the bottommost nanoribbon, nanosheet, or nanowire.

[0111] Example 4 includes the integrated circuit of any of Examples 1-3, wherein the dielectric layer is a first dielectric layer, and the integrated circuit further includes a second dielectric layer below the dielectric filler, such that the second dielectric layer is between the dielectric filler and the first dielectric layer.

[0112] Example 5 includes the integrated circuit of Example 4, wherein the dielectric fill includes silicon and oxygen, and the second dielectric layer includes silicon and nitrogen.

[0113] Example 6 includes the integrated circuit of any of Examples 1-5, further comprising a silicide layer including silicon and titanium on a top surface of the source or drain region.

[0114] Example 7 includes the integrated circuit of any of Examples 1-6, wherein the dielectric filler extends through at least a portion of a total thickness of the dielectric layer in the third direction.

[0115] Example 8 includes the integrated circuit of any of Examples 1-7, wherein the dielectric fill contacts a lower portion of the gate structure.

[0116] Example 9 includes the integrated circuit of any of Examples 1-8, wherein the first direction is orthogonal to the second direction.

[0117] Example 10 includes the integrated circuit of any of Examples 1-9, wherein the gate structure includes a gate dielectric and a gate electrode on the gate dielectric.

[0118] Example 11 includes the integrated circuit of any of Examples 1-10, wherein a top surface of the dielectric fill contacts a bottom surface of the source or drain region.

[0119] Example 12 is a printed circuit board including the integrated circuit of any one of Examples 1-11,

[0120] Example 13 is an electronic device comprising a chip package, the chip package comprising one or more tube cores. At least one of the one or more tube cores comprises: a semiconductor device having one or more semiconductor bodies extending from a source or drain region in a first direction and a gate structure extending on the one or more semiconductor bodies in a second direction different from the first direction; a dielectric layer under the gate structure; and a dielectric filler under the source or drain region. The top surface of the dielectric filler contacts the bottom surface of the source or drain region, and the top surface of the dielectric filler is above the top surface of the dielectric layer.

[0121] Example 14 includes the electronic device of Example 13, wherein the one or more semiconductor bodies are nanoribbons, nanosheets, or nanowires comprising germanium, silicon, or any combination thereof.

[0122] Example 15 includes the electronic device of Example 14, wherein a top surface of the dielectric filler is lower than a bottom surface of the bottommost nanoribbon, nanosheet, or nanowire.

[0123] Example 16 includes the electronic device of any of Examples 13-15, wherein the dielectric layer is a first dielectric layer, and at least one of the one or more dies further includes a second dielectric layer below the dielectric filler, such that the second dielectric layer is between the dielectric filler and the first dielectric layer.

[0124] Example 17 includes the electronic device of Example 16, wherein the dielectric fill includes silicon and oxygen, and the second dielectric layer includes silicon and nitrogen.

[0125] Example 18 includes the electronic device of any of Examples 13-17, further comprising a silicide layer including silicon and titanium on a top surface of the source or drain region.

[0126] Example 19 includes the electronic device of any of Examples 13-18, wherein the dielectric filler extends through at least a portion of the total thickness of the dielectric layer in the third direction.

[0127] Example 20 includes the electronic device of any of Examples 13-19, wherein the dielectric fill contacts a lower portion of the gate structure.

[0128] Example 21 includes the electronic device of any of Examples 13-20, wherein the first direction is orthogonal to the second direction.

[0129] Example 22 includes the electronic device of any of Examples 13-21, wherein the gate structure includes a gate dielectric and a gate electrode on the gate dielectric, wherein the gate dielectric is on the dielectric layer.

[0130] Example 23 includes the electronic device of any of Examples 13-22, further comprising a printed circuit board, wherein the chip package is attached to the printed circuit board.

[0131] Example 24 is a method of forming an integrated circuit. The method includes: forming a multilayer fin extending in a first direction on a substrate, the substrate having a first material layer alternating with a second material layer and a sub-fin below the alternating material layer; forming a first dielectric layer adjacent to the sub-fin; forming a sacrificial gate and a spacer on the sidewall of the sacrificial gate, the sacrificial gate extending in a second direction on the multilayer fin, the second direction being different from the first direction; removing an exposed portion of the multilayer fin adjacent to the sacrificial gate and at least a portion of the sub-fin below the exposed portion of the multilayer fin so that a groove is formed in the sub-fin; forming a dielectric material in the groove so that a top surface of the dielectric material is above a top surface of the sub-fin; forming a source or drain region on the dielectric material, and the source or drain region is coupled to an end of the second material layer; removing the sacrificial gate and forming a gate structure on the first material layer; removing the sub-fin from the back side of the integrated circuit; and forming a second dielectric layer to replace the sub-fin.

[0132] Example 25 includes the method of Example 24, wherein the first material layer includes silicon and germanium, and the second material layer includes silicon.

[0133] Example 26 includes the method of Example 24 or 25, wherein forming the dielectric material includes filling the recess with the dielectric material.

[0134] Example 27 includes the method of any of Examples 24-26, wherein forming the dielectric material includes forming a dielectric liner along a sidewall of the recess.

[0135] Example 28 includes the method of Example 27, wherein forming the source or drain region includes epitaxially growing the source or drain region over the dielectric liner such that an air gap exists between the source or drain region and the dielectric liner within the recess.

[0136] Example 29 includes the method of Example 28, wherein the dielectric liner is a first dielectric liner, and the method further includes forming a second dielectric liner within the recess, the second dielectric liner being formed on the first dielectric liner and on a lower surface of the source or drain region.

[0137] Example 30 is an integrated circuit comprising: one or more semiconductor bodies extending from a source or drain region in a first direction; a gate structure extending on the one or more semiconductor bodies in a second direction different from the first direction; a dielectric layer below the gate structure; and a dielectric liner below the source or drain region. The dielectric liner is within a cavity in the dielectric layer such that an air gap exists between a bottom surface of the source or drain region and the dielectric liner within the cavity.

[0138] Example 31 includes the integrated circuit of Example 30, wherein the one or more semiconductor bodies are nanoribbons, nanosheets, or nanowires comprising germanium, silicon, or any combination thereof.

[0139] Example 32 includes the integrated circuit of Example 31, wherein the entire dielectric liner is below the bottom surface of the bottommost nanoribbon, nanosheet, or nanowire.

[0140] Example 33 includes the integrated circuit of any of Examples 30-32, wherein the dielectric layer is a first dielectric layer, and the integrated circuit further includes a second dielectric layer below the dielectric liner, such that the second dielectric layer is between the dielectric liner and the first dielectric layer.

[0141] Example 34 includes the integrated circuit of any of Examples 30-33, wherein the dielectric liner includes aluminum and oxygen, and the dielectric layer includes silicon and oxygen.

[0142] Example 35 includes the integrated circuit of any of Examples 30-34, wherein the dielectric liner extends to a height at least above a top surface of the dielectric layer.

[0143] Example 36 includes the integrated circuit of any of Examples 30-35, wherein the dielectric liner is a first dielectric liner, and the integrated circuit further comprises a second dielectric liner on the first dielectric liner and on a bottom surface of the source or drain region within the cavity.

[0144] Example 37 includes the integrated circuit of Example 36, wherein the second dielectric liner includes silicon and nitrogen.

[0145] Example 38 includes the integrated circuit of any of Examples 30-37, wherein the first direction is orthogonal to the second direction.

[0146] Example 39 includes the integrated circuit of any of Examples 30-38, wherein the gate structure includes a gate dielectric and a gate electrode on the gate dielectric, wherein the gate dielectric is on the dielectric layer.

[0147] Example 40 is a printed circuit board including the integrated circuit of any one of Examples 30-39.

[0148] The foregoing description of the embodiments of the present disclosure has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present disclosure to the precise form disclosed. Many modifications and variations are possible in light of the present disclosure. It is intended that the scope of the present disclosure is not limited by this detailed description, but rather by the appended claims.

Claims

1. An integrated circuit, comprising: A semiconductor device having one or more semiconductor bodies extending from a source or drain region in a first direction, and a gate structure extending over the one or more semiconductor bodies in a second direction different from the first direction; a dielectric layer beneath the gate structure; as well as A dielectric filler below the source or drain region such that a top surface of the dielectric filler is above a top surface of the dielectric layer. 2 . The integrated circuit of claim 1 , wherein the one or more semiconductor bodies are nanoribbons, nanosheets, or nanowires comprising germanium, silicon, or any combination thereof.

3. The integrated circuit of claim 2, wherein a top surface of the dielectric filler is lower than a bottom surface of the bottommost nanoribbon, nanosheet or nanowire.

4. The integrated circuit of claim 1, wherein the dielectric layer is a first dielectric layer, and the integrated circuit further comprises a second dielectric layer below the dielectric filler, such that the second dielectric layer is between the dielectric filler and the first dielectric layer.

5. The integrated circuit of claim 4, wherein the dielectric fill comprises silicon and oxygen, and the second dielectric layer comprises silicon and nitrogen. 6 . The integrated circuit of claim 1 , further comprising a silicide layer including silicon and titanium on a top surface of the source or drain region.

7. An integrated circuit as claimed in any one of claims 1 to 6, wherein the dielectric filler extends through at least a portion of the total thickness of the dielectric layer in the third direction.

8. The integrated circuit of any one of claims 1 to 6, wherein the dielectric filler contacts a lower portion of the gate structure.

9. The integrated circuit of any one of claims 1 to 6, wherein the first direction is orthogonal to the second direction.

10. The integrated circuit of any one of claims 1 to 6, wherein the gate structure comprises a gate dielectric and a gate electrode on the gate dielectric.

11. An integrated circuit as claimed in any one of claims 1 to 6, wherein a top surface of the dielectric filler contacts a bottom surface of the source or drain region.

12. A printed circuit board comprising the integrated circuit according to any one of claims 1 to 6.

13. An electronic device comprising: A chip package, comprising one or more dies, at least one of the one or more dies comprising: A semiconductor device having one or more semiconductor bodies extending from a source or drain region in a first direction, and a gate structure extending over the one or more semiconductor bodies in a second direction different from the first direction; a dielectric layer beneath the gate structure; and A dielectric filler is provided below the source or drain region such that a top surface of the dielectric filler contacts a bottom surface of the source or drain region and a top surface of the dielectric filler is above a top surface of the dielectric layer.

14. The electronic device of claim 13, wherein the one or more semiconductor bodies are nanoribbons, nanosheets, or nanowires comprising germanium, silicon, or any combination thereof.

15. The electronic device of claim 14, wherein a top surface of the dielectric filler is lower than a bottom surface of the bottommost nanoribbon, nanosheet or nanowire.

16. The electronic device of any one of claims 13 to 15, wherein the dielectric layer is a first dielectric layer, and at least one of the one or more dies further comprises a second dielectric layer below the dielectric filler, such that the second dielectric layer is between the dielectric filler and the first dielectric layer.

17. The electronic device of claim 16, wherein the dielectric filler comprises silicon and oxygen, and the second dielectric layer comprises silicon and nitrogen.

18. The electronic device of any one of claims 13 to 15, wherein the dielectric filler contacts a lower portion of the gate structure.

19. An integrated circuit comprising: one or more semiconductor bodies extending from the source or drain region in a first direction; a gate structure extending over the one or more semiconductor bodies in a second direction different from the first direction; a dielectric layer beneath the gate structure; as well as A dielectric liner is disposed below the source or drain region, the dielectric liner being within a cavity in the dielectric layer such that an air gap exists between a bottom surface of the source or drain region and the dielectric liner within the cavity.

20. The integrated circuit of claim 19, wherein the one or more semiconductor bodies are nanoribbons, nanosheets, or nanowires comprising germanium, silicon, or any combination thereof.

21. The integrated circuit of claim 20, wherein the entire dielectric liner is below the bottom surface of the bottommost nanoribbon, nanosheet or nanowire.

22. The integrated circuit of any one of claims 19 to 21, wherein the dielectric layer is a first dielectric layer, and the integrated circuit further comprises a second dielectric layer below the dielectric liner, such that the second dielectric layer is between the dielectric liner and the first dielectric layer.

23. An integrated circuit as claimed in any one of claims 19 to 21, wherein the dielectric liner extends to a height at least above a top surface of the dielectric layer.

24. The integrated circuit of any one of claims 19 to 21, wherein the dielectric liner is a first dielectric liner, and the integrated circuit further comprises a second dielectric liner on the first dielectric liner and on a bottom surface of the source or drain region within the cavity.

25. An integrated circuit as claimed in any one of claims 19 to 21, wherein the gate structure comprises a gate dielectric and a gate electrode on the gate dielectric, wherein the gate dielectric is on the dielectric layer.

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