Semiconductor device, semiconductor device preparation method and display panel
By setting a low crystallinity first crystallinity region between the drain region and the channel region of the semiconductor device, and limiting its position by overlapping the edge orthoprojection, the problems of leakage current and reliability of the existing semiconductor devices are solved, and higher performance is achieved.
Patent Information
- Application Number
- CN202411911870.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-03-28
AI Technical Summary
There is room for improvement in the performance of existing semiconductor devices, especially in terms of leakage current and reliability.
The position of the first crystallinity region is limited by setting a low crystallinity between the drain region and the channel region of the semiconductor device, and by defining the orthoprojection overlap of the first edge and the second edge. This structure is similar to a light doped structure at the drain end (LDD structure) to reduce the leakage current in the drain region.
The first crystallinity region with low crystallinity can effectively reduce the leakage current of the leakage region, enhance the reliability of the semiconductor device, and improve its operating performance.
Smart Images
Figure CN119730385A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of electronic products, and in particular, relates to a semiconductor device, a method for preparing a semiconductor device, and a display panel. Background Art
[0002] Organic Light Emitting Diode (OLED) and flat display panels based on technologies such as Light Emitting Diode (LED) are widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc. due to their advantages such as high image quality, power saving, thin body and wide application range, becoming the mainstream in display panels.
[0003] Currently, major display panels all include array substrates, which usually include semiconductor devices for driving the display panel and determining its display performance. However, the performance of existing semiconductor devices needs to be improved.
[0004] Therefore, there is an urgent need for a new semiconductor device, a method for preparing a semiconductor device, and a display panel. Summary of the invention
[0005] The embodiments of the present application provide a semiconductor device, a method for preparing a semiconductor device, and a display panel. By limiting the orthographic projection of a first edge on a first substrate and the orthographic projection of a second edge on the first substrate to at least partially overlap, the position of a first crystallinity region formed is limited between a drain region and a channel region. The first crystallinity region with low crystallinity can play a role similar to a lightly doped structure at the drain end, thereby reducing the leakage current at the drain end, enhancing the reliability of the semiconductor device, and improving the performance of the semiconductor device.
[0006] On the one hand, an embodiment of the present application provides a semiconductor device, comprising: a first substrate; a light-shielding layer, arranged on one side of the first substrate, the light-shielding layer comprising a first edge; a semiconductor layer, arranged on a side of the light-shielding layer away from the first substrate, the semiconductor layer comprising a channel region and a source region and a drain region respectively arranged on both sides of the channel region, the semiconductor layer further comprising a first crystallinity region arranged between the drain region and the channel region, the crystallinity of the semiconductor layer in the first crystallinity region being lower than the crystallinity of the semiconductor layer in the channel region; a gate layer, arranged on a side of the semiconductor layer away from the first substrate, the gate layer comprising a second edge, in a direction perpendicular to the plane where the first substrate is located, the orthographic projections of the first edge and the second edge on the semiconductor layer both at least partially fall within the first crystallinity region, and the orthographic projection of the first edge on the first substrate and the orthographic projection of the second edge on the first substrate at least partially overlap.
[0007] According to one aspect of the present application, along a direction parallel to the first substrate, the light-shielding layer includes a third edge arranged opposite to the first edge, and the gate layer includes a fourth edge arranged opposite to the second edge, and along a direction perpendicular to the plane where the first substrate is located, the orthographic projection of the third edge on the first substrate and the orthographic projection of the fourth edge on the first substrate at least partially overlap; preferably, along a direction perpendicular to the plane where the first substrate is located, the orthographic projection of the third edge on the first substrate and the orthographic projection of the fourth edge on the first substrate overlap.
[0008] According to one aspect of the present application, it also includes a second crystallinity region, which is arranged between the source region and the channel region, and the crystallinity of the semiconductor layer in the second crystallinity region is lower than the crystallinity of the semiconductor layer in the channel region.
[0009] According to one aspect of the present application, along a first direction, an extension length of the gate layer is greater than an extension length of the source region and the drain region, and the first direction is parallel to a plane where the first substrate is located.
[0010] According to one aspect of the present application, in a direction perpendicular to the plane where the first substrate is located, the orthographic projection of the light shielding layer on the semiconductor layer at least covers the channel region.
[0011] According to one aspect of the present application, the light shielding layer includes a first side surface, an angle between an extension direction of the first side surface and a direction of a plane where the first substrate is located is an acute angle, and the first side surface includes the first edge.
[0012] According to one aspect of the present application, the light shielding layer includes a metal material.
[0013] On the other hand, an embodiment of the present application provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device in any of the above embodiments, comprising the following steps: providing a first substrate, forming a light shielding layer on one side of the first substrate, the light shielding layer comprising a first edge; forming a semiconductor material layer on the side of the light shielding layer away from the first substrate, and crystallizing the semiconductor material layer to form a polycrystalline silicon semiconductor material layer, the polycrystalline silicon semiconductor material layer comprising a first crystallinity region; forming a gate layer on the side of the polycrystalline silicon semiconductor material layer away from the first substrate, the gate layer comprising a second edge, in a direction perpendicular to the plane where the first substrate is located, the orthographic projection of the second edge on the semiconductor layer at least partially falls within the first crystallinity region, and the orthographic projection of the first edge on the first substrate and the orthographic projection of the second edge on the first substrate at least partially overlap; using the gate layer as a shield, doping the polycrystalline silicon semiconductor material layer to form a semiconductor layer, the semiconductor layer comprising a channel region and a source region and a drain region respectively arranged on both sides of the channel region, the first crystallinity region being arranged between the drain region and the channel region, and the crystallinity of the semiconductor layer in the first crystallinity region being lower than the crystallinity of the semiconductor layer in the channel region.
[0014] According to another aspect of the present application, the step of crystallizing the semiconductor material layer to form a polycrystalline silicon semiconductor material layer includes: irradiating the semiconductor material layer with a laser to form a polycrystalline silicon semiconductor material layer.
[0015] Another aspect of the present invention provides a display panel, comprising the semiconductor device in any one of the above embodiments.
[0016] Compared with the prior art, the semiconductor device provided in the embodiment of the present invention includes a first substrate, a light shielding layer, a semiconductor layer and a gate layer. In the present embodiment, the semiconductor layer also includes a first crystallinity region arranged between the drain region and the channel region. The crystallinity of the semiconductor layer in the first crystallinity region is lower than that in the channel region, and the orthographic projections of the first edge and the second edge on the semiconductor layer at least partially fall within the first crystallinity region. The reason for forming the first crystallinity region is that during preparation, it is necessary to form a light shielding layer first and then form a semiconductor layer. The light shielding layer has a certain thickness, and the position of the first edge of the light shielding layer corresponding to the semiconductor layer will be uneven (because the amplitude of the unevenness is relatively small, the unevenness is not clearly shown in the figure), resulting in the semiconductor layer being uneven during the crystallization process. The crystallinity of the uneven position corresponding to the edge is low, and during preparation, the gate layer can be used as a shield to dope the semiconductor layer to form a channel region at the position corresponding to the gate layer, and the source region and the drain region are formed on both sides of the channel region that are not shielded by the gate layer, that is, the second edge of the gate layer will affect the formation position of the channel region and the drain region, and the position of the first crystallinity region formed is limited to between the drain region and the channel region by limiting the orthographic projection of the first edge on the first substrate and the orthographic projection of the second edge on the first substrate to at least partially overlap, and the inventors have found that the first crystallinity region with low crystallinity can play a role similar to the LDD structure (drain-end lightly doped structure), which can reduce the leakage current in the drain region, enhance the reliability of the semiconductor device, and improve the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0018] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;
[0019] Figure 2 is a top view of a semiconductor device provided by an embodiment of the present invention;
[0020] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;
[0021] Figure 4 is a top view of another semiconductor device provided by an embodiment of the present invention;
[0022] Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;
[0023] Figure 6 is a top view of another semiconductor device provided by an embodiment of the present invention;
[0024] Figure 7 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;
[0025] Figure 8 is a cross-sectional schematic diagram of a structure obtained in step S110 in a method for preparing a semiconductor device provided by an embodiment of the present invention;
[0026] Fig. 9 is a cross-sectional schematic diagram of a structure obtained in step S120 in a method for preparing a semiconductor device provided by an embodiment of the present invention;
[0027] Fig.10 It is a schematic cross-sectional view of a structure obtained in step S130 in a method for preparing a semiconductor device provided in an embodiment of the present invention.
[0028] In the attached figure:
[0029] 1-first substrate; 2-light-shielding layer; 3-semiconductor layer; 31-polycrystalline silicon semiconductor material layer; 4-insulating layer; 5-second substrate layer; 6-buffer layer; B1-first edge; B2-second edge; B3-third edge; B4-fourth edge; S-source region; D-drain region; Y-channel region; G-gate layer; J1-first crystallinity region; J2-second crystallinity region; X-first direction. DETAILED DESCRIPTION
[0030] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.
[0031] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0032] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.
[0033] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.
[0034] The present application provides a semiconductor device, a method for manufacturing a semiconductor device and a display panel. Figures 1 to 10 Various embodiments of a semiconductor device, a method for manufacturing a semiconductor device, and a display panel are described.
[0035] See also Figure 1 to Figure 2A semiconductor device provided in an embodiment of the present application includes: a first substrate 1; a light shielding layer 2, which is arranged on one side of the first substrate 1, and the light shielding layer 2 includes a first edge B1; a semiconductor layer 3, which is arranged on the side of the light shielding layer 2 away from the first substrate 1, and the semiconductor layer 3 includes a channel region Y and a source region S and a drain region D respectively arranged on both sides of the channel region Y, and the semiconductor layer 3 also includes a first crystallinity region J1 arranged between the drain region D and the channel region Y, and the crystallinity of the semiconductor layer 3 in the first crystallinity region J1 is lower than the crystallinity of the semiconductor layer 3 in the channel region Y; a gate layer G, which is arranged on the side of the semiconductor layer 3 away from the first substrate 1, and the gate layer G includes a second edge B2, and in a direction perpendicular to the plane where the first substrate 1 is located, the orthographic projections of the first edge B1 and the second edge B2 on the semiconductor layer 3 both at least partially fall within the first crystallinity region J1, and the orthographic projection of the first edge B1 on the first substrate 1 and the orthographic projection of the second edge B2 on the first substrate 1 at least partially overlap.
[0036] The semiconductor device provided by the embodiment of the present invention includes a first substrate 1, a light shielding layer 2, a semiconductor layer 3 and a gate layer G. In the present embodiment, the semiconductor layer 3 also includes a first crystallinity region J1 arranged between the drain region D and the channel region Y. The crystallinity of the semiconductor layer 3 in the first crystallinity region J1 is lower than that of the semiconductor layer 3 in the channel region Y, and the orthographic projections of the first edge B1 and the second edge B2 on the semiconductor layer 3 at least partially fall within the first crystallinity region J1. The reason for forming the first crystallinity region J1 is that during preparation, it is necessary to form the light shielding layer 2 first and then form the semiconductor layer 3. The light shielding layer 2 has a certain thickness, and the position of the first edge B1 of the light shielding layer 2 corresponding to the semiconductor layer 3 will have unevenness (because the amplitude of the unevenness is relatively small, the unevenness is not clearly shown in the figure), resulting in the semiconductor layer 3 being uneven on the first edge during the crystallization process. The uneven position corresponding to the edge B1 has a lower crystallinity. During preparation, the gate layer G can be used as a shield to dope the semiconductor layer 3 to form a channel region Y at the position corresponding to the gate layer G, and a source region S and a drain region D are formed on both sides of the channel region Y that are not shielded by the gate layer G. That is, the second edge B2 of the gate layer G will affect the formation position of the channel region Y and the drain region D. By limiting the orthographic projection of the first edge B1 on the first substrate 1 and the orthographic projection of the second edge B2 on the first substrate 1 to at least partially overlap, the position of the formed first crystallinity region J1 is limited to between the drain region D and the channel region Y. The inventors have found that the low-crystallinity first crystallinity region J1 can play a role similar to the LDD structure (drain-end lightly doped structure), which can reduce the leakage current of the drain region D, enhance the reliability of the semiconductor device, and improve the performance of the semiconductor device.
[0037] Among them, the LDD structure is to set a low-doped drain region D near the drain in the channel, so that the low-doped drain region D also bears part of the voltage and reduces the high electric field at the drain end. Therefore, this structure can prevent the hot electron degradation effect.
[0038] It should be noted that, in this embodiment, the semiconductor material for preparing the semiconductor layer 3 needs to be crystallized and transformed into a polysilicon material under laser irradiation, and due to the influence of the first edge B1 of the light shielding layer 2, the corresponding position of the semiconductor material will be uneven, thereby affecting the irradiation effect of the laser, and thus making the crystallinity of this part lower than that of other parts of the semiconductor material, and the crystallinity of the semiconductor layer 3 in the first crystallinity region J1 finally formed is lower than that of the semiconductor layer 3 in the channel region Y. The inventors have found through research that when the first crystallinity region J1 is provided between the drain region D and the channel region Y, it can play a role similar to the LDD structure, reduce the drain leakage current, and enhance the reliability of the semiconductor device.
[0039] In this embodiment, the first edge B1 and the second edge B2 can be understood as the edge of one side of the light shielding layer 2 and the gate layer G close to the drain region D. Compared with the semiconductor device in the prior art, the embodiment of the present invention can increase the size and area of the gate layer G so that the orthographic projection of the second edge B2 of the gate layer G on the first substrate 1 coincides with the orthographic projection of the first edge B1 on the first substrate 1 and the orthographic projection of the second edge B2 on the first substrate 1.
[0040] Optionally, along the first direction X, the extension length of the gate layer G is greater than the extension lengths of the source region S and the drain region D, and the first direction X is parallel to the plane where the first substrate 1 is located.
[0041] like Figure 1 and Figure 2 As shown, in the above embodiment, the extension length of the gate layer G along the first direction X can be increased so that the orthographic projection of the first edge B1 on the first substrate 1 and the orthographic projection of the second edge B2 on the first substrate 1 at least partially overlap. At the same time, by limiting the extension length of the gate layer G to be greater than the extension lengths of the source region S and the drain region D, it can also be ensured that the performance of the semiconductor meets the requirements.
[0042] Or, if Figure 3 and Figure 4 As shown, the size and area of the light-shielding layer 2 can be reduced so that the light-shielding layer 2 shrinks relative to the semiconductor layer 3, and the first edge B1 moves inward toward the channel region Y, so that the orthographic projection of the second edge B2 of the gate layer G on the first substrate 1 coincides with the orthographic projection of the first edge B1 on the first substrate 1 and the orthographic projection of the second edge B2 on the first substrate 1.
[0043] In this embodiment, the semiconductor device can adopt a single-layer substrate structure, that is, the semiconductor device only includes a first substrate 1, or the semiconductor device can also adopt a double-layer substrate structure, that is, the semiconductor device also includes an insulating layer 4, a second substrate layer 5 and a buffer layer 6 arranged on one side of the first substrate 1, and the shading layer 2 can be arranged between any two adjacent layers of the first substrate 1, the insulating layer 4, the second substrate layer 5 and the buffer layer 6, or the shading layer 2 can also be formed inside the second substrate layer 5, without special limitation.
[0044] See also Figures 5 and 6 In some optional embodiments, along a direction parallel to the first substrate 1, the light shielding layer 2 includes a third edge B3 arranged opposite to the first edge B1, and the gate layer G includes a fourth edge B4 arranged opposite to the second edge B2, and along a direction perpendicular to the plane where the first substrate 1 is located, the orthographic projection of the third edge B3 on the first substrate 1 and the orthographic projection of the fourth edge B4 on the first substrate 1 at least partially overlap.
[0045] In this embodiment, compared with the semiconductor device in the prior art, the first edge B1 and the third edge B3 of the light-shielding layer 2 can be retracted relative to the semiconductor layer 3, while the size of the gate layer G remains unchanged, so that in the direction perpendicular to the plane where the first substrate 1 is located, the orthographic projection of the third edge B3 on the first substrate 1 and the orthographic projection of the fourth edge B4 on the first substrate 1 at least partially overlap, so as to form a symmetrical structure of the source and drain ends, thereby improving the symmetry of the semiconductor device and facilitating preparation.
[0046] Optionally, in a direction perpendicular to the plane where the first substrate 1 is located, the orthographic projection of the third edge B3 on the first substrate 1 and the orthographic projection of the fourth edge B4 on the first substrate 1 coincide with each other, thereby improving the symmetry of the semiconductor layer 3 .
[0047] It can be understood that when the orthographic projection of the third edge B3 on the first substrate 1 and the orthographic projection of the fourth edge B4 on the first substrate 1 are limited to at least partially overlap, a low crystallinity region can be formed correspondingly between the source region S and the channel region Y. Optionally, the semiconductor device also includes a second crystallinity region J2, which is arranged between the source region S and the channel region Y, and the crystallinity of the semiconductor layer 3 in the second crystallinity region J2 is lower than the crystallinity of the semiconductor layer 3 in the channel region Y.
[0048] In the present embodiment, the second crystallinity region J2 may be formed between the source region S and the channel region Y to adjust the performance of the semiconductor device so that the performance of the semiconductor device meets the requirements.
[0049] In some optional embodiments, the orthographic projection of the light shielding layer 2 on the semiconductor layer 3 at least covers the channel region Y in a direction perpendicular to the plane where the first substrate 1 is located.
[0050] In this embodiment, the light shielding layer 2 can be used to shield the light from one side of the first substrate 1 to prevent external light from irradiating the channel region Y and affecting the electrical performance of the channel region Y, thereby improving the reliability of the semiconductor device.
[0051] Optionally, the light shielding layer 2 can be made of a material with good light shielding property, such as metal, ink, etc. For example, the light shielding layer 2 can be made of a metal material, such as copper, aluminum, titanium, etc., and the preparation process is simple and convenient.
[0052] In some optional embodiments, the light shielding layer 2 includes a first side surface, an angle between an extension direction of the first side surface and a direction of a plane where the first substrate 1 is located is an acute angle, and the first side surface includes a first edge B1.
[0053] In this embodiment, since the light-shielding layer 2 is usually prepared by a process such as evaporation, a slope angle is formed on the side of the light-shielding layer 2, that is, the angle between the extension direction of the first side and the direction of the plane where the first substrate 1 is located is an acute angle, and the specific angle is determined by the process. The existence of this inclined surface will cause the corresponding position of the semiconductor layer 3 located above to form a non-flat portion. In the crystallization process, this non-flat portion corresponds to the formation of a first crystallinity area J1 with low crystallinity.
[0054] The first edge B1 may be an outer edge of an orthographic projection of the first side surface on the first substrate 1 .
[0055] See also Figure 7 The present invention also provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device in any of the above embodiments, comprising the following steps:
[0056] S110: Provide a first substrate 1, and form a light shielding layer 2 on one side of the first substrate 1, wherein the light shielding layer 2 includes a first edge B1, such as Figure 8 As shown;
[0057] S120: forming a semiconductor material layer on the side of the light shielding layer 2 away from the first substrate 1, and performing crystallization treatment on the semiconductor material layer to form a polycrystalline silicon semiconductor material layer 31, wherein the polycrystalline silicon semiconductor material layer 31 includes a first crystallinity region J1, such as Fig. 9 As shown;
[0058] S130: forming a gate layer G on the side of the polycrystalline silicon semiconductor material layer 31 away from the first substrate 1, the gate layer G comprising a second edge B2, in a direction perpendicular to the plane where the first substrate 1 is located, the orthographic projection of the second edge B2 on the semiconductor layer 3 at least partially falls within the first crystallinity region J1, the orthographic projection of the first edge B1 on the first substrate 1 and the orthographic projection of the second edge B2 on the first substrate 1 at least partially overlap, such as Fig.10 As shown;
[0059] S140: With the gate layer G as a shield, the polysilicon semiconductor material layer 31 is doped to form a semiconductor layer 3, wherein the semiconductor layer 3 includes a channel region Y and a source region S and a drain region D respectively disposed on both sides of the channel region Y, a first crystallinity region J1 is disposed between the drain region D and the channel region Y, and the crystallinity of the semiconductor layer 3 in the first crystallinity region J1 is lower than the crystallinity of the semiconductor layer 3 in the channel region Y, such as Figure 1 shown.
[0060] In the semiconductor device preparation method provided by the embodiment of the present invention, during preparation, it is necessary to first form a light shielding layer 2 and then form a semiconductor material layer. The light shielding layer 2 has a certain thickness, and the position of the semiconductor material layer corresponding to the first edge B1 thereof will be uneven, resulting in that during the crystallization process of the semiconductor material layer, the crystallinity of the uneven position corresponding to the first edge B1 is low. During preparation, the gate layer G can be used as a shield to perform doping treatment on the polycrystalline silicon semiconductor material layer 31, and a channel region Y is formed at the position corresponding to the gate layer G, and the portions on both sides of the channel region Y that are not shielded by the gate layer G are The source region S and the drain region D are formed separately, that is, the second edge B2 of the gate layer G will affect the formation position of the channel region Y and the drain region D. By limiting the orthographic projection of the first edge B1 on the first substrate 1 and the orthographic projection of the second edge B2 on the first substrate 1 to at least partially overlap, the position of the formed first crystallinity region J1 is limited to between the drain region D and the channel region Y. The inventors have found through research that the first crystallinity region J1 with low crystallinity can play a role similar to the LDD structure (lightly doped structure at the drain end), which can reduce the drain leakage current, enhance the reliability of the semiconductor device, and improve the performance of the semiconductor device.
[0061] In step S110, the first substrate 1 can be a hard substrate, such as a glass substrate; or a flexible substrate, and its material can be polyimide, polystyrene, polyethylene terephthalate, polyparaxylene, polyethersulfone or polyethylene naphthalate. The substrate is mainly used to support the device disposed thereon. The light shielding layer 2 can be made of metal material and formed by an evaporation process.
[0062] In step S120, the semiconductor material layer includes an amorphous silicon material, and the semiconductor material layer can be irradiated with a laser to form a polycrystalline silicon semiconductor material layer 31. Due to the influence of the first edge B1 of the light shielding layer 2, the corresponding position of the semiconductor material layer is uneven, which in turn affects the irradiation effect of the laser, and thus makes the crystallinity of this part lower than that of other parts of the semiconductor material. The crystallinity of the semiconductor layer 3 in the finally formed first crystallinity region J1 is lower than that of the semiconductor layer 3 in the channel region Y.
[0063] In step S130, the gate layer G can be made of metal material and formed by an evaporation process, and the size of the gate layer G or the light shielding layer 2 is limited so that the orthographic projection of the first edge B1 on the first substrate 1 and the orthographic projection of the second edge B2 on the first substrate 1 at least partially overlap.
[0064] In step S140, the gate layer G can play a role similar to that of a mask plate to block ions from the back side of the gate layer G of the first substrate 1 during the doping process, thereby forming a channel region Y that is not ion-implanted at the position corresponding to the gate layer G, and forming a source region S and a drain region D that are ion-implanted and have a higher doping concentration at the portions on both sides of the channel region Y that are not blocked by the gate layer G. The second edge B2 of the gate layer G will affect the formation position of the channel region Y and the drain region D. By limiting the orthographic projection of the first edge B1 on the first substrate 1 and the orthographic projection of the second edge B2 on the first substrate 1 to at least partially overlap, the position of the first crystallinity region J1 formed is limited to between the drain region D and the channel region Y.
[0065] An embodiment of the present invention further provides a display panel, comprising the semiconductor device in any one of the above embodiments.
[0066] The display panel provided by the embodiment of the present invention may be provided with semiconductor devices inside to meet display requirements.
[0067] The display panel provided by the embodiment of the present invention has the technical effect of the technical solution of the semiconductor device in any of the above embodiments, and the explanation of the structures and terms that are the same as or corresponding to the above embodiments will not be repeated here.
[0068] The above are only specific implementation methods of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.
[0069] It should also be noted that the exemplary embodiments mentioned in this application describe some methods or systems based on a series of steps or devices. However, this application is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiment, or in a different order from the embodiment, or several steps can be performed simultaneously.
Claims
1. A semiconductor device, characterized in that: include: a first substrate; A light shielding layer, disposed on one side of the first substrate, the light shielding layer comprising a first edge; A semiconductor layer is disposed on a side of the light shielding layer away from the first substrate, the semiconductor layer comprises a channel region and a source region and a drain region respectively disposed on both sides of the channel region, the semiconductor layer further comprises a first crystallinity region disposed between the drain region and the channel region, the crystallinity of the semiconductor layer in the first crystallinity region is lower than the crystallinity of the semiconductor layer in the channel region; A gate layer is arranged on the side of the semiconductor layer away from the first substrate, and the gate layer includes a second edge. In a direction perpendicular to the plane where the first substrate is located, the orthographic projections of the first edge and the second edge of the semiconductor layer at least partially fall within the first crystallinity region, and the orthographic projection of the first edge on the first substrate and the orthographic projection of the second edge on the first substrate at least partially overlap.
2. The semiconductor device according to claim 1, wherein: In a direction parallel to the first substrate, the light shielding layer includes a third edge arranged opposite to the first edge, and the gate layer includes a fourth edge arranged opposite to the second edge, and in a direction perpendicular to the plane where the first substrate is located, an orthographic projection of the third edge on the first substrate and an orthographic projection of the fourth edge on the first substrate at least partially overlap; Preferably, in a direction perpendicular to the plane where the first substrate is located, an orthographic projection of the third edge on the first substrate and an orthographic projection of the fourth edge on the first substrate coincide with each other.
3. The semiconductor device according to claim 2, characterized in that The semiconductor layer further includes a second crystallinity region, wherein the second crystallinity region is disposed between the source region and the channel region, and the crystallinity of the semiconductor layer in the second crystallinity region is lower than the crystallinity of the semiconductor layer in the channel region.
4. The semiconductor device according to claim 1, wherein: Along a first direction, an extension length of the gate layer is greater than an extension length of the source region and an extension length of the drain region, and the first direction is parallel to a plane where the first substrate is located.
5. The semiconductor device according to claim 1, wherein: In a direction perpendicular to the plane where the first substrate is located, an orthographic projection of the light shielding layer on the semiconductor layer at least covers the channel region.
6. The semiconductor device according to claim 1, wherein: The light shielding layer includes a first side surface, an extending direction of the first side surface and a direction of a plane where the first substrate is located form an acute angle, and the first side surface includes the first edge.
7. The semiconductor device according to claim 1, wherein: The light shielding layer includes a metal material.
8. A method for preparing a semiconductor device, for preparing the semiconductor device according to any one of claims 1 to 7, characterized in that: The following steps are involved: Providing a first substrate, forming a light shielding layer on one side of the first substrate, wherein the light shielding layer includes a first edge; forming a semiconductor material layer on a side of the light shielding layer away from the first substrate, and performing crystallization treatment on the semiconductor material layer to form a polycrystalline silicon semiconductor material layer, wherein the polycrystalline silicon semiconductor material layer includes a first crystallinity region; A gate layer is formed on a side of the polycrystalline silicon semiconductor material layer facing away from the first substrate, the gate layer comprises a second edge, an orthographic projection of the second edge on the semiconductor layer at least partially falls within the first crystallinity region in a direction perpendicular to the plane where the first substrate is located, and an orthographic projection of the first edge on the first substrate and an orthographic projection of the second edge on the first substrate at least partially overlap; With the gate layer as a shield, the polycrystalline silicon semiconductor material layer is doped to form a semiconductor layer, wherein the semiconductor layer includes a channel region and a source region and a drain region respectively arranged on both sides of the channel region, the first crystallinity region is arranged between the drain region and the channel region, and the crystallinity of the semiconductor layer in the first crystallinity region is lower than the crystallinity of the semiconductor layer in the channel region.
9. The method for preparing a semiconductor device according to claim 8, characterized in that: The step of performing a crystallization process on the semiconductor material layer to form a polycrystalline silicon semiconductor material layer comprises: The semiconductor material layer is irradiated with laser to form a polycrystalline silicon semiconductor material layer.
10. A display panel, characterized in that: A semiconductor device comprising any one of claims 1 to 7.