Layout structure of the chip

Abstract

The present invention discloses a layout structure of a chip, comprising: a high-voltage module, on which a plurality of first pad pins are arranged, and a high-voltage electrostatic discharge circuit is arranged around the first pad pins; a low-voltage module, on which a plurality of second pad pins are arranged, and a low-voltage electrostatic discharge circuit is arranged around the second pad pins; a power conversion circuit is further arranged around the low-voltage electrostatic discharge circuit, and the low-voltage module can be connected to a high-voltage power supply through the power conversion circuit; wherein, the first pad pins are encapsulated into the chip / the first pad pins and the second pad pins are encapsulated into the chip to connect to the high-voltage power supply and / or the low-voltage power supply to supply power to the chip. The chip structure provided by the present invention can realize multiple power supply modes, has good compatibility and low cost.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip layout, and particularly relates to a layout structure of a chip. Background Art

[0002] To meet the requirements of more power supply voltages in the market, a chip will support more power supply modes. Therefore, a metal option method is adopted in the chip to support multiple power supply modes, effectively reducing the circuit area to achieve higher integration.

[0003] To meet the multiple power supply modes of the chip, higher requirements are put forward for the Electro-Static Discharge (ESD) circuit of the chip. It is necessary to solve not only the ESD problem of the high-voltage version of the chip, but also the ESD problem of the low-voltage version of the chip. The ESD circuit in the chip is for protecting the chip from damage caused by electrostatic discharge, and the area overhead is relatively large. Especially for multi-power multi-pin chips such as Field Programmable Gate Array (FPGA), the ESD circuit area occupies a large area. The metal option method makes the chip into multiple power supply versions, such as high-voltage version and low-voltage version, and selects a certain version for tape-out according to requirements; its purpose is to reduce the area overhead of the ESD circuit. However, the chip layout differences between different power supply versions are relatively large, bringing great difficulties to the chip production and manufacturing, and increasing the production cost.

[0004] Therefore, there is currently a lack of a chip with an ESD circuit that can simultaneously achieve power supply with high-voltage power and / or low-voltage power. Summary of the Invention

[0005] An embodiment of the present invention provides a layout structure of a chip, which can solve the problem that the current chip cannot simultaneously achieve power supply with high-voltage power and / or low-voltage power on the same chip structure.

[0006] An embodiment of the present invention provides a layout structure of a chip, including:

[0007] A high-voltage module, on which a plurality of first pad pins are provided, and a high-voltage electrostatic discharge circuit is provided around the first pad pins;

[0008] A low-voltage module, on which a plurality of second pad pins are provided, and a low-voltage electrostatic discharge circuit is provided around the second pad pins; a power conversion circuit is further provided around the low-voltage electrostatic discharge circuit, and the low-voltage module is connected to a high-voltage power supply through the power conversion circuit;

[0009] Wherein, the first pad pin is encapsulated out of the chip, or the first pad pin and the second pad pin are encapsulated out of the chip, to connect to a high-voltage power supply and / or a low-voltage power supply to supply power to the chip.

[0010] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: According to the layout structure of the chip provided by the present invention, by providing an electrostatic discharge circuit at the positions where the low-voltage module and the high-voltage module are connected to an external power supply, and providing pad pins for connecting to the external power supply around the electrostatic discharge circuit, the chip can be connected to different pad pins according to different supply voltages to achieve multiple power supply modes, thereby improving the compatibility of the chip structure and reducing the chip manufacturing cost. Description of the Drawings

[0011] Figure 1 It is a schematic diagram of a layout structure of a chip provided by an embodiment of the present invention;

[0012] Figure 2 It is a schematic diagram of a specific layout structure of a chip provided by an embodiment of the present invention. Detailed Embodiments

[0013] In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present invention. However, those skilled in the art should clearly understand that the present invention can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present invention.

[0014] It should be understood that when used in the specification and claims of the present invention, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0015] It should also be understood that the term "and / or" as used in the specification and claims of the present invention refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0016] As used in the specification and claims of the present invention, the term "if" can be interpreted as "when", "once", "in response to a determination", or "in response to a detection" depending on the context. Similarly, the phrase "if a determination is made" or "if [the described condition or event] is detected" can be interpreted as meaning "once a determination is made", "in response to a determination", "once [the described condition or event] is detected", or "in response to a detection of [the described condition or event]" depending on the context.

[0017] In addition, in the description of the specification and the appended claims of the present invention, the terms "first", "second", "third", etc. are only used for differential description and cannot be construed as indicating or implying relative importance.

[0018] The reference to "one embodiment" or "some embodiments" etc. in the specification of the present invention means that a specific feature, structure or characteristic described in connection with that embodiment is included in one or more embodiments of the present invention. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear at different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0019] The present invention will be further described in detail below in conjunction with specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0020] Embodiment 1

[0021] Figure 1 Shown is a schematic diagram of the layout structure of a chip provided by an embodiment of the present invention. By way of example and not limitation, referring to Figure 1 , the chip may include a high-voltage module 1 and a low-voltage module 2.

[0022] In a possible implementation manner, referring to Figure 1 , a plurality of first pad pins P1 may be provided on the high-voltage module 1, and a high-voltage electrostatic discharge circuit E1 is provided around the first pad pins P1. Similarly, a plurality of second pad pins P2 may be provided on the low-voltage module 2, and a low-voltage electrostatic discharge circuit E2 may also be provided around the second pad pins. In addition, a power conversion circuit V2 may be provided on the low-voltage module 2, and the power conversion circuit V2 may be provided around the low-voltage electrostatic discharge circuit E2.

[0023] Specifically, the high-voltage electrostatic discharge circuit E1 may be used to protect other components in the high-voltage module 1 from electrostatic hazards. Correspondingly, the low-voltage electrostatic discharge circuit E2 may be used to protect other components in the low-voltage module 2 from electrostatic hazards, and the power conversion circuit V2 may be used to convert the input high-voltage power supply into the low-voltage power supply required by the low-voltage module 2.

[0024] Exemplarily, the high-voltage module 1 may include some components in the chip that require high-voltage power supply, the low-voltage module 2 may include some components in the chip that require low-voltage power supply, and the power conversion circuit V2 may be a low-dropout linear regulator.

[0025] Based on different power supplies, the first pad pin can be encapsulated outside the chip, or the first pad pin and the second pad pin can be encapsulated outside the chip, and the first pad pin outside the chip or the first pad pin and the second pad pin are led out of the chip and connected to the power supply. Specifically, the first pad pin can be connected to the high-voltage power supply and the low-voltage power supply, and the second pad pin can be connected to the low-voltage power supply, so as to supply power to the chip. When the power supplies are different, only different pad pins need to be encapsulated outside the chip, and there is no need to design different chip layout structures for different power supplies; it can improve the compatibility of the chip structure, thereby reducing the chip manufacturing cost.

[0026] In one example, if the chip is powered by a high-voltage power supply, the first pad pin P1 can be encapsulated outside the chip, and the first pad pin P1 is led out and connected to the high-voltage power supply.

[0027] At this time, the second pad pin P2 is idle and encapsulated inside the chip. The high-voltage power supply can supply power to the high-voltage module 1, and the power conversion circuit V2 can convert the high-voltage power supply into a low-voltage power supply to supply power to the low-voltage module 2.

[0028] In another example, if the chip is powered by a low-voltage power supply, the first pad pin P1 and the second pad pin P2 can be encapsulated outside the chip, and the first pad pin P1 and the second pad pin P2 are led out and connected to the low-voltage power supply.

[0029] Exemplarily, the first pad pin P1 and the second pad pin P2 can be connected and then connected to the low-voltage power supply. Since the operating range of the high-voltage module is relatively wide, the low-voltage power supply can directly supply power to the high-voltage module 1 and the low-voltage module 2. At this time, the connection between the high-voltage module 1 and the power conversion circuit V2 can be disconnected through metal option.

[0030] In yet another example, if the chip is powered by both a low-voltage power supply and a high-voltage power supply, the first pad pin P1 and the second pad pin P2 can be encapsulated outside the chip at the same time. The first pad pin P1 is led out and connected to the high-voltage power supply, and the second pad pin P2 is led out and connected to the low-voltage power supply.

[0031] At this time, the high-voltage power supply supplies power to the high-voltage module 1, and the low-voltage power supply supplies power to the low-voltage module 2. Similarly, the connection between the high-voltage module 1 and the power conversion circuit V2 can be disconnected through metal option.

[0032] Therefore, for the chip layout structure provided by the present invention, only different encapsulation methods need to be selected according to different power supply requirements of users, and a single chip layout structure can be used to achieve multiple power supply modes. Therefore, the chip layout structure provided by the present invention has good compatibility and can reduce the manufacturing cost of the chip.

[0033] Embodiment 2

[0034] Based on Embodiment 1, Figure 2 The figure shows a schematic diagram of a specific layout structure of a chip provided by an embodiment of the present invention.

[0035] In a possible implementation, referring to Figure 2 , in order to provide a more uniform input current, the first pad pin P1 can be evenly surrounded by the inner boundary of the high-voltage module 1. Since the purpose of setting the high-voltage electrostatic discharge circuit E1 is to protect the high-voltage module 1 from electrostatic damage, the high-voltage electrostatic discharge circuit E1 can be arranged around the first pad pin P1 for connecting the power supply. In order to better implement the circuit protection function and reduce the number of high-voltage electrostatic discharge circuits in the chip, a high-voltage electrostatic discharge circuit E1 can be arranged between every two first pad pins P1.

[0036] Similarly, the second pad pin P2 can be evenly surrounded by the outer boundary of the low-voltage module 2, and a set of low-voltage electrostatic discharge circuits E2 and a power conversion circuit V2 are arranged between every two second pad pins P2. Since the power conversion circuit V2 will supply a low-voltage power supply to the low-voltage module when the chip is powered by a high-voltage power supply, a low-voltage electrostatic discharge circuit E2 also needs to be arranged around the power conversion circuit V2.

[0037] Similarly, in order to reduce the number of low-voltage electrostatic discharge circuits E2 in the chip, the power conversion circuit V2 and the low-voltage electrostatic discharge circuit E2 can be arranged alternately.

[0038] According to the layout structure of the chip provided by the present invention, by arranging electrostatic discharge circuits at the positions where the low-voltage module and the high-voltage module are connected to the external power supply, and arranging pad pins for connecting the external power supply around the electrostatic discharge circuits, the chip can be connected to different pad pins according to different supply voltages to achieve multiple modes of power supply, thereby improving the compatibility of the chip structure and reducing the chip manufacturing cost.

[0039] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

Claims

1. A layout structure of a chip, characterized in that, Including: A high-voltage module, on which a plurality of first pad pins are provided. A high-voltage electrostatic discharge circuit is provided around the first pad pins, and the first pad pins are evenly arranged around the inner boundary of the high-voltage module; A low-voltage module, on which a plurality of second pad pins are provided. A low-voltage electrostatic discharge circuit is provided around the second pad pins, and the second pad pins are evenly arranged around the outer boundary of the low-voltage module; A power conversion circuit is further provided around the low-voltage electrostatic discharge circuit, and the low-voltage module can be connected to a high-voltage power supply through the power conversion circuit; Wherein, if the chip is powered by the high-voltage power supply, the first pad pins are encapsulated out of the chip, the high-voltage power supply is connected to the high-voltage module through the first pad pins, the second pad pins are idle, the high-voltage power supply powers the high-voltage module, and the power conversion circuit is used to convert the high-voltage power supply into a low-voltage power supply to power the low-voltage module; if the chip is powered by the low-voltage power supply, the first pad pins and the second pad pins are encapsulated out of the chip, the low-voltage power supply is connected to the high-voltage module through the first pad pins, and the low-voltage power supply is connected to the low-voltage module through the second pad pins; The low-voltage power supply powers the low-voltage module and the high-voltage module; if the chip is powered by the high-voltage power supply and the low-voltage power supply, the first pad pins and the second pad pins are encapsulated out of the chip; the high-voltage power supply is connected to the high-voltage module through the first pad pins, the low-voltage power supply is connected to the low-voltage module through the second pad pins, the high-voltage power supply powers the high-voltage module, and the low-voltage power supply powers the low-voltage module.

2. The layout structure of the chip according to claim 1, wherein A high-voltage electrostatic discharge circuit is provided between every two of the first pad pins.

3. The layout structure of the chip according to claim 1 or 2, characterized in that A set of the low-voltage electrostatic discharge circuit and the power conversion circuit is provided between every two of the second pad pins.

4. The layout structure of the chip according to claim 3, wherein The low-voltage electrostatic discharge circuit and the power conversion circuit are arranged alternately.

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