Image sensor

Abstract

An image sensor includes: pixels each including two photodiodes arranged side by side in a first direction; a deep trench isolation structure; a floating diffusion region; and a transfer gate. The deep trench isolation structure includes: an internal structure extending in a second direction perpendicular to the first direction and separating the two PDs of each pixel from each other in the first direction; and an outer structure extending in the first direction and the second direction and separating the pixels from each other in the first direction and the second direction. The floating diffusion region is disposed between a central portion of the outer structure extending in the first direction and an edge of the inner structure. The transfer gate is disposed adjacent to the floating diffusion region such that one or more transfer gates are disposed on each photodiode. For each pixel, the two photodiodes share the floating diffusion region.

Description

Technical Field

[0001] Devices and apparatuses consistent with the present disclosure relate to an image sensor, and more particularly, to an image sensor including a two-photodiode (2PD) pixel structure. Background Art

[0002] Image sensors generally have a plurality of unit pixels arranged in a two-dimensional array structure. Recently, the size of pixels has been reduced, and a shared pixel structure has been proposed. However, the shared pixel structure increases the complexity of the arrangement and leads to the disadvantage that the conversion gain and arrangement efficiency of the image sensor may be reduced. Summary of the invention

[0003] One aspect is to provide an image sensor configured to improve conversion gain (CG), increase layout efficiency and size of pixel transistors, and reduce metal wiring layers.

[0004] According to an aspect of one or more embodiments, an image sensor is provided, comprising: a plurality of pixels, each of the plurality of pixels comprising two photodiodes (PDs) arranged side by side in a first direction; a deep trench isolation (DTI) structure, the deep trench isolation structure comprising: an internal DTI structure, the internal DTI structure extending in a second direction perpendicular to the first direction and separating the two PDs of each of the plurality of pixels from each other in the first direction; and an external DTI structure, the external DTI structure extending in the first direction and the second direction and separating the plurality of pixels from each other in the first direction and the second direction; a floating diffusion (FD) region, the floating diffusion region being arranged between a central portion of the external DTI structure extending along the first direction and an edge of the internal DTI structure; and a plurality of transfer gates (TGs), the plurality of transfer gates being arranged adjacent to the FD region so that at least one of the plurality of TGs is arranged on each PD, wherein, for each of the plurality of pixels, the two PDs of the pixel share the FD region.

[0005] According to another aspect of one or more embodiments, an image sensor is provided, the image sensor comprising: a shared pixel, the shared pixel comprising four pixels, each of the four pixels comprising two photodiodes (PDs) arranged side by side in a first direction; a deep trench isolation (DTI) structure, the DTI structure comprising: an internal DTI structure, the internal DTI structure extending in a second direction perpendicular to the first direction and separating the two PDs of each of the four pixels from each other in the first direction; and an external DTI structure, the external DTI structure extending in the first direction and the second direction and separating the four pixels from each other in the first direction and the second direction; a floating diffusion (FD) region, the FD region being disposed between a central portion of the external DTI structure extending along the first direction and an edge of the internal DTI structure; a plurality of transfer gates (TGs), the plurality of TGs being disposed adjacent to the FD region so that at least one of the plurality of TGs is disposed on each PD; a reset gate (RG), the RG being disposed at an inner portion of the shared pixel in any one of the four pixels of the shared pixel; and a source follower gate (FG) configured to provide a plurality of transfer gates (TGs) disposed adjacent to the FD region so that at least one of the plurality of TGs is disposed on each PD; A gate, SF), wherein the SF is arranged at the inner portion of the shared pixel in at least one other pixel of the four pixels of the shared pixel and is adjacent to the RG, wherein the two PDs of each of the pixels share the FD region.

[0006] According to another aspect of one or more embodiments, an image sensor is provided, the image sensor comprising: a shared pixel, the shared pixel comprising four pixels, each of the four pixels comprising two photodiodes (PDs) arranged side by side in a first direction; a deep trench isolation (DTI) structure, the deep trench isolation structure comprising: an internal DTI structure, the internal DTI structure extending in a second direction perpendicular to the first direction and separating the two PDs of each of the four pixels from each other in the first direction; and an external DTI structure, the external DTI structure extending in the first direction and the second direction and separating the four PDs from each other in the first direction and the second direction. pixels are separated from each other; a floating diffusion (FD) region, the FD region is arranged between the central part of the outer DTI structure extending along the first direction and the edge of the inner DTI structure; and a plurality of transfer gates (TGs), the plurality of TGs are arranged adjacent to the FD region, so that at least one TG of the plurality of TGs is arranged on each PD; wherein each group of two pixels of the four pixels adjacent to each other in the second direction forms a sub-shared pixel, the shared pixel includes two sub-shared pixels adjacent to each other in the first direction, the FD region is arranged between two pixels of each of the sub-shared pixels, and the four PDs of each of the sub-shared pixels share the FD region of the sub-shared pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is an equivalent circuit diagram corresponding to a shared pixel of an image sensor according to an embodiment;

[0009] Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 A plan view of a shared pixel of an image sensor shown in FIG.

[0010] Figure 3A and Figure 3B 1 and 2 are diagrams respectively showing the wiring routing of the floating diffusion (FD) region and the wiring routing of the image sensor of the comparative example. Figure 1 A plan view of the wiring routing of the FD region of the image sensor shown in FIG.

[0011] Figure 4A and Figure 4B is a plan view showing a shared pixel of an image sensor according to some embodiments;

[0012] FIG. 5A to FIG. 5C1 and 2 are respectively a plan view showing a shared pixel of an image sensor according to some embodiments and a cross-sectional view showing a transfer gate of the image sensor;

[0013] Fig. 6A and Figure 6B are plan views respectively showing shared pixels of an image sensor and wiring routing of an FD region of the image sensor according to some embodiments;

[0014] Figures 7 to 11 is a plan view showing a shared pixel of an image sensor according to some embodiments;

[0015] Fig.12 is a diagram showing a method according to an embodiment of the present invention. Figure 2 A plan view of a structure in which shared pixels of an image sensor are arranged in a two-dimensional array structure;

[0016] Fig.13 is a block diagram showing an image sensor according to an embodiment;

[0017] Fig.14 is a block diagram illustrating an electronic device including an image sensor according to an embodiment. DETAILED DESCRIPTION

[0018] Aspects of the embodiments of the present disclosure are not limited to those mentioned above, and other aspects of various embodiments will be clearly understood by those skilled in the art through the following description.

[0019] Typically, each unit pixel may include a photodiode and a plurality of pixel transistors. For example, the pixel transistor may include a transfer transistor, a reset transistor, a source follower transistor, and a select transistor. Recently, the size of pixels has been reduced, and therefore, image sensors use a shared pixel structure in which a plurality of pixels share pixel transistors to relatively increase the area of ​​the photodiode. In the shared pixel structure, the pixels may be separated from each other by a deep trench isolation (DTI) structure.

[0020] Hereinafter, various embodiments will be described with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals represent the same elements, and their repeated descriptions are omitted for the sake of brevity.

[0021] Figure 1 is an equivalent circuit diagram corresponding to a shared pixel SPX of the image sensor 100 according to an embodiment, and Figure 2 is a diagram showing a method according to an embodiment of the present invention. Figure 1 FIG. 1 is a plan view of a shared pixel SPX of an image sensor 100 shown in FIG. The image sensor 100 may include a two-dimensional array structure (eg, see FIG. 1 ) on a substrate. Fig.12 ) are arranged into multiple shared pixels SPX.

[0022] refer to Figure 1 and Figure 2 , one shared pixel SPX among a plurality of shared pixels SPX is shown by way of example. Each shared pixel in the shared pixels SPX may include four unit pixels PX arranged in a 2*2 structure. For example, the four unit pixels PX may include a first unit pixel PX1, a second unit pixel PX2, a third unit pixel PX3, and a fourth unit pixel PX4. Hereinafter, for the convenience of description, the term "unit pixel" is referred to as "pixel" for short.

[0023] Each of the first to fourth pixels PX1 to PX4 may include two photodiodes (PD) 110. For example, the first pixel PX1 may include a first PD PD1-1 and a second PD PD1-2, the second pixel PX2 may include a third PD PD2-1 and a fourth PD PD2-2, the third pixel PX3 may include a fifth PD PD3-1 and a sixth PD PD3-2, and the fourth pixel PX4 may include a seventh PD PD4-1 and an eighth PD PD4-2.

[0024] Each of the four pixels PX may include two PDs 110, a portion of a floating diffusion (FD) region 140, and at least one pixel transistor. In a vertical structure, the pixel transistor may be disposed on a substrate (eg, a reference Figure 5C 101) and the PD 110 may be disposed in the substrate 101. For example, the PD 110 may be disposed in the lower portion of the active region 160 of the pixel transistor. Figure 2 In the embodiment, the exposed portion between the deep trench isolation (DTI) structure 120 and the active region 160 may correspond to the device isolation layer 115, and the PD 110 may not be exposed outside the DTI structure 120. In some embodiments, the pixel transistor may include, for example, a transfer transistor TX, a reset transistor RX, a source follower transistor SFX, and / or a selection transistor SX. FIG. 5A to FIG. 5C The substrate 101 and the PD 110 are further described.

[0025] In some embodiments, the device isolation layer 115 may be disposed on the front side FS of the substrate 101 (refer to Figure 5B) on, and active regions 160 may be defined. In some embodiments, each of the active regions 160 may include: a region in which the transmission gate 130 and the FD region 140 are disposed, a region in which the gate 150 is disposed, and a region in which the ground contact 170 is disposed. The bottom surface of the device isolation layer 115 may be spaced apart from the PD 110. The depth of the device isolation layer 115 may be less than the depth of the DTI structure 120. The device isolation layer 115 may be, for example, a shallow trench isolation (STI) layer. The DTI structure 120 may overlap a portion of the device isolation layer 115. For example, the DTI structure 120 may extend through the device isolation layer 115.

[0026] Each pixel in the pixel PX may include two PDs 110, and two transfer gates 130 may be arranged on each of the PDs 110. For example, each of the first PD PD1-1 and the second PD PD1-2 of the first pixel PX1 may include a first transfer gate 130-1 and a second transfer gate 130-2. The first transfer gate 130-1 and the second transfer gate 130-2 may transfer charges generated by the corresponding PD 110 to the adjacent FD region 140. Charge leakage may be reduced by providing two transfer gates 130 on one PD 110. In some embodiments, one PD 110, two transfer gates 130, and the FD region 140 may form one transfer transistor TX. In some embodiments, each of the two transfer gates 130 may have a configuration similar to Figure 5C However, the structure of the transfer gate 130 is not limited to the single vertical gate structure.

[0027] The four pixels PX may be separated from each other by the DTI structure 120. In some embodiments, the two PDs 110 in each of the four pixels PX may also be separated from each other by the DTI structure 120. Figure 2 For example, the DTI structure 120 may include an outer DTI structure 120out that separates the pixels PX from each other, and an inner DTI structure 120in that separates the two PDs 110 in each pixel of the pixel PX from each other.

[0028] The external DTI structure 120out may include a portion extending in the x-direction and a portion extending in the y-direction. The portion of the external DTI structure 120out extending in the y-direction may completely separate two adjacent pixels PX from each other in the x-direction. The portion of the external DTI structure 120out extending in the x-direction may partially separate two adjacent pixels PX from each other in the y-direction. For example, the portion of the external DTI structure 120out extending in the x-direction may be divided into two portions by a portion of the FD region 140.

[0029] The internal DTI structure 120in may be disposed in each pixel in the pixel PX and extend in the y direction to separate the two PDs 110 from each other. Therefore, in each pixel in the pixel PX, the two PDs 110 may be disposed on respective sides of the internal DTI structure 120in in the x direction. In some embodiments, two transmission gates 130 may be disposed on each side of the internal DTI structure 120in in the x direction. In other words, for example, referring to Figure 2 In the third pixel PX3 in FIG. 1 , the first transmission gate 130-1 and the second transmission gate 130-2 of the fifth PD PD3-1 may be disposed on one side of the internal DTI structure 120in separating the fifth PD PD3-1 from the sixth PD PD3-2, and the first transmission gate 130-1 and the second transmission gate 130-2 of the sixth PD PD3-2 may be disposed on the other side of the internal DTI structure 120in separating the fifth PD PD3-1 from the sixth PD PD3-2. The FD region 140 may be adjacent to an edge of the internal DTI structure 120in in the y direction.

[0030] In some embodiments, the x direction and the y direction are relative concepts. When the shared pixel SPX is rotated 90°, the x direction may be the y direction, and the y direction may be the x direction. Therefore, the extension direction and structure of the external DTI structure 120out and the internal DTI structure 120in may not be limited to the directions and structures described above.

[0031] In some embodiments, the DTI structure 120 may prevent charges generated by light incident on the PD 110 of a specific pixel PX from entering an adjacent pixel PX or PD 110. That is, the DTI structure 120 may prevent optical crosstalk between adjacent pixels PX. The DTI structure 120 may extend from the front side FS of the substrate 101 to the back side BS (refer to FIG. Figure 5C ) and can penetrate the substrate 101.

[0032] The DTI structure 120 will now be further described. The DTI structure 120 may include a central conductive layer and an outer insulating layer. The central conductive layer may be disposed in a central portion of the DTI structure 120 and may include, for example, polysilicon doped with a dopant. A ground voltage or a negative voltage may be applied to the central conductive layer. When the ground voltage or the negative voltage is applied to the central conductive layer, the positive charge generated by the pixel PX may be induced by the voltage of the central conductive layer and removed through the ground contact. As a result, the DTI structure 120 may improve the dark current characteristics of the image sensor 100 through the central conductive layer. The outer insulating layer may be disposed at an outer portion of the DTI structure 120 to surround the central conductive layer. The outer insulating layer may insulate the central conductive layer from the substrate 101. The outer insulating layer may include, for example, a silicon oxide layer, a silicon oxynitride layer, or a silicon nitride layer.

[0033] In some embodiments, a buried layer may be disposed in the central conductive layer. The buried layer may have functions such as preventing the formation of voids in the DTI structure 120 and preventing bending of the substrate 101 by offsetting the tensile stress applied to the substrate 101 during the high temperature process. Therefore, the buried layer may include a material having a thermal expansion coefficient different from that of the central conductive layer. For example, the buried layer may include a metal oxide, a metal nitride, a metal, or a combination thereof. Alternatively, the buried layer may include a silicon compound such as SiCN, SiON, SiOC, etc.

[0034] The DTI structure 120 may be provided by forming a deep trench in the substrate 101 and filling the inside of the deep trench with an insulating material and a conductive material. Depending on whether the deep trench is formed in the front side FS or the back side BS of the substrate 101, the DTI structure 120 may be referred to as a front DTI (FDTI) structure or a back DTI (BDTI) structure. In some embodiments, the DTI structure 120 may have various shapes depending on the shape of the trench. For example, in some embodiments, the DTI structure 120 may not completely penetrate the substrate 101. In Figure 1 and Figure 2 In the image sensor 100 of the embodiment shown in FIG. 1 , the DTI structure 120 may have a FDTI structure. However, the DTI structure 120 is not limited thereto.

[0035] The FD region 140 may be located between two adjacent pixels PX in the y direction. For example, the FD region 140 may be formed by doping a high concentration dopant in the active region 160 between two adjacent pixels PX in the y direction. For example, the first FD region 140 (1) may be disposed between the first pixel PX1 and the second pixel PX2, and the second FD region 140 (2) may be disposed between the third pixel PX3 and the fourth pixel PX4. Therefore, the first pixel PX1 and the second pixel PX2 may share the first FD region 140 (1), and the first pixel PX1 and the second pixel PX2 and the first FD region 140 (1) may form a first sub-shared pixel SPXs1. In some embodiments, the third pixel PX3 and the fourth pixel PX4 share the second FD region 140 (2), and the third pixel PX3 and the fourth pixel PX4 and the second FD region 140 (2) may form a second sub-shared pixel SPXs2. As a result, the four PDs 110 of the first and second pixels PX1 and PX2 may share one FD region 140 (ie, first FD region 140 ( 1 )), and the four PDs 110 of the third and fourth pixels PX3 and PX4 may share one FD region 140 (ie, second FD region 140 ( 2 )).

[0036] In some embodiments, because two pixels PX form a sub-sharing pixel, the shared pixel SPX may include two sub-sharing pixels SPXs1 and SPXs2 adjacent to each other in the x direction. In some embodiments, because two pixels PX share one FD region 140, the shared pixel SPXs may have a simple wiring connection relationship. Figure 3A and Figure 3B The wiring connection relationship of the shared pixel SPX is described.

[0037] like Figure 2 As shown, the sharing pixel SPX may have an approximately square shape in a plan view. However, the planar shape of the sharing pixel SPX is not limited to the square shape.

[0038] In some embodiments, a microlens may be disposed on each pixel in the pixel PX, on each of the sub-shared pixels SPXs1 and SPXs2, or on the entire shared pixel SPX. Fig. 8A and Figure 8B The arrangement of shared pixels SPX and microlenses is described.

[0039] Despite Figure 2 Only one shared pixel SPX is shown in the figure, but the image sensor 100 according to the embodiment may include a plurality of shared pixels SPX arranged in a two-dimensional array structure. That is, in the image sensor 100 according to the embodiment, the plurality of shared pixels SPX may be arranged in the x direction and the y direction. Fig.12Describe the two-dimensional array structure of shared pixels SPX.

[0040] The connection relationship between the PD 110, the FD region 140 and the pixel transistor can be based on Figure 1 The equivalent circuit diagram shown in is described as follows: the four PDs PD1-1, PD1-2, PD2-1 and PD2-2 of the first sub-shared pixel SPXs1 can be respectively connected to the source regions of the corresponding four transmission transistors TX1-1, TX1-2, TX2-1 and TX2-2; and the four PDs PD3-1, PD3-2, PD4-1 and PD4-2 of the second sub-shared pixel SPXs2 can be respectively connected to the source regions of the corresponding four transmission transistors TX3-1, TX3-2, TX4-1 and TX4-2.

[0041] The drain regions of the four transfer transistors TX1-1, TX1-2, TX2-1, and TX2-2 of the first sub-shared pixel SPXs1 and the drain regions of the four transfer transistors TX3-1, TX3-2, TX4-1, and TX4-2 of the second sub-shared pixel SPXs2 may be connected to the source region of the reset transistor RX. In other words, the common drain region of the four transfer transistors TX1-1, TX1-2, TX2-1, and TX2-2 of the first sub-shared pixel SPXs1 may correspond to the first FD region FD1 (e.g., Figure 2 The first FD region 140 (1) in the second sub-shared pixel SPXs2 may correspond to the first FD region 140 (1) in the second sub-shared pixel SPXs2, and the common drain region of the four transfer transistors TX3-1, TX3-2, TX4-1 and TX4-2 of the second sub-shared pixel SPXs2 may correspond to the second FD region FD2 (eg, Figure 2 In some embodiments, the source region of the reset transistor RX may correspond to the two FD regions 140 connected to each other by wiring. That is, the source region of the reset transistor RX may correspond to the first FD region FD1 of the first sub-sharing pixel SPXs1 and the second FD region FD2 of the second sub-sharing pixel SPXs2. The first FD region FD1 and the second FD region FD2 may be connected to the source follower gate SF of the source follower transistor SFX by wiring (refer to Figure 3B ).like Figure 1 As can be seen in FIG. 1 , the drain region of the reset transistor RX and the drain region of the source follower transistor SFX can be connected to the power supply voltage Vpix. In some embodiments, the source region of the source follower transistor SFX and the drain region of the selection transistor SX can be connected to each other. In some embodiments, the output line is connected to the source region of the selection transistor SX, and therefore, the voltage of the source region of the selection transistor SX can be output as the output voltage Vout.

[0042] In some embodiments, pixel transistors such as source follower transistor SFX, reset transistor RX, and select transistor SX may be implemented by gate 150 and active region 160 disposed in pixel PX sharing pixel SPX. Figure 3B A specific arrangement structure of the source follower transistor SFX, the reset transistor RX, and the select transistor SX is described.

[0043] In some embodiments, the size of the pixel transistor may be determined by the size of the gate 150. The size of the gate 150 in the x-direction may be the width of the gate 150, and the size of the gate 150 in the y-direction may be the length of the gate 150. Figure 2 As can be seen in FIG. 1 , the width of the gate 150 may be determined to some extent by the DTI structure 120. In the image sensor 100 according to the embodiment, the gate 150 may have a first gate length Lg1. In some embodiments, the first gate length Lg1 of the gate 150 may be changed, and thus the size of the pixel transistor may be changed. In the image sensor 100 according to the embodiment, the size of the pixel transistor may be changed to improve the charge transfer efficiency, the conversion gain (CG), etc.

[0044] The ground contact 170 may be disposed in the active regions 160 of the first sub-sharing pixel SPXs1 and the second sub-sharing pixel SPXs2, respectively. For example, based on the entire sharing pixel SPX, the ground contact 170 of the first sub-sharing pixel SPXs1 may be disposed in the right outer portion in the x direction and adjacent to the center portion in the y direction, as shown in FIG. Figure 2 shown. Figure 2 It is shown that the ground contact 170 of the first sub-sharing pixel SPXs1 is disposed in the first pixel PX1. However, the embodiment is not limited thereto, and in some embodiments, the ground contact 170 of the first sub-sharing pixel SPXs1 may be disposed in the second pixel PX2. Similarly, based on the entire sharing pixel SPX, the ground contact 170 of the second sub-sharing pixel SPXs2 may be disposed in the left outer portion in the x direction and adjacent to the center portion in the y direction. In some embodiments, the ground contact 170 of the second sub-sharing pixel SPXs2 may be disposed in the fourth pixel PX4.

[0045] The location of the ground contact 170 is not limited to Figure 2 The position in the shared pixel SPX of the image sensor 100 shown in FIG. That is, the ground contact 170 may be provided at various positions in the shared pixel SPX according to the structure of the shared pixel SPX. Figure 4A , Figure 4B , Fig. 6A , Figure 7 etc. describe various arrangements of ground contacts.

[0046] Figure 3A and Figure 3B 1 and 2 are diagrams showing the wiring routing of the FD region of the image sensor Com. of the comparative example and the wiring routing of the FD region of the image sensor Com. of the reference example. Figure 1 FIG. 1 is a plan view of the wiring routing of the FD region 140 of the image sensor 100 of the embodiment described above. Figure 1 Given the following pair Figure 3A and Figure 3B For the sake of brevity, the above references will be briefly described or omitted. Figure 1 and Figure 2 The description given is the same as the description given.

[0047] refer to Figure 3A , in the image sensor Com. of the comparative example, the shared pixel may include four pixels. In some embodiments, each pixel in the pixel may include two PDs, and an FD region may be set in each of the PDs. A ground contact GND may be set in the central portion of each pixel in the pixel. Therefore, in the image sensor Com. of the comparative example, eight FD regions may be arranged in the shared pixel, and the eight FD regions may be connected to the source region of the reset transistor and the source follower gate of the source follower transistor SF through wiring. As a result, in the image sensor Com. of the comparative example, the wiring line between the FD region and the pixel transistor may be complicated. Typically, the wiring includes a metal such as copper (Cu), and the complex wiring routing increases resistance and reduces conversion gain (CG). Here, CG may refer to the rate at which the charge generated by the PD is transferred to and accumulated in the FD region, and the charge may be converted into voltage by the source follower transistor. In addition, in the image sensor Com. of the comparative example, the complex wiring routing may make it difficult to increase the layout efficiency and size of the pixel transistor, and may increase the wiring layer.

[0048] In contrast, reference Figure 3B , in the image sensor 100 according to the embodiment, the shared pixel SPX includes four pixels PX, and two pixels PX form one sub-shared pixel while sharing one FD region 140 with each other. Therefore, only two FD regions 140 are provided in the shared pixel SPX, and the two FD regions 140 are connected to the source region of the reset transistor RX and the source follower gate SF of the source follower transistor SFX through wiring. As a result, as Figure 3B As shown, in the image sensor 100, the wiring route between the FD region 140 and the pixel transistor can be simple. The simple wiring route can improve the CG by reducing the resistance. In addition, in the image sensor 100, the simple wiring route can increase the layout efficiency and size of the pixel transistor and help reduce the wiring layer. Figure 4B or Fig.11The increase in arrangement efficiency and size of pixel transistors is further described.

[0049] In the image sensor 100, one gate 150 may be provided for each PD 110 in the outer portion of the shared pixel SPX. Therefore, eight gates 150 may be arranged in the shared pixel SPX. At least three of the eight gates 150 may be used for the pixel transistor of the shared pixel SPX. For example, in some embodiments, the left gate 150 of the first pixel PX1 may be used as the reset gate RG of the reset transistor RX. In some embodiments, the right gate 150 of the third pixel PX3 may be used as the source follower gate SF of the source follower transistor SFX, and the left gate 150 of the third pixel PX3 may be used as the selection gate SG of the selection transistor SX. The position of the gate 150 for the pixel transistor is not limited thereto. For example, in some embodiments, the reset gate RG may be provided in the third pixel PX3, and the source follower gate SF and the selection gate SG may be provided in the first pixel PX1. In some embodiments, the gates 150 of the second pixel PX2 and the fourth pixel PX4 may be used as the gates of the pixel transistor.

[0050] In some embodiments, the gate 150 that does not form a pixel transistor may correspond to a dummy gate. The dummy gate may be used in the image sensor 100 to implement other operating characteristics. For example, the dummy gate may be used to implement a double CG or triple CG of a shared pixel SPX. In some embodiments, the dummy gate may be used as an additional source follower gate SF to form a plurality of source follower gates SF.

[0051] Figure 4A and Figure 4B are plan views respectively illustrating shared pixels SPX of image sensors 100a and 100b according to some embodiments. Figure 1 Given the following pair Figure 4A and Figure 4B For the sake of brevity, the above references will be briefly described or omitted. Figures 1 to 3B The description given is the same as the description given.

[0052] refer to Figure 4A , the image sensor 100a and the reference Figure 2 The difference of the described image sensor 100 is the location of the ground contact 170a. For example, in the image sensor 100a, the ground contact 170a can be arranged adjacent to the central portion of the shared pixel SPX in the x-direction and the y-direction. For example, the ground contact 170a can be arranged adjacent to the central portion of the external DTI structure 120out of the shared pixel SPX arranged in a cross (╋) shape. Figure 4A, the ground contact 170a is disposed in the first pixel PX1 and the third pixel PX3 in the center portion of the shared pixel SPX. However, the position of the ground contact 170a is not limited thereto. For example, according to some embodiments, the ground contact 170a may be disposed at the center portion of the shared pixel SPX in the second pixel PX2 and the fourth pixel PX4, the first pixel PX1 and the fourth pixel PX4, or the second pixel PX2 and the third pixel PX3.

[0053] In the image sensor 100a, the wiring connection structure between the FD region 140 and the pixel transistor can be similar to Figure 3B Hereinafter, when the shared pixel SPX has a structure including two sub-sharing pixels SPXs1 and SPXs2 and two FD regions 140, the wiring connection structure between the FD region 140 and the pixel transistor may be the same as that shown in FIG. Figure 3B The wiring connection structures shown in are basically the same unless otherwise specified.

[0054] refer to Figure 4B , the image sensor 100b and Figure 2 The image sensor 100 shown in FIG. 1 is different in the position of the ground contact 170 b and the arrangement of the gate 150. For example, in the image sensor 100 b, the ground contact 170 b may be arranged to be located in the outer portion of the shared pixel SPX in the x-direction and the y-direction. For example, assuming that four pixels PX form a quadrant, the ground contact 170 b may be arranged in the outer portion of the second quadrant and the fourth quadrant. However, the position of the ground contact 170 b is not limited thereto. For example, in some embodiments, the ground contact 170 b may be arranged in the outer portion of the first quadrant and the third quadrant, in the outer portion of the first quadrant and the second quadrant, or in the outer portion of the third quadrant and the fourth quadrant.

[0055] Since the ground contact 170b is disposed at the outer portion of the shared pixel SPX in the image sensor 100b, the gate disposed on the upper portion of the corresponding active region 160 may be omitted. Figure 4B Although not shown in the figure, in the image sensor 100b, the right gate 150 of the third pixel PX3 may be the reset gate RG of the reset transistor RX, the right gate 150 of the first pixel PX1 may be the selection gate SG of the selection transistor SX, and the left gate 150 of the first pixel PX1 may be the source follower gate SF of the source follower transistor SFX. In some embodiments, the gates of the pixel transistors may be disposed in the second pixel PX2 and the fourth pixel PX4. In the image sensor 100b, the position of the ground contact 170b may be diversified, and the arrangement efficiency of the pixel transistors may be improved.

[0056] FIG. 5A to FIG. 5C 1 and 2 are plan views respectively illustrating a shared pixel SPX and cross-sectional views of transfer gates 130 a and 130 a ′ of image sensors 100 c and 100 c ′ according to some embodiments. Figure 5B and Figure 5C are cross-sectional views showing the transmission gates 130a and 130a' in the x direction, respectively. Figure 1 Given the following pair FIG. 5A to FIG. 5C For the sake of brevity, the above references will be briefly described or omitted. Figures 1 to 4B The description given is the same as the description given.

[0057] refer to Figure 5A and Figure 5B , the image sensor 100c and the reference Figure 2 The image sensor 100 described differs in that one transfer gate 130a is provided for each PD 110. For example, the image sensor 100c may include a substrate 101, a PD 110, a DTI structure 120, a transfer gate 130a, an FD region 140, and a gate 150.

[0058] The substrate 101 may include a front side FS and a back side BS opposite to the front side FS (see Figure 5B ). A wiring layer may be provided on the front side FS of the substrate 101, and a light transmission layer may be provided on the back side BS of the substrate 101. The light transmission layer may include, for example, a color filter and a microlens. Light may be incident on the PD 110 through the light transmission layer provided on the back side BS of the substrate 101.

[0059] The substrate 101 may be a substrate in which an epitaxial layer of a first conductivity type is grown on a bulk silicon substrate of the first conductivity type (e.g., p-type). In some embodiments, the substrate 101 may include only the epitaxial layer in a state where the bulk silicon substrate is completely removed. In some embodiments, the substrate 101 may be a bulk silicon substrate including a well of the first conductivity type. In some embodiments, the substrate 101 may include various types of substrates, such as a substrate including an epitaxial layer of a second conductivity type (e.g., n-type) or a silicon-on-insulator (SOI) substrate.

[0060] PD 110 may generate and accumulate charges in proportion to the intensity of light (i.e., the amount of light) incident on PD 110 through the back side BS of substrate 101. PD 110 may each include, for example, a first dopant region doped with a dopant of a first conductivity type (e.g., p-type) and a second dopant region doped with a dopant of a second conductivity type (e.g., n-type). The first dopant region and the second dopant region may form a pn junction. In some embodiments, substrate 101 may serve as the first dopant region. In this case, substrate 101 and the second dopant region may form PD 110, and the first dopant region may not be formed additionally. In some embodiments, PD 110 may be respectively disposed at the center of pixel PX in substrate 101. For example, as Figure 5B As shown, the PD 110 may be disposed in the substrate 101 below the transmission gate 130 a of the transmission transistor TX.

[0061] In the image sensor 100c, one transfer transistor TX is provided for each PD 110, and the transfer transistor TX may include a transfer gate 130a. Considering the functional aspects of the transistor, the transfer gate 130a, the PD 110, and the FD region 140 may form one transfer transistor TX. In other words, the PD 110 / FD region 140 may form the source / drain of the transfer transistor TX.

[0062] The transmission gate 130a may include polysilicon. However, the material of the transmission gate 130a is not limited to polysilicon. For example, in some embodiments, the transmission gate 130a may be formed as a multilayer structure including a barrier layer and at least one metal layer. In some embodiments, the transmission gate 130a may have, for example, a dual vertical gate structure. Therefore, the transmission gate 130a may include two vertical extension portions 132 and a connecting portion 134. The two vertical extension portions 132 may extend into the interior of the substrate 101 in the vertical direction and may be spaced apart from each other in the x direction. Here, the vertical direction may refer to the z direction perpendicular to the upper surface of the substrate 101. The connecting portion 134 may connect the two vertical extension portions 132 to each other on the upper surface of the substrate 101. Here, the vertical extension portion 132 and the connecting portion 134 are merely terms used to distinguish between them, and the vertical extension portion 132 and the connecting portion 134 may include the same material and may be formed as a single piece. For example, in some embodiments, the vertical extension portion 132 and the connecting portion 134 may be formed as a single piece using polysilicon.

[0063] like Figure 5AAs shown, the horizontal cross-section of the transmission gate 130a may have a rectangular shape. At a level above the connection portion 134 in the z direction, the horizontal cross-section of the transmission gate 130a may have a rectangular shape. At a level below the connection portion 134 in the z direction, the horizontal cross-section of the transmission gate 130a may have a shape in which two small rectangular shapes of the vertical extension portion 132 are spaced apart from each other in the x direction.

[0064] The lower surface and side surfaces of the vertical extension portion 132 and the lower surface of the connection portion 134 may be surrounded by a gate insulating layer 135. For example, the gate insulating layer 135 may be disposed between the vertical extension portion 132 and the substrate 101, between the connection portion 134 and the substrate 101, and on the upper surface of the substrate 101 outside the transmission gate 130a in the x-direction.

[0065] In the image sensor 100c, the transfer gate 130a having a dual vertical gate structure is provided, and therefore, as in the case where two transfer gates 130 having a vertical gate structure are provided, charge leakage can be reduced. In some embodiments, because the connection portion 134 provided in the upper portion of the transfer gate 130a is wide, the gate contact 180 may not have a large area and may not be misaligned. That is, because the connection portion 134 provided in the upper portion of the transfer gate 130a is wide, the gate contact 180 may have a relatively small area, and the gate contact may be easily aligned on the connection portion 134. For example, when only two transfer gates are provided without a connection portion, since the gate contacts are respectively provided on the transfer gates, the contact area may increase. In some embodiments, because the upper surfaces of the two transfer gates are narrow, misalignment may occur between the gate contact and the two transfer gates. However, in the image sensor 100c, the transfer gate 130a includes the connection portion 134. Therefore, only one gate contact 180 may be used, and the area of ​​the gate contact 180 may be reduced. Furthermore, since the connection portion 134 has a relatively large upper surface area, misalignment between the connection portion 134 and the gate contact 180 may be reduced.

[0066] In some embodiments, a spacer having a certain thickness may be disposed between the connection portion 134 of the transmission gate 130a and the substrate 101 to remove a potential hump of the transmission gate 130a. The potential hump may refer to a phenomenon in which an electric field is concentrated at the edge of the active region corresponding to the curved portion of the gate. Due to the spacer, the length of the vertical extension portion 132 of the transmission gate 130a may increase the thickness of the spacer. Therefore, the thickness of the spacer may be appropriately determined by considering the length of the vertical extension portion 132 of the transmission gate 130a and the effect of removing the potential hump.

[0067] refer to Figure 5A and Figure 5C , the image sensor 100c' and the reference Figure 5B The image sensor 100c described is similar in that one transmission gate 130a' is provided for each PD 110. However, the image sensor 100c' is similar to the reference Figure 5B The image sensor 100c described differs in that the transfer gate 130a' may have a single vertical gate structure. For example, in some embodiments, the image sensor 100c' may include a substrate 101, a PD 110, a DTI structure 120, a transfer gate 130a', an FD region 140, and a gate 150. The substrate 101, the PD 110, the DTI structure 120, the FD region 140, and the gate 150 may be the same as in the reference 100. Figure 2 and Figure 5B The described image sensors 100 and 100 c are identical to those thereof, and thus duplicate descriptions thereof are omitted for the sake of brevity.

[0068] like Figure 5C As shown, the transmission gate 130a' may have a single vertical gate structure. Therefore, the transmission gate 130a' may include a vertical extension portion 132 and a horizontal extension portion 136. The vertical extension portion 132 may extend into the interior of the substrate 101 in a vertical direction. The horizontal extension portion 136 may extend from the vertical extension portion 132 on the upper surface of the substrate 101 in a horizontal direction. The vertical extension portion 132 and the horizontal extension portion 136 of the transmission gate 130a' are only terms used to distinguish between them, and the vertical extension portion 132 and the horizontal extension portion 136 may include the same material and may be formed as a single piece.

[0069] In the image sensor 100c', the vertical extension portion 132 of the transfer gate 130a' may extend vertically into the interior of the substrate 101, and the horizontal extension portion 136 may extend on the substrate 101. Therefore, even when the vertical extension portion 132 is small, a sufficient area of ​​the gate contact 180 may be ensured by the horizontal extension portion 136. As a result, the gate contact 180 may not have a large area and may not be misaligned. In other words, the gate contact 180 may have a relatively small area and may be more easily aligned on the horizontal extension portion 136. In some embodiments, a spacer having a certain thickness may be provided between the horizontal extension portion 136 of the transfer gate 130a and the substrate 101 to remove a potential hump of the transfer gate 130a'.

[0070] Fig. 6A and Figure 6B1 and 10 are plan views showing a shared pixel SPXa of the image sensor 100d according to the embodiment and a plan view showing a wiring line of the FD region of the image sensor 100d according to the embodiment, respectively. Figure 1 Given the following pair Fig. 6A and Figure 6B For the sake of brevity, the above references are briefly described or omitted. Figures 1 to 5C The description given is the same as the description given.

[0071] refer to Fig. 6A and Figure 6B , the image sensor 100d and the reference Figure 2 The difference of the described image sensor 100 is that the two pixels PX do not share the FD region 140a, and the two pixels PX can still constitute a sub-shared pixel. However, the embodiment is not limited to this. For example, in the image sensor 100d, the shared pixel SPXa may include four pixels PX1a to PX4a, and the concept of configuring a sub-shared pixel by two pixels PX may not be used. In some embodiments, the four pixels PX1a to PX4a can be completely separated from each other by the DTI structure 120a (e.g., by the external DTI structure 120out).

[0072] Each pixel in the pixel PX may include an FD region 140a. Therefore, in each pixel in the pixel PX, two PDs 110 may share the FD region 140a. Figure 6B As shown, according to the arrangement structure of the FD regions 140 a , the four FD regions 140 a of the shared pixel SPXa may be connected to the source region of the reset transistor RX and the source follower gate SF of the source follower transistor SFX through wiring.

[0073] In some embodiments, the ground contact 170c may be provided in each pixel PX. For example, the ground contact 170c may be provided in the outer portion of the shared pixel SPXa in the x direction and adjacent to its central portion in the y direction. However, the position of the ground contact 170c is not limited thereto. For example, in some embodiments, the ground contact 170c may be provided in each pixel of the pixel PX adjacent to the central portion of the shared pixel SPXa in the x direction and the y direction.

[0074] In some embodiments, the wiring connection structure between the FD region 140a and the pixel transistor of the image sensor 100d may be Figure 3A The wiring connection structure of the FD region of the image sensor Com. of the comparative example shown in FIG is simple. Therefore, the image sensor 100d can also contribute to improving CG, increasing the layout efficiency and size of pixel transistors, and reducing wiring layers.

[0075] Figures 7 to 11100e, 100f, 100g, 100h, and 100i are plan views respectively showing shared pixels SPXb and SPX of image sensors 100e, 100, 100f, 100g, 100h, and 100i according to some embodiments. Figure 1 Given the following pair Figures 7 to 11 For the sake of brevity, the above references are briefly described or omitted. Figures 1 to 6B The description given is the same as the description given.

[0076] refer to Figure 7 , the image sensor 100e may differ from the reference in terms of the structure of the shared pixel SPXb Figure 2 The image sensor 100 described above. For example, in the image sensor 100e, the shared pixel SPXb may include four pixels PX1b to PX4b, and the concept of configuring the sub-shared pixel by two pixels PX may not be used. Therefore, each pixel in the pixel PX may include the FD region 140a. Therefore, in each pixel in the pixel PX, two PDs 110 may share the FD region 140a.

[0077] The layout and wiring connection structure of the FD region 140a can be similar to Figure 6B The layout and wiring connection structure of the FD region 140a shown in FIG. 1 are substantially the same. Hereinafter, when each pixel PX of a shared pixel includes the FD region 140a, the wiring connection structure between the FD region 140a and the pixel transistor may be the same as that of FIG. Figure 6B The wiring connection structures shown in are basically the same unless otherwise specified.

[0078] In the image sensor 100e, the four pixels PX1b to PX4b of the shared pixel SPXb may be incompletely separated from each other by the DTI structure 120b (e.g., the external DTI structure 120out). For example, the ground contact 170d, which is a common ground contact of the shared pixel SPXb, may be provided in the central portion of the shared pixel SPXb in the x-direction and the y-direction. Due to the ground contact 170d provided in the central portion of the shared pixel SPXb, the portion of the external DTI structure 120out extending in the x-direction may be divided such that a portion of the external DTI structure 120out is provided on each side of the ground contact 170d in the x-direction, and the portion of the external DTI structure 120out extending in the y-direction may be divided such that a portion of the external DTI structure 120out is provided on each side of the ground contact 170d in the y-direction.

[0079] refer to Fig. 8A In the image sensor 100, four micro lenses 190 may be provided corresponding to four pixels PX of the shared pixel SPX. As described above, the micro lenses 190 may be provided on the lower surface of the substrate 101. Therefore, Fig. 8AA dotted line is shown corresponding to the microlens 190. In some embodiments, although the microlens 190 is shown to have a quadrilateral planar shape corresponding to the planar shape of the pixel PX, the planar shape of the microlens 190 is not limited to a quadrilateral square, but may have a circular or elliptical shape.

[0080] In some embodiments, each pixel in the pixel PX includes two PDs 110, and the transfer transistor TX is provided corresponding to each PD in the PD110. Therefore, at least one pixel in the pixel PX can be used to implement auto focus (AF). In some embodiments, AF can be performed in various ways. For example, AF can be performed by methods such as a contrast AF method, a phase difference AF method, an imaging plane phase difference AF method, or a dual pixel AF method. The dual pixel AF method refers to a method of using two or more PDs 110 as one AF pixel. According to the dual pixel AF method, the PDs 110 of the AF pixels are individually controlled so that when AF information is used, the PDs 110 can operate like a phase difference sensor using a photodetection signal of the PDs 110, and when image information is used, the photodetection signals of the PDs 110 can be combined and output as an image signal. The image sensor 100 can perform AF by using a dual pixel AF method of two PDs 110 in the pixel PX.

[0081] refer to Figure 8B In the image sensor 100f, two micro lenses 190a corresponding to two sub-sharing pixels SPXs1 and SPXs2 of the sharing pixel SPX may be provided. The micro lenses 190a may be provided on the lower surface of the substrate 101, and Figure 8B A dotted line corresponding to the microlens 190a is shown. In some embodiments, the microlens 190a may have a quadrilateral planar shape extending in the y direction and corresponding to the planar shape of the sub-shared pixels SPXs1 and SPXs2. However, the microlens 190 is not limited thereto and may have an elliptical planar shape extending in the y direction.

[0082] In the image sensor 100f, each of the sub-sharing pixels SPXs1 and SPXs2 may include two pixels PX. Therefore, the upper pixel PX and the lower pixel PX of each of the sub-sharing pixels SPXs1 and SPXs2 may be used to implement AF. That is, in the image sensor 100f, at least one of the sub-sharing pixels SPXs1 and SPXs2 may perform AF by a dual-pixel AF method using two pixels PX.

[0083] refer to Fig. 9 , the structure of the shared pixel SPX of the image sensor 100g can be compared with the reference Figure 2The structures of the shared pixels SPX of the described image sensor 100 are substantially the same. For example, the shared pixel SPX may include two sub-shared pixels SPXs1 and SPXs2 adjacent to each other in the x direction, and each of the sub-shared pixels SPXs1 and SPXs2 may include two pixels PX adjacent to each other in the y direction.

[0084] In the image sensor 100g, the FD region 140 may be disposed in the central portion of each of the sub-sharing pixels SPXs1 and SPXs2 and may be shared by two pixels PX. In some embodiments, the FD region 140 may be formed in the active region 160 disposed in the central portion of each of the sub-sharing pixels SPXs1 and SPXs2.

[0085] Since the FD region 140 is disposed in the central portion of each of the sub-sharing pixels SPXs1 and SPXs2, the outer DTI structure 120out extending in the x direction within each of the sub-sharing pixels SPXs1 and SPXs2 may be divided into two portions located on both sides in the x direction by the active region 160 including the FD region 140. For example, the two portions of the outer DTI structure 120out may be spaced apart from each other by a first separation distance Sx in the x direction.

[0086] In some embodiments, because the FD region 140 is disposed in the central portion of each of the sub-sharing pixels SPXs1 and SPXs2, the internal DTI structures 120in disposed in two pixels PX adjacent to each other in the y direction may be separated from each other by the active region 160 including the FD region 140. For example, the internal DTI structures 120in disposed in two pixels PX adjacent to each other in the y direction may be spaced apart from each other by the second separation distance Sy in the y direction.

[0087] In the image sensor 100g, at least one of the first separation distance Sx and the second separation distance Sy may be adjusted to adjust the potential barrier between adjacent pixels PX and / or prevent optical crosstalk. For example, the first separation distance Sx may be reduced to increase the potential barrier between pixels PX adjacent to each other in the y direction in each of the sub-shared pixels SPXs1 and SPXs2, thereby enhancing electrical isolation and reducing optical crosstalk. In some embodiments, the second separation distance Sy may be reduced to enhance electrical isolation between PDs 110 adjacent to each other in the x direction in each pixel of the pixel PX, thereby reducing optical crosstalk. In some embodiments, the adjustment of the first separation distance Sx may correspond to an adjustment between pixels (inter-pixel adjustment), and the adjustment of the second separation distance Sy may correspond to an adjustment in a pixel (intra-pixel adjustment).

[0088] refer to Fig.10, the structure of the shared pixel SPX of the image sensor 100h can be compared with the reference Figure 2 The structures of the shared pixels SPX of the described image sensor 100 are substantially the same. For example, the shared pixel SPX may include two sub-shared pixels SPXs1 and SPXs2 adjacent to each other in the x direction, and each of the sub-shared pixels SPXs1 and SPXs2 may include two pixels PX adjacent to each other in the y direction.

[0089] In the image sensor 100h, the inner DTI structure 120in of the DTI structure 120 may have a first width Wx in the x-direction. In some embodiments, the outer DTI structure 120out of the DTI structure 120 may have a predetermined width in the x-direction or the y-direction. For example, the outer DTI structure 120out arranged in the central portion of the sub-shared pixels SPXs1 and SPXs2 in the y-direction and extending in the x-direction may have a second width Wy in the y-direction.

[0090] In the image sensor 100h, at least one of the first width Wx and the second width Wy may be adjusted to adjust the potential barrier between adjacent pixels PX and / or prevent optical crosstalk. For example, the first width Wx may be increased to enhance the electrical isolation between the PDs 110 in the x direction and reduce the optical crosstalk. In some embodiments, the second width Wy may be increased to enhance the electrical isolation between adjacent pixels PX in the y direction and reduce the optical crosstalk in each of the sub-shared pixels SPXs1 and SPXs2. In some embodiments, the adjustment of the first width Wx may correspond to the adjustment in the pixel PX, and the adjustment of the second width Wy may correspond to the adjustment between the pixels PX.

[0091] refer to Fig.11 , the structure of the shared pixel SPX of the image sensor 100i may be similar to that of the reference Figure 4B The structure of the shared pixel SPX of the image sensor 100b is described. For example, the ground contact 170b may be disposed in the outer portion of the shared pixel SPX in the x-direction and the y-direction. In some embodiments, the gate may not be disposed in the active region 160 in which the ground contact 170b is disposed.

[0092] In the image sensor 100i, the size of the gate 150a of the shared pixel SPX may be larger than the reference Figure 4BThe size of the gate 150 of the shared pixel SPX of the image sensor 100b described above is shown. For example, in the image sensor 100i, the gate 150a may have a second gate length Lg2 in the y direction. The second gate length Lg2 may be greater than the first gate length Lg1. Therefore, the size of the pixel transistors such as the reset transistor RX, the source follower transistor SFX, and the select transistor SX may be increased by increasing the size of the gate 150a.

[0093] In the image sensor 100i, the gate 150a may have a second gate length Lg2. In some embodiments, the second gate length Lg2 of the gate 150a may be changed, and thus the size of the pixel transistor may be changed. For example, in the image sensor 100i, characteristics such as charge transfer efficiency and CG may be improved by increasing the size of the gate 150a and the size of the pixel transistor.

[0094] Fig.12 Reference Figure 2 FIG. 1 is a plan view of a two-dimensional array structure of a shared pixel SPX of an image sensor 100 described above. Figure 1 and Figure 2 Given the following pair Fig.12 For the sake of brevity, the above references are briefly described or omitted. Figures 1 to 11 The description given is the same as the description given.

[0095] refer to Fig.12 , the image sensor 100 may have a reference Figure 2 The sharing pixels SPX are described as being arranged in a two-dimensional array structure in the x-direction and the y-direction. The sharing pixels SPX adjacent to each other in the x-direction and the y-direction may be spaced apart from each other by the DTI structure 120 (eg, the outer DTI structure 120out). Fig.12 Shown is a reference Figure 2 The shared pixels SPX of the described image sensor 100 are arranged in a two-dimensional array structure. In various embodiments, reference FIG. 3B to FIG. 5A and FIG. 6A to FIG. 11 The shared pixels SPX, SPXa, and SPXb of the described image sensors 100 a to 100 i may also be arranged in a two-dimensional array structure.

[0096] Fig.13 1 is a block diagram showing the entire image sensor 1000 according to an embodiment. Figure 1 and Figure 2 Given the following pair Fig.13 For the sake of brevity, the above references are briefly described or omitted. Figures 1 to 12 The description given is the same as the description given.

[0097] refer to Fig.13 , the image sensor 1000 may include a pixel array 1100, a timing controller (T / C) 1010, a row decoder 1020, and an output circuit 1030. The image sensor 1000 may be, for example, a charge coupled device (CCD) image sensor or a complementary metal oxide semiconductor (CMOS) image sensor.

[0098] In some embodiments, image sensor 1000 may be a reference Figure 2 , FIG. 3B to FIG. 5A and FIG. 6A to FIG. 11 Any one of the image sensors 100 and 100a to 100i described herein. Therefore, the pixel array 1100 may include a plurality of shared pixels SPX, SPXa or SPXb arranged in a plurality of rows and a plurality of columns to form a two-dimensional array structure. The row decoder 1020 may select a row from the row of the pixel array 1100 in response to a row address signal output from the timing controller 1010. The output circuit 1030 may output an image signal in units of columns from a plurality of pixels and / or shared pixels SPX arranged in the selected row. The output circuit 1030 may include an analog-to-digital converter (ADC). For example, the output circuit 1030 may include a plurality of ADCs arranged for the columns between the column decoder and the pixel array 1100, respectively, or an ADC arranged at the output end of the column decoder. In some embodiments, the timing controller 1010, the row decoder 1020 and the output circuit 1030 may be implemented as one chip or a separate chip.

[0099] In the image sensor 1000, each of the shared pixels SPX may include two sub-shared pixels SPXs1 and SPXs2, and each of the sub-shared pixels SPXs1 and SPXs2 may include two pixels PX and one FD region 140. Therefore, the wiring connection relationship between the FD region 140 and the pixel transistor may be simple, thereby improving the CG, increasing the layout efficiency and size of the pixel transistor, and reducing the wiring layer.

[0100] Fig.14 2 is a block diagram showing an electronic device 2000 including the image sensor 1000 according to an embodiment. Figure 1 , Figure 2 and Fig.13 Given the following pair Fig.14 For the sake of brevity, the above references are briefly described or omitted. Figures 1 to 13 The description given is the same as the description given.

[0101] refer to Fig.14, an electronic device 2000 including an image sensor 1000 (hereinafter referred to as "electronic device 2000") may include an imaging device 2100, the image sensor 1000, and a processor (PRO.) 2200. The electronic device 2000 may be, for example, a camera. The imaging device 2100 may form an optical image by focusing light reflected from an object OBJ. The imaging device 2100 may include an objective lens 2010, a lens driver (L-DR.) 2120, an aperture 2130, and an aperture driver (I-DR.) 2140. Although for ease of description, Fig.14 Only one lens is shown, but in some embodiments, the objective lens 2010 may include multiple lenses having different sizes and shapes. In some embodiments, the electronic device 2000 may be a mobile camera, and in a mobile camera, the aperture 2130 and the aperture driver 2140 may be omitted.

[0102] The lens driver (L-DR.) 2120 may communicate information about focus detection with the processor 2200, and may adjust the position of the objective lens 2010 according to a control signal received from the processor 2200. The lens driver 2120 may move the objective lens 2010 to adjust the distance between the objective lens 2010 and the object OBJ, or may adjust the positions of the respective lenses included in the objective lens 2010. The lens driver 2120 may drive the objective lens 2010 to adjust the focus on the object OBJ. In some embodiments, the lens driver 2120 may receive AF information and adjust the positions of the respective lenses of the objective lens 2010 to adjust the focus.

[0103] The aperture driver (I-DR.) 2140 may communicate information about the amount of light with the processor 2200, and may adjust the aperture 2130 according to a control signal received from the processor 2200. For example, the aperture driver 2140 may increase or decrease the diameter of the aperture 2130 according to the amount of light entering the interior of the electronic device 2000 through the objective lens 2010. In some embodiments, the aperture driver 2140 may adjust the opening time of the aperture 2130.

[0104] Image sensor 1000 may generate an electrical image signal based on the intensity of incident light. Image sensor 1000 may be, for example, a reference Figure 2 , FIG. 3B to FIG. 5A and FIG. 6A to FIG. 11 In some embodiments, image sensor 1000 may be any one of image sensors 100a to 100i described above. Fig.13 Thus, the image sensor 1000 may include a pixel array (PA) 1100, a timing controller (T / C) 1010, and an output circuit (OC) 1030. In some embodiments, although Fig.14Although not shown in the figure, the image sensor 1000 may further include a row decoder 1020 .

[0105] The processor 2200 may control the overall operation of the electronic device 2000 and perform an image processing function. For example, the processor 2200 may provide control signals for the operation of components such as the lens driver 2120, the iris driver 2140, and the timing controller 1010.

[0106] Although various embodiments have been particularly shown and described with reference to the drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. An image sensor, comprising: A plurality of pixels, each of the plurality of pixels comprises two PDs arranged side by side in a first direction, the PDs being photodiodes; A DTI structure, wherein the DTI is deep trench isolation, and the DTI structure comprises: an inner DTI structure, which extends in a second direction perpendicular to the first direction and separates the two PDs of each pixel in the plurality of pixels from each other in the first direction; and an outer DTI structure, which extends in the first direction and the second direction and separates the plurality of pixels from each other in the first direction and the second direction; an FD region, the FD being a floating diffusion, the FD region being arranged between a central portion of the outer DTI structure and an edge of the inner DTI structure extending along the first direction; and a plurality of TGs, the TGs being transmission gates, the plurality of TGs being arranged adjacent to the FD region, so that at least one TG among the plurality of TGs is arranged on each PD, For each pixel among the plurality of pixels, the two PDs of the pixel share the FD region.

2. The image sensor according to claim 1, wherein: Each group of two pixels adjacent to each other in the second direction among the plurality of pixels forms a sub-shared pixel, Each group of two sub-sharing pixels adjacent to each other in the first direction forms a shared pixel, and The shared pixels are arranged in a two-dimensional array structure in the first direction and in the second direction.

3. The image sensor according to claim 2, wherein: In each sub-sharing pixel, the FD region is disposed between two pixels of the sub-sharing pixel, and The two PDs of each of the two pixels of the sub-sharing pixel share the FD region of the sub-sharing pixel.

4. The image sensor according to claim 3, wherein: Each sub-shared pixel includes a ground contact region, and The ground contact area is arranged in one of the following: A first arrangement structure, wherein the ground contact region is arranged in an outer portion of each of the shared pixels in the first direction and adjacent to a central portion thereof in the second direction; a second arrangement structure, wherein the ground contact region is arranged adjacent to a central portion of each of the shared pixels in the first direction and the second direction; and A third arrangement structure, wherein the ground contact region is arranged in an outer portion of each of the shared pixels in the first direction and the second direction.

5. The image sensor according to claim 4, wherein: The active region and the gate corresponding to the PD are arranged in the outer portion of the pixel in the second direction, Wherein, in the third arrangement structure, the ground contact region is arranged in the active region corresponding to a portion of the PD instead of the gate, and Wherein, in the third arrangement structure, the length of the gate in the second direction is greater than the length of the gate in the second direction in the first arrangement structure and the second arrangement structure.

6. The image sensor according to claim 3, wherein: In each sub-shared pixel: The FD region is arranged in the central portion of the sub-sharing pixel, The two internal DTI structures of the sub-shared pixel are separated from each other by the FD region in the second direction, and The outer DTI structure of the sub-sharing pixel extending in the first direction and separating two pixels of the sub-sharing pixel is divided into two parts in the first direction, wherein there is one part on each side of the FD region.

7. The image sensor according to claim 6, wherein: A separation distance between the two inner DTI structures in the second direction and a separation distance between the two portions of the outer DTI structure in the first direction are adjustable.

8. The image sensor according to claim 2, wherein: The width of the inner DTI structure in the first direction and the width of the outer DTI structure in the first direction or the second direction are adjustable.

9. The image sensor according to claim 2, further comprising: a reset gate disposed in one pixel of each shared pixel at an inner portion of the shared pixel; as well as a source follower gate disposed in at least one other pixel of each shared pixel at a position adjacent to the reset gate at the inner portion of the shared pixel, In which, in each of the sub-shared pixels, two FD regions are set corresponding to the two pixels of the sub-shared pixel, and the two FD regions are connected to the source follower gate through wiring, or one FD region is set and shared by the two pixels of the sub-shared pixel, and the one FD region is connected to the source follower gate through wiring.

10. The image sensor according to claim 2, wherein: In each of the sub-shared pixels: Two FD regions are provided corresponding to two pixels of the sub-sharing pixel, and The ground contact regions of the two pixels are disposed in an outer portion of each of the shared pixels in the first direction and adjacent to a central portion thereof in the second direction.

11. The image sensor according to claim 2, wherein: In each of the sub-shared pixels: Two FD regions are provided corresponding to two pixels of the sub-sharing pixel, and Wherein, in each of the shared pixels: A ground contact area is provided in a central portion in the first direction and the second direction, and The outer DTI structures extending in the first direction and the outer DTI structures extending in the second direction are each separated by the ground contact region.

12. The image sensor according to claim 2, further comprising a microlens covering the sub-shared pixel, in, The image sensor performs autofocus.

13. The image sensor according to claim 1, wherein: Two TGs are arranged on each of the PDs.

14. An image sensor, comprising: A shared pixel, wherein the shared pixel includes four pixels, each of the four pixels includes two PDs arranged side by side in a first direction, the PDs being photodiodes; A DTI structure, wherein the DTI is deep trench isolation, and the DTI structure comprises: an inner DTI structure, which extends in a second direction perpendicular to the first direction and separates the two PDs of each of the four pixels from each other in the first direction; and an outer DTI structure, which extends in the first direction and the second direction and separates the four pixels from each other in the first direction and the second direction; An FD region, the FD being a floating diffusion, the FD region being disposed between a central portion of the outer DTI structure extending along the first direction and an edge of the inner DTI structure; a plurality of TGs, the TGs being transfer gates, the plurality of TGs being arranged adjacent to the FD region such that at least one TG among the plurality of TGs is disposed on each PD; a reset gate disposed at an inner portion of the shared pixel in any one of the four pixels of the shared pixel; and a source follower gate disposed at the inner portion of the shared pixel in at least one other pixel of the four pixels of the shared pixel and adjacent to the reset gate, The two PDs of each pixel share the FD region.

15. The image sensor according to claim 14, wherein: Each group of two pixels adjacent to each other in the second direction among the four pixels forms a sub-shared pixel, The shared pixel includes two sub-shared pixels adjacent to each other in the first direction, The FD region is disposed between two pixels of each of the sub-sharing pixels, and The four PDs of each of the sub-sharing pixels share the FD region of the sub-sharing pixel.

16. The image sensor according to claim 15, wherein: Each sub-shared pixel includes a ground contact region, and The ground contact area is arranged in one of the following: a first arrangement structure, wherein the ground contact region is arranged in an outer portion of the shared pixel in the first direction and adjacent to a central portion thereof in the second direction; A second arrangement structure, wherein the ground contact region is arranged adjacent to a central portion of the shared pixel in the first direction and the second direction; and A third arrangement structure, wherein the ground contact region is arranged in an outer portion of the shared pixel in the first direction and the second direction.

17. The image sensor according to claim 15, wherein: In each sub-shared pixel: Two FD regions are provided corresponding to two pixels of the sub-shared pixel. The ground contact area of ​​the shared pixel is disposed in a central portion of the shared pixel in the first direction and the second direction, and In the shared pixel, the outer DTI structure extending in the first direction and the outer DTI structure extending in the second direction are each separated by the ground contact region.

18. The image sensor according to claim 14, wherein: The two FD regions of the shared pixel are connected to the source follower gate through wiring, or the four FD regions of the shared pixel are connected to the source follower gate through wiring.

19. An image sensor, comprising: A shared pixel, wherein the shared pixel includes four pixels, each of the four pixels includes two PDs arranged side by side in a first direction, the PDs being photodiodes; A DTI structure, wherein the DTI is deep trench isolation, and the DTI structure comprises: an inner DTI structure, which extends in a second direction perpendicular to the first direction and separates the two PDs of each of the four pixels from each other in the first direction; and an outer DTI structure, which extends in the first direction and the second direction and separates the four pixels from each other in the first direction and the second direction; an FD region, the FD being a floating diffusion, the FD region being disposed between a central portion of the outer DTI structure and an edge of the inner DTI structure extending along the first direction; and a plurality of TGs, the TGs being transfer gates, the plurality of TGs being arranged adjacent to the FD region such that at least one TG among the plurality of TGs is disposed on each PD; wherein each group of two pixels adjacent to each other in the second direction among the four pixels forms a sub-shared pixel, The shared pixel includes two sub-shared pixels adjacent to each other in the first direction, The FD region is disposed between two pixels of each of the sub-sharing pixels, and The four PDs of each of the sub-sharing pixels share the FD region of the sub-sharing pixel.

20. The image sensor according to claim 19, wherein: Each sub-shared pixel includes a ground contact region, and The ground contact area is arranged in one of the following: a first arrangement structure, wherein the ground contact region is arranged in an outer portion of the shared pixel in the first direction and adjacent to a central portion thereof in the second direction; A second arrangement structure, wherein the ground contact region is arranged adjacent to a central portion of the shared pixel in the first direction and the second direction; and A third arrangement structure, wherein the ground contact area is arranged in an outer portion of the shared pixel in the first direction and the second direction, The two FD regions of the shared pixel are connected to the source follower gate through wiring.

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