Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a silicon wafer, and carrying out the texturing of the surface of the silicon wafer, so as to form a textured surface; depositing a first protective layer on the first surface of the silicon wafer; preparing a smooth surface on the second surface of the silicon wafer, removing the textured surface of the second surface of the silicon wafer, the smooth surface comprising more than one planar groove with different depths, and the planar groove comprising more than one smooth step; removing the first protection layer on the first surface of the silicon wafer through acid pickling; depositing passivation layers on the first surface and the second surface of the silicon wafer, and depositing transparent conductive film layers on the passivation layers; metal grid lines are prepared on the transparent conductive thin film layer of the silicon wafer, and the plane where the positions of the metal grid lines on the second face of the silicon wafer are located is lower than the plane where the positions without the metal grid lines are located, so that the contact area of the metal grid lines and the silicon wafer is increased. According to the manufacturing method of the semiconductor device provided by the invention, the adhesive force of the grid line and the silicon wafer is increased, and the contact resistance is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the vigorous development of the photovoltaic industry, more and more photovoltaic cells are developing rapidly, among which crystalline silicon cells have occupied 90% of the market. Crystalline silicon cells include mainstream cells such as heterojunction cells, tunnel oxide passivation contact cells, and back contact cells. Among them, the current conversion efficiency of heterojunction cells has reached 26.81%. The preparation process of heterojunction cells is simple and only requires four processes. Compared with other crystalline silicon cells, it does not require high-temperature processes and the overall energy consumption is relatively low, but the process requirements are extremely strict.

[0003] With the development of heterojunction cells, the conversion efficiency has gradually increased and is close to the conversion efficiency limit of crystalline silicon cells. Therefore, the existing structure needs to be upgraded. The upgraded cells that have appeared are single-sided velvet cells, that is, the front of the cell is a velvet structure, and the back is a flat structure. The conversion efficiency is improved by reusing light. However, when the back of the silicon wafer is flat, there will be problems such as low adhesion between the gate line and the silicon wafer, and high contact resistance between the gate line and the silicon wafer. Therefore, it is necessary to propose a new method for manufacturing semiconductor devices to solve the above problems. Summary of the invention

[0004] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0005] In view of the existing problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a silicon wafer, and texturing a surface of the silicon wafer to form a textured surface;

[0007] Depositing a first protective layer on the first surface of the silicon wafer;

[0008] Preparing a smooth surface on the second surface of the silicon wafer, removing the velvet surface of the second surface of the silicon wafer, wherein the smooth surface comprises more than one planar groove with different depths, and the planar groove comprises more than one smooth step;

[0009] Removing the first protective layer on the first surface of the silicon wafer by pickling;

[0010] Depositing a passivation layer on the first surface and the second surface of the silicon wafer, and depositing a transparent conductive thin film layer on the passivation layer;

[0011] Metal gate lines are prepared on the transparent conductive film layer of the silicon wafer, and the plane where the metal gate lines on the second surface of the silicon wafer are located is lower than the plane where no metal gate lines are located, so as to increase the contact area between the metal gate lines and the silicon wafer.

[0012] In one embodiment of the present application, the smooth surface is a silicon wafer surface without a pyramid structure, and the reflectivity range of the smooth surface is greater than 45%;

[0013] The depth of the planar groove ranges from 1 to 50 nm, and the width ranges from 1 to 30 um;

[0014] The planar grooves are evenly distributed, and the width between the planar grooves is the distance between the metal grid lines;

[0015] The depth of the smooth steps inside the planar grooves ranges from 1 to 10 nm.

[0016] In one embodiment of the present application, preparing a smooth surface on the second surface of the silicon wafer to remove the velvet surface of the second surface of the silicon wafer includes:

[0017] Laser is used to remove different thicknesses of the second surface of the silicon wafer to form the smooth surface.

[0018] In one embodiment of the present application, preparing a smooth surface on the second surface of the silicon wafer to remove the velvet surface of the second surface of the silicon wafer includes:

[0019] Depositing a second protective layer on the second surface of the silicon wafer, wherein the second protective layer is a uniformly distributed protective layer of different thicknesses, and the thickness of the second protective layer at the metal gate line position is less than the thickness of the second protective layer at the position without the metal gate line;

[0020] The second surface after the protective layer is deposited is polished to remove the velvet surface of the second surface of the silicon wafer to form the smooth surface.

[0021] In one embodiment of the present application, the polishing of the second surface after the protective layer is deposited includes:

[0022] During the polishing process, the thickness of the second protective layer is different. The thinner the protective layer is, the greater the polishing and etching depth is, and the deeper the silicon wafer is etched.

[0023] In one embodiment of the present application, depositing a second protective layer on the second surface of the silicon wafer includes:

[0024] Depositing a third protective layer on the second surface of the silicon wafer, and removing the third protective layer with different thicknesses using a laser to form second protective layers with different thicknesses;

[0025] Alternatively, a second protective layer of different thicknesses is deposited on the second surface of the silicon wafer using a mask.

[0026] In one embodiment of the present application, the second protective layer is distributed in an array, and the second protective layer includes more than one array;

[0027] Each array of the array distribution decreases from the first thickness in sequence until it decreases to the nth thickness of 0, and then increases from the nth thickness to the first thickness in sequence, and the lateral distance of each thickness in the array is 0; n is a positive integer;

[0028] The width of each array after removing the two first thicknesses is in the range of 1-30 um;

[0029] The width between the nth thickness of each array is the distance between the metal gate lines.

[0030] In one embodiment of the present application, depositing a second protective layer of different thicknesses on the second surface of the silicon wafer using a mask includes:

[0031] When depositing the first thickness, the remaining areas are blocked by a mask. When depositing the second thickness, the remaining areas except the first and second thickness areas are blocked by a mask. When depositing the third thickness, the remaining areas except the first, second and third thickness areas are blocked by a mask... until each thickness is completely deposited.

[0032] In one embodiment of the present application, the plane where the metal gate lines are located is lower than the plane where no metal gate lines are located, and during the gate line printing process, slurry powder is embedded in the silicon wafer to increase the surface area of ​​the metal gate lines in contact with the silicon wafer.

[0033] Another aspect of an embodiment of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by the method as described above.

[0034] According to the method for manufacturing a semiconductor device provided by the present invention, texturing is performed on the surface of a silicon wafer, a smooth surface is prepared on the second side of the silicon wafer, and the texturing on the second side of the silicon wafer is removed, so that the second side of the silicon wafer forms a smooth surface of uniformly distributed different depths, thereby increasing the contact area between the metal gate line and the silicon wafer, increasing the adhesion between the metal gate line and the silicon wafer, improving the pulling force, and reducing the contact resistance, thereby improving the photoelectric conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0036] Figure 1 A cross-sectional schematic diagram of a semiconductor device manufactured by the prior art is shown;

[0037] Figure 2 A cross-sectional schematic diagram of another semiconductor device manufactured by the prior art is shown;

[0038] Figure 3 A schematic flow chart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention;

[0039] Figure 4 A schematic cross-sectional view of a semiconductor device obtained by a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0040] Figure 5 A schematic cross-sectional view of a semiconductor device obtained by a method for manufacturing a semiconductor device according to another embodiment of the present invention is shown.

[0041] Figure 6 A schematic diagram showing different thicknesses of the protective layer of a silicon wafer after etching;

[0042] Figure 7 A schematic diagram showing the embedding of slurry powder into a silicon wafer after the metal gate line is prepared;

[0043] Figure 8 The test data of the electrical performance test and the tensile test are shown.

[0044] Figure numerals: 1, silicon wafer; 2, passivation layer; 3, N-type amorphous / microcrystalline silicon film; 4, P-type amorphous / microcrystalline silicon film; 5, transparent conductive film layer; 6, metal gate line; 11, first depth; 12, second depth. DETAILED DESCRIPTION

[0045] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0046] It should be understood that the present invention can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0047] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0048] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0051] Figure 1 A cross-sectional schematic diagram of a semiconductor device manufactured by the prior art is shown. Figure 1 As shown, the silicon wafer 1 is cleaned, the damaged layer and impurities on the surface of the silicon wafer 1 are removed, and the silicon wafer 1 is textured to prepare a double-sided textured silicon wafer 1 substrate. A passivation layer 2 is deposited on the front of the silicon wafer 1, and an N-type amorphous / microcrystalline silicon film 3 is doped. A passivation layer 2 is deposited on the back of the silicon wafer 1, and a P-type amorphous / microcrystalline silicon film 4 is doped. A transparent conductive film layer 5 is deposited on both sides of the silicon wafer 1, and metal gate lines 6 are printed on both sides of the silicon wafer 1. The gate lines 6 are dried and cured to prepare a finished battery cell.

[0052] Figure 2 A cross-sectional schematic diagram of another semiconductor device manufactured by the prior art is shown. Figure 2 As shown, the silicon wafer 1 is cleaned, the damaged layer and impurities on the surface of the silicon wafer 1 are removed, and the silicon wafer 1 is textured to prepare a double-sided textured silicon wafer 1 substrate. The front of the silicon wafer 1 after textured is protected, and a silicon oxide film is deposited on the front of the silicon wafer 1, and the back is not treated. The back of the silicon wafer 1 is polished, and the back of the silicon wafer 1 is etched with a sodium hydroxide solution to remove the velvet on the back, so that the back is a planar structure. The silicon wafer 1 is cleaned and the silicon oxide film layer on the front is removed. A passivation layer 2 is deposited on the front of the silicon wafer 1, and an N-type amorphous / microcrystalline silicon film 3 is doped. A passivation layer 2 is deposited on the back of the silicon wafer 1, and a P-type amorphous / microcrystalline silicon film 4 is doped. A transparent conductive film is deposited on both sides of the silicon wafer 1, and metal gate lines 6 are printed on both sides of the silicon wafer 1. The gate lines 6 are dried and cured to prepare a finished battery cell.

[0053] That is, the front of the cell is a velvet structure, and the back is a flat structure, and the conversion efficiency is improved by reusing light. However, when the back of the silicon wafer 1 is a flat surface, the adhesion between the gate line 6 and the silicon wafer 1 is low, and the contact resistance between the gate line 6 and the silicon wafer 1 is high.

[0054] Therefore, in view of the above technical problems, the present invention provides a method for manufacturing a semiconductor device. Figure 3 A flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown; Figure 4 A schematic cross-sectional view of a semiconductor device obtained by a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown; Figure 5 A schematic cross-sectional view of a semiconductor device obtained by a method for manufacturing a semiconductor device according to another embodiment of the present invention is shown.

[0055] Combine the following Figure 3 as well as Figure 4 and Figure 5 A method for manufacturing a semiconductor device according to an embodiment of the present invention is described in detail.

[0056] First refer to Figure 3 A method for manufacturing a semiconductor device according to an embodiment of the present invention is described. Figure 3 As shown, the method for manufacturing a semiconductor device includes the following steps:

[0057] In step S110, a silicon wafer is provided, and a surface of the silicon wafer is textured to form a textured surface.

[0058] In step S120 , a first protective layer is deposited on the first surface of the silicon wafer.

[0059] In step S130, a smooth surface is prepared on the second surface of the silicon wafer, and the velvet surface of the second surface of the silicon wafer is removed to form a smooth surface, wherein the smooth surface includes more than one planar grooves of different depths, and the planar grooves include more than one smooth step.

[0060] In step S140, the first protective layer on the first surface of the silicon wafer is removed by pickling.

[0061] In step S150, a passivation layer is deposited on the first surface and the second surface of the silicon wafer, and a transparent conductive thin film layer is deposited on the passivation layer.

[0062] In step S160, metal gate lines 6 are prepared on the transparent conductive film layer 5 of the silicon wafer 1, and the plane where the metal gate lines 6 on the second surface of the silicon wafer 1 are located is lower than the plane where there are no metal gate lines 6, so as to increase the contact area between the metal gate lines 6 and the silicon wafer 1.

[0063] The method for manufacturing a semiconductor device of the present invention forms a uniformly distributed smooth surface of different depths on the second surface of the silicon wafer by texturing the surface of a silicon wafer, preparing a smooth surface on the second surface of the silicon wafer, and removing the texturing on the second surface of the silicon wafer, thereby increasing the contact area between the metal gate line and the silicon wafer, increasing the adhesion between the metal gate line and the silicon wafer, improving the pulling force, reducing the contact resistance, and improving the photoelectric conversion efficiency.

[0064] Combine the following Figure 4 Figure 5 An exemplary description is given of an implementation process of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0065] The semiconductor device may be any suitable device known to those skilled in the art. In this embodiment, the technical solution of the present invention is explained and illustrated mainly by taking the case where the semiconductor device is a solar cell as an example.

[0066] In the embodiment of the present application, in step S110 , a silicon wafer 1 is provided, and a surface of the silicon wafer 1 is textured to form a textured surface.

[0067] The silicon wafer 1 is divided into single crystal silicon and polycrystalline silicon according to different crystal orientations. Single crystal silicon has the highest conversion efficiency when used in solar cells and still occupies a dominant position in large-scale applications and industrial production, so single crystal silicon is used. In one embodiment, before the surface of the silicon wafer 1 is textured to form a velvet surface, the method also includes: using an alkaline solution to clean the silicon wafer 1 to remove the damaged layer and impurities on the surface of the silicon wafer 1. The cleaning temperature range is 20-80°C, and the cleaning time range is 100-600s. Alkaline solutions include sodium hydroxide, hydrogen peroxide, hydrochloric acid, hydrofluoric acid, ozone water, and deionized water. The silicon wafer 1 needs to be cleaned after a series of processing procedures. The purpose of cleaning is to eliminate various pollutants adsorbed on the surface of the silicon wafer 1. The cleanliness of the cleaning directly affects the yield and reliability of the battery cell.

[0068] In one embodiment, the surface of the silicon wafer 1 is textured to form a velvet surface, including: using a texturing solution to texture the surface of the silicon wafer 1, the texturing temperature range is 70-85°C, and the texturing time range is 300-800s. A pyramid structure is prepared on the surface of the silicon wafer 1 to form a velvet surface, the velvet surface size range is 1-4um, and the velvet surface reflectivity range is 9-12%. The texturing solution includes sodium hydroxide, a texturing additive, and deionized water. Texturing is the first process in manufacturing crystalline silicon cells, also known as "surface texturing." An effective velvet structure causes the incident light to be reflected and refracted multiple times on the surface of the silicon wafer 1, which increases the absorption of light, reduces the reflectivity, and helps to improve the performance of the battery. In the preparation process of the battery, both sides of the silicon wafer 1 are velvet after texturing.

[0069] In an embodiment of the present application, a first protective layer is deposited on the first surface of the silicon wafer 1 in step S120. After texturing, both sides of the silicon wafer 1 are velvet surfaces, and then the velvet surface on one side needs to be processed so that its surface is etched into a plane. Before etching the velvet surface on one side, the velvet surface on the other side needs to be protected to ensure that the velvet surface on the other side is not damaged during the etching process. After texturing, the silicon wafer 1 is masked, and a first protective layer is deposited on the first surface of the silicon wafer 1. The protective layer can be a silicon oxide or silicon nitride layer, and the deposition thickness ranges from 10 to 100 nm.

[0070] In an embodiment of the present application, in step S130, a smooth surface is prepared on the second surface of the silicon wafer 1, and the velvet surface of the second surface of the silicon wafer 1 is removed. The smooth surface includes more than one planar grooves of different depths, and the planar grooves include more than one smooth step.

[0071] After the second surface of the silicon wafer 1 is made into a plane, the photoelectric conversion efficiency is further improved. The plane is conducive to the photons that should escape from the inside of the silicon wafer 1 to return to the inside of the silicon wafer 1 through plane reflection, which increases the utilization rate of light, which is mainly reflected in the improvement of open circuit voltage and short circuit current. Since the surface of the processed silicon wafer 1 is flat and has low roughness, the surface area is greatly reduced, the surface recombination loss is limited, and the photoelectric conversion efficiency is further improved.

[0072] In one embodiment, the smooth surface is a silicon wafer 1 surface without a pyramid structure, and the smooth surface reflectivity range is greater than 45%. The depth range of the planar groove is 1-50nm, and the width range is 1-30um. The planar grooves are evenly distributed, and the width between the planar grooves is the distance between the metal grid lines 6. The depth range of the smooth steps inside the planar grooves is 1-10nm.

[0073] In one embodiment, a smooth surface is prepared on the second surface of the silicon wafer 1 to remove the velvet surface on the second surface of the silicon wafer 1 , including: using a laser to remove different thicknesses of the second surface of the silicon wafer 1 to form a smooth surface.

[0074] The second side of the silicon wafer 1 may not be coated for protection, and the laser may be directly used to remove different thicknesses of the second side. The laser is used to remove the second thickness area, and the thickness is 1-10nm. Then, the laser is used to remove the third thickness area, and the thickness is 1-20nm. Then, the fourth thickness area is removed, and the thickness is 1-30nm... until a smooth surface is finally obtained. The smooth surface means that there is no pyramid structure on the surface of the silicon wafer 1, and the reflectivity range of the smooth surface is greater than 45%;

[0075] In one embodiment, a smooth surface is prepared on the second surface of the silicon wafer 1 to remove the velvet on the second surface of the silicon wafer 1, including: depositing a second protective layer on the second surface of the silicon wafer 1, the second protective layer being a uniformly distributed protective layer of different thicknesses, the thickness of the second protective layer at the metal gate line position being less than the thickness of the second protective layer at the position without the metal gate line; polishing the second surface after depositing the protective layer to remove the velvet on the second surface of the silicon wafer 1 to form a smooth surface.

[0076] After texturing, the silicon wafer 1 is masked, and a second protective layer is deposited on the second side of the silicon wafer. The protective layer on the second side of the silicon wafer 1 is deposited as a uniformly distributed silicon oxide or silicon nitride film layer of different thicknesses. When preparing the protective layer, a uniformly distributed protective film layer of different thicknesses is prepared on the side to be etched, especially at the gate line position, the film layer is thinner, and at the position without the gate line, the film layer is thicker.

[0077] The second surface after the protective layer is deposited is polished to remove the velvet on the second surface of the silicon wafer to form a smooth surface, and the second surface of the silicon wafer 1 is etched with a sodium hydroxide solution to remove the velvet on the second surface, so that the second surface forms a planar structure with uniform distribution and different depths under the action of oxide layers of different thicknesses. Through alkaline polishing, defects and impurities on the silicon surface can be removed to generate a smooth surface, thereby improving the energy conversion efficiency of the battery.

[0078] like Figure 6 As shown, in one embodiment, during the polishing process, due to the different thicknesses of the second protective layer, the thinner the protective layer, the greater the polishing and etching depth, and the deeper the etching depth of the silicon wafer 1. The smooth surface obtained by the polishing process is a surface of the silicon wafer 1 without a pyramid structure, and the smooth surface reflectivity range is greater than 45%. Inside the etched silicon wafer, the first depth 11 is greater than the second depth 12.

[0079] During etching, the etching depth of the silicon wafer 1 at the position of the gate line 6 is greater, and the etching depth of the silicon wafer 1 at the position without the gate line 6 is smaller, and it is ensured that the velvet surface is completely etched into a plane, so as to ensure the utilization rate of the silicon wafer 1 to light, and the plane at the position of the gate line 6 is lower than the plane at the position without the gate line 6. During the printing process of the gate line 6, the slurry powder is embedded inside, increasing the contact area between the gate line 6 and the silicon substrate, thereby increasing the adhesion, improving the pulling force, and reducing the contact resistance with the silicon substrate. Different gradient etching of the surface is performed on the basis of the original plane, so as to ensure that the plane structure does not change significantly, and also stabilize the utilization rate of light inside the silicon wafer 1. After the gate line 6 is printed, the slurry powder can enter the position where the etching depth of the silicon wafer 1 is greater, improve the adhesion between the gate line 6 and the silicon wafer 1, and improve the pulling force.

[0080] In one embodiment, a second protective layer is deposited on the second surface of the silicon wafer 1, including: depositing a third protective layer on the second surface of the silicon wafer 1, and using a laser to remove different thicknesses of the third protective layer to form a second protective layer of different thicknesses; or using a mask to deposit a second protective layer of different thicknesses on the second surface of the silicon wafer 1.

[0081] Exemplarily, the above-mentioned second protective layer can be completed by using a laser. A chain oxidation furnace is used to perform full coating on the second side of the silicon wafer 1, and the deposition thickness is 1-50nm. Then, a laser is used to remove the second thickness area with a thickness of 1-10nm. Then, a laser is used to remove the third thickness area with a thickness of 1-20nm. Then, the fourth thickness area is removed with a thickness of 1-30nm... until the film layer is completely removed in the final thickness area to obtain a second protective layer of different thicknesses.

[0082] In one embodiment, a second protective layer of different thicknesses is deposited on the second surface of the silicon wafer 1 using a mask, including: when depositing the first thickness, the remaining areas are blocked using a mask, when depositing the second thickness, the remaining areas except the first thickness and the second thickness areas are blocked using a mask, when depositing the third thickness, the remaining areas except the first thickness, the second thickness and the third thickness areas are blocked using a mask, etc., until each thickness is fully deposited. A chain oxidation furnace can be selected for thin film deposition, and a mask can be used to deposit second protective layers of different thicknesses respectively.

[0083] In one embodiment, the second protective layer is distributed in an array, and the second protective layer includes more than one array. Each array of the array distribution decreases from the first thickness until it decreases to the nth thickness of 0, and then increases from the nth thickness to the first thickness. The lateral distance of each thickness in the array is 0, and n is a positive integer. The width of each array after removing the two first thicknesses ranges from 1 to 30 um, and the width between the nth thickness of each array is the distance between the metal grid lines 6.

[0084] The thickness of the second protective layer is the first thickness, the second thickness, the third thickness, ... the nth thickness, ... the third thickness, the second thickness, the first thickness, starting from a long side of the silicon wafer 1, and is distributed in an array. The thickness control method is the first thickness> the second thickness> the third thickness> ...> the nth thickness. The lateral distance between each thickness is 0, and the connection is tight. The first thickness is controlled at 3-50nm, the second thickness is controlled at 2-40nm, the third thickness is controlled at 1-30nm, ..., the nth thickness is controlled at 0nm, and it is in a decreasing trend. The thinnest film layer is not deposited, and the thickness is 0nm. The width between the second thickness from the left to the second thickness from the right in each array is controlled at 1-30um, and the width between the nth thicknesses between adjacent arrays is equal to the spacing of the screen grid lines 6 of the screen printing;

[0085] In one embodiment, Figure 4 As shown, the second side of the silicon wafer 1 is masked, and a uniformly distributed silicon oxide film of different thicknesses is deposited on the back side. The thicknesses are the first thickness, the second thickness, the third thickness, the second thickness, the first thickness, the second thickness, the third thickness, the second thickness, the first thickness, the first thickness, etc. from left to right starting from the long side. The distance between each thickness is 0, which is closely connected. The width of the adjacent third thickness on the surface of the silicon wafer 1 is the same as the distance between the printed gate lines 6. The width of the adjacent second thickness plus the third thickness plus the second thickness on the surface is 30um. The deposition equipment uses a chain oxidation furnace. First, the first thickness is deposited. Except for the first thickness, the remaining areas are blocked with a mask plate, and 10nm is deposited. Then the second thickness is deposited. Except for the first thickness and the second thickness areas, the remaining areas are blocked with a mask plate, and 10nm is deposited. The third thickness area is not subjected to coating treatment. After the coating treatment, the first thickness of the silicon wafer 1 is 20nm, the second thickness is 10nm, and the third thickness is 0nm.

[0086] In one embodiment, Figure 5 As shown, the second side of the silicon wafer 1 is masked, and a uniformly distributed silicon oxide film of different thicknesses is deposited on the second side. The thicknesses are the first thickness, the second thickness, the third thickness, the fourth thickness, the third thickness, the second thickness, the first thickness, the second thickness, the third thickness, the fourth thickness, the third thickness, the second thickness, the first thickness, the second thickness, the third thickness, the fourth thickness, the third thickness, the second thickness, the first thickness... starting from the long side, the distance between each thickness is 0, which is closely connected. The width of the adjacent fourth thickness on the surface of the silicon wafer 1 is the same as the distance between the printed gate lines 6. The width of the adjacent second, third, fourth thickness plus the third and second thickness on the surface is 30um. The deposition equipment uses a chain oxidation furnace. First, the first thickness is deposited. The mask is used to block the remaining areas except the first thickness. The deposition is 10nm. Then the second thickness is deposited. The mask is used to block the remaining areas except the first thickness and the second thickness areas. The deposition is 10nm. Then the third thickness is deposited. The mask is used to block the remaining areas except the first thickness and the second thickness areas. The deposition is 10nm. The fourth thickness area is not coated. After the coating treatment, the first thickness of the silicon wafer 1 is 30 nm, the second thickness is 20 nm, the third thickness is 10 nm, and the fourth thickness is 0 nm.

[0087] In an embodiment of the present application, the first protective layer on the first surface of the silicon wafer 1 is removed by pickling in step S140. The first protective layer on the first surface of the silicon wafer 1 is cleaned, and the cleaning solution includes hydrofluoric acid and deionized water. The cleaning temperature is controlled at 20-30° C. and the cleaning time is controlled at 100-600 seconds. The silicon wafer 1 is cleaned to remove the silicon oxide film layer on the first surface.

[0088] In an embodiment of the present application, a passivation layer 2 is deposited on the first and second surfaces of the silicon wafer 1 in step S150, and a transparent conductive film layer 5 is deposited on the passivation layer 2. The passivation layer 2 is deposited on the front and back surfaces of the cleaned silicon wafer 1, and a doped amorphous silicon or microcrystalline silicon film layer is deposited. A passivated amorphous silicon film and a doped N-type amorphous or microcrystalline silicon film 3 are deposited on the front surface of the silicon wafer 1, and a passivated amorphous silicon film and a doped P-type amorphous or microcrystalline silicon film 4 are deposited on the back surface of the silicon wafer 1. A transparent conductive film layer is deposited on the front and back surfaces of 1 after the passivation layer 2 is deposited.

[0089] In an embodiment of the present application, in step S160, a metal grid line 6 is prepared on the transparent conductive film layer 5 of the silicon wafer 1, the thickness of the second protective layer at the metal grid line 6 position is less than the thickness of the second protective layer at the position without the metal grid line 6, and the plane where the metal grid line 6 position is located is lower than the plane where the position without the metal grid line 6 is located, so as to increase the surface area of ​​the metal grid line 6 in contact with the silicon wafer 1. The metal grid lines 6 are printed on both sides of the silicon wafer 1, and the grid lines 6 are dried and cured to prepare finished battery cells. As a key material affecting the conductivity of solar cells, the height, width, quantity and other factors of the battery grid lines themselves will determine the photoelectric conversion rate of the solar cell.

[0090] like Figure 7 As shown, in one embodiment, the plane where the metal gate line 6 is located is lower than the plane where the position without the metal gate line 6 is located, and the slurry powder is embedded in the silicon wafer 1 during the printing process of the gate line 6 to increase the surface area of ​​the metal gate line 6 in contact with the silicon wafer 1. During the printing process of the gate line 6, the contact area between the slurry powder and the silicon wafer 1 at different etching depths increases, which can reduce the contact resistance between the slurry and the silicon wafer 1 and improve the conversion efficiency.

[0091] like Figure 8 As shown, the above four embodiments are subjected to electrical performance tests and tension tests. From the analysis of the data, it can be seen that Example 2 makes certain adjustments to the back side on the basis of Example 1. After the back side is prepared as a plane, the conversion efficiency is improved by 0.213%. Since the plane is conducive to the passivation of the amorphous silicon film, and the plane of the back side is conducive to the photons that should have escaped from the inside of the silicon wafer 1 to return to the inside of the silicon wafer 1 through plane reflection, the utilization rate of light is increased, which is mainly manifested in the improvement of open circuit voltage and short circuit current. However, due to the planar structure, the contact area between the gate line 6 and the silicon wafer 1 is reduced after printing, resulting in a certain degree of decrease in the tension on the back side. In contrast, Examples 3 and 4 make further adjustments to the back side on the basis of Example 2, add grooves of different depths on the back side, increase the contact area between the gate line 6 slurry powder and the silicon wafer 1, increase the adhesion between the gate line 6 and the silicon wafer 1, and reduce the contact resistance. The conversion efficiency is increased by 0.103% and 0.134%, respectively, and the tension of the battery cell is improved.

[0092] The method for manufacturing a semiconductor device of the present invention forms a uniformly distributed smooth surface of different depths on the second surface of the silicon wafer by texturing the surface of a silicon wafer, preparing a smooth surface on the second surface of the silicon wafer, and removing the texturing on the second surface of the silicon wafer, thereby increasing the contact area between the metal gate line and the silicon wafer, increasing the adhesion between the metal gate line and the silicon wafer, improving the pulling force, reducing the contact resistance, and improving the photoelectric conversion efficiency.

[0093] The present invention has been described by the above embodiments, but it should be understood that the above embodiments are only for the purpose of example and description, and are not intended to limit the present invention to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present invention is not limited to the above embodiments, and more variations and modifications can be made according to the teachings of the present invention, and these variations and modifications all fall within the scope of the protection claimed by the present invention. The protection scope of the present invention is defined by the attached claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a silicon wafer, and texturing a surface of the silicon wafer to form a textured surface; Depositing a first protective layer on the first surface of the silicon wafer; Preparing a smooth surface on the second surface of the silicon wafer, removing the velvet surface of the second surface of the silicon wafer, wherein the smooth surface comprises more than one planar groove with different depths, and the planar groove comprises more than one smooth step; Removing the first protective layer on the first surface of the silicon wafer by pickling; Depositing a passivation layer on the first surface and the second surface of the silicon wafer, and depositing a transparent conductive thin film layer on the passivation layer; Metal gate lines are prepared on the transparent conductive film layer of the silicon wafer, and the plane where the metal gate lines on the second surface of the silicon wafer are located is lower than the plane where no metal gate lines are located, so as to increase the contact area between the metal gate lines and the silicon wafer.

2. The manufacturing method according to claim 1, characterized in that The smooth surface is a silicon wafer surface without a pyramid structure, and the reflectivity range of the smooth surface is greater than 45%; The depth of the planar groove ranges from 1 to 50 nm, and the width ranges from 1 to 30 um; The planar grooves are evenly distributed, and the width between the planar grooves is the distance between the metal grid lines; The depth of the smooth steps inside the planar grooves ranges from 1 to 10 nm.

3. The manufacturing method according to claim 1, characterized in that: Preparing a smooth surface on the second side of the silicon wafer to remove the velvet surface on the second side of the silicon wafer comprises: Laser is used to remove different thicknesses of the second surface of the silicon wafer to form the smooth surface.

4. The manufacturing method according to claim 1, characterized in that: Preparing a smooth surface on the second side of the silicon wafer to remove the velvet surface on the second side of the silicon wafer comprises: Depositing a second protective layer on the second surface of the silicon wafer, wherein the second protective layer is a uniformly distributed protective layer of different thicknesses, and the thickness of the second protective layer at the metal gate line position is less than the thickness of the second protective layer at the position without the metal gate line; The second surface after the protective layer is deposited is polished to remove the velvet surface of the second surface of the silicon wafer to form the smooth surface.

5. The manufacturing method according to claim 4, characterized in that: The polishing process of the second surface after the protective layer is deposited comprises: During the polishing process, the thickness of the second protective layer is different. The thinner the protective layer is, the greater the polishing and etching depth is, and the deeper the silicon wafer is etched.

6. The manufacturing method according to claim 4, characterized in that: Depositing a second protective layer on the second surface of the silicon wafer comprises: Depositing a third protective layer on the second surface of the silicon wafer, and removing the third protective layer with different thicknesses using a laser to form second protective layers with different thicknesses; Alternatively, a second protective layer of different thicknesses is deposited on the second surface of the silicon wafer using a mask.

7. The manufacturing method according to claim 6, characterized in that: The second protective layer is distributed in an array, and the second protective layer includes more than one array; Each array of the array distribution decreases from the first thickness in sequence until it decreases to the nth thickness of 0, and then increases from the nth thickness to the first thickness in sequence, and the lateral distance of each thickness in the array is 0; n is a positive integer; The width of each array after removing the two first thicknesses is in the range of 1-30 um; The width between the nth thickness of each array is the distance between the metal gate lines.

8. The manufacturing method according to claim 6, characterized in that: Depositing a second protective layer of different thicknesses on the second surface of the silicon wafer using a mask comprises: When depositing the first thickness, the remaining areas are blocked by a mask. When depositing the second thickness, the remaining areas except the first and second thickness areas are blocked by a mask. When depositing the third thickness, the remaining areas except the first, second and third thickness areas are blocked by a mask... until each thickness is completely deposited.

9. The manufacturing method according to claim 1, characterized in that: The plane where the metal gate lines are located is lower than the plane where the non-metal gate lines are located. During the gate line printing process, the slurry powder is embedded in the silicon wafer to increase the surface area of ​​the metal gate lines in contact with the silicon wafer.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 9.

Images