Preparation method and module of joint passivation back contact battery with reverse leakage channel

Abstract

The present invention belongs to the technical field of back contact batteries, and specifically relates to a method and module for preparing a combined passivation back contact battery with a reverse leakage channel, including: S5, performing surface micro-etching on the back side after removing the mask layer, and controlling the etching depth to be 0.5-100Å; S6, depositing a second semiconductor layer on the back side; S7, forming a second opening area; S8, depositing a transparent conductive film layer; S9, forming an isolation groove, and at least part of the edge of the isolation groove is at a distance from the edge of the velvet surface, and within the distance, the corresponding second doped silicon crystal layer, the intrinsic amorphous silicon layer, and the first doped polysilicon layer after surface micro-etching form a reverse leakage channel PN junction. The present invention can form an effective reverse leakage channel that is uniformly distributed, stable and controllable, can avoid regional heating caused by current concentration, thereby protecting the battery cell from damage by hot spots, and at the same time obtaining a higher battery efficiency; the use of bypass diodes can be eliminated, reducing costs and increasing power generation.

Description

Technical Field

[0001] The present invention belongs to the technical field of back contact batteries, and in particular relates to a preparation method and a module of a combined passivation back contact battery with a reverse leakage channel. Background Art

[0002] Solar cell modules are composed of multiple solar cells connected in series, which are connected by wires to form a larger battery module. Usually one or more bypass diodes are placed in parallel at both ends of the battery string. In the absence of obstruction, the solar cell module works normally, and the current flows from the battery cell to the external circuit through the wire. When a part of the battery module is blocked or fails, the battery cell in that part may not be able to generate current normally, or even become a load, consuming the current generated by other batteries, causing a hot spot effect. In this case, the bypass diode starts to work, allowing the current to bypass the damaged or blocked battery string and continue to flow to the external circuit through the diode, thereby protecting the solar cell module from damage.

[0003] However, whenever a number of cells in a battery string are blocked or damaged, the number of blocked or damaged cells makes the battery string reach the bypass diode operating voltage, then the battery string (such as each battery string of crystalline silicon cells connected in parallel with bypass diodes has 20-24 cells) will be short-circuited (equivalent to being short-circuited) due to the operation of the bypass diode, and will not participate in the power generation of the component, resulting in a loss of power generation. However, if the bypass diode is not set, once part of the battery back is blocked and becomes a load, the local battery will be severely heated and the component will be damaged, causing greater damage. If a bypass diode is added to each battery cell, it will incur extremely high costs.

[0004] Although CN118630076A discloses that at least part of the overlapping area between two semiconductors of the finger-like cross structure is a reverse leakage area, its reverse leakage channel needs to be formed by natural defects generated when the amorphous film layer is deposited. Since the generation of defects is random, it is impossible to accurately set the resistance of all reverse leakage channels, which is not conducive to the uniform distribution of leakage current. The reverse leakage channel is unstable and cannot achieve the effect of truly replacing the bypass diode; that is, the final actual reverse current concentration position is unpredictable due to the limitation of defect distribution. Under special circumstances, the leakage may still be concentrated in certain positions to produce a hot spot effect.

[0005] Although CN118472073A discloses that only a part of the first doped semiconductor part and only a part of the second doped semiconductor part are electrically connected to form a reverse leakage area. The reverse leakage area is at least arranged in the edge area, and the distribution density of the reverse leakage area in the edge area is greater than the distribution density of the reverse leakage area in the middle area. However, it sets a reverse leakage channel at the edge of the silicon wafer, but the two electrodes of opposite polarities are not connected to the two ends of the reverse leakage channel. For example, in the attached figure, electrodes 28 and 27 are electrodes of opposite polarities, but the reverse leakage channel is only connected to electrode 28, and there is no electrode at the other end, so the reverse leakage channel cannot play the role of the reverse leakage channel.

[0006] The early patents had a similar structure, but did not make special settings for the reverse leakage channel to form a stable and controllable reverse channel.

[0007] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0008] The purpose of the present invention is to overcome the defects of the prior art that the reverse leakage channel of the combined passivated back contact battery is uncontrollable, unstable, and cannot truly replace the bypass diode. A method and module for preparing a combined passivated back contact battery with a reverse leakage channel are provided, which can form an effective reverse leakage channel that is evenly distributed, stable and controllable, and can avoid regional heating caused by current concentration, thereby protecting the battery cell from damage by hot spots, and at the same time obtaining higher battery efficiency; the use of the bypass diode can be eliminated, reducing costs and increasing power generation.

[0009] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a method for preparing a combined passivation back contact battery with a reverse leakage channel, comprising:

[0010] S1, provide silicon wafers;

[0011] S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer which are arranged in sequence;

[0012] S3, performing a first etching opening on the back surface obtained in S2 to form a first opening area;

[0013] S4, forming a textured surface at least in the first opening area by texturing cleaning, and removing the mask layer; further comprising the following steps:

[0014] S5, performing surface micro-etching on the back side after removing the mask layer, and controlling the etching depth to be 0.5-100Å;

[0015] S6, depositing a second semiconductor layer on the back side, wherein the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon crystal layer arranged in sequence;

[0016] S7, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a second opening area spaced apart from the first opening area;

[0017] S8, depositing a transparent conductive film layer on the back surface obtained in S7; and controlling the sheet resistance of the transparent conductive film layer to be 40Ω / □-200Ω / □, and the sheet resistance of the first doped polysilicon layer to be 30Ω / □-300Ω / □;

[0018] S9, performing a third etching opening on the corresponding portion of the transparent conductive film layer in the overlapping area between the first opening area and the second opening area according to a preset pattern to form an isolation groove, and at least a portion of the edge of the isolation groove is at a distance from the edge of the textured surface, and within the distance, the corresponding second doped silicon crystal layer, the intrinsic amorphous silicon layer, and the first doped polysilicon layer after surface micro-etching form a reverse leakage channel PN junction, and the reverse leakage channel PN junction is evenly distributed on the back side;

[0019] S10, forming metal electrodes on the outer surfaces of the corresponding transparent conductive film layers in the first opening area and the second opening area.

[0020] In some preferred embodiments of the present invention, the etching rate of the surface micro-etching is controlled to be 0.01-5Å / s in S5.

[0021] In some preferred embodiments of the present invention, the surface micro-etching in S5 is performed by introducing a trace amount of etching gas into the plasma.

[0022] Preferably, the trace etching gas includes CF 4 NF 3 、SiF 4 , C 2 H 6 , C 3 F 8 , SF 6 At least one of .

[0023] Preferably, the conditions for surface micro-etching include: the flow rate of the micro-etching gas is 30-3000 sccm, and the time is 20-1000 s.

[0024] In some preferred embodiments of the present invention, the ratio of the etching depth of the surface micro-etching to the thickness of the first doped polysilicon layer is 0.01-0.2:10.

[0025] In some preferred embodiments of the present invention, the sheet resistance of the first doped polysilicon layer and the sheet resistance of the transparent conductive film layer are not both at the lower limit of their respective ranges.

[0026] In some preferred embodiments of the present invention, the method of controlling the square resistance of the first doped polysilicon layer includes: taking the phosphorus doping concentration of the first doped polysilicon layer as C and the thickness as T, satisfying: when C is 1e18 cm -3 -5e19cm -3 When T is 120nm-300nm; at 5e19cm -3 <C≤1e21cm -3 When, 60nm≤T<120nm.

[0027] In some preferred embodiments of the present invention, the thickness of the transparent conductive film layer is 20 nm-300 nm.

[0028] In some preferred embodiments of the present invention, the first opening area in S3 extends in a strip shape and is arranged at intervals along the Y-axis direction of the back side, and a distance is left between the edge of the first opening area and the edge of the silicon wafer in the X-axis direction of the back side. The isolation groove in S9 extends along the circumferential direction of the P-type semiconductor layer, so that the transparent conductive film layer corresponding to the surface of the P-type semiconductor layer is disconnected from the transparent conductive film layer corresponding to the surface of the N-type semiconductor layer.

[0029] In some preferred embodiments of the present invention, the reverse leakage channel PN junction is arranged in the X-axis direction and / or the Y-axis direction on the back side of the battery, and the reverse leakage channel PN junction is distributed in a continuous extension manner or in an interval uniform distribution.

[0030] In some preferred embodiments of the present invention, the reverse leakage channel PN junction has the following distribution structure:

[0031] Distribution structure 1: The reverse leakage channel PN junctions are evenly distributed in the X-axis direction of the isolation groove in an interval manner, and a reverse leakage channel PN junction is also arranged between the edge of the first opening area and the edge of the silicon wafer in the X-axis direction of the back side, and the isolation groove extends across the textured surface in the corresponding part where the reverse leakage channel PN junction is not arranged;

[0032] Distributed structure 2: The reverse leakage channel PN junction is arranged between the edge of the first opening area and the edge of the silicon wafer in the X-axis direction of the back side;

[0033] Distribution structure 3: The reverse leakage channel PN junction is distributed in a continuous extension along the isolation groove.

[0034] In some preferred embodiments of the present invention, the ratio of the total length of the PN junction of the reverse leakage channel to the total length of the isolation trench is 0.1%-100%.

[0035] In some preferred embodiments of the present invention, when the square resistance of the first doped polysilicon layer is 80Ω / □-300Ω / □ and / or the square resistance of the transparent conductive film layer is 70Ω / □-200Ω / □, the total length of the reverse leakage channel PN junction accounts for 60%-100% of the total length of the isolation trench.

[0036] In some preferred embodiments of the present invention, when the square resistance of the first doped polysilicon layer is 30Ω / □-79Ω / □ and / or the square resistance of the transparent conductive film layer is 40Ω / □-69Ω / □, the total length of the reverse leakage channel PN junction accounts for 0.1%-59% of the total length of the isolation trench.

[0037] Preferably, the total length L of the isolation trench is determined according to the side length a and the pitch width b of the corresponding back contact battery, and satisfies: L=(2a / b+3)a.

[0038] In a second aspect, the present invention provides a combined passivation back contact battery, which is prepared by the combined passivation back contact battery preparation method with a reverse leakage channel set as described in the first aspect, and the parallel resistance Rsh of the combined passivation back contact battery in an IV test is 5-200Ω.

[0039] In a third aspect, the present invention provides a back-contact battery module that does not require a bypass diode, which includes several combined passivated back-contact batteries as described in the second aspect, and several combined passivated back-contact batteries are connected in series to form a battery string, and no bypass diode is required at the end of the battery string.

[0040] Beneficial effects:

[0041] The present invention adopts the above technical scheme, especially in the post-texturing method, to perform surface micro-etching of a suitable depth on the first doped polysilicon layer on the back side after removing the mask layer. Since the interface defects of the polysilicon after surface micro-etching are significantly more than those of single crystal silicon, the formed heterojunction reverse dark current is significantly higher than the PN junction of the battery (for example, in one embodiment, the PN junction of the battery is composed of P-type amorphous silicon-intrinsic amorphous silicon-N-type single crystal silicon wafer), the second semiconductor layer deposited thereafter will increase more defects at the interface, and with at least part of the edge of the isolation groove being at a distance from the edge of the texturing surface, a stable and controllable effective reverse leakage channel can be formed. The corresponding second doped silicon crystal layer, intrinsic amorphous silicon layer and first doped polycrystalline silicon layer with surface micro-etching within this distance form a reverse leakage channel PN junction, the reverse leakage channel PN junction is connected in parallel with the battery PN junction, and the reverse leakage channel PN junction is evenly distributed, which can avoid current concentration leading to regional heating, thereby protecting the battery cell from damage by hot spots and obtaining higher battery efficiency at the same time; wherein, one end of the reverse leakage channel of the present invention is connected to the metal electrode corresponding to the first opening area through a transparent conductive film layer, and the other end is connected to the metal electrode corresponding to the second opening area through the first doped polycrystalline silicon layer to form a reverse leakage channel. In the combined passivation structure of the present invention, by controlling the square resistance of the transparent conductive film layer to be 40Ω / □-200Ω / □ and the square resistance of the first doped polysilicon layer to be 30Ω / □-300Ω / □, and cooperating with surface micro-etching, it is possible to achieve precise control of the overall resistance of the reverse leakage channel, which is beneficial to generate a uniformly distributed reverse leakage channel on the entire battery, and the resistance of the reverse leakage channel can be uniformly set by the square resistance of the film layer, the channel area, and the channel distribution position, so that the reverse leakage is evenly distributed on the battery cell, thereby dispersing the reverse leakage current and reducing the heating phenomenon (hot spot effect) caused by local current concentration.

[0042] Among them, after surface micro-etching, the deposited second semiconductor layer will increase more defects at the corresponding interface. Although there are many defects in the PN junction at this place, it will still produce a photoelectric voltage (photovoltaic effect) under illumination. A forward voltage will be generated under illumination, which is consistent with the PN junction voltage direction of the battery body and participates in power generation; at this time, due to the forward voltage, the reverse resistance is close to infinity, and no leakage will occur, which will not affect normal power generation. When the light is weakened (such as when there is a blockage or the light is weak), the forward voltage generated by the defective PN junction is not enough to prevent the majority of carriers from migrating through the defects. The reverse leakage channel will be turned on and play a role. The current will flow through the reverse leakage channel. The cell will not generate electricity, but other unblocked cells will still generate electricity normally. This is the effect of the reverse leakage channel under weak light conditions brought by the stacked structure of the combined passivated back contact battery, which effectively reduces the hot spot effect. If it is a conventional HJT or other bifacial battery, it is impossible to set a reverse leakage channel. The reverse current will inevitably find a very small part of the battery defect to leak, which will inevitably cause heat concentration to produce a hot spot effect.

[0043] The combined passivation back contact battery obtained by the present invention has an Rsh of 5-200Ω in the IV test, and the reverse leakage channel will not affect the battery efficiency. Otherwise, if Rsh is too small, it will cause serious leakage defects in the battery cell and affect the battery efficiency. The reverse dark current of the PN junction of the reverse leakage channel is significantly higher than that of the battery PN junction. Under the same reverse voltage (such as -15V reverse bias), the reverse dark current I of the back contact battery with the reverse leakage channel is the reverse dark current I of the back contact battery without the reverse leakage channel. 0 5-1000 times, such as Fig.11 As shown, it can be seen that when reverse biased, since the current of the solar cell PN junction is very small, most of the current is shunted by the reverse leakage channel PN junction. Since the reverse leakage channel is evenly distributed, current concentration leading to regional heating is avoided, thereby protecting the battery cell from damage by hot spots.

[0044] The present invention also provides a back-contact battery module that does not require the addition of a bypass diode. The module uses the above-mentioned specially configured back-contact battery. Each back-contact battery is provided with a plurality of reverse leakage channels. When the illumination is normal, the battery PN junction and the reverse leakage channel PN junction work normally to generate electricity. When a battery cell is blocked or damaged, the battery cell cannot generate electricity and becomes a load. Therefore, a reverse bias is generated at both ends of the battery cell. The evenly distributed reverse leakage channels disperse the reverse current, making the heat of the battery cell more dispersed, and avoiding the failure of the battery cell due to local concentrated heat. The present invention can eliminate the use of bypass diodes, reduce costs, and increase power generation; this is because when the battery module is partially blocked, only the blocked battery cell does not participate in power generation, and other battery cells generate electricity normally, so the power generation and power generation efficiency can be increased. In the traditional module using bypass diodes, generally one bypass diode is provided for 20-30 batteries. Once the module is blocked and reaches the bypass diode working condition, the entire battery string is short-circuited, and the battery string will not participate in the module power generation.

[0045] In the preferred embodiment of the present invention, by setting the distribution structure and / or length ratio of the PN junction of the reverse leakage channel, it is more conducive to controlling the heat distribution of the battery cell during reverse leakage, dispersing the reverse current, and achieving the purpose of dispersing heat, thereby controlling the local heating of the battery cell and avoiding the possibility of damage to the battery cell caused by hot spots when the local heating temperature is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 It is a top view and a cross-sectional view of embodiment 1 of the present invention.

[0048] Figure 2 for Figure 1 A partial enlarged view of .

[0049] Figure 3 A cross-sectional view of a reverse leakage channel according to an embodiment of the present invention.

[0050] Figure 4 This is the infrared distribution diagram of the reverse pressurization of Example 1 of the present invention.

[0051] Figure 5 It is a top view and a cross-sectional view of embodiment 2 of the present invention.

[0052] Figure 6 for Figure 5 A partial enlarged view of .

[0053] Figure 7 This is the infrared distribution diagram of the reverse pressurization of Example 2 of the present invention.

[0054] Figure 8 It is a top view and a cross-sectional view of embodiment 3 of the present invention.

[0055] Fig. 9 for Figure 8 A partial enlarged view of .

[0056] Fig.10 This is the infrared distribution diagram of the reverse pressurization of Example 3 of the present invention.

[0057] Fig.11 It is a reverse bias current comparison curve of a battery PN junction and a PN junction with several reverse leakage channels.

[0058] Description of Reference Numerals

[0059] 1. Silicon wafer, 21. N-type doped polysilicon layer, 21a. Tunneling silicon oxide layer, 22. P-type doped amorphous silicon layer, 22a. Intrinsic amorphous silicon layer, 31. First transparent conductive film layer, 32. Second transparent conductive film layer, 4. Isolation groove, 41. Reverse leakage channel, 51. N-type fine gate electrode, 52. P-type fine gate electrode. DETAILED DESCRIPTION

[0060] In the present invention, unless otherwise specified, directional words such as "upper, lower, left, right" are generally understood in conjunction with the directions shown in the drawings and actual applications.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0062] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0063] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed in this article. Among them, the terms "optional" and "optional" all mean that they may be included or not included (or may be present or not).

[0064] In the present invention, the area close to the silicon wafer is referred to as the inside, and the area far from the silicon wafer is referred to as the outside.

[0065] In a first aspect, the present invention provides a method for preparing a combined passivation back contact battery with a reverse leakage channel, comprising:

[0066] S1, provide silicon wafers;

[0067] S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer which are arranged in sequence;

[0068] S3, performing a first etching opening on the back surface obtained in S2 to form a first opening area;

[0069] S4, forming a textured surface at least in the first opening area by texturing cleaning, and removing the mask layer;

[0070] S5, performing surface micro-etching on the back side after removing the mask layer, and controlling the etching depth to be 0.5-100Å;

[0071] S6, depositing a second semiconductor layer on the back side, wherein the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon crystal layer arranged in sequence;

[0072] S7, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a second opening area spaced apart from the first opening area;

[0073] S8, depositing a transparent conductive film layer on the back surface obtained in S7; and controlling the sheet resistance of the transparent conductive film layer to be 40Ω / □-200Ω / □, and the sheet resistance of the first doped polysilicon layer to be 30Ω / □-300Ω / □;

[0074] S9, performing a third etching opening on the corresponding portion of the transparent conductive film layer in the overlapping area between the first opening area and the second opening area according to a preset pattern to form an isolation groove, and at least a portion of the edge of the isolation groove is at a distance from the edge of the textured surface, and within the distance, the corresponding second doped silicon crystal layer, the intrinsic amorphous silicon layer, and the first doped polysilicon layer after surface micro-etching form a reverse leakage channel PN junction, and the reverse leakage channel PN junction is evenly distributed on the back side;

[0075] S10, forming metal electrodes on the outer surfaces of the corresponding transparent conductive film layers in the first opening area and the second opening area.

[0076] The silicon wafer of the present invention is preferably a single crystal silicon wafer.

[0077] In some preferred embodiments of the present invention, the etching rate of the surface micro-etching controlled in S5 is 0.01-5Å / s, and specifically can be 0.01Å / s, 0.02Å / s, 0.03Å / s, 0.04Å / s, 0.05Å / s, 0.06Å / s, 0.07Å / s, 0.08Å / s, 0.09Å / s, 0.10Å / s, 0.12Å / s, 0.1 5Å / s, 0.20Å / s, 0.25Å / s, 0.30Å / s, 0.35Å / s, 0.40Å / s, 0.50Å / s, 1Å / s, 1.5Å / s, 2Å / s, 2.5Å / s, 3Å / s, 3.5Å / s, 4Å / s, 4.5Å / s, 5Å / s, etc. and the range between any two point values, for example, 0.01-0.09Å / s may be preferred. Using a suitable etching speed for surface micro-etching is more conducive to controlling the size and number of surface defects of the first doped polysilicon layer and achieving uniform, moderate and appropriate defect distribution.

[0078] In some preferred embodiments of the present invention, the surface micro-etching in S5 is performed by introducing a trace amount of etching gas into the plasma.

[0079] Preferably, the trace etching gas includes CF 4 NF 3 、SiF4 , C 2 H 6 , C 3 F 8 , SF 6 More preferably, the trace etching gas includes NF 3 , which is more conducive to controlling the etching speed while avoiding the introduction of new impurity defects.

[0080] Preferably, the surface micro-etching conditions include: the flow rate of the micro-etching gas is 30-3000sccm, and the time is 20-1000s. The surface micro-etching using the preferred process conditions is more conducive to controlling the etching speed, avoiding excessive etching of the film layer or insufficient etching, and failing to achieve the effect of the reverse leakage channel.

[0081] In the surface micro-etching process of the present invention, necessary auxiliary gas may be introduced to maintain the plasma excitation state. The auxiliary gas may be, for example, Ar, N 2 , He and other inert gases, and may also include O in special cases. 2 , H 2 Auxiliary gases such as etchant and etchant may also be introduced, but impurity elements may be introduced, which can be selected according to actual needs. Further preferably, the flow rate of the auxiliary gas is 5-2000 times that of the trace etching gas, and the flow rate of the auxiliary gas is 300-60000 sccm.

[0082] In some preferred embodiments of the present invention, the ratio of the etching depth of the surface micro-etching to the thickness of the first doped polysilicon layer is 0.01-0.2:10, which is more conducive to avoiding over-etching of the polysilicon film layer, resulting in other defects such as the polycrystalline layer being too thin, resulting in reduced efficiency. The ratio of the etching depth of the surface micro-etching to the thickness of the first doped polysilicon layer is 0.01-0.2:10, for example, it can be any point value such as 0.01:10, 0.02:10, 0.03:10, 0.04:10, 0.05:10, 0.08:10, 0.09:10, 0.10:10, 0.12:10, 0.15:10, 0.17:10, 0.20:10, and the range between any two point values.

[0083] In some preferred embodiments of the present invention, the square resistance of the first doped polysilicon layer and the square resistance of the transparent conductive film layer are not taken at the lower limit of their respective ranges at the same time. The adoption of this preferred solution is more conducive to avoiding the situation where the reverse leakage channel resistance is too small, so as to reserve a preset length ratio range for the reverse leakage channel. If the reverse leakage channel resistance is too small, the length ratio of the reverse leakage channel needs to be set small, resulting in concentrated reverse leakage and easy generation of hot spot defects.

[0084] In some preferred embodiments of the present invention, the method of controlling the square resistance of the first doped polysilicon layer includes: taking the phosphorus doping concentration of the first doped polysilicon layer as C and the thickness as T, satisfying: when C is 1e18 cm -3 -5e19cm -3 When T is 120nm-300nm; at 5e19cm -3 <C≤1e21cm -3 When 60nm≤T<120nm. The preferred solution is more conducive to controlling the appropriate thickness of the first doped polysilicon layer according to the doping concentration of the first doped polysilicon layer, so as to avoid the first doped polysilicon layer having too small square resistance, resulting in too small total resistance of the reverse leakage channel, and causing the battery parallel resistance Rsh to exceed a reasonable range and affect the efficiency of the battery cell; or the first doped polysilicon layer having too large square resistance, resulting in too large total resistance of the reverse leakage channel, and failing to effectively protect the component from reverse leakage.

[0085] In some preferred embodiments of the present invention, the thickness of the transparent conductive film layer is 20nm-300nm. A transparent conductive film layer with an appropriate thickness is more conducive to controlling the square resistance of the transparent conductive film layer on the P-type electrode side in the reverse leakage channel to avoid defects caused by too small or too large total resistance of the reverse leakage channel.

[0086] In some preferred embodiments of the present invention, the first opening area in S3 extends in a strip shape and is arranged at intervals along the Y-axis direction of the back side, and a distance is left between the edge of the first opening area and the edge of the silicon wafer in the X-axis direction of the back side. More preferably, the isolation groove in S9 extends along the circumferential direction of the P-type semiconductor layer, so that the transparent conductive film layer corresponding to the surface of the P-type semiconductor layer is disconnected from the transparent conductive film layer corresponding to the surface of the N-type semiconductor layer.

[0087] In some preferred embodiments of the present invention, the reverse leakage channel PN junction is arranged in the X-axis direction and / or the Y-axis direction on the back of the battery. Preferably, the reverse leakage channel PN junction is distributed in a continuous extension or in an interval uniform distribution. The reverse leakage channel PN junction is evenly distributed, which is more conducive to the reverse current being evenly distributed on the battery and generating heat evenly when the reverse leakage channel is working; avoiding the hot spot effect caused by local current concentration to damage the battery or components.

[0088] In the first preferred embodiment of the present invention, the reverse leakage channel PN junctions are evenly distributed in the X-axis direction of the isolation groove in an intermittent manner, and the reverse leakage channel PN junctions are also arranged between the edge of the first opening area and the edge of the silicon wafer in the X-axis direction of the back side, and the isolation grooves extend across the textured surface in the corresponding part where the reverse leakage channel PN junctions are not arranged. This embodiment is more conducive to actively setting the distribution length and distribution density of the reverse leakage channel according to needs, so that the current distribution of the reverse leakage channel is more uniform when it is working, the single channel current is smaller, and the working temperature is reduced.

[0089] In the second preferred embodiment of the present invention, the reverse leakage channel PN junction is arranged between the edge of the first opening area in the X-axis direction of the back side and the edge of the silicon wafer. In this embodiment, the reverse leakage channel is arranged in the edge area of ​​the battery, which is more conducive to controlling the battery to appropriately increase the total resistance of the reverse leakage channel, increase the battery parallel resistance Rsh value, and minimize the influence of the reverse leakage channel on the battery efficiency test.

[0090] In the third preferred embodiment of the present invention, the PN junctions of the reverse leakage channel are distributed in a continuous extension along the isolation groove. This embodiment is more conducive to reducing the reverse current of each reverse leakage channel to the maximum extent, so that the battery heat is minimized when the reverse leakage channel is working.

[0091] In some preferred embodiments of the present invention, the total length of the PN junction of the reverse leakage channel accounts for 0.1%-100% of the total length of the isolation groove, which is more conducive to adjusting the total area of ​​the reverse leakage channel according to the square resistance of each film layer and the micro-etching conditions to balance the battery efficiency test and the reverse leakage effect.

[0092] In some preferred embodiments of the present invention, when the square resistance of the first doped polysilicon layer is 80Ω / □-300Ω / □ and / or the square resistance of the transparent conductive film layer is 70Ω / □-200Ω / □, the total length of the reverse leakage channel PN junction accounts for 60%-100% of the total length of the isolation trench.

[0093] In some preferred embodiments of the present invention, when the square resistance of the first doped polysilicon layer is 30Ω / □-79Ω / □ and / or the square resistance of the transparent conductive film layer is 40Ω / □-69Ω / □, the total length of the reverse leakage channel PN junction accounts for 0.1%-59% of the total length of the isolation trench.

[0094] By adopting the above-mentioned preferred scheme of the present invention, the proportion of the reverse leakage channel length is adjusted according to the square resistance of the first doped polysilicon layer and the transparent conductive film layer. When the square resistance is small, the proportion of the reverse leakage channel length is set to be small; when the square resistance is large, the proportion of the reverse leakage channel length is large, which is more conducive to controlling the total resistance of the reverse leakage channel and avoiding affecting the battery efficiency test.

[0095] Preferably, the total length L of the isolation trench is determined according to the side length a and the pitch width b of the corresponding back contact battery, and satisfies: L=(2a / b+3)a.

[0096] In a preferred embodiment of the present invention, the total length of the isolation trench is 30-150 m, more preferably 30-90 m.

[0097] It is understandable that one of the first doped polysilicon layer and the second doped silicon layer is N-type and the other is P-type. The reverse leakage channel is arranged between the strip-shaped N-type conductive region and the P-type conductive region, or arranged at the end region of the strip-shaped N-type conductive region and the P-type conductive region.

[0098] Preferably, in the present invention, the preparation method further comprises: in S6, a step of depositing a passivation layer and an anti-reflection layer on the light-receiving surface after depositing the second semiconductor layer.

[0099] In a second aspect, the present invention provides a combined passivation back contact battery, which is prepared by the combined passivation back contact battery preparation method with a reverse leakage channel set as described in the first aspect, and the parallel resistance Rsh of the combined passivation back contact battery in an IV test is 5-200Ω.

[0100] More preferably, the parallel resistance Rsh of the combined passivated back contact cell in the IV test is 15-150Ω. This preferred solution can effectively avoid the hot spot effect and also avoid the reverse leakage channel resistance in the IV test being too small to affect the solar cell test efficiency.

[0101] In a specific embodiment of the present invention, a combined passivation cell comprises a silicon substrate, an N-type semiconductor layer disposed on the back side of the silicon substrate, a plurality of first opening areas arranged at intervals along the Y-axis direction are provided in the N-type semiconductor layer, the first opening area is a velvet surface, and the other non-opening areas are polished surfaces, a P-type semiconductor layer is embedded in the first opening area, the edge of the P-type semiconductor layer continues to extend outward to directly cover the outer surface of an adjacent portion of the first semiconductor layer to form an overlapping area, the uncovered area is a second opening area, and a transparent conductive film layer is provided on the outer surfaces of the N-type semiconductor layer and the P-type semiconductor layer, a metal electrode is provided outside the first opening area and the second opening area respectively corresponding to the transparent conductive film layer, the N-type semiconductor layer comprises a tunneling oxide layer and an N-type doped polycrystalline silicon layer, the P-type semiconductor layer comprises an intrinsic amorphous silicon layer and a P-type doped amorphous silicon layer, an isolation groove is provided on the portion of the transparent conductive film layer located in the overlapping area, and the isolation groove is located between the first opening area and the second opening area. One end of the reverse leakage channel of the present invention is connected to the metal electrode corresponding to the first opening area through the transparent conductive film layer, and the other end is connected to the metal electrode corresponding to the second opening area through the first doped polysilicon layer to form a reverse leakage channel.

[0102] In a third aspect, the present invention provides a back-contact battery module that does not require a bypass diode, comprising a plurality of the combined passivation back-contact batteries described in the second aspect, wherein the plurality of combined passivation back-contact batteries are connected in series to form a battery string, and a bypass diode is not required at the end of the battery string. The back-contact battery module of the present invention does not require a bypass diode, and can protect the battery cells from damage by hot spots, while obtaining a higher battery efficiency; the use of the bypass diode can be eliminated, reducing costs and increasing power generation.

[0103] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0104] Example 1

[0105] A back contact battery is prepared by the following steps:

[0106] S1, prepare a silicon wafer 1;

[0107] S2, forming a first semiconductor layer and a mask layer on the back side of the silicon wafer 1 in sequence, wherein the first semiconductor layer includes a tunneling silicon oxide layer 21a with a thickness of 1.5 nm and an N-type doped polysilicon layer 21 (with a thickness of 120 nm and an effective doping concentration of 4e19 cm -3 ); The square resistance of the N-type doped polysilicon layer 21 is 130Ω / □;

[0108] S3, performing a first etching on the first semiconductor layer to form a plurality of first opening areas spaced apart along the Y-axis direction, and leaving a gap between the edge of the first opening area and the edge of the silicon wafer 1 in the X-axis direction;

[0109] S4, texturing cleaning, forming a texturing surface in the first opening area and the front side, and removing all mask layers;

[0110] S5, after removing the mask layer, the back surface is micro-etched. The method for micro-etching the surface is as follows: introducing a small amount of etching gas NF into the plasma 3 Micro-etching of the surface, gas NF 3 The flow rate of the auxiliary gas Ar is 30 sccm, the flow rate of the auxiliary gas Ar is 30000 sccm, the time is 50 s, the etching speed is controlled to be 0.05 Å / s, and the etching depth is 2.5 Å. The ratio of the etching depth of the surface micro-etching to the thickness of the N-type doped polysilicon layer 21 is 0.02:10.

[0111] S6, depositing a second semiconductor layer: forming a second semiconductor layer on the back side, the second semiconductor layer comprising an intrinsic amorphous silicon layer 22a with a thickness of 4 nm and a P-type doped amorphous silicon layer 22 (with a thickness of 10 nm and an effective doping concentration of 1e20 cm-1) formed in sequence on the back side. -3 ); and after depositing the second semiconductor layer, a passivation layer and an anti-reflection layer are sequentially deposited on the light-receiving surface;

[0112] S7, opening the second semiconductor layer: performing a second etching on the unopened area on the back side to expose the first semiconductor layer, forming a plurality of second opening areas spaced apart from the first opening areas;

[0113] S8, depositing a transparent conductive film layer with a thickness of 50 nm (including a first transparent conductive film layer 31 corresponding to the N-type region and a second transparent conductive film layer 32 corresponding to the P-type region) on the back side, wherein the sheet resistance of the transparent conductive film layer is 90Ω / □;

[0114] S9, opening the transparent conductive film layer corresponding to the overlapping area between the first opening area and the second opening area, making an isolation groove 4, according to Figure 1 , Figure 2 The graphical distribution shown has a preset reverse leakage channel 41, and part of the edge of the isolation groove 4 is at a distance from the edge of the textured surface. Within this distance, the corresponding P-type doped amorphous silicon layer 22, the intrinsic amorphous silicon layer 22a, and the N-type doped polysilicon layer 21 after surface micro-etching form a reverse leakage channel PN junction, and the reverse leakage channel PN junction is arranged at intervals inside and at the edge of the battery and is evenly distributed; that is, the reverse leakage channel PN junction is evenly distributed in the X-axis direction of the isolation groove 4 in an interval manner, and a reverse leakage channel PN junction is also arranged between the edge of the first opening area and the edge of the silicon wafer 1 in the X-axis direction of the back, and the corresponding part of the isolation groove 4 where the reverse leakage channel PN junction is not arranged extends across the textured surface. The total length of the reverse leakage channel PN junction accounts for 60% of the total length of the isolation groove 4, and the total length of the isolation groove 4 is 50m.

[0115] S10, forming an N-type fine gate electrode 51 and a P-type fine gate electrode 52 on the transparent conductive film layer in the first opening area and the second opening area, respectively, to form metal electrodes. The cross-sectional view of the PN junction portion of the reverse leakage channel of the obtained battery is as follows: Figure 3 shown.

[0116] The obtained back contact battery was subjected to reverse pressure infrared test, and the infrared distribution was as follows Figure 4 As shown, it can be seen that the reverse leakage channel is divided into multiple points, and the reverse current is dispersed in multiple areas of the battery cell.

[0117] The obtained back-contact cells are assembled into a battery string module, specifically, 20 back-contact cells are connected in series, and the ends are directly led out through wires. No bypass diode is provided.

[0118] Example 2

[0119] The method of Example 1 is followed, except that the distribution of the reverse leakage channel is different, as shown in FIG. Figure 5 , Figure 6 As shown, the reverse leakage channel is set in the space between the edge of the first opening area and the edge of the silicon wafer in the X-axis direction, and the reverse leakage channel is only set at the edge positions on both sides of the battery, so the total length of the reverse leakage channel is about 0.158m / total length of the isolation groove is 50m=0.316%. The advantage of this embodiment is that fewer reverse channels are set, and the corresponding transparent conductive film layer thickness is set to 100nm and the square resistance is 45Ω / □.

[0120] The obtained back contact battery was subjected to reverse pressure infrared test, and the infrared distribution was as follows Figure 7 As shown, it can be seen that the reverse leakage channel causes the current to be dispersed across the battery cell.

[0121] Example 3

[0122] The method of Example 1 is followed, except that the distribution of the reverse leakage channel is different, as shown in FIG. Figure 8 , Fig. 9 As shown, the reverse leakage channel is extended along the isolation groove (that is, the isolation groove is at a distance from the velvet surface of the first opening area), that is, the length of the reverse leakage channel is 100% of the length of the isolation groove, that is, the reverse leakage channel is set in both the X-axis direction and the Y-axis direction.

[0123] The obtained back contact battery was subjected to reverse pressure infrared test, and the infrared distribution was as follows Fig.10 As shown, it can be seen that the reverse leakage current is not concentrated and there is no obvious reverse heating point.

[0124] Example 4

[0125] The method of Example 1 is referred to, except that the etching speed of the surface micro-etching is adjusted to 0.10Å / s in S5 until the target etching depth is reached. The process that needs to be adjusted to meet this condition is: a trace amount of etching gas NF is introduced into the plasma. 3 Micro-etching of the surface, gas NF 3 The flow rate of the auxiliary gas Ar is 30000 sccm, and the time is 25 s.

[0126] Example 5

[0127] The method of Example 1 is followed, except that the micro-etching gas NF 3 Replaced by CF 4 , C.F. 4 The flow rate of the auxiliary gas Ar is 30000 sccm, and the flow rate of the auxiliary gas O is 50 sccm. 2 The flow rate is 1000 sccm and the time is 50 s.

[0128] Example 6

[0129] The method of Example 1 is referred to, except that the thickness of the transparent conductive film layer is adjusted to 60 nm, and the sheet resistance of the obtained transparent conductive film layer is 75Ω / □.

[0130] Example 7

[0131] The method of Example 1 is referred to, except that the total length of the PN junction of the reverse leakage channel is adjusted to account for 10% of the total length of the isolation trench, and specifically, the length of a single PN junction of the reverse leakage channel is uniformly reduced.

[0132] Comparative Example 1

[0133] The method of Example 1 is referred to, except that the surface micro-etching of S5 is not performed, but S6 is performed directly after S4.

[0134] Comparative Example 2

[0135] The method of Example 1 is followed, except that the etching depth in S5 is controlled to be 200Å. The process that needs to be adjusted to meet this condition is: a trace amount of etching gas NF is introduced into the plasma. 3 Micro-etching of the surface, gas NF 3 The flow rate of the auxiliary gas Ar is 30000 sccm, and the time is 100 s.

[0136] Comparative Example 3

[0137] The method of Example 1 is referred to, except that the sheet resistance of the first doped polysilicon layer is adjusted to 20Ω / □.

[0138] Test Case

[0139] The battery string modules obtained in the above embodiments and comparative examples were subjected to performance tests, and the results are shown in Table 1. Among them, the battery IV parameters (fill factor, battery efficiency, parallel resistance) and the reverse bias maximum temperature test values ​​are all taken as the median values ​​of all batteries tested in the corresponding example grouped battery cells.

[0140] The test method for the maximum temperature of reverse bias: According to a single cell, reverse bias 15V for 2 minutes, and use an infrared thermal imager to test the maximum temperature reached by the cell.

[0141] The test method for the percentage of battery string power attenuation when a single battery is blocked: According to the single battery string composed of 20 modules connected in series, the battery string power without any blocking test is recorded as W 1 ; Use a black curtain to cover a single cell in the battery string and test the battery string power, recorded as W 2 , T = (W 2 -W 1 ) / W 1 ×100%.

[0142] After a single cell blocks an outdoor hot spot test, the battery string power attenuation percentage is: The battery string power before the outdoor hot spot test, recorded as W 0 ; Battery string power after single cell blocking outdoor hot spot test, recorded as Wt The battery string module obtained from the corresponding example without the bypass diode installed was subjected to an outdoor hot spot simulation test for 60 days to compare the battery string power attenuation percentage before and after the test. The battery string power attenuation percentage calculation formula is: t = (W t -W 0 ) / W 0 ×100%.

[0143] Table 1

[0144]

[0145] It can be seen from the above results that, compared with the comparative example, the embodiment of the present invention can form a stable and controllable effective reverse leakage channel, avoid current concentration leading to regional heating, thereby protecting the battery cell from damage by hot spots, and obtaining higher battery efficiency; the use of bypass diodes can be eliminated, reducing costs, reducing battery attenuation, and increasing power generation.

[0146] Further, according to Examples 1 and 2-7, it can be seen that the preferred solution of the present invention is more conducive to evenly dispersing the heat distribution of the battery cell during reverse bias, which can effectively avoid the hot spot effect and protect the component from continuous power generation. Among them, the channel resistance of Example 7 is larger, the heat is more concentrated, and the temperature is slightly higher.

[0147] Among them, in Comparative Example 1, no surface micro-etching was performed, and there were local defects and uneven heat distribution, resulting in high local temperatures, which led to local damage to the battery cell in the hot spot test and caused irreversible power loss. In Comparative Example 2, excessive etching resulted in serious leakage, affecting battery efficiency. In Comparative Example 3, the polycrystalline square resistance was low and the leakage channel ratio was high, resulting in serious leakage, slightly affecting battery efficiency. The embodiments of the present invention can effectively avoid regional heating caused by current concentration without the need for bypass diodes, thereby protecting the battery cell from damage by hot spots, while obtaining higher battery efficiency and reducing battery attenuation.

[0148] The preferred embodiments of the present invention are described in detail above, but the present invention is not limited thereto. Within the technical concept of the present invention, the technical solution of the present invention can be subjected to a variety of simple modifications, including the combination of various technical features in any other suitable manner, and these simple modifications and combinations should also be regarded as the contents disclosed by the present invention and belong to the protection scope of the present invention.

Claims

1. A method for preparing a combined passivation back contact battery with a reverse leakage channel, comprising: S1, provide silicon wafers; S2, forming a first semiconductor layer and a mask layer in sequence on the back side of the silicon wafer, wherein the first semiconductor layer comprises a tunneling oxide layer and a first doped polysilicon layer which are arranged in sequence; S3, performing a first etching opening on the back surface obtained in S2 to form a first opening area; S4, performing texturing cleaning to form a texturing surface at least in the first opening area, and removing the mask layer; characterized in that it also includes the following steps: S5, performing surface micro-etching on the back side after removing the mask layer, and controlling the etching depth to be 0.5-100Å; S6, depositing a second semiconductor layer on the back side, wherein the second semiconductor layer comprises an intrinsic amorphous silicon layer and a second doped silicon crystal layer arranged in sequence; S7, performing a second etching opening on a portion of the second semiconductor layer on the back side of the silicon wafer to form a second opening area spaced apart from the first opening area; S8, depositing a transparent conductive film layer on the back surface obtained in S7; and controlling the sheet resistance of the transparent conductive film layer to be 40Ω / □-200Ω / □, and the sheet resistance of the first doped polysilicon layer to be 30Ω / □-300Ω / □; S9, performing a third etching opening on the corresponding portion of the transparent conductive film layer in the overlapping area between the first opening area and the second opening area according to a preset pattern to form an isolation groove, and at least a portion of the edge of the isolation groove is at a distance from the edge of the textured surface, and within the distance, the corresponding second doped silicon crystal layer, the intrinsic amorphous silicon layer, and the first doped polysilicon layer after surface micro-etching form a reverse leakage channel PN junction, and the reverse leakage channel PN junction is evenly distributed on the back side; S10, forming metal electrodes on the outer surfaces of the corresponding transparent conductive film layers in the first opening area and the second opening area.

2. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 1, characterized in that: The etching rate of the surface micro-etching is controlled to be 0.01-5Å / s in S5.

3. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 1, characterized in that: The surface micro-etching described in S5 is performed by introducing a small amount of etching gas into the plasma; wherein, The trace etching gas includes at least one of CF4, NF3, SiF4, C2H6, C3F8, and SF6, and / or the conditions for surface micro-etching include: the flow rate of the trace etching gas is 30-3000sccm, and the time is 20-1000s.

4. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 1, characterized in that: The ratio of the etching depth of the surface micro-etching to the thickness of the first doped polysilicon layer is (0.01-0.2):

10.

5. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 1, characterized in that: The sheet resistance of the first doped polysilicon layer and the sheet resistance of the transparent conductive film layer do not take the lower limit values ​​of their respective ranges at the same time.

6. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 1, characterized in that: The method of controlling the square resistance of the first doped polysilicon layer includes: taking the phosphorus doping concentration of the first doped polysilicon layer as C and the thickness as T, satisfying: when C is 1e18 cm -3 -5e19cm -3 When T is 120nm-300nm; at 5e19cm -3 <C≤1e21cm -3 When 60nm≤T<120nm; And / or, the thickness of the transparent conductive film layer is 20nm-300nm.

7. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 1, characterized in that: The first opening area in S3 extends in a strip shape and is arranged at intervals along the Y-axis direction of the back side, and a distance is left between the edge of the first opening area and the edge of the silicon wafer in the X-axis direction of the back side. The isolation groove in S9 extends along the circumferential direction of the P-type semiconductor layer, so that the transparent conductive film layer corresponding to the surface of the P-type semiconductor layer is disconnected from the transparent conductive film layer corresponding to the surface of the N-type semiconductor layer.

8. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 1 or 7, characterized in that: The reverse leakage channel PN junction is arranged in the X-axis direction and / or the Y-axis direction of the back side of the battery, and the reverse leakage channel PN junction is distributed in a continuous extension manner or in an interval uniform distribution.

9. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 8, characterized in that: The reverse leakage channel PN junction has the following distribution structure: Distribution structure 1: The reverse leakage channel PN junctions are evenly distributed in the X-axis direction of the isolation groove in an interval manner, and a reverse leakage channel PN junction is also arranged between the edge of the first opening area and the edge of the silicon wafer in the X-axis direction of the back side, and the isolation groove extends across the textured surface in the corresponding part where the reverse leakage channel PN junction is not arranged; Distributed structure 2: The reverse leakage channel PN junction is arranged between the edge of the first opening area and the edge of the silicon wafer in the X-axis direction of the back side; Distribution structure 3: The reverse leakage channel PN junction is distributed in a continuous extension along the isolation groove.

10. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 8, characterized in that: The ratio of the total length of the PN junction of the reverse leakage channel to the total length of the isolation trench is 0.1%-100%.

11. The method for preparing a combined passivation back contact battery with a reverse leakage channel according to claim 10, characterized in that: When the square resistance of the first doped polysilicon layer is 80Ω / □-300Ω / □ and / or the square resistance of the transparent conductive film layer is 70Ω / □-200Ω / □, the total length of the reverse leakage channel PN junction accounts for 60%-100% of the total length of the isolation trench; when the square resistance of the first doped polysilicon layer is 30Ω / □-79Ω / □ and / or the square resistance of the transparent conductive film layer is 40Ω / □-69Ω / □, the total length of the reverse leakage channel PN junction accounts for 0.1%-59% of the total length of the isolation trench; And / or, the total length L of the isolation trench is determined according to the side length a and the pitch width b of the corresponding back contact battery, and satisfies: L=(2a / b+3)a.

12. A combined passivation back contact cell, characterized in that: The battery is prepared by the method for preparing a combined passivation back contact battery with a reverse leakage channel as described in any one of claims 1 to 11, and the parallel resistance Rsh of the combined passivation back contact battery in an IV test is 5-200Ω.

13. A back contact battery module without bypass diode, characterized in that: It comprises a plurality of combined passivated back contact cells as claimed in claim 12, wherein the plurality of combined passivated back contact cells are connected in series to form a cell string, and no bypass diode is required at the end of the cell string.

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