Semiconductor chip and semiconductor device

Abstract

The invention is suitable for the field of semiconductor packaging, and provides a semiconductor device. The semiconductor device comprises a substrate and a semiconductor chip, one surface of the substrate is a packaging surface, the semiconductor chip is packaged on the packaging surface, the top of the semiconductor chip is provided with an electrode, the packaging surface is provided with a wiring part used for being connected with the electrode through a wire, the semiconductor chip is provided with a gap, and the gap is provided with a gap. And at least part of the wiring part is positioned in the notch. According to the semiconductor device provided by the invention, under the condition that the area of the substrate is fixed, the effective area of the semiconductor chip is effectively increased, the signal intensity of product application is improved, the use performance of the product is better, and the user experience is good.

Description

[0001] This application is a divisional application of the invention patent application with application date of April 29, 2022, application number 202210472559.9, and invention name “A semiconductor device”. Technical Field

[0002] The invention belongs to the field of semiconductor packaging, and in particular relates to a semiconductor device. Background Art

[0003] In the semiconductor packaging industry, semiconductor devices that are packaged in a vertical structure or upright structure, such as light-emitting devices LEDs and photosensitive devices, are generally composed of a substrate, a semiconductor chip, connecting wires, and an external sealing adhesive. During the packaging process, the positive and negative electrodes of the semiconductor chip are connected to the positive and negative pads of the substrate (there are two types of chips:), and then the internal structure is protected by the encapsulation adhesive to complete the finished product packaging. Figure 1 and Figure 2 As shown, the semiconductor chip 92 is usually square. When the semiconductor chip 92 is placed on the substrate 91, the pad 93 needs to be exposed for subsequent wire bonding. The semiconductor chip 92 cannot block the pad 93. In the prior art, one side of the semiconductor chip 92 forms a strip area 94 with one side of the substrate 91. The strip area 94 will form a semiconductor blank area, which will limit the signal strength of the product application under a specific package size, that is, the light-emitting area of ​​the light-emitting device LED is reduced, and the light-sensitive area of ​​the light-sensitive device is reduced. For the photosensitive device that cannot be sensitive to light in the blank area, the impact is particularly obvious in the application of photodetectors, affecting product performance. Summary of the invention

[0004] The purpose of the present invention is to overcome the above-mentioned deficiencies of the prior art and provide a semiconductor device, which, when the substrate size is constant, has a larger effective area of ​​the semiconductor chip and better product performance.

[0005] The technical solution of the present invention is: a semiconductor device, including a substrate and a semiconductor chip, one side of the substrate is a packaging surface, the semiconductor chip is packaged on the packaging surface, an electrode is arranged on the top of the semiconductor chip, the packaging surface is provided with a wiring part for connecting to the electrode through a wire, the semiconductor chip is provided with a notch, and at least part of the wiring part is located in the notch.

[0006] Optionally, the notch is located at a corner or edge of the semiconductor chip.

[0007] Optionally, the boundary of the substrate is rectangular, and the boundary formed by the semiconductor chip and the notch is rectangular.

[0008] Optionally, the notch is rectangular, triangular or fan-shaped.

[0009] Optionally, the electrode includes a positive electrode and a negative electrode, and the wiring portion includes a positive electrode pad and a negative electrode pad; The positive electrode pad and the negative electrode pad are arranged on the packaging surface and are both close to a corner of the substrate, a corner of the semiconductor chip is provided with the notch, and the positive electrode pad and the negative electrode pad are both located in the notch; Alternatively, the positive electrode pad and the negative electrode pad are arranged on the packaging surface and are respectively close to two corners on the same side of the substrate, the two corners on the same side of the semiconductor chip are respectively provided with the notches, the positive electrode pad is located in one of the notches, and the negative electrode pad is located in the other notch; Alternatively, the positive electrode pad and the negative electrode pad are arranged on the packaging surface and are respectively close to the two corners in the diagonal direction of the substrate, and the two corners in the diagonal direction of the semiconductor chip are respectively provided with the notches, the positive electrode pad is located in one of the notches, and the negative electrode pad is located in the other notch.

[0010] Optionally, the semiconductor chip is provided with a local step groove close to the notch, and the electrode is located at the local step groove to reduce the height space occupied by the packaged product.

[0011] Optionally, the partial step groove is close to a corner of the notch, and a planar shape of the partial step groove is rectangular, triangular or trapezoidal.

[0012] Optionally, a side of the semiconductor chip away from the packaging surface is a front side, and the wire between the electrode and the wiring portion is not higher than the front side of the semiconductor chip.

[0013] Optionally, the side of the semiconductor chip facing the packaging surface is the back side, and a avoidance groove is provided on the back side of the semiconductor chip near the notch, the avoidance groove passes through the notch, the minimum distance between the side wall of the avoidance groove and the wiring part is L1, the minimum distance between the side wall of the notch and the wiring part is L2, and L1 is greater than L2.

[0014] Optionally, four semiconductor chips are arranged on the substrate, the notches of the four semiconductor chips are respectively located at four corners of the substrate, a spacing area is formed between the four semiconductor chips, and black glue is filled in the spacing area.

[0015] A semiconductor device provided by the present invention effectively increases the effective area of ​​a semiconductor chip under the condition of a certain substrate area, thereby improving the signal strength of product applications, improving product performance, and providing a better user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 is a top view of a semiconductor device in the prior art; Figure 2 is a top view of a semiconductor device in the prior art; Figure 3 is a top view of a semiconductor device (the notch is rectangular and has a pad) provided by an embodiment of the present invention; Figure 4 is a top view of a substrate of a semiconductor device (with a rectangular notch) provided by an embodiment of the present invention; Figure 5 is a top view of a substrate of a semiconductor device (with a notch in a triangular shape) provided by an embodiment of the present invention; Figure 6 is a top view of a semiconductor device (the notch is rectangular and has two pads) provided by an embodiment of the present invention; Figure 7 yes Figure 4 A partial enlarged view of the middle A; Figure 8 yes Figure 5 A partial enlarged view of point B in the middle; Fig. 9 is a three-dimensional diagram of a semiconductor device provided by an embodiment of the present invention; Fig.10 is a three-dimensional diagram of a semiconductor device (provided with a partial stepped groove) provided by an embodiment of the present invention; Fig.11 It is a three-dimensional diagram of a semiconductor device (with a partial step groove provided on the front side and a avoidance groove provided on the back side) provided by an embodiment of the present invention; Fig.12 It is a three-dimensional diagram of a semiconductor device (including four semiconductor chips) provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.

[0020] In addition, in the embodiments of the present invention, if there are terms indicating orientation or positional relationships such as "longitudinal", "transverse", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., they are based on the orientation or positional relationships or conventional placement states or usage states shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the structure, feature, device or element referred to must have a specific orientation or positional relationship, nor must it be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. In the description of the present invention, unless otherwise specified, "multiple" means two or more.

[0021] The various specific technical features and embodiments described in the specific implementation methods can be combined in any suitable manner unless there is any contradiction. For example, different implementation methods can be formed by combining different specific technical features / embodiments. In order to avoid unnecessary repetition, the various possible combinations of the specific technical features / embodiments in the present invention will not be described separately.

[0022] like Figures 3 to 6 As shown, a semiconductor device provided by an embodiment of the present invention includes a substrate 1 and a semiconductor chip 2, and the semiconductor chip 2 can be a light-emitting chip or a photosensitive chip. The semiconductor chip 2 is connected to an electrode 22. One side of the substrate 1 is a packaging surface, and the semiconductor chip 2 is packaged on the packaging surface, that is, the back of the semiconductor chip 2 is attached to the packaging surface of the substrate 1. The packaging surface is provided with a wiring portion 4 for connecting to the electrode 22, and the semiconductor chip 2 is provided with a notch 20 that can be formed by a cutting line, and at least part of the wiring portion 4 is located in the notch 20, which reduces the blank area of ​​the semiconductor chip 2 on the substrate 1. When the area of ​​the substrate 1 is constant, the use area of ​​the semiconductor chip 2 is effectively increased, and the signal strength of the product application is improved. When the semiconductor chip 2 takes a photosensitive chip as an example, under the premise of a certain area of ​​the substrate 1, the photosensitive area is effectively increased, the photosensitive performance is effectively improved, the product performance is better, and the user experience is good.

[0023] In this embodiment, the area of ​​the notch 20 is defined as follows: the area enclosed by the extension line extending from the outer boundary of the semiconductor chip 2 to the notch 20 and the cutting line. The cutting line can be straight, folded (eg, right-angled) or curved.

[0024] Specifically, the notch 20 may be located at a corner of the semiconductor chip 2 , with part or all of the wiring portion 4 located within the notch 20 ; or, the notch 20 may be located inside the semiconductor chip 2 , that is, the notch 20 is in a closed shape, with all of the wiring portion 4 located within the notch 20 .

[0025] In this embodiment, the notch 20 is located at a corner of the semiconductor chip 2 , and part or all of the wiring portion 4 is located in the notch 20 .

[0026] Specifically, the substrate 1 may be rectangular (the shapes referred to in this embodiment are all planar shapes, the same below), the semiconductor chip 2 may be rectangular and have the notch 20 at at least one corner. It can be understood that the shape of the semiconductor chip 2 without processing to form the notch 20 is the basic shape. Taking the semiconductor chip 2 with a basic rectangular shape as an example, the shape of the semiconductor chip 2 after processing to form the notch 20 is the actual shape, and the difference between the actual shape and the basic shape is the notch 20. That is, the actual shape of the semiconductor chip 2 may be a rectangle with at least one corner missing, so as to facilitate processing.

[0027] In a specific application, the notch 20 may be rectangular (eg Figure 3 , Figure 4 as shown), triangles (as Figure 5 In this embodiment, the notch is a rectangular shape. In order to save cutting stroke, the notch can be triangular, and a straight line can be used as a cutting line to cut the semiconductor chip 2. However, when the pad shape and the distance between the pad and the chip are fixed, the chip area can be relatively maximized by using right-angle cutting. The length and width of the pad 4 are a and b respectively, and the minimum distance between the semiconductor chip 2 or its solid crystal area and the pad 4 is X.

[0028] like Figure 8 As shown, when the notch 20 is in the shape of a triangle (isosceles right triangle), the area S1 of the entire notch 20 is a²+ab+2ax+bx+b² / 4+x².

[0029] like Figure 7 As shown, when the notch 20 is rectangular, the area S2 of the entire rectangular notch 20 is ab+ax+bx+x². Based on the area calculation result, S1-S2=a²+ax+b² / 4 is subtracted. Obviously, S1>S2. Therefore, right-angle cutting can ensure that the chip area is maximized relative to straight-line cutting.

[0030] Specifically, Figure 6 As shown, the connection portion 4 includes a positive electrode pad 41 and a negative electrode pad 42 . The positive electrode pad 41 is used to connect the positive electrode of the semiconductor chip 2 , and the negative electrode pad 42 is used to connect the negative electrode of the semiconductor chip 2 .

[0031] In this embodiment, Figures 3 to 8 As shown, taking the substrate 1 and the semiconductor chip 2 as rectangular as an example, the length and width of the semiconductor chip 2 are smaller than the length and width of the substrate 1, and the semiconductor chip 2 is completely located within the boundary of the substrate 1. The positive electrode pad 41 and the negative electrode pad 42 are arranged on the packaging surface and are close to a corner of the substrate 1. The positive electrode pad 41 and the negative electrode pad 42 are arranged adjacent to each other, and the notch 20 is provided at a corner of the semiconductor chip 2, and the positive electrode pad 41 and the negative electrode pad 42 are both located in the notch 20, and the notch 20 only needs to be processed at a corner of the semiconductor chip 2.

[0032] Alternatively, the positive electrode pad 41 and the negative electrode pad 42 are arranged on the packaging surface and are respectively close to the two corners on the same side of the substrate 1, and the two corners on the same side of the semiconductor chip 2 are respectively provided with the notches 20, the positive electrode pad 41 is located in one of the notches 20, and the negative electrode pad 42 is located in the other notch 20, and the notches 20 need to be formed by processing the two corners on the same side of the semiconductor chip 2.

[0033] Alternatively, the positive electrode pad 41 and the negative electrode pad 42 are arranged on the packaging surface and are respectively close to the two corners in the diagonal direction of the substrate 1, and the two corners in the diagonal direction of the semiconductor chip 2 are respectively provided with the notches 20, the positive electrode pad 41 is located in one of the notches 20, and the negative electrode pad 42 is located in the other notch 20, and the notches 20 need to be formed by processing the two corners in the line direction of the semiconductor chip 2 respectively.

[0034] Specifically, Fig.10 As shown, the semiconductor chip 2 is provided with a local step groove 21 near the notch 20 , and the semiconductor chip 2 has an electrode 22 , and the electrode 22 is located at the local step groove 21 to reduce the space occupied by the product in the height direction.

[0035] Specifically, the partial step groove 21 is close to the corner of the notch 20 and penetrates the notch 20 . The plane shape of the partial step groove 21 can be a suitable shape such as a rectangle, a triangle or a trapezoid.

[0036] Specifically, the side of the semiconductor chip 2 away from the packaging surface is the front side, and the welding wire between the electrode 22 and the wiring portion 4 is not higher than the front side of the semiconductor chip 2, or the welding wire is slightly higher than the front side of the semiconductor chip 2, thereby reducing the space occupied by the semiconductor device in the height direction, and effectively solving the problem of the horizontal size of the product and the spatial height of the finished product being restricted by the welding wire connection.

[0037] Specifically, Fig.11As shown, the side of the semiconductor chip 2 facing the packaging surface is the back side, and a relief groove 25 is provided on the back side of the semiconductor chip 2 near the notch 20, and the relief groove passes through the notch 20. The minimum distance between the side wall of the relief groove and the wiring part 4 is L1, and the minimum distance between the side wall (cutting line) of the notch 20 and the wiring part 4 is L2, and L1 is greater than L2. The lower surface of the chip is set in a stepped shape, while ensuring the spacing between the semiconductor chip 2 and the wiring part 4, the effective area of ​​the upper surface of the semiconductor chip 2 is increased as much as possible.

[0038] In specific applications, a combination of physical cutting and laser cutting can be used to cut a rectangular semiconductor chip 2 (corresponding wafer) into a shape with a right-angle notch 20. The notch 20 is used to provide space for electrical connection, so that the pad after electrical connection basically does not protrude beyond the basic shape of the semiconductor chip 2, which can greatly increase the effective area of ​​the semiconductor chip 2 and greatly improve the product signal strength under a certain packaging size. The performance advantages are obvious in high-end applications (such as photodetectors, etc.).

[0039] like Figures 9 to 11 As shown, in order to make the semiconductor device highly compact in space, the substrate of the semiconductor device can be ground into a local step groove 21 by local grinding, so that the semiconductor device has a high-low step structure. By arranging the electrode 22 at the local step groove 21, the high step portion is above the local step groove 21, and the high step portion of the semiconductor chip 2 is connected with a conductive line to achieve conduction, the semiconductor device becomes thinner after packaging.

[0040] In specific applications, the chip wafer can be cut into a designed shape by combining pure laser cutting, or other physical cutting methods can be used to cut the chip wafer into a corresponding rectangular shape (basic shape), and then the portion where the wiring portion 4 (pad) is to be placed is cut and removed by laser to form a notch 20. That is, the wafer of the semiconductor chip 2 can be cut and formed in one time to obtain the actual shape, or it can be cut into a basic shape first, and then cut to form the notch 20 to obtain the actual shape.

[0041] Furthermore, if Fig.12 As shown, four semiconductor chips 2 are provided on the substrate 1, and the notches 20 of the four semiconductor chips 2 are respectively located at the four corners of the substrate 1, and a spacing area 5 is formed between the four semiconductor chips 2. The spacing area 5 is filled with black glue. The notches of the four semiconductor chips 2 are located at the four corners of the substrate 1, ensuring that the central part of the overall packaged semiconductor device is more evenly sensitive to light. At the same time, the spacing area 5 is filled with black glue, which is beneficial to the reception of external light and has a better photosensitivity effect.

[0042] An embodiment of the present invention further provides an electronic device having the above-mentioned semiconductor device. The electronic device may be an electronic device having an LED chip, such as an LED light emitting device, or an electronic device having a photosensitive chip, such as a photodetector or a camera.

[0043] A semiconductor device and an electronic device having the semiconductor device provided in an embodiment of the present invention effectively increase the use area of ​​the semiconductor chip 2 when the area of ​​the substrate 1 is constant, thereby improving the signal strength of the product application. When the semiconductor chip 2 is a photosensitive chip, for example, under the premise that the area of ​​the substrate 1 is constant, the photosensitive area is effectively increased, the photosensitivity is effectively improved, the product performance is better, and the user experience is better.

[0044] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modification, equivalent substitution or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor chip, which is a photosensitive chip. An electrode is arranged on the top of the semiconductor chip. The semiconductor chip is provided with a notch, which is located at a corner or edge of the semiconductor chip. The boundary formed by the semiconductor chip and the notch is rectangular. A local step groove is arranged on the semiconductor chip near the notch, and the electrode is located at the local step groove.

2. A semiconductor chip as claimed in claim 1, characterized in that: The notch is formed by laser cutting.

3. A semiconductor chip as claimed in claim 1, characterized in that: The local step groove is formed by local grinding.

4. A semiconductor chip as claimed in claim 1, characterized in that: The notch is rectangular, triangular or fan-shaped.

5. A semiconductor chip as claimed in claim 1, characterized in that: The electrodes include a positive electrode and a negative electrode; The notch is provided at one corner of the semiconductor chip, and the positive electrode pad and the negative electrode pad are both located in the notch; Alternatively, the two corners on the same side of the semiconductor chip are respectively provided with the notches, the positive electrode pad is located in one of the notches, and the negative electrode pad is located in the other notch; Alternatively, the two corners of the semiconductor chip in the diagonal direction are respectively provided with the notches, the positive electrode pad is located in one of the notches, and the negative electrode pad is located in the other notch.

6. A semiconductor chip as claimed in claim 1, characterized in that: The partial step groove is close to the corner of the notch, and the plane shape of the partial step groove is rectangular, triangular or trapezoidal.

7. A semiconductor chip as claimed in claim 1, characterized in that: A avoidance groove is arranged on the back side of the semiconductor chip near the notch, and the avoidance groove passes through the notch.

8. A semiconductor device, comprising a substrate and a semiconductor chip, wherein the semiconductor chip is a photosensitive chip, one side of the substrate is a packaging surface, the semiconductor chip is packaged on the packaging surface, an electrode is provided on the top of the semiconductor chip, the packaging surface is provided with a wiring portion for connecting to the electrode through a wire, the semiconductor chip is provided with a notch, at least part of the wiring portion is located in the notch, the notch is located at a corner or edge of the semiconductor chip, the boundary formed by the semiconductor chip and the notch is rectangular, the semiconductor chip is provided with a local step groove close to the notch, and the electrode is located at the local step groove.

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