Semiconductor light emitting device

Abstract

A semiconductor light emitting device includes a current limiting layer and a semiconductor light emitting laminate. The semiconductor light emitting laminate is disposed on the current limiting layer and has a bottom surface in contact with the current limiting layer. The current limiting layer includes an insulating layer and a plurality of conductive portions. The plurality of conductive portions are disposed in the insulating layer and are in contact with the bottom surface. The area ratio of the plurality of conductive parts with respect to the bottom surface is 7% or more and 15% or less.

Description

Technical Field

[0001] The present invention relates to a semiconductor light emitting device. Background Art

[0002] Japanese Patent Application Laid-Open No. 2020-65041 (Patent Document 1) discloses a semiconductor light-emitting device. Summary of the invention

[0003] An object of the present disclosure is to provide a semiconductor light emitting device capable of improving light output when a high current is injected.

[0004] The semiconductor light-emitting device of the present invention includes a current limiting layer and a semiconductor light-emitting stack. The semiconductor light-emitting stack is arranged on the current limiting layer and has a bottom surface in contact with the current limiting layer. The current limiting layer includes an insulating layer and a plurality of conductive parts. The plurality of conductive parts are arranged in the insulating layer and in contact with the bottom surface. The area ratio of the plurality of conductive parts relative to the bottom surface is greater than 7% and less than 15%. The above-mentioned area ratio is the ratio of the second area of ​​the plurality of conductive parts overlapping with the bottom surface to the first area of ​​the bottom surface when the bottom surface is viewed from above. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 It is a schematic top view of a semiconductor light emitting device according to an embodiment.

[0006] Figure 2 A semiconductor light emitting device according to an embodiment Figure 1 A schematic cross-sectional view taken along the section line II-II is shown.

[0007] Figure 3 This is a schematic cross-sectional view showing one step of a method for manufacturing a semiconductor light emitting device according to an embodiment.

[0008] Figure 4 The method for manufacturing a semiconductor light emitting device according to the embodiment is as follows: Figure 3 A schematic partial enlarged cross-sectional view of the step following the step shown.

[0009] Figure 5 The method for manufacturing a semiconductor light emitting device according to the embodiment is as follows: Figure 4 A schematic partial enlarged cross-sectional view of the step following the step shown.

[0010] Figure 6 The method for manufacturing a semiconductor light emitting device according to the embodiment is as follows: Figure 5 A schematic partial enlarged cross-sectional view of the step following the step shown.

[0011] Figure 7 The method for manufacturing a semiconductor light emitting device according to the embodiment is as follows: Figure 6A schematic partial enlarged cross-sectional view of the step following the step shown.

[0012] Figure 8 The method for manufacturing a semiconductor light emitting device according to the embodiment is as follows: Figure 7 A schematic partial enlarged cross-sectional view of the step following the step shown.

[0013] Fig. 9 The method for manufacturing a semiconductor light emitting device according to the embodiment is as follows: Figure 8 A schematic partial enlarged cross-sectional view of the step following the step shown.

[0014] Fig.10 The method for manufacturing a semiconductor light emitting device according to the embodiment is as follows: Fig. 9 A schematic partial enlarged cross-sectional view of the step following the step shown.

[0015] Fig.11 The method for manufacturing a semiconductor light emitting device according to the embodiment is as follows: Fig.10 A schematic partial enlarged cross-sectional view of the step following the step shown.

[0016] Fig.12 This is a diagram showing a graph of the relationship between the area ratio of the plurality of conductive portions to the bottom surface of the semiconductor light emitting stack and the light output of the semiconductor light emitting device.

[0017] Fig.13 This is a graph showing the relationship between the carrier concentration of the p-type contact layer and the forward voltage of the semiconductor light-emitting device.

[0018] Fig.14 It is a schematic top view of a semiconductor light emitting device according to a first modified example of the embodiment.

[0019] Fig.15 It is a schematic top view of a semiconductor light emitting device according to a second modification example of the embodiment.

[0020] Fig.16 It is a schematic top view of a semiconductor light emitting device according to a third modified example of the embodiment.

[0021] Description of Reference Numerals

[0022] 1 semiconductor light emitting device, 2 mesa structure, 10 substrate, 11, 12 main surfaces, 13 anode electrode, 14 reflective layer, 14a first metal layer, 14b second metal layer, 15 current limiting layer, 16 insulating layer, 17 conductive portion, 20 semiconductor light emitting stack, 20a bottom surface, 21 first p-type layer, 22 p-type contact layer, 23 p-type window layer, 24 first p-type cladding layer, 25 first semiconductor light emitting layer, 26 first n-type layer, 27 first n-type cladding layer, 28 tunnel diode layer, 29n ++Tunnel layer, 30p ++ Tunnel layer, 31 second p-type layer, 32 second p-type cladding layer, 33 second semiconductor light-emitting layer, 35 second n-type layer, 36 second n-type cladding layer, 37 n-type window layer, 37a concave-convex structure, 38 n-type contact layer, 40 cathode electrode, 41 pad electrode, 42 dendrite electrode, 45 growth substrate, 46 supporting substrate, 47 etching stop layer, 48 resist. DETAILED DESCRIPTION

[0023] [Detailed description]

[0024] The details of the embodiments of the present disclosure are described based on the accompanying drawings. In addition, in the following drawings, the same reference numerals are marked on the same or corresponding parts, and their descriptions are not repeated. The structures of at least a part of the embodiments described below can also be arbitrarily combined.

[0025] Reference Figure 1 and Figure 2 The semiconductor light emitting device 1 of the embodiment is described. The semiconductor light emitting device 1 is, for example, a light emitting diode (LED). The semiconductor light emitting device 1 includes a substrate 10 , an anode electrode 13 , a reflective layer 14 , a current confinement layer 15 , a semiconductor light emitting stack 20 , and a cathode electrode 40 .

[0026] The substrate 10 includes a main surface 11 and a main surface 12 opposite to the main surface 11. The substrate 10 is, for example, p ++ A semiconductor substrate such as a silicon (Si) substrate, or a conductor substrate such as a metal substrate containing at least one of aluminum (Al), copper (Cu), gold (Au) and silver (Ag).

[0027] The reflective layer 14 is arranged on the main surface 11 of the substrate 10. The reflective layer 14 is arranged on the surface of the current limiting layer 15 on the opposite side of the semiconductor light-emitting stack 20. The reflective layer 14 reflects the light radiated from the semiconductor light-emitting stack 20. The thickness of the reflective layer 14 is, for example, 0.1 μm or more and 3.0 μm or less. The reflective layer 14 is formed, for example, by Au or an alloy containing Au. The reflective layer 14 can be a single layer of an Au layer, a single layer of an Au alloy layer, a stack of an Au layer and other metal layers, or a stack of an Au alloy layer and other metal layers. In the case where the reflective layer 14 is a stack, the outermost surface of the reflective layer 14 in contact with the semiconductor light-emitting stack 20 is preferably formed by an Au layer or an Au alloy layer (for example, a gold-beryllium-nickel (Au Be Ni) alloy, etc.). In the case where the reflective layer 14 is a stack, the reflective layer 14 is, for example, a stack of (current limiting layer 15 side) Au / Ti (substrate 10 side).

[0028] The reflective layer 14 may also be formed by forming a growth substrate 45 (see Figure 6) is bonded to the substrate 10, and the first metal layer 14a (refer to Figure 6 ) and the second metal layer 14b (refer to Figure 6 ) are bonded. Therefore, a boundary (bonding surface) between the first metal layer 14a and the second metal layer 14b may exist in the reflective layer 14. In addition, when the reflective layer 14 is formed of a plurality of metal materials, no clear boundary may be formed between the plurality of metal materials, and the composition of the plurality of metal materials may gradually change in the thickness direction of the reflective layer 14.

[0029] The current confinement layer 15 is disposed on the reflective layer 14. The current confinement layer 15 includes an insulating layer 16 and a plurality of conductive portions 17. The insulating layer 16 is formed of, for example, silicon dioxide (SiO2).

[0030] A plurality of conductive portions 17 are arranged in the insulating layer 16. Specifically, the plurality of conductive portions 17 are formed in a plurality of through holes formed in the insulating layer 16. The plurality of conductive portions 17 are, for example, a plurality of conductive pillars. The plurality of conductive portions 17 are in contact with the reflective layer 14 and the bottom surface 20a of the semiconductor light-emitting stack 20, and electrically connect the reflective layer 14 to the semiconductor light-emitting stack 20. Specifically, the plurality of conductive portions 17 are in contact with the reflective layer 14 and the p-type contact layer 22, and electrically connect the reflective layer 14 to the p-type contact layer 22. When the main surface 11 is viewed from above, the plurality of conductive portions 17 each have a diameter of, for example, 5 μm or more and 15 μm or less. When the main surface 11 is viewed from above, the plurality of conductive portions 17 may also be uniformly arranged.

[0031] The plurality of conductive portions 17 are formed of, for example, a metal material such as Au or an alloy such as a gold-beryllium (AuBe) alloy. When the wavelength of light emitted from the semiconductor light-emitting layer (the first semiconductor light-emitting layer 25 and the second semiconductor light-emitting layer 33) is greater than 800 nm and less than 1000 nm, the plurality of conductive portions 17 made of Au have a higher reflectivity for the light emitted from the semiconductor light-emitting layer than the plurality of conductive portions 17 made of AuBe. Therefore, the plurality of conductive portions 17 made of Au increase the light output of the semiconductor light-emitting device 1.

[0032] The semiconductor light emitting stack 20 includes a bottom surface 20a in contact with the current confinement layer 15. A mesa structure 2 may be formed in the semiconductor light emitting stack 20. The semiconductor light emitting stack 20 includes a first p-type layer 21, a first semiconductor light emitting layer 25, a first n-type layer 26, a tunnel diode layer 28, a second p-type layer 31, a second semiconductor light emitting layer 33, and a second n-type layer 35.

[0033] The first p-type layer 21 is disposed on the current confinement layer 15 . The first p-type layer 21 includes a p-type contact layer 22 , a p-type window layer 23 , and a first p-type cladding layer 24 .

[0034] The p-type contact layer 22 is disposed on the current confinement layer 15. The p-type contact layer 22 is a low resistance layer for making ohmic contact with the plurality of conductive portions 17. The p-type contact layer 22 is, for example, a layer having the highest p-type doping concentration or carrier concentration (hole concentration) in the first p-type layer 21. The p-type contact layer 22 is, for example, an AlGaAsP layer doped with a p-type dopant such as carbon (C) or a GaP layer doped with a p-type dopant such as zinc (Zn). The carrier concentration (hole concentration) of the p-type contact layer 22 is, for example, 1×10 19 cm -3 The carrier concentration (hole concentration) of the p-type contact layer 22 can be 2×10 19 cm -3 Above, it can also be 5×10 19 cm -3 above.

[0035] The p-type window layer 23 is disposed on the p-type contact layer 22. The p-type window layer 23 is, for example, an AlGaAs layer doped with carbon (C).

[0036] The first p-type cladding layer 24 is disposed on the p-type window layer 23 . The first p-type cladding layer 24 is, for example, an AlGaAs layer doped with carbon (C). The Al composition ratio of the first p-type cladding layer 24 is higher than that of the p-type window layer 23 .

[0037] The first semiconductor light emitting layer 25 is arranged on the first p-type layer 21 (first p-type cladding layer 24). The first semiconductor light emitting layer 25 is a layer that radiates light when current is injected into the semiconductor light emitting device 1. The wavelength of light radiated from the first semiconductor light emitting layer 25 is, for example, greater than 800 nm and less than 1000 nm. The first semiconductor light emitting layer 25 is, for example, a multiple quantum well (MQW) layer. In the first semiconductor light emitting layer 25, for example, an MQW layer in which InGaAs well layers and AlGaAsP barrier layers are alternately stacked. The first semiconductor light emitting layer 25 is, for example, an undoped layer.

[0038] The first n-type layer 26 is disposed on the first semiconductor light emitting layer 25. The first n-type layer 26 is, for example, a first n-type cladding layer 27. The first n-type cladding layer 27 is, for example, an AlGaAs layer doped with selenium (Se). The Al composition ratio of the first n-type cladding layer 27 is as high as that of the first p-type cladding layer 24.

[0039] The tunnel diode layer 28 is disposed between the first n-type layer 26 and the second p-type layer 31, and is in contact with the first n-type layer 26 and the second p-type layer 31. The tunnel diode layer 28 allows holes injected from the anode electrode 13 to pass to the second semiconductor light emitting layer 33, and allows electrons injected from the cathode electrode 40 to pass to the first semiconductor light emitting layer 25. Therefore, electrons and holes are injected into each of the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33, and the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33 radiate light.

[0040] The tunnel diode layer 28 includes, for example, an n-type layer disposed on the first n-type cladding layer 27. ++ Tunnel layer 29 and configuration in n ++ p on tunnel layer 29 ++ Tunnel layer 30. n ++ The tunnel layer 29 is, for example, an AlGaAs layer doped with tellurium (Te). ++ The tunnel layer 30 is, for example, an AlGaAs layer doped with carbon (C). ++ The Al composition ratio and p ++ The Al composition ratio of the tunnel layer 30 is as low as the Al composition ratio of the p-type window layer 23 .

[0041] The second p-type layer 31 is disposed on the tunnel diode layer 28 (p ++ The second p-type layer 31 is, for example, a second p-type cladding layer 32. The second p-type cladding layer 32 is, for example, an AlGaAs layer doped with carbon (C). The Al composition ratio of the second p-type cladding layer 32 is as high as that of the first p-type cladding layer 24.

[0042] The second semiconductor light emitting layer 33 is arranged on the second p-type layer 31 (the second p-type cladding layer 32). The second semiconductor light emitting layer 33 is a layer that radiates light when current is injected into the semiconductor light emitting device 1. The wavelength of the light radiated from the second semiconductor light emitting layer 33 is, for example, greater than 800 nm and less than 1000 nm. For example, the second semiconductor light emitting layer 33 is configured in the same manner as the first semiconductor light emitting layer 25, and radiates light having the same wavelength as the first semiconductor light emitting layer 25. Since light is radiated from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33, the light output of the semiconductor light emitting device 1 is increased. The second semiconductor light emitting layer 33 is, for example, a multiple quantum well (MQW) layer. In the second semiconductor light emitting layer 33, for example, it is an MQW layer in which InGaAs well layers and AlGaAsP barrier layers are alternately stacked. The second semiconductor light emitting layer 33 is, for example, an undoped layer.

[0043] The second n-type layer 35 is disposed on the second semiconductor light emitting layer 33. The second n-type layer 35 includes a second n-type cladding layer 36, an n-type window layer 37, and an n-type contact layer 38.

[0044] The second n-type cladding layer 36 is disposed on the second semiconductor light emitting layer 33. The second n-type cladding layer 36 is, for example, an AlGaAs layer doped with selenium (Se). The Al composition ratio of the second n-type cladding layer 36 is as high as that of the first n-type cladding layer 27.

[0045] The n-type window layer 37 is arranged on the second n-type cladding layer 36. The n-type window layer 37 is, for example, an AlGaAs layer doped with silicon (Si). The Al composition ratio of the n-type window layer 37 is lower than the Al composition ratio of the second n-type cladding layer 36. The Al composition ratio of the n-type window layer 37 is as low as the Al composition ratio of the p-type window layer 23. A concavo-convex structure 37a is formed in a portion of the surface of the n-type window layer 37 exposed from the n-type contact layer 38 and the cathode electrode 40. The concavo-convex structure 37a improves the light extraction efficiency from the semiconductor light emitting device 1.

[0046] The n-type contact layer 38 is disposed on the n-type window layer 37. The n-type contact layer 38 is a low resistance layer for making ohmic contact with the cathode electrode 40. The n-type contact layer 38 is, for example, a layer having the highest n-type doping concentration or carrier concentration (electron concentration) in the second n-type layer 35. The n-type contact layer 38 is, for example, a GaAs layer doped with silicon (Si).

[0047] The anode electrode 13 is disposed on the main surface 12 of the substrate 10. The anode electrode 13 is formed of, for example, a metal material such as Au or an alloy containing Au. In the present embodiment, the anode electrode 13 is, for example, a stacked body of Ti / Au (on the substrate 10 side).

[0048] The cathode electrode 40 is formed of, for example, a metal material such as Au or an alloy containing Au. In the present embodiment, the cathode electrode 40 is, for example, a stack of AuGeNi / Au (n-type contact layer 38 side). The cathode electrode 40 includes a pad electrode 41 and a branch electrode 42. In order to inject current into the semiconductor light-emitting device 1, a conductive wire (not shown) is bonded to the pad electrode 41. The branch electrode 42 extends in a branch-like manner from the pad electrode 41 in a manner that divides the semiconductor light-emitting stack 20 into a plurality of regions when viewed from above the main surface 11.

[0049] The area ratio of the plurality of conductive portions 17 to the bottom surface 20a of the semiconductor light emitting stack 20 is 7% or more and 15% or less. In the present specification, the area ratio of the plurality of conductive portions 17 to the bottom surface 20a of the semiconductor light emitting stack 20 is a ratio of the area of ​​the plurality of conductive portions 17 overlapping the bottom surface 20a of the semiconductor light emitting stack 20 to the first area of ​​the bottom surface 20a of the semiconductor light emitting stack 20 when viewed from above the principal surface 11. The top view of the principal surface 11 of the substrate 10 is the top view of the bottom surface 20a of the semiconductor light emitting stack 20.

[0050] Reference Figures 2 to 11, an example of a method for manufacturing the semiconductor light emitting device 1 of the present embodiment is described.

[0051] Reference Figure 3 , a semiconductor light emitting stack 20 is formed on a growth substrate 45. The growth substrate 45 includes a support substrate 46 and an etching stopper layer 47. The support substrate 46 is formed of, for example, GaAs. The etching stopper layer 47 is disposed on the support substrate 46. The etching stopper layer 47 is formed of, for example, AlInGaP. The etching stopper layer 47 is formed on the support substrate 46 by, for example, an epitaxial growth method such as an organic metal chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method.

[0052] The semiconductor light emitting stack 20 is formed on the growth substrate 45 (etching stop layer 47) by an epitaxial growth method such as an organic metal chemical vapor deposition (MOCVD) method or a molecular beam epitaxy (MBE) method. The n-type contact layer 38, the n-type window layer 37, the second n-type cladding layer 36, the second semiconductor light emitting layer 33, the second p-type cladding layer 32, and the p-type cladding layer 33 are sequentially stacked from the growth substrate 45 side. ++ Tunnel layer 30, n ++ The tunnel layer 29 , the first n-type cladding layer 27 , the first semiconductor light emitting layer 25 , the first p-type cladding layer 24 , the p-type window layer 23 , and the p-type contact layer 22 form a semiconductor light emitting stack 20 .

[0053] Reference Figure 4 , a current limiting layer 15 is formed on the p-type contact layer 22. Specifically, an insulating layer 16 is formed on the p-type contact layer 22 by chemical vapor deposition (CVD). A plurality of through holes are formed in the insulating layer 16 by etching a portion of the insulating layer 16. A plurality of conductive portions 17 are formed in the plurality of through holes by vapor deposition. In this way, the current limiting layer 15 is formed.

[0054] Reference Figure 5 , a first metal layer 14a is formed on the current limiting layer 15 by evaporation. The first metal layer 14a is formed of Au or an alloy containing Au. At least the outermost surface of the first metal layer 14a is formed of Au. In this way, a stacked body including the semiconductor light-emitting stacked body 20, the current limiting layer 15 and the first metal layer 14a is formed on the growth substrate 45.

[0055] Reference Figure 6, the substrate 10 is bonded to the stack formed on the growth substrate 45. Specifically, the second metal layer 14b is formed on the main surface 11 of the substrate 10 by evaporation. The second metal layer 14b is formed of Au or an alloy containing Au. At least the outermost surface of the second metal layer 14b is formed of Au. Then, the first metal layer 14a and the second metal layer 14b are bonded. The first metal layer 14a and the second metal layer 14b are bonded, for example, by thermal compression. The first metal layer 14a and the second metal layer 14b are bonded to each other to form the reflective layer 14.

[0056] Reference Figure 7 , the growth substrate 45 is removed. Specifically, the support substrate 46 is removed by wet etching. The etching stopper layer 47 is hardly etched by the wet etching and functions as an etching stopper layer for the wet etching. Then, the etching stopper layer 47 is removed by another etching. In this way, the growth substrate 45 is removed.

[0057] Reference Figure 8 , the n-type contact layer 38 is patterned. Specifically, a resist 48 is formed on the n-type contact layer 38. The resist 48 has, for example, the same pattern as the cathode electrode 40. Then, the n-type contact layer 38 is etched using the resist 48 as a mask. A portion of the n-type contact layer 38 exposed from the resist 48 is removed, and the n-type contact layer 38 having the same pattern as the cathode electrode 40 is formed. The n-type window layer 37 is exposed from the resist 48 and the n-type contact layer 38 through the opening of the resist 48 and the opening of the n-type contact layer 38.

[0058] Reference Fig. 9 For example, by frosting, a concavo-convex structure 37a is formed on the surface of the n-type window layer 37 exposed from the resist 48. The frosting may be performed by wet etching or dry etching.

[0059] Reference Fig.10 , and the resist 48 is removed. A cathode electrode 40 is formed on the n-type contact layer 38. The cathode electrode 40 is formed, for example, by vapor deposition of a metal layer and removal of a portion of the metal layer by a lift-off method.

[0060] Reference Fig.11 , a mesa structure 2 is formed on the semiconductor light emitting stack 20. The mesa structure 2 is formed, for example, by wet etching the side surface of the semiconductor light emitting stack 20. Then, an anode electrode 13 is formed on the main surface 12 of the substrate 10, for example, by vapor deposition. In this way, the semiconductor light emitting device 1 is obtained.

[0061] The operation of the semiconductor light emitting device 1 according to this embodiment will be described.

[0062] A voltage higher than that of the cathode electrode 40 is applied to the anode electrode 13, and a forward bias voltage V is applied to the semiconductor light emitting device 1. f A forward current I flows from the anode electrode 13 to the cathode electrode 40. f In this embodiment, the forward current I f The current is high at 3 amperes or more, and the light output of the semiconductor light emitting device 1 is high at 1 W or more. Holes are injected from the anode electrode 13 through the substrate 10, the reflective layer 14, and the plurality of conductive portions 17 into the semiconductor light emitting device 1. Electrons are injected from the cathode electrode 40 into the semiconductor light emitting device 1. Electrons and holes pass through the tunnel diode layer 28. Therefore, carriers (electrons and holes) are injected into the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33.

[0063] Electrons and holes are combined in the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33, and light is emitted from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33. The light emitted from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33 is reflected by the reflective layer 14 and the plurality of conductive portions 17. The light emitted from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33 is taken out to the outside of the semiconductor light emitting device 1 through the concavo-convex structure 37a and the like. In this way, the semiconductor light emitting device 1 emits light.

[0064] Reference Fig.12 and Fig.13 The results of the sample of the semiconductor light emitting device 1 shown in the figure are used to illustrate the function of the semiconductor light emitting device 1 of the present embodiment. The sample of the semiconductor light emitting device 1 includes a reflective layer 14 formed of Au and a p-type contact layer 22 formed of AlGaAsP doped with carbon (C). In the sample, each of the plurality of conductive portions 17 has a diameter of 10 μm, the bottom surface 20a of the semiconductor light emitting stack 20 has a size of 1020 μm×1020 μm when viewed from above the main surface 11, and the wavelength of light emitted from the first semiconductor light emitting layer 25 and the second semiconductor light emitting layer 33 is 940 nm.

[0065] Fig.12 It is a graph showing the relationship between the area ratio of the plurality of conductive parts 17 to the bottom surface 20 a of the semiconductor light emitting stack 20 and the light output of the semiconductor light emitting device 1 . Fig.12 The light output of the semiconductor light emitting device 1 shown is a forward current I of 5 amperes. f Light output P5 of the semiconductor light emitting device 1 when injected into the semiconductor light emitting device 1 .

[0066] like Fig.12 As shown, the light output P5 of the semiconductor light emitting device 1 when the area ratio is less than 7% is lower than the light output P5 of the semiconductor light emitting device 1 when the area ratio is 7% to 15%. The reason is as follows.

[0067] The holes do not pass through the insulating layer 16 in the current limiting layer 15, but pass through the multiple conductive parts 17 in the current limiting layer 15. Therefore, when the above-mentioned area ratio is less than 7%, the holes are locally concentrated in the semiconductor light-emitting stack 20. If a high current such as 5 amperes is injected into the semiconductor light-emitting device 1, non-luminescent recombination of carriers (electrons and holes) occurs more frequently, and the luminous efficiency of the semiconductor light-emitting device 1 decreases. That is, when the above-mentioned area ratio is less than 7%, a droop effect occurs. In contrast, when the above-mentioned area ratio is 7% or more, the local concentration of holes in the semiconductor light-emitting stack 20 is alleviated. Therefore, even if a high current such as 5 amperes is injected into the semiconductor light-emitting device 1, the non-luminescent recombination of carriers is suppressed, and the luminous efficiency of the semiconductor light-emitting device 1 is increased. That is, when the above-mentioned area ratio is 7% or more, the droop effect is suppressed.

[0068] like Fig.12 As shown, the light output P5 of the semiconductor light emitting device 1 when the area ratio is greater than 15% is lower than the light output P5 of the semiconductor light emitting device 1 when the area ratio is greater than 7% and less than 15%. The reason is that when the area ratio is greater than 15%, the current density in the semiconductor light emitting stack 20 becomes too low, and the light emission efficiency of the semiconductor light emitting device 1 is reduced.

[0069] Fig.13 The relationship between the carrier concentration (hole concentration) of the p-type contact layer 22 and the forward voltage V of the semiconductor light emitting device 1 is shown in FIG. f The carrier concentration of the p-type contact layer 22 is adjusted by the amount of carbon (C) doped into the p-type contact layer 22 formed of AlGaAsP. Fig.13 The forward voltage V of the semiconductor light emitting device 1 is shown f is the forward current I of 1 ampere f The forward voltage V of the semiconductor light emitting device 1 when the semiconductor light emitting device 1 is injected f1 .

[0070] like Fig.13 As shown, the carrier concentration in the p-type contact layer 22 is 1.0×10 19 cm -3 In the above case, the ohmic contact between the plurality of conductive portions 17 and the p-type contact layer 22 is improved, so the forward voltage V f For example, by forming the p-type contact layer 22 from AlGaAsP doped with carbon (C), more carbon (C) can be doped into the p-type contact layer 22 made of AlGaAsP, and the carrier concentration of the p-type contact layer 22 can be easily made 1.0×1019 cm -3 above.

[0071] In contrast, the carrier concentration in the p-type contact layer 22 is less than 1.0×10 19 cm -3 In the case of , the ohmic contact between the plurality of conductive portions 17 and the p-type contact layer 22 is insufficient, so the forward voltage V f For example, when the p-type contact layer 22 is formed of GaP doped with zinc (Zn), the carrier concentration of the p-type contact layer 22 is less than 1.0×10 19 cm -3 .

[0072] Modifications of this embodiment will be described.

[0073] The arrangement of the branch electrodes 42 is not limited to Figure 1 The configuration of the branch electrodes 42 shown in FIG. Fig.14 The configuration of the branch electrodes 42 shown may also be Fig.15 The configuration of the branch electrodes 42 is shown.

[0074] like Fig.16 As shown in FIG. 1 , when viewed from above the main surface 11, the plurality of conductive portions 17 may be arranged unevenly. Fig.16 As shown, the first area ratio of the plurality of conductive portions 17 in the central portion of the semiconductor light emitting stack 20 may be smaller than the second area ratio of the plurality of conductive portions 17 in the peripheral portion of the semiconductor light emitting stack 20. The first area ratio is the ratio of the area of ​​the plurality of conductive portions 17 overlapping with the central portion of the semiconductor light emitting stack 20 relative to the area of ​​the central portion of the semiconductor light emitting stack 20 when viewed from the main surface 11. The second area ratio is the ratio of the area of ​​the plurality of conductive portions 17 overlapping with the peripheral portion of the semiconductor light emitting stack 20 relative to the area of ​​the peripheral portion of the semiconductor light emitting stack 20 when viewed from the main surface 11.

[0075] The semiconductor light emitting device 1 includes two semiconductor light emitting layers (a first semiconductor light emitting layer 25 and a second semiconductor light emitting layer 33), but may include one semiconductor light emitting layer or may include three or more semiconductor light emitting layers. The semiconductor light emitting device 1 may also be a laser diode (LD).

[0076] Effects of the semiconductor light emitting device 1 of this embodiment will be described.

[0077] The semiconductor light emitting device 1 of the present invention includes a current limiting layer 15 and a semiconductor light emitting stack 20. The semiconductor light emitting stack 20 is arranged on the current limiting layer 15 and has a bottom surface 20a in contact with the current limiting layer 15. The current limiting layer 15 includes an insulating layer 16 and a plurality of conductive portions 17. The plurality of conductive portions 17 are arranged in the insulating layer 16 and in contact with the bottom surface 20a. The area ratio of the plurality of conductive portions 17 to the bottom surface 20a is greater than 7% and less than 15%. The above-mentioned area ratio is the ratio of the second area of ​​the plurality of conductive portions 17 overlapping the bottom surface 20a when the bottom surface 20a is viewed from above to the first area of ​​the bottom surface 20a.

[0078] Since the above-mentioned area ratio is 7% or more, the local concentration of holes in the semiconductor light-emitting stack 20 is alleviated. Even if a high current is injected into the semiconductor light-emitting device 1, the non-luminescent recombination of carriers (electrons and holes) is suppressed, and the luminous efficiency of the semiconductor light-emitting device 1 is increased. That is, when the above-mentioned area ratio is 7% or more, the droop effect is suppressed. In addition, since the above-mentioned area ratio is 15% or less, the current density in the semiconductor light-emitting stack 20 can be prevented from becoming too low. The luminous efficiency of the semiconductor light-emitting device 1 is increased. Therefore, the light output of the semiconductor light-emitting device 1 when a high current is injected is improved.

[0079] In the semiconductor light emitting device 1 of the present embodiment, the plurality of conductive portions 17 are formed of gold (Au).

[0080] Therefore, the reflectivity of the plurality of conductive portions 17 for light emitted from the semiconductor light emitting layer (first semiconductor light emitting layer 25) increases. The light is reflected by the plurality of conductive portions 17, is not absorbed by the substrate 10, and is emitted to the outside of the semiconductor light emitting device 1. The light output of the semiconductor light emitting device 1 increases.

[0081] In the semiconductor light emitting device 1 of the present embodiment, the semiconductor light emitting stack 20 includes a p-type contact layer 22 in contact with the plurality of conductive portions 17. The carrier concentration of the p-type contact layer 22 is 1×10 19 cm -3 above.

[0082] Therefore, the ohmic contact between the plurality of conductive portions 17 and the p-type contact layer 22 is improved. The forward voltage V f reduce.

[0083] In the semiconductor light emitting device 1 of the present embodiment, the p-type contact layer 22 is formed of p-AlGaAsP doped with a p-type dopant.

[0084] Therefore, the carrier concentration of the p-type contact layer 22 can be easily increased to 1×10 19 cm -3The ohmic contact between the plurality of conductive portions 17 and the p-type contact layer 22 is improved. The forward voltage V of the semiconductor light emitting device 1 f reduce.

[0085] The semiconductor light emitting device 1 of the present embodiment further includes a reflective layer 14 disposed on the surface of the current confinement layer 15 on the opposite side to the semiconductor light emitting stack 20 . The plurality of conductive portions 17 are in contact with the reflective layer 14 .

[0086] The light emitted from the semiconductor light emitting stack 20 is reflected by the reflective layer 14 and is therefore not absorbed by the substrate 10 but emitted to the outside of the semiconductor light emitting device 1. The light output of the semiconductor light emitting device 1 is increased.

[0087] In the semiconductor light emitting device 1 of the present embodiment, the plurality of conductive portions 17 are evenly arranged in a plan view of the bottom surface 20 a .

[0088] Therefore, the semiconductor light emitting device 1 can emit light uniformly, and the light output of the semiconductor light emitting device 1 increases.

[0089] In the semiconductor light emitting device 1 of the present embodiment, the first area ratio of the plurality of conductive portions 17 in the central portion of the semiconductor light emitting stack 20 is smaller than the second area ratio of the plurality of conductive portions 17 in the peripheral portion of the semiconductor light emitting stack 20. The first area ratio is the ratio of the area of ​​the plurality of conductive portions 17 overlapping the central portion of the semiconductor light emitting stack 20 when viewed from the bottom surface 20a to the area of ​​the central portion of the semiconductor light emitting stack 20. The second area ratio is the ratio of the area of ​​the plurality of conductive portions 17 overlapping the peripheral portion of the semiconductor light emitting stack 20 when viewed from the bottom surface 20a to the area of ​​the peripheral portion of the semiconductor light emitting stack 20.

[0090] Therefore, it is possible to alleviate the concentration of carriers in the central portion of the semiconductor light-emitting stack 20. Even when a high current is injected into the semiconductor light-emitting device 1, non-luminescent recombination of carriers is suppressed, and the luminous efficiency of the semiconductor light-emitting device 1 is increased. The droop effect is suppressed. The light output of the semiconductor light-emitting device 1 when a high current is injected is improved.

[0091] Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

[0092] (Note 1)

[0093] A semiconductor light emitting device, comprising:

[0094] a current confining layer; and

[0095] a semiconductor light emitting stack, which is disposed on the current limiting layer and has a bottom surface in contact with the current limiting layer,

[0096] The current limiting layer includes an insulating layer and a plurality of conductive portions arranged in the insulating layer and in contact with the bottom surface.

[0097] The area ratio of the plurality of conductive portions to the bottom surface is 7% or more and 15% or less,

[0098] The area ratio is a ratio of a second area of ​​the plurality of conductive portions overlapping the bottom surface to a first area of ​​the bottom surface when the bottom surface is viewed from above.

[0099] (Note 2)

[0100] The semiconductor light emitting device according to Appendix 1, wherein:

[0101] The plurality of conductive portions are formed of gold.

[0102] (Note 3)

[0103] The semiconductor light emitting device according to Appendix 1 or 2, wherein:

[0104] The semiconductor light emitting stack includes a p-type contact layer in contact with the plurality of conductive portions.

[0105] The carrier concentration of the p-type contact layer is 1×10 19 cm -3 above.

[0106] (Note 4)

[0107] A semiconductor light emitting device according to Appendix 3, wherein:

[0108] The p-type contact layer is formed of p-AlGaAsP doped with a p-type dopant.

[0109] (Note 5)

[0110] The semiconductor light emitting device according to any one of appendices 1 to 4, wherein:

[0111] It also includes a reflective layer, which is arranged on the surface of the current confinement layer on the opposite side to the semiconductor light emitting stack.

[0112] The plurality of conductive portions are in contact with the reflective layer.

[0113] (Note 6)

[0114] The semiconductor light emitting device according to any one of Supplements 1 to 5, wherein:

[0115] In the plan view of the bottom surface, the plurality of conductive portions are evenly arranged.

[0116] (Note 7)

[0117] The semiconductor light emitting device according to any one of Supplements 1 to 5, wherein:

[0118] A first area ratio of the plurality of conductive portions in a central portion of the semiconductor light emitting stack is smaller than a second area ratio of the plurality of conductive portions in a peripheral portion of the semiconductor light emitting stack.

[0119] The first area ratio is a ratio of the area of ​​the plurality of conductive portions overlapping the central portion of the semiconductor light emitting stack relative to the area of ​​the central portion of the semiconductor light emitting stack when viewed from above the bottom surface.

[0120] The second area ratio is a ratio of the area of ​​the plurality of conductive portions overlapping the peripheral portion of the semiconductor light emitting stack to the area of ​​the peripheral portion of the semiconductor light emitting stack in the plan view of the bottom surface.

[0121] The embodiments disclosed this time should be considered as illustrative in all aspects and not restrictive. The scope of the present invention is indicated by the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor light emitting device, characterized in that: include: A current limiting layer; and a semiconductor light emitting stack, which is disposed on the current limiting layer and has a bottom surface in contact with the current limiting layer, The current limiting layer includes an insulating layer and a plurality of conductive portions arranged in the insulating layer and in contact with the bottom surface. The area ratio of the plurality of conductive portions to the bottom surface is 7% or more and 15% or less, The area ratio is a ratio of a second area of ​​the plurality of conductive portions overlapping the bottom surface to a first area of ​​the bottom surface when the bottom surface is viewed from above.

2. The semiconductor light emitting device according to claim 1, characterized in that: The plurality of conductive portions are formed of gold.

3. The semiconductor light emitting device according to claim 1 or 2, characterized in that: The semiconductor light emitting stack includes a p-type contact layer in contact with the plurality of conductive portions. The carrier concentration of the p-type contact layer is 1×10 19 cm -3 above.

4. The semiconductor light emitting device according to claim 3, characterized in that: The p-type contact layer is formed of p-AlGaAsP doped with a p-type dopant.

5. The semiconductor light emitting device according to any one of claims 1 to 4, characterized in that: It also includes a reflective layer, which is arranged on the surface of the current confinement layer on the opposite side to the semiconductor light emitting stack. The plurality of conductive portions are in contact with the reflective layer.

6. The semiconductor light emitting device according to any one of claims 1 to 5, characterized in that: In the plan view of the bottom surface, the plurality of conductive portions are evenly arranged.

7. The semiconductor light emitting device according to any one of claims 1 to 5, characterized in that: A first area ratio of the plurality of conductive portions in a central portion of the semiconductor light emitting stack is smaller than a second area ratio of the plurality of conductive portions in a peripheral portion of the semiconductor light emitting stack. The first area ratio is a ratio of the area of ​​the plurality of conductive portions overlapping the central portion of the semiconductor light emitting stack relative to the area of ​​the central portion of the semiconductor light emitting stack when viewed from above the bottom surface. The second area ratio is a ratio of the area of ​​the plurality of conductive portions overlapping the peripheral portion of the semiconductor light emitting stack to the area of ​​the peripheral portion of the semiconductor light emitting stack in the plan view of the bottom surface.

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