Testing method and testing device for chip, upper computer, chip and equipment

Abstract

The invention provides a test method and a test device for a chip, an upper computer, the chip and equipment. The method comprises the following steps: obtaining a test circuit built according to the requirement of a hot plug test bench, wherein the test circuit comprises at least one battery module and at least one chip; connecting the at least one chip to the at least one battery module; and testing the function of the at least one chip.

Description

Testing method, testing device, host computer, chip and equipment for chip Technical Field

[0001] The present application relates to the field of battery management technology, and in particular to a chip testing method, testing device, host computer, chip and equipment. Background Art

[0002] Energy conservation and emission reduction are key to the sustainable development of the automotive industry. Electric vehicles, due to their energy-saving and environmentally friendly advantages, have become an important component of the sustainable development of the automotive industry. For electric vehicles, battery technology is a key factor in their development.

[0003] In the field of battery management, various chips are often used to sample batteries and collect their various status. However, these chips are often exposed to live or hot-swappable plugging and unplugging, placing a severe test on the chip's voltage resistance. Therefore, an effective chip testing solution is desired.

[0004] Summary of the Invention

[0005] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, one purpose of the present application is to propose a chip testing method, a testing device, a host computer, a chip and equipment to effectively test the chip performance.

[0006] An embodiment of the first aspect of the present application provides a testing method for a chip, comprising: determining a configuration mode of a test circuit, the test circuit comprising at least one chip and at least one battery module, the at least one chip being capable of being connected to the at least one battery module according to the configuration mode; connecting the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode; determining whether an operation termination condition is met; and testing the performance of the at least one chip in response to determining that the operation termination condition is met.

[0007] In the technical solution of the embodiment of the present application, a standard hot-swap test equipment solution is proposed to standardize hot-swap testing. In practical applications, it can reduce the differences in testing between different chip manufacturers and achieve standardized and normalized chip testing.

[0008] In some embodiments, the test circuit also includes a switch matrix, which is located between the at least one chip and the at least one battery module, and the switch matrix is ​​capable of connecting the at least one chip to the at least one battery module according to the configuration mode, and wherein connecting the at least one chip to the at least one battery module includes: performing a closing operation for closing at least two switches in the switch matrix.

[0009] According to such an embodiment, chip testing can be flexibly performed based on the switch matrix, the complex manual plug-in and plug-out process can be avoided, the required scenarios and working conditions can be flexibly simulated, and the hot-swap function of the AFE can be tested accurately, quickly and more closely to the actual application situation.

[0010] In some embodiments, at least one chip includes a first chip, at least one battery module includes a first battery module, and the hot swap test bench is required to include a first configuration mode, the first configuration mode indicating that the first chip is configured to be connected to corresponding switches of the switch matrix, so that when the corresponding switches are turned on, the sampling channel lines of the first chip can be respectively connected to the corresponding sampling leads of the first battery module.

[0011] According to such an embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration mode of the test close to the chip usage scenario, common chip usage scenarios can be simulated, thereby obtaining more reliable test results.

[0012] In some embodiments, in response to determining that the test circuit is constructed according to the first configuration mode, performing the closing operation includes: closing a pair of switches corresponding to a pair of sampling channel lines in the first chip when none of the switches corresponding to the remaining sampling channel lines except a pair of sampling channel lines associated with the maximum battery potential difference are closed.

[0013] According to such an embodiment, it is possible to further test the operating conditions that may occur in the application scenario for the simulated usage scenario. In particular, by making the test conditions correspond to the configuration mode of the circuit, that is, by simulating the common operating conditions corresponding to the current usage scenario of the chip, it is possible to simulate the common operating conditions corresponding to the current usage scenario of the chip, thereby obtaining true and reliable test results. According to such an embodiment, by first closing the switches of a pair of sampling channel lines associated with the maximum battery potential difference, the maximum voltage difference on the chip can be created. Therefore, according to such an embodiment, by simulating the worst operating conditions, it is more helpful to test the chip function, and the chip obtained after such testing will have satisfactory reliability even when dealing with extreme operating conditions.

[0014] In some embodiments, in response to determining that the test circuit is built according to the first configuration mode, performing the closing operation also includes: after a pair of switches corresponding to a pair of sampling channel lines are closed, causing the switches corresponding to the remaining sampling channel lines in the first chip to be randomly closed.

[0015] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario. By simulating common operating conditions corresponding to the chip's usage scenario, realistic and reliable test results can be obtained. Specifically, by simulating the worst-case operating condition of closing both ends first and then randomly closing the remaining switches, it is possible to cover not only harsh operating conditions but also other common plugging and unplugging conditions. In addition, the use of random closure logic can make the simulation results more realistic and comprehensive.

[0016] In some embodiments, in response to determining that the test circuit is constructed according to the first configuration mode, performing the closing operation includes: randomly closing switches corresponding to sampling channel lines of the first chip.

[0017] According to such an embodiment, it is possible to simulate more common plugging and unplugging conditions by randomly closing the switches corresponding to all sampling channel lines for the simulated usage scenario, thereby making the simulation results more realistic and comprehensive, and thereby obtaining a functionally reliable chip and reducing possible failures during chip use.

[0018] In some embodiments, at least one chip includes a first chip, and at least one battery module includes at least two battery modules connected in series. The hot swap test bench is required to include a second configuration mode, and the second configuration mode indicates that the first chip is configured to be connected to the corresponding switches of the switch matrix, so that when the corresponding switches are turned on, the sampling channel lines of the first chip can be respectively connected to the corresponding sampling leads of the at least two battery modules.

[0019] According to such an embodiment, standardized usage scenario-based testing can be achieved, where the number of sampling channel lines covering the first chip is greater than the number of sampling leads of a single battery module or other scenarios where one chip can be used to sample two or more batteries, thereby achieving true and reliable simulation and testing of such common usage scenarios.

[0020] In some embodiments, in response to determining that the test circuit is in the second configuration mode, performing a closing operation includes: closing the switches corresponding to the sampling leads of the remaining battery modules except the positive side battery module in the at least two battery modules when none of the switches corresponding to the sampling leads of the positive side battery modules in the at least two battery modules are closed; and closing the switch corresponding to the sampling lead associated with the highest battery potential of the positive side battery module after a first time delay has passed since the switches corresponding to the sampling leads of the remaining battery modules were closed.

[0021] According to such an embodiment, the operating conditions that may occur in the application scenario can be further tested for the simulated usage scenario, and a relatively harsh operating condition can be simulated for a scenario in which a chip is connected to two or more battery modules, thereby improving the reliability of the chip obtained by such a testing method.

[0022] In some embodiments, performing the closing operation further includes: after the switch corresponding to the sampling lead associated with the highest battery potential is closed, randomly closing the switches corresponding to the remaining sampling leads of the positive side battery module except the sampling lead associated with the highest battery potential.

[0023] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario, and by using random closed logic, the simulation results can be made more realistic and comprehensive. Specifically, for the first simulated operating condition of the second example scenario, the risks to be borne by sampling channel lines other than the sampling channel line that will be subjected to the maximum voltage difference can also be simulated, thereby performing risk testing and assessment on each sampling channel line of the chip and the corresponding circuit components, obtaining more reliable test results.

[0024] In some embodiments, in response to determining that the test circuit is in the second configuration mode, performing a closing operation includes: closing the switches corresponding to the sampling leads of the remaining battery modules except the negative side battery module in the at least two battery modules when none of the switches corresponding to the sampling leads of the negative side battery modules in the at least two battery modules are closed; and closing the switch corresponding to the sampling lead associated with the lowest battery potential of the negative side battery module after a second delay has passed since the switches corresponding to the sampling leads of the remaining battery modules were closed.

[0025] According to such an embodiment, another relatively severe working condition can be simulated for the second scenario where one chip is connected to two or more battery modules.

[0026] In some embodiments, performing the closing operation further includes: after the switch corresponding to the sampling lead associated with the lowest battery potential is closed, randomly closing the switches corresponding to the remaining sampling leads of the negative side battery module except the sampling lead associated with the lowest battery potential.

[0027] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario, and by using random closure logic, the simulation results can be made more realistic and comprehensive. Specifically, the second simulation condition for the second example scenario can also simulate the risks to be borne by the sampling channel line other than the sampling channel line that will be subjected to the maximum voltage difference, to obtain more reliable test results.

[0028] In some embodiments, at least one chip includes a first chip and a second chip, and at least one battery module includes a first battery module. Obtaining a test circuit built according to the requirements of a hot-swap test bench includes determining that the test circuit is built according to the third configuration mode. The third configuration mode indicates that the first chip and the second chip are configured to be connected to corresponding switches in a switch matrix, so that when the corresponding switches are turned on, the first chip and the second chip can be connected to corresponding sampling leads of the first battery module.

[0029] According to such an embodiment, the number of sampling channel lines that can cover the first chip is less than the number of sampling leads of a single battery module or other scenarios where two or more chips can be used to sample a single battery, thereby achieving true and reliable simulation and testing of such common usage scenarios.

[0030] In some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to the adjacent first sampling lead and second sampling lead of the first battery module, and the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third sampling lead and fourth sampling lead of the first battery module associated with the maximum battery potential difference. In response to determining that the test circuit is constructed according to the third configuration mode, performing a closing operation includes: when the switches corresponding to the remaining sampling channel lines of the first chip and the second chip except the first sampling channel line and the second sampling channel line are not closed, closing the switches corresponding to the first sampling channel line and the second sampling channel line; and after the switches corresponding to the first sampling channel line and the second sampling channel line are closed for a third time delay, closing the switches corresponding to the third sampling channel line and the switches corresponding to the fourth sampling channel line.

[0031] According to such an embodiment, the test effect and the reliability of the chip obtained by the test can be improved by simulating harsh scenarios, and the chip obtained after such testing will have satisfactory reliability even when dealing with extreme working conditions.

[0032] In some embodiments, performing the closing operation further includes: after the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed, randomly closing the switches corresponding to the remaining sampling channel lines of the first chip and the second chip except the first sampling channel line, the second sampling channel line, the third sampling channel line and the fourth sampling channel line.

[0033] According to this embodiment, the simulated usage scenario can be further tested for operating conditions that may occur in the application scenario; using random closure logic can make the simulation results more realistic and comprehensive. In other words, for the first simulated operating condition of the third example scenario, the risks to sampling channel lines other than the sampling channel line that will experience the maximum voltage difference can also be simulated to fully test the chip's tolerance capabilities.

[0034] In some embodiments, in response to determining that the test circuit is constructed according to the third configuration mode, performing the closing operation includes: randomly closing switches corresponding to the sampling channel lines of the first chip and the second chip.

[0035] According to this embodiment, in addition to the worst-case operating conditions provided, other more common operating conditions in practice can also be simulated during testing. According to this embodiment, other common plugging and unplugging conditions can be covered. In addition, the use of random closure logic can make the simulation results more realistic, thereby obtaining reliable and comprehensive test results.

[0036] In some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to the adjacent first sampling lead and second sampling lead of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third sampling lead and fourth sampling lead of the first battery module associated with the maximum battery potential difference, and the third configuration mode also indicates that the first sampling channel line is electrically connected to the second sampling channel line.

[0037] According to such an embodiment, it is possible to further consider the example scenario of the chip being short-circuited in advance, thereby more comprehensively covering the scenarios that the chip may face, thereby obtaining reliable test results.

[0038] In some embodiments, in response to determining that the test circuit is built according to the third configuration mode, performing a closing operation includes: closing the switches corresponding to the sampling channel lines of the second chip when none of the switches corresponding to the sampling channel lines of the first chip are closed; and closing the switches corresponding to the third sampling channel line after the switches corresponding to the sampling channel lines of the second chip are closed for a third time delay.

[0039] According to such an embodiment, the severe working conditions that may be endured during hot plugging and unplugging with a chip short-circuited can be simulated, thereby obtaining reliable test results.

[0040] In some embodiments, performing the closing operation further includes: after the switch corresponding to the third sampling channel line is closed, randomly closing the switches corresponding to the remaining sampling channel lines of the first chip except the third sampling channel line.

[0041] According to such an embodiment, other common plugging and unplugging conditions and various sampling channel lines can be covered, so that risk testing and evaluation can be performed on each sampling channel line of the chip and the corresponding circuit parts to obtain more reliable test results.

[0042] In some embodiments, the operation end condition includes at least one of the following: the number of executions of the closing operation for at least one chip reaches a first threshold, or the number of executions of the closing operation based on a specific configuration mode reaches a second threshold for the specific configuration mode.

[0043] According to such an embodiment, by defining the end condition, the chip test can be further standardized.

[0044] In some embodiments, the testing method also includes, in response to determining that the operation termination condition is not met: performing a power-off operation on the at least one chip; discharging the capacitor in the at least one chip; and repeatedly performing the closing operation for closing at least two switches in the switch matrix and testing the function of the at least one chip, wherein the operation termination condition includes at least one of the following items: the number of executions of the closing operation for the at least one chip reaches a first threshold, or the number of executions for each operating condition in the at least one operating condition reaches a second threshold for the operating condition.

[0045] According to such an embodiment, the influence of capacitor charging can be reduced, and a more realistic test effect can be obtained.

[0046] In some embodiments, the testing method further includes: in response to determining that the step of connecting the at least one chip to the at least one battery module is being performed for the first time, adjusting the voltage of a single cell of a battery in the at least one battery module to a specified value before testing the function of the at least one chip. According to such an embodiment, the stability of the test can be ensured.

[0047] In some embodiments, the testing method further includes testing the function of the at least one chip including performing a supply voltage range test on the at least one chip.

[0048] An embodiment of the second aspect of the present application provides a testing device for a chip, comprising: at least one battery module; a switch matrix; and a host computer capable of controlling the operation of at least one switch in the switch matrix, wherein the switch matrix is ​​configured to connect at least one chip to at least one battery module, and the host computer is configured to execute a method according to an embodiment of the present application.

[0049] In some embodiments, the testing device further includes at least one discharge unit, which is capable of discharging a corresponding capacitor in the at least one chip when the at least one discharge unit is turned on.

[0050] According to such an embodiment, the influence of capacitor charging can be reduced, and a more realistic test effect can be obtained.

[0051] An embodiment of the third aspect of the present application provides a host computer, which is capable of controlling the operation of at least one switch in a switch matrix, the switch matrix being configured to connect at least one chip to at least one battery module, wherein the host computer is configured to execute a method according to an embodiment of the present application.

[0052] An embodiment of the fourth aspect of the present application provides a chip for a battery, which is tested according to the method of the embodiment of the present application.

[0053] An embodiment of the fifth aspect of the present application provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of the embodiment of the present application.

[0054] An embodiment of the sixth aspect of the present application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute a method according to an embodiment of the present application.

[0055] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0057] FIG1 is a schematic structural diagram of a vehicle according to some embodiments of the present application;

[0058] FIG2 is a schematic diagram of the exploded structure of a battery according to some embodiments of the present application;

[0059] FIG3 is a schematic diagram of the exploded structure of a battery cell according to some embodiments of the present application;

[0060] FIG4 is a schematic flow chart of a chip testing method according to some embodiments of the present application;

[0061] FIG5 is a schematic diagram of a test circuit according to some embodiments of the present application;

[0062] FIG6 is a schematic diagram of a test circuit according to some other embodiments of the present application;

[0063] FIG7 is a schematic diagram of a test circuit according to yet other embodiments of the present application;

[0064] FIG8 is a schematic diagram of a test circuit according to yet other embodiments of the present application;

[0065] FIG9 is a schematic diagram of a testing device according to some embodiments of the present application;

[0066] FIG10 is a schematic diagram of a computer device according to some embodiments of the present application;

[0067] FIG11 is a schematic diagram of a test circuit according to some other embodiments of the present application;

[0068] FIG12 is a schematic diagram of a test circuit according to yet other embodiments of the present application;

[0069] FIG13 is a schematic diagram of a test circuit according to yet other embodiments of the present application;

[0070] FIG14 is a schematic diagram of test circuits according to yet other embodiments of the present application.

[0071] Description of reference numerals:

[0072] Vehicles 1000;

[0073] Battery 100, controller 200, motor 300;

[0074] Box body 10, first part 11, second part 12;

[0075] Battery cell 20, end cap 21, electrode terminal 21a, housing 22, battery cell assembly 23, tab 23a;

[0076] Test circuit 500, first battery module 510, switch matrix 520, first chip 530, sampling leads 510-1, 510-2, 510-3 ... 510-N, switches 520-1, 520-2, 520-3 ... 520-N, sampling channel lines 530-1, 530-2, 530-3 ... 530-N;

[0077] Test circuit 600, first battery module 611, second battery module 612, switch matrix 620, first chip 630, sampling leads 610-1, 610-n, 610-(n+1) ... 610-N, switches 620-1, 620-n, 620-(n+1) ... 620-N, sampling channel lines 630-1, 630-n, 630-(n+1) ... 630-N;

[0078] Test circuit 700, first battery module 710, switch matrix 720, first chip 731, second chip 732, sampling leads 710-1, 710-n, 710-(n+1) ... 710-N, switches 720-1, 720-n, 720-(n+1) ... 720-N, sampling channel lines 730-1, 730-n, 730-(n+1) ... 730-N;

[0079] Test circuit 800, first battery module 810, switch matrix 820, first chip 831, second chip 832, sampling leads 810-1, 810-n, 810-(n+1) ... 810-N, switches 820-1, 820-n, 820-(n+1) ... 820-N, sampling channel lines 830-1, 830-n, 830-(n+1) ... 830-N;

[0080] Test circuit 900, first battery module 910, switch matrix 920, first chip 930, host computer 940, sampling leads 910-1, 910-2, 910-3 ... 910-N, switches 920-1, 920-2, 920-3 ... 920-N, sampling channel lines 930-1, 930-2, 930-3 ... 930-N;

[0081] Electronic device 1000;

[0082] Test circuit 1100, at least one battery module 1110, switch matrix 1120, at least one chip 1130, host computer 1140, discharge unit 1150, chips 1131 and 1132, battery modules 1111 and 1112;

[0083] Test circuit 1200, at least one battery module 1210, switch matrix 1220, at least one chip 1230, host computer 1240, discharge unit 1250, chip 1231, battery modules 1211 and 1212;

[0084] Test circuit 1300, at least one battery module 1210, switch matrix 1320, at least one chip 1330, host computer 1340, discharge unit 1350, chips 1331 and 1332, battery module 1311;

[0085] Test circuit 1400 , at least one battery module 1210 , switch matrix 1420 , at least one chip 1430 , host computer 1440 , discharge unit 1450 , chips 1431 and 1432 , and battery module 1411 . DETAILED DESCRIPTION

[0086] The following embodiments of the technical solution of the present application will be described in detail with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present application and are therefore only examples and are not intended to limit the scope of protection of the present application.

[0087] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions.

[0088] In the description of the embodiments of the present application, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. Throughout the different embodiments of the present application, the objects described by "first", "second", etc. should not always be regarded as the same objects. For example, the "first chip" described in one embodiment of the present application may correspond to the "second chip" in another embodiment, and the "first battery module" described in one embodiment of the present application may correspond to the "second battery module" or "third battery module" in another embodiment, and so on. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0089] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0090] In the description of the embodiments of this application, the term "and / or" is simply a description of the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this document generally indicates that the associated objects are in an "or" relationship.

[0091] In the description of the embodiments of the present application, the term "multiple" refers to more than two (including two). Similarly, "multiple groups" refers to more than two groups (including two groups), and "multiple pieces" refers to more than two pieces (including two pieces).

[0092] In the description of the embodiments of the present application, the technical terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0093] In the description of the embodiments of the present application, unless otherwise expressly specified or limited, technical terms such as "installed," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; internal connections between two components or interactions between two components. Those skilled in the art can understand the specific meanings of the above terms in the embodiments of the present application based on specific circumstances.

[0094] / / Overview of the main line of invention

[0095] Currently, market developments indicate that power batteries are becoming increasingly widely used. They are not only used in energy storage systems such as hydropower, thermal, wind, and solar power plants, but are also widely used in electric vehicles like electric bicycles, electric motorcycles, and electric vehicles, as well as in military equipment and aerospace. As power battery applications continue to expand, market demand is also growing.

[0096] In the field of battery management, various chips, including but not limited to analog front-end chips, are often needed to manage and sample batteries. For example, chips can be used to collect information such as battery cell voltage and temperature, or they can be used to support battery balancing functions. Therefore, stable chips are extremely important.

[0097] However, the applicant has noted that chips used in the battery management field are often subject to hot-swap scenarios. This is particularly because the chip itself needs to be connected to a battery, and batteries, as a power source, often have voltage differences between their different pins. Therefore, this poses a more severe test on the chip's functionality.

[0098] The applicant also notes that currently, in the field of battery management systems, there is no effective solution for hot-swap testing of analog front-end chips used for sampling. This lack of an effective testing solution may lead to failures in end applications. Furthermore, the applicant notes that existing, incomplete individual testing solutions often simulate operating conditions by manually pressing on and off buttons, requiring significant human involvement and lacking flexibility and comprehensiveness.

[0099] To this end, the applicant has discovered through research that a hot-swap testing method that can be used in a variety of application scenarios can be designed to achieve flexible chip testing.

[0100] Based on the above considerations, in order to fully verify the hot-swap performance of the chip at the chip design end, a test method for the chip is proposed, including: determining a configuration mode of a test circuit, the test circuit including at least one chip, at least one battery module and a switch matrix, the switch matrix being between the at least one chip and the at least one battery module, and the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode; performing a closing operation for closing at least two switches in the switch matrix based on the configuration mode; determining whether an operation end condition is met; and testing the performance of the at least one chip in response to determining that the operation end condition is met.

[0101] According to such a test scheme, a standardized hot-swap test can be obtained, and the hot-swap performance of the chip can be fully verified before the chip is put into use (for example, at the chip design end), thereby reducing the occurrence of chip abnormalities in the application and alleviating terminal application losses.

[0102] / / Application scenario introduction

[0103] In the embodiments of the present application, the battery cells used in the chips can be, but are not limited to, used in electrical devices such as vehicles, ships, or aircraft. Electrical devices using batteries as power sources can include, but are not limited to, mobile phones, tablets, laptops, electric toys, power tools, electric vehicles, electric cars, ships, spacecraft, and the like. Electric toys can include fixed or mobile electric toys, such as game consoles, electric car toys, electric ship toys, and electric airplane toys, and spacecraft can include airplanes, rockets, space shuttles, and spacecraft, among others.

[0104] For the convenience of description, the following embodiments are described by taking a vehicle 1000 as an example of an electrical device according to an embodiment of the present application.

[0105] Please refer to Figure 1, which is a schematic structural diagram of a vehicle 1000 provided in some embodiments of the present application. The vehicle 1000 can be a fuel vehicle, a gas vehicle or a new energy vehicle. The new energy vehicle can be a pure electric vehicle, a hybrid vehicle or an extended-range vehicle, etc. A battery 100 is provided inside the vehicle 1000, and the battery 100 can be provided at the bottom, head or tail of the vehicle 1000. The battery 100 can be used to power the vehicle 1000. For example, the battery 100 can serve as an operating power source for the vehicle 1000. The vehicle 1000 may also include a controller 200 and a motor 300. The controller 200 is used to control the battery 100 to power the motor 300, for example, for starting, navigating and driving the vehicle 1000.

[0106] In some embodiments of the present application, the battery 100 can serve not only as an operating power source for the vehicle 1000, but also as a driving power source for the vehicle 1000, replacing or partially replacing fuel or natural gas to provide driving power for the vehicle 1000.

[0107] Please refer to Figure 2, which is an exploded view of a battery 100 provided in some embodiments of the present application. The battery 100 includes a housing 10 and a battery cell 20, with the battery cell 20 housed within the housing 10. The housing 10 provides a storage space for the battery cell 20 and can have various structures. In some embodiments, the housing 10 can include a first portion 11 and a second portion 12, which overlap each other and together define a storage space for the battery cell 20. The second portion 12 can be a hollow structure with one end open. The first portion 11 can be a plate-like structure, with the first portion 11 overlapping the open side of the second portion 12, so that the first portion 11 and the second portion 12 together define a storage space. Alternatively, the first portion 11 and the second portion 12 can each be a hollow structure with one end open, with the open side of the first portion 11 overlapping the open side of the second portion 12. Of course, the housing 10 formed by the first portion 11 and the second portion 12 can have various shapes, such as a cylinder, a rectangular parallelepiped, etc.

[0108] In the battery 100, there may be multiple battery cells 20, and the multiple battery cells 20 may be connected in series, in parallel, or in a hybrid connection. A hybrid connection refers to a combination of series and parallel connections among the multiple battery cells 20. The multiple battery cells 20 may be directly connected in series, in parallel, or in a hybrid connection, and then the entire battery cell 20 may be housed within the housing 10. Alternatively, the battery 100 may be constructed by first connecting multiple battery cells 20 in series, in parallel, or in a hybrid connection to form a battery module, which is then connected in series, in parallel, or in a hybrid connection to form a complete battery module, and then housed within the housing 10. The battery 100 may also include other structures, such as a busbar assembly for electrically connecting the multiple battery cells 20.

[0109] Each battery cell 20 may be a secondary battery or a primary battery, and may also be a lithium-sulfur battery, a sodium-ion battery, or a magnesium-ion battery, but is not limited thereto. The battery cell 20 may be cylindrical, flat, rectangular, or in other shapes.

[0110] Please refer to Figure 3, which is a schematic diagram of the exploded structure of a battery cell 20 provided in some embodiments of the present application. A battery cell 20 is the smallest unit that makes up a battery. As shown in Figure 3, a battery cell 20 includes an end cap 21, a housing 22, a cell assembly 23, and other functional components.

[0111] The end cap 21 is a component that covers the opening of the housing 22 to isolate the internal environment of the battery cell 20 from the external environment. Without limitation, the shape of the end cap 21 can be adapted to the shape of the housing 22 to fit the housing 22. According to some embodiments, the end cap 21 can be made of a material with a certain hardness and strength (such as an aluminum alloy). This prevents the end cap 21 from deforming when subjected to compression or collision, giving the battery cell 20 greater structural strength and improved safety. The end cap 21 can be provided with functional components such as electrode terminals 21a. The electrode terminals 21a can be used to electrically connect to the battery cell assembly 23 to output or input electrical energy to the battery cell 20. In some embodiments, the end cap 21 can also be provided with a pressure relief mechanism for relieving internal pressure when the internal pressure or temperature of the battery cell 20 reaches a threshold. The end cap 21 can also be made of a variety of materials, such as copper, iron, aluminum, stainless steel, aluminum alloy, plastic, etc., and the embodiments of the present application are not particularly limited in this regard. In some embodiments, an insulating member may be provided inside the end cap 21 to isolate the electrical connection components in the housing 22 from the end cap 21 to reduce the risk of short circuit. For example, the insulating member may be made of plastic, rubber, or the like.

[0112] The housing 22 is a component that cooperates with the end cap 21 to form the internal environment of the battery cell 20. This internal environment can be used to accommodate the battery cell assembly 23, electrolyte, and other components. The housing 22 and end cap 21 can be separate components. An opening can be provided in the housing 22, and the end cap 21 is placed over the opening to form the internal environment of the battery cell 20. Alternatively, the end cap 21 and housing 22 can be integrated. Specifically, the end cap 21 and housing 22 can form a common connection surface before other components are inserted into the housing. When the interior of the housing 22 needs to be enclosed, the end cap 21 is placed over the housing 22. The housing 22 can have a variety of shapes and sizes, such as a rectangular parallelepiped, a cylindrical shape, a hexagonal prism, etc. Specifically, the shape of the housing 22 can be determined based on the specific shape and size of the battery cell assembly 23. The housing 22 can be made of a variety of materials, such as copper, iron, aluminum, stainless steel, aluminum alloy, plastic, etc., and this embodiment of the present application does not impose any specific limitations on this.

[0113] The battery cell assembly 23 is a component in the battery cell 100 where electrochemical reactions occur. One or more battery cell assemblies 23 may be contained in the shell 22. The battery cell assembly 23 is mainly formed by winding or stacking positive and negative electrode sheets, and a separator is usually provided between the positive and negative electrode sheets. The parts of the positive and negative electrode sheets with active substances constitute the main body of the battery cell assembly, and the parts of the positive and negative electrode sheets without active substances each constitute a tab 23a. The positive and negative electrode tabs may be located together at one end of the main body or respectively at both ends of the main body. During the charge and discharge process of the battery, the positive active substance and the negative active substance react with the electrolyte, and the tabs 23a connect the electrode terminals to form a current loop.

[0114] The following describes a chip testing method 400 according to an embodiment of the present application with reference to FIG4 . As shown in FIG4 , the method 400 may include:

[0115] In step S401 , a configuration mode of a test circuit is determined, where the test circuit includes at least one chip and at least one battery module, and the at least one chip can be connected to the at least one battery module according to the configuration mode.

[0116] At step S402 , the at least one chip is connected to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

[0117] Furthermore, it is understood that a configuration mode can be used to represent a simulated test scenario. A specific configuration mode of a circuit can be implemented, for example, by manually constructing a test bench or by other means. As an example, a configuration mode can be selected from a predetermined set of test modes. As another example, a configuration mode can be selected based on actual conditions, such as the number of sampling channel lines of a chip, the number of cells in a battery module, the characteristics of a specific application scenario in which the chip will be installed, and the like.

[0118] According to the embodiments of the present application, a standard hot-swap test equipment solution is proposed to standardize hot-swap testing. In practical applications, it can reduce the differences in testing between different chip manufacturers and achieve standardized and normalized chip testing.

[0119] In particular, according to the embodiments of the present application, the hot-swap function of the chip can be fully verified before the chip is put into use (for example, at the chip design end), thereby reducing the occurrence of chip anomalies in the application and alleviating terminal application losses.

[0120] The embodiments of this application can be applied to the field of battery management systems, and are particularly suitable for hot-swap testing of analog front-end (AFE) chips, such as those used to sample and manage batteries in new energy vehicles. Therefore, the methods according to the embodiments of this application can also accelerate the design and implementation of terminals, and further promote the healthy development of the new energy vehicle industry.

[0121] In some embodiments, the method further includes testing the performance of the at least one chip. In some embodiments, the method further includes: determining whether an operation termination condition is satisfied before testing the performance of the at least one chip; and testing the performance of the at least one chip in response to determining that the operation termination condition is satisfied.

[0122] It is understood that in some exemplary embodiments, electrical data can be obtained for testing and verification at the end of the working condition and the switch connection process. In some additional or optional exemplary embodiments, electrical data can also be obtained for testing and verification during the switch connection process of each working condition.

[0123] Exemplarily, the method may further include steps S403-S404. In step S403, it is determined whether an operation end condition is satisfied.

[0124] At step S404 , in response to determining that the operation end condition is satisfied, the performance of the at least one chip is tested.

[0125] Satisfying the operation end condition means that the chip's operating condition simulation (e.g., pressurization or power-up) has ended, and the chip can be used for performance testing. As a specific and non-limiting example of an operation end condition, when the closing operation is completed, that is, when at least two switches that need to be closed based on the current configuration mode have been closed (or, have been closed and a certain time delay has passed), the "operation end condition" is considered to be satisfied. Other non-limiting examples of operation end conditions will be described in more detail below.

[0126] The process of testing the performance of the at least one chip may include various functional and performance tests of the chip as understood by those skilled in the art, such as but not limited to one or more tests performed under specific temperature, air pressure, etc. conditions.

[0127] According to some embodiments, the method may include obtaining a test circuit built according to the requirements of a hot-swap test bench, the test circuit including at least one battery module and at least one chip; connecting the at least one chip to the at least one battery module; and testing the function of the at least one chip. The test circuit built according to the requirements of the hot-swap test bench may be a test circuit built according to a desired circuit design, which can be used to simulate one or more desired simulated scenarios or operating conditions. The test circuit built according to the requirements of the hot-swap test bench can be used to connect at least one battery module and the at least one chip, but it is understood that in the step of obtaining the test circuit, the battery module and the chip may have been previously unconnected, for example, never connected, previously connected but disconnected, previously connected but disconnected and fully discharged, and so on.

[0128] It is understood that the chip here may be an analog front-end (AFE) chip, which can be used to process analog signals provided by a signal source and digitize them, and has modules such as an ADC, a multiplexer, and a state machine. More specifically, the chip here may be an analog front-end chip for electric vehicles.

[0129] At least one chip can be combined into a cell monitoring unit (CMU). A CMU can refer to a circuit module obtained by manufacturing an analog front-end chip according to a typical recommended circuit design.

[0130] Hot plugging refers to hot plugging and unplugging a module without turning off the system power.

[0131] According to some embodiments, the test circuit further includes a switch matrix, which is located between the at least one chip and the at least one battery module, and the switch matrix is ​​capable of connecting the at least one chip to the at least one battery module according to the configuration mode, and wherein powering on the at least one chip includes: based on at least one operating condition corresponding to the test circuit, performing a closing operation for closing at least two switches in the switch matrix.

[0132] It is understood that the statement that the switch matrix is ​​capable of "connecting" the at least one chip to the at least one battery module according to at least one operating condition corresponding to the test circuit (or, as described below, according to the configuration mode) does not require that the corresponding switches of the switch matrix are closed, nor does it require that the chip is already in an electrically connected state with the corresponding battery module when the configuration mode of the test circuit is determined. Instead, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode may mean that the first ends of the corresponding switches of the switch matrix are connected to the corresponding connection points of the at least one chip (e.g., the corresponding sampling channel lines), and the second ends of the corresponding switches are connected to the corresponding connection points of at least one battery module of the at least one chip (e.g., the corresponding sampling leads), so that when the corresponding switches are turned on, the chip can be connected to the battery module according to the desired configuration mode. By closing at least two switches in the switch matrix, an electrical connection is established between the chip and the battery module, and a path can be formed between the chip and the battery module, thereby simulating the scenario of hot plugging and unplugging the chip.

[0133] It is also understandable that although a switch matrix is ​​described here, the present disclosure is not limited thereto, and other technical means that can be understood by those skilled in the art and can connect the chip to the battery module can be used to implement the hot plug test according to the present disclosure.

[0134] According to the embodiments of the present application, the switch can be closed based on the configuration mode of the test circuit and the corresponding operating conditions, thereby realizing a standardized chip testing solution.

[0135] According to the embodiments of the present application, by introducing a switch matrix into the configuration circuit, the complex manual plug-in and plug-out process can be avoided, the required scenarios and working conditions can be flexibly simulated, and the hot-swap function of the AFE can be tested accurately, quickly and more closely to the actual application situation.

[0136] According to some embodiments, performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy, wherein the first strategy is used to preferentially close two switches that form a power-on loop with a maximum potential difference; or a second strategy, wherein the second strategy is used to preferentially close switches that can form a path between the at least one battery module.

[0137] According to some embodiments, the at least one chip may include a first chip, and the at least one battery module may include a first battery module. In such embodiments, determining the configuration mode of the test circuit may include determining that the test circuit is in a first configuration mode, wherein the first configuration mode indicates that the first chip is configured to be connected to corresponding switches of the switch matrix, such that when the corresponding switches are turned on, sampling channel lines of the first chip can be respectively connected to corresponding sampling leads of the first battery module.

[0138] It is understood that a configuration mode can be used to represent a simulated test scenario. A specific configuration mode of a circuit can be implemented, for example, by manually building a test bench or through other means. As an example, a configuration mode can be selected from a predetermined set of test modes. As another example, a configuration mode can be selected based on actual conditions, such as the number of sampling channels of the chip, the number of cells in the battery module, the characteristics of the specific application scenario in which the chip will be installed, etc.

[0139] According to such an example, a common usage scenario in which a chip is fully connected to a battery module can be simulated through a first configuration mode, which is referred to as the first example scenario for the convenience of description. As a specific example, the number of sampling channel lines of the first chip can be equal to the number of sampling leads of the first battery module. Figure 5 shows an example diagram of a test circuit for the first configuration mode of the first example scenario. As shown in Figure 5, in the test circuit 500, the first chip 530 is configured to be connected to the corresponding switches 520-1, 520-2, 520-3...520-N of the switch matrix 520, so that when the corresponding switches 520-1, 520-2, 520-3...520-N are turned on, the sampling channel lines 530-1, 530-2, 530-3...530-N of the first chip 530 can be respectively connected to the corresponding sampling leads 510-1, 510-2, 510-3...510-N of the first battery module 510.

[0140] It is understood that although FIG5 shows a one-to-one correspondence between the sampling channels of the first chip and the sampling leads of the first battery module, it is understood that the present application is not limited thereto. As another non-limiting example, in such an embodiment, the number of sampling channels of the first chip may be less than the number of sampling leads of the battery module. For example, only certain sampling leads of the battery module may be sampled, and so on.

[0141] Furthermore, it is understood that although FIG5 shows N switches for connecting N sampling channel lines to N sampling leads, the number N is not limited here, and it is only necessary that N is greater than or equal to 2 so that a voltage difference can be formed on the chip when the corresponding switches are connected.

[0142] According to such an embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration mode of the test close to the chip usage scenario, common chip usage scenarios can be simulated, thereby obtaining more reliable test results.

[0143] According to some embodiments, in response to determining that the test circuit is in the first configuration mode, performing the closing operation includes: closing a pair of switches corresponding to the pair of sampling channel lines in the first chip except for a pair of sampling channel lines associated with the maximum battery potential difference when none of the switches corresponding to the remaining sampling channel lines in the first chip are closed.

[0144] Thus, for the first configuration mode, that is, the first example scenario that is expected to be simulated, a relatively harsh operating condition in which the chip will withstand the maximum possible voltage difference can be provided. For the sake of convenience, this is referred to as the first simulation condition for the first example scenario. It can be understood that the battery potential difference "associated with" a pair of sampling channel lines refers to the potential difference between a pair of sampling leads to which the pair of sampling channel lines will be connected after the corresponding switches are closed. In addition, it can be understood that a pair of sampling channel lines being associated with the maximum battery potential difference means that among the values ​​of the battery potential differences that can be associated with all pairs of sampling channel lines of the first chip, the battery potential difference associated with the pair of sampling channel lines will be the largest. 5 , as a specific example, in an embodiment where the number of sampling channel lines of the first chip is the same as the number of sampling leads of the first battery and they correspond one-to-one, the pair of sampling channel lines associated with the maximum battery potential difference will be the two sampling channel lines to be connected to the sampling lead 510-1 closest to the positive electrode side and the sampling lead 510-N closest to the negative electrode side of the first battery, i.e., 530-1 and 530-N as shown in FIG5 . In such an example, switches 520-1 and 520-N may be closed preferentially before closing the remaining switches.

[0145] It should be understood that throughout this document, phrases such as "closing a pair of switches when none of the other switches are closed," "closing two switches when none of the other switches are closed," "prioritizing closing two switches," or "prioritizing closing a pair of switches" to describe the closing order of two specific switches relative to the closing order of the remaining switches are not intended to limit the closing order of the "pair of switches" or "two switches," unless otherwise specified. Rather, such phrases may include, but are not limited to, the following scenarios: closing the two switches simultaneously, first closing one of the two switches and immediately closing the other, first closing one of the two switches and closing the other after a certain or random delay, etc., as long as the closing time of the two switches satisfies a specific relationship with the "rest of the switches" (e.g., closing earlier than the "rest of the switches").

[0146] It is also understood that closing the pair of switches when none of the switches corresponding to the remaining sampling channel lines are closed can mean closing the pair of switches first or with priority over the remaining switches. It is understood that such a statement does not require that all switches other than the pair of switches be closed in the subsequent closing operation, but only that the pair of switches be closed first. As a specific, non-limiting example, the closing operation can be considered complete only after the pair of switches corresponding to the largest potential difference is closed.

[0147] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario. In particular, by aligning the test conditions with the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current usage scenario of the chip, it is possible to obtain true and reliable test results.

[0148] According to this embodiment, by first closing the switches of the pair of sampling channel lines associated with the largest battery potential difference, the maximum voltage difference on the chip can be generated. Therefore, according to this embodiment, simulating the worst-case operating conditions further facilitates chip performance testing. The resulting chip will have satisfactory reliability even under extreme operating conditions.

[0149] According to some embodiments, in response to determining that the test circuit is in the first configuration mode, performing the closing operation further includes: after the pair of switches corresponding to the pair of sampling channel lines are closed, causing the switches corresponding to the remaining sampling channel lines in the first chip to be randomly closed.

[0150] Thus, the first simulation condition of the first example scenario can also simulate the closure of switches other than the sampling channel line that will be subjected to the maximum voltage difference. It is understood that the expression of random closure used throughout this document can include any of the following: the closing order of the switches is random, the closing delay between each two switches closed in sequence is random, or other random closing parameters that can be understood by those skilled in the art. As a specific non-limiting example, the closing order can include any one or more of sequential, reverse, grouped random order (for example: 2 groups, 3 groups, 4 groups), and random number random order.

[0151] 5 as a specific, non-limiting example, after closing switches 520 - 1 and 520 -N, switches 520 - 2 , 520 - 3 . . . and so on may be randomly closed.

[0152] According to such an embodiment, it is possible to further test the operating conditions that may occur in the application scenario for the simulated usage scenario, and obtain true and reliable test results by simulating common operating conditions corresponding to the chip usage scenario.

[0153] Specifically, by simulating the worst-case scenario of closing both ends first and then randomly closing the remaining switches, we can cover not only the worst-case scenarios but also other common plugging and unplugging scenarios. Furthermore, using random closing logic makes the simulation results more realistic and comprehensive.

[0154] According to some embodiments, in response to determining that the test circuit is in the first configuration mode, performing the closing operation may include: causing switches corresponding to sampling channel lines of the first chip to be randomly closed.

[0155] Therefore, for the first example scenario, in addition to the worst working condition provided, other working conditions that are more common in practice can also be simulated in the test. For the convenience of description, they are referred to as the second simulated working conditions for the first example scenario.

[0156] 5 as a specific non-limiting example, according to the second simulation condition, the switches 520 - 1 ˜ 520 -N may be randomly closed, or at least two of the switches 520 - 1 ˜ 520 -N may be randomly closed.

[0157] It will be appreciated that the closing operation according to this embodiment can be combined with the closing operation according to other embodiments of the present application. For example, for a first configuration mode, one or more closing operations can be performed to close the switches at both ends for a first simulated operating condition, and then, for the same chip, one or more closing operations can be performed to randomly close all switches for a second simulated operating condition, or vice versa. After each closing operation, the switches can be opened, and according to some embodiments, the chip can be discharged. Such exemplary embodiments are further described below.

[0158] According to such an embodiment, it is possible to further test the operating conditions that may occur in the application scenario for the simulated usage scenario. In particular, by simulating common operating conditions corresponding to the chip usage scenario, authentic and reliable test results are obtained.

[0159] In particular, by randomly closing the switches corresponding to all sampling channel lines, more common plugging and unplugging conditions can be simulated, making the simulation results more realistic and comprehensive, and thereby obtaining chips with reliable performance and reducing possible failures during chip use.

[0160] According to some embodiments, the at least one chip may include a first chip, the at least one battery module includes at least two battery modules connected in series, and determining the configuration mode of the test circuit includes determining that the test circuit is in a second configuration mode, the second configuration mode indicating that: the first chip is configured to be connected to the corresponding switches of the switch matrix, so that when the corresponding switches are turned on, the sampling channel lines of the first chip can be respectively connected to the corresponding sampling leads of the at least two battery modules.

[0161] According to such an example, a common usage scenario in which a chip is connected to two or more battery modules can be simulated by a second configuration mode, which is referred to as the second example scenario for the convenience of description. It can be understood that the at least two battery modules connected in series may include the negative electrode of the first battery module being connected to the positive electrode of the second battery module, the negative electrode of the second battery module being connected to the positive electrode of the third battery module... and so on. The sampling channel lines of the first chip can be respectively connected to the corresponding sampling leads of the at least two battery modules, which may mean that the number of sampling channel lines of the first chip is greater than the number of sampling leads of a single battery module in the at least two battery modules. For example, the number of sampling channel lines of the first chip can be equal to the sum of the number of sampling leads of the at least two battery modules.

[0162] Figure 6 shows an example of a second configuration mode for the second example scenario. As shown in Figure 6, in the test circuit 600, the first chip 630 is configured to be connected to the corresponding switches 620-1, ..., 620-n, 620-(n+1), ..., 620-N of the switch matrix 620, so that when the corresponding switches 620-1, ..., 620-n, 620-(n+1), ..., 620-N are turned on, the sampling channel lines 630-1, ..., 630-n of the first chip 630 can be respectively connected to the corresponding sampling leads 610-1 ..., 610-n of the first battery module 611 of the two battery modules 611, 612 connected in series, and the sampling channel lines 630-(n+1), ..., 630-N of the first chip 630 can be respectively connected to the corresponding sampling leads 610-(n+1) ..., 610-N of the second battery module 612.

[0163] It is understood that although FIG6 shows that the at least one battery module includes two battery modules connected in series, more battery modules may also be included. In addition, although FIG6 shows that the sampling channel lines of the first chip correspond one-to-one with the sampling leads of the two battery modules, it is understood that the present application is not limited to this. As another non-limiting example, in such an embodiment, the number of sampling channels of the first chip may also be less than the sum of the number of sampling leads of the battery modules. For example, only certain sampling leads of the battery modules may be sampled, and so on.

[0164] Furthermore, it should be understood that although FIG6 illustrates that the first chip includes N sampling channel lines, each of which can be connected to n sampling leads 610-1…610-n of the first battery module 611 and (Nn) sampling leads of the second battery module 612, these values ​​are not limiting. As a specific example, the first battery module 611 and the second battery module 612 can have the same number of sampling leads, for example, N=2n. In other examples, the first battery module 611 and the second battery module 612 (and, according to some other embodiments, other battery modules connected in series) can have different numbers of sampling leads.

[0165] According to such an embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration mode of the test close to the chip usage scenario, common chip usage scenarios can be simulated, thereby obtaining more reliable test results.

[0166] Specifically, this embodiment can cover scenarios where the number of sampling channel lines on the first chip exceeds the number of sampling leads on a single battery module, or where a single chip can be used to sample two or more batteries, thereby enabling reliable simulation and testing of such common usage scenarios. It is understandable that in this second example scenario, the maximum voltage that the chip can withstand may be greater than the voltage of a single battery module, so covering such scenarios in testing is very beneficial.

[0167] According to some embodiments, in response to determining that the test circuit is in the second configuration mode, performing the closing operation may include: closing the switches corresponding to the sampling leads of the remaining battery modules of the at least two battery modules except the positive side battery module when none of the switches corresponding to the sampling leads of the positive side battery module of the at least two battery modules are closed; and closing the switch corresponding to the sampling lead associated with the highest battery potential of the positive side battery module after a first time delay has passed since the switches corresponding to the sampling leads of the remaining battery modules were closed.

[0168] According to this embodiment, for the second configuration mode, i.e., the second example scenario to be simulated, a working condition can be provided: because the negative-side battery module has already been installed, the sampling channel line corresponding to the positive-side battery module may already be set to a relatively negative voltage potential. In this case, when the positive-side battery module is installed, the chip may be subjected to a large voltage difference in an instant. For ease of description, this is referred to as the first simulation working condition for the second example scenario.

[0169] As those skilled in the art will appreciate, the positive-side battery module can be the battery module closest to the positive electrode of the at least two battery modules connected in series; in other words, the battery module with the highest battery potential. For example, continuing with the example of FIG6 , the positive-side battery module can be the first battery module 611, the "remaining battery modules" can be the second battery module 612, the sampling lead associated with the highest battery potential can be sampling lead 610-1, and the corresponding switch can be switch 620-1. In other words, switches 620-(n+1), ..., 620-N can be closed before switches 620-1, ..., 620-n, and after a certain first delay, the farthest switch 620-1 is closed. The first delay can be any delay selected as needed by those skilled in the art. For example, a longer first delay can be selected to ensure that sampling channel lines 630-1 to 630-n that have not yet been connected to the corresponding sampling lead are already at a relatively low voltage, a shorter first delay can be selected to increase testing efficiency, or a suitable compromise can be found. Alternatively, the first delay can be randomly selected.

[0170] According to some embodiments, closing the switches corresponding to the sampling leads of the remaining battery modules among the at least two battery modules may further include: preferentially closing the switches corresponding to a pair of sampling leads associated with the maximum battery potential difference among the sampling leads of the remaining battery modules, thereby locally simulating relatively harsh working conditions; or, the switches corresponding to the sampling leads of the remaining battery modules may be randomly closed.

[0171] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario. In particular, by aligning the test conditions with the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current usage scenario of the chip, it is possible to obtain true and reliable test results.

[0172] Specifically, through the current embodiment, a relatively severe working condition can be simulated for a scenario where a chip is connected to two or more battery modules, thereby improving the reliability of the chip obtained through such a testing method.

[0173] According to some embodiments, performing the closing operation may further include: after the switch corresponding to the sampling lead associated with the highest battery potential is closed, randomly closing the switches corresponding to the remaining sampling leads of the positive side battery module except the sampling lead associated with the highest battery potential.

[0174] 6 , after closing the farthest switch 620 - 1 , the second switch (not shown) to the nth switch ( 620 - n ) and so on may be closed randomly, thereby performing a power-on test on the corresponding sampling channel line.

[0175] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario, and by using random closed logic, the simulation results can be made more realistic and comprehensive. Specifically, for the first simulated operating condition of the second example scenario, the risks to be borne by sampling channel lines other than the sampling channel line that will be subjected to the maximum voltage difference can also be simulated, thereby performing risk testing and assessment on each sampling channel line of the chip and the corresponding circuit components, obtaining more reliable test results.

[0176] According to some embodiments, in response to determining that the test circuit is in the second configuration mode, performing the closing operation may include: closing the switches corresponding to the sampling leads of the remaining battery modules of the at least two battery modules except the negative side battery module when none of the switches corresponding to the sampling leads of the negative side battery module of the at least two battery modules are closed; and closing the switch corresponding to the sampling lead associated with the lowest battery potential of the negative side battery module after a second delay has passed since the switches corresponding to the sampling leads of the remaining battery modules were closed.

[0177] For the second example scenario, a symmetrical operating condition is provided corresponding to the first operating condition. Because the positive-side battery module has already been installed, the sampling channel corresponding to the negative-side battery module may already be set to a relatively positive voltage potential. At this time, when the negative-side battery module is installed, the chip may be subjected to a large voltage difference in an instant. For ease of description, this is referred to as the second simulation condition for the second example scenario.

[0178] Similarly, as will be understood by those skilled in the art, the negative side battery module may be the battery module closest to the negative electrode of at least two battery modules connected in series, in other words, the battery module with the lowest battery potential. For example, continuing to refer to the example of Figure 6, the negative side battery module may be the second battery module 612, and the "rest of the battery modules" may be the first battery module 611. In other words, switches 620-1, ...620-n may be closed before closing switches 620-(n+1), ...620-N, and after a certain second delay, the farthest switch 620-N is closed. The second delay may be similar to the first delay, for example, it may be the same or similar value as the first delay, or it may be selected according to a strategy similar to the first delay, and will not be described in detail here.

[0179] According to some embodiments, closing the switches corresponding to the sampling leads of the remaining battery modules of the at least two battery modules except the negative-side battery module may include: preferentially closing the switches corresponding to a pair of sampling leads associated with the maximum battery potential difference among the sampling leads of the remaining battery modules, thereby locally simulating relatively harsh working conditions; or, randomly closing the switches corresponding to the sampling leads of the remaining battery modules.

[0180] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario. In particular, by aligning the test conditions with the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current usage scenario of the chip, it is possible to obtain true and reliable test results.

[0181] Specifically, through the current embodiment, another relatively severe working condition is simulated for the second scenario where one chip is connected to two or more battery modules.

[0182] It can be understood that for this second scenario, according to some embodiments, the second operating condition here can be combined with the above-mentioned first operating condition (for example, each test is performed once or multiple times), so as to more comprehensively cover the various application scenarios that the chip may experience, making the test more standardized, comprehensive and reliable.

[0183] According to some embodiments, performing the closing operation may further include: after the switch corresponding to the sampling lead associated with the lowest battery potential is closed, randomly closing the switches corresponding to the remaining sampling leads of the negative side battery module except the sampling lead associated with the lowest battery potential.

[0184] Continuing with the example of FIG6 , for example, after closing the farthest switch 620 -N, the (n+1)th switch to the (N-1)th switch (not shown) and so on may be closed using a random strategy, thereby performing a power-on test on the corresponding sampling channel line.

[0185] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario, and by using random closure logic, the simulation results can be made more realistic and comprehensive. Specifically, the second simulation condition for the second example scenario can also simulate the risks to be borne by the sampling channel line other than the sampling channel line that will be subjected to the maximum voltage difference, to obtain more reliable test results.

[0186] According to some embodiments, the at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and determining the configuration mode of the test circuit includes determining that the test circuit is in a third configuration mode, the third configuration mode indicating that: the first chip and the second chip are configured to be connected to corresponding switches in the switch matrix, so that when the corresponding switches are turned on, the first chip and the second chip can be connected to corresponding sampling leads of the first battery module.

[0187] Based on this example, a third configuration mode can be used to simulate a scenario where two chips are connected to a battery module. For the sake of convenience, this is referred to as the third example scenario. For example, the number of sampling leads of the first battery module can be equal to the sum of the number of sampling channels of the first chip and the second chip. Alternatively, the third example scenario may only require that the number of sampling leads of the first battery module be equal to the number of sampling channels of the first chip, thereby requiring more than one chip to sample the first battery module, without requiring that the number of sampling leads of the first battery module be strictly equal to the number of sampling channels of the first chip and the second chip.

[0188] Figure 7 shows an example of a third configuration mode for a third example scenario. As shown in Figure 7, in a test circuit 700, a first chip 731 is configured to be connected to corresponding switches 720-1, ..., 720-n of the switch matrix 720, and a second chip 732 is configured to be connected to corresponding switches 720-(n+1), ..., 720-N of the switch matrix 720, such that when the corresponding switches 720-1, ..., 720-n, 720-(n+1), ..., 720-N are turned on, the sampling channel lines 730-1, ..., 730-N of the first chip 731 and the second chip 732 can be connected to the corresponding sampling leads 710-1, ..., 710-n, 710-(n+1), ..., 710-N of the battery module 710, respectively.

[0189] It is understood that although FIG7 shows the first chip 731 and the second chip 732, the present application is not limited to this. For example, there may also be a situation where three or more chips sample the same battery module. In addition, although FIG7 shows that the sampling channel lines of the first chip 731 and the second chip 732 correspond one-to-one to the sampling leads of the battery module 710, it is understood that the present application is not limited to this. For example, only certain sampling leads of the battery module may be sampled, and so on. In addition, it is understood that the first chip 731 and the second chip 732 may have the same number of sampling channel lines, for example, N=2n, and the first chip 731 and the second chip 732 may also have different numbers of sampling leads, and the present application is not limited to this.

[0190] According to such an embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration mode of the test close to the chip usage scenario, common chip usage scenarios can be simulated, thereby obtaining more reliable test results.

[0191] Specifically, such an embodiment can cover scenarios where the number of sampling channel lines of the first chip is less than the number of sampling leads of a single battery module or where two or more other chips can be used to sample a single battery, thereby achieving true and reliable simulation and testing of such common usage scenarios.

[0192] According to some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first sampling leads and second sampling leads of the first battery module, and the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third sampling lead and the fourth sampling lead of the first battery module associated with the maximum battery potential difference. In response to determining that the test circuit is in the third configuration mode, performing the closing operation may include: closing the switches corresponding to the first sampling channel line and the second sampling channel line when none of the switches corresponding to the remaining sampling channel lines of the first chip and the second chip except the first sampling channel line and the second sampling channel line are closed; and closing the switches corresponding to the third sampling channel line and the switches corresponding to the fourth sampling channel line after a third time delay has elapsed since the switches corresponding to the first sampling channel line and the second sampling channel line were closed.

[0193] According to this embodiment, for the third configuration mode, i.e., the third example scenario to be simulated, a working condition can be provided: first, the switches corresponding to the adjacent sampling channel lines of the two chips are closed. For ease of description, this is referred to as the first simulation working condition for the third example scenario.

[0194] Continuing with reference to FIG7 , in this exemplary scenario, the adjacent first and second sampling leads of the first battery module are sampling leads 710-n and 710-(n+1), and the corresponding first sampling channel line of the first chip is sampling channel line 730-n, and the second sampling channel line of the second chip is sampling channel line 730-(n+1). The third and fourth sampling leads associated with the maximum battery potential difference are sampling leads 710-1 and 710-N, respectively. Therefore, the third sampling channel line of the first chip can be sampling channel line 730-1, and the fourth sampling channel line of the second chip can be sampling channel line 730-N.

[0195] As shown in FIG7 , it can be understood that, for the third example scenario, the first simulated operating condition envisioned here will be the worst operating condition, because in this scenario, the two adjacent sampling channel lines 730-n and 730-(n+1) of the two chips are respectively connected to the adjacent sampling leads in the battery module through corresponding switches. At this time, the two chips can be approximately regarded as a large chip in the circuit. Therefore, if the switches 720-1 and 720-N corresponding to the two sampling channel lines 730-1 and 730-N at the farthest ends of the chip are turned on, the chip will withstand the voltage of the entire battery module 710.

[0196] In addition, it can be understood that, as described above, the term "closing the switches corresponding to the first sampling channel line and the second sampling channel line" used herein may include but is not limited to the following operating logic: closing switches 720-n and 720-(n+1) simultaneously or almost simultaneously within an allowable error; closing one of switches 720-n and 720-(n+1) first, and immediately closing the other switch; closing one of switches 720-n and 720-(n+1) first, and closing the other switch after a certain delay or a random delay, etc., as long as it is ensured that the two switches corresponding to the first sampling channel line and the second sampling channel line are closed before the other switches are closed so that the two chips can be electrically connected.

[0197] Similarly, it can be understood that “closing the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line” may include but is not limited to the following operation logic: closing the switches 720-1 and 720-N simultaneously or almost simultaneously within an allowable error; first closing one of the switches 720-1 and 720-N and immediately closing the other switch; first closing one of the switches 720-1 and 720-N and closing the other switch after a certain delay or a random delay, etc.

[0198] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario. In particular, by aligning the test conditions with the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current usage scenario of the chip, it is possible to obtain true and reliable test results.

[0199] Specifically, through the current embodiment, the test effect and the reliability of the chip obtained by the test can be improved by simulating harsh scenarios, and the chip obtained after such testing will have satisfactory reliability even when dealing with extreme working conditions.

[0200] According to some embodiments, performing the closing operation may further include: after the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed, randomly closing the switches corresponding to the remaining sampling channel lines of the first chip and the second chip except the first sampling channel line, the second sampling channel line, the third sampling channel line, and the fourth sampling channel line.

[0201] Continuing with the example of FIG. 7 , for example, after first closing the adjacent switches 720 - n and 720 -(n+1), and then closing the farthest switches 720 - 1 and 720 -N, the remaining switches (not shown) may be closed in a random strategy to perform a power-on test on the corresponding sampling channel lines.

[0202] According to this embodiment, the simulated usage scenario can be further tested for operating conditions that may occur in the application scenario; using random closure logic can make the simulation results more realistic and comprehensive. In other words, for the first simulated operating condition of the third example scenario, the risks to sampling channel lines other than the sampling channel line that will experience the maximum voltage difference can also be simulated to fully test the chip's tolerance capabilities.

[0203] According to some embodiments, in response to determining that the test circuit is in the third configuration mode, performing the closing operation may include: randomly closing switches corresponding to sampling channel lines of the first chip and the second chip.

[0204] Continuing with FIG7 , and for ease of description, this operating condition is referred to herein as the second simulation operating condition for the third example scenario. In the second simulation operating condition for the third example scenario, any two or more of switches 720-1, ..., 720-n, 720-(n+1), ..., 720-N may be closed, and such closings may follow a random order, and / or there may be a random time delay between two sequentially closed switches.

[0205] Therefore, for the third example scenario, in addition to the worst-case operating condition provided, other more common operating conditions in practice can also be simulated during testing. This embodiment can cover other common plugging and unplugging conditions. Furthermore, using randomized closed logic can make the simulation results more realistic, thereby obtaining reliable and comprehensive test results.

[0206] According to some embodiments, the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first sampling lead and second sampling lead of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third sampling lead and fourth sampling lead of the first battery module associated with the maximum battery potential difference, and the third configuration mode can also indicate that the first sampling channel line is electrically connected to the second sampling channel line.

[0207] According to this example, in the third example scenario described above, the two chips are further short-circuited. For ease of description, this scenario can be referred to as the fourth example scenario. The fourth example scenario can be used to cover practical applications where the number of sampling channel lines of a single chip is less than the number of sampling leads of a single battery to be sampled. In this case, two or more chips can be short-circuited or connected in series in advance.

[0208] Refer to FIG8 as an example. Similar to FIG7, in the test circuit 800 of FIG8, the first chip 831 is configured to be connected to the corresponding switches 820-1, ... 820-n of the switch matrix 820, and the second chip 832 is configured to be connected to the corresponding switches 820-(n+1), ... 820-N of the switch matrix 820, so that when the corresponding switches 820-1, ... 820-n, 820-(n+1), ... 820-N are turned on, the sampling channel lines 830-1, ... 830-N of the first chip 831 and the second chip 832 can be respectively connected to the corresponding sampling leads 810-1 ... 810-n, 810-(n+1) ... 810-N of the battery module 810. It should also be understood that the number of channels, the number of chips, etc. in the figure are merely examples, and the present application is not limited thereto.

[0209] As shown in FIG8 , the first chip 831 and the second chip 832 are electrically connected via a shorting wire 8301 .

[0210] According to such an embodiment, standardized usage scenario-based testing can be achieved. In particular, by making the circuit configuration mode of the test close to the chip usage scenario, common chip usage scenarios can be simulated, thereby obtaining more reliable test results.

[0211] Specifically, such an embodiment further considers a fourth example scenario in which the chip is short-circuited in advance on the basis of the third scenario, thereby being able to more comprehensively cover the scenarios that the chip may face, thereby obtaining reliable test results.

[0212] According to some embodiments, in response to determining that the test circuit is in the third configuration mode, performing the closing operation may include: closing the switch corresponding to the sampling channel line of the second chip when none of the switches corresponding to the sampling channel line of the first chip are closed; and closing the switch corresponding to the third sampling channel line after a third delay has passed since the switch corresponding to the sampling channel line of the second chip is closed.

[0213] Continuing with Figure 8 as an example, in this exemplary scenario, the adjacent first and second sampling leads of the first battery module are sampling leads 810-n and 810-(n+1), and the corresponding first sampling channel line of the first chip is sampling channel line 830-n, and the second sampling channel line of the second chip is sampling channel line 830-(n+1). The third and fourth sampling leads associated with the maximum battery potential difference are sampling leads 810-1 and 810-N, respectively. Therefore, the third sampling channel line of the first chip can be sampling channel line 830-1, and the fourth sampling channel line of the second chip can be sampling channel line 830-N. In other words, switches 820-(n+1) to 820-N can be closed first, and after the third time delay, switch 820-1 can be closed. For ease of description, this operating condition can be referred to as the first operating condition for the fourth exemplary scenario.

[0214] According to some embodiments, in response to determining that the test circuit is in the third configuration mode, performing the closing operation may include: closing the switch corresponding to the sampling channel line of the first chip when none of the switches corresponding to the sampling channel line of the second chip are closed; and closing the switch corresponding to the fourth sampling channel line after a fourth time delay has elapsed since the switch corresponding to the sampling channel line of the first chip was closed. It will be understood that this operating condition is symmetrical to the first operating condition described above and, for ease of distinction, may be referred to as the second operating condition.

[0215] It is understandable that the third delay and / or the fourth delay may be similar to the first delay and the second delay, for example, may be the same or similar value as the first delay or the second delay, or may be selected according to a strategy similar to the first delay or the second delay, and will not be described in detail here.

[0216] According to such an embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario. In particular, by aligning the test conditions with the circuit configuration mode, that is, by simulating common operating conditions corresponding to the current usage scenario of the chip, it is possible to obtain true and reliable test results.

[0217] Specifically, through the current embodiment, by first closing one of the chips and then delaying the closing of the farthest switch in the other chip, it is possible to simulate the harsh working conditions that can be endured when the chip is plugged in and out under power when it is short-circuited, thereby obtaining reliable test results.

[0218] According to some embodiments, performing the closing operation may further include: after the switch corresponding to the third sampling channel line is closed, randomly closing switches corresponding to the remaining sampling channel lines of the first chip except the third sampling channel line.

[0219] Continuing to refer to FIG8 as an example, for the first operating condition of the fourth example scenario, after the switch 820-1 is closed, the switches (eg, 820-n) corresponding to the remaining sampling channel lines (eg, 830-n) of the first chip 831 may be randomly closed.

[0220] It is understandable that for the aforementioned matching working condition, i.e., the second working condition of the fourth example scenario, subsequent random operations may also be performed. For example, after the switch corresponding to the sampling channel line of the first chip is closed and the switch corresponding to the fourth sampling channel line is closed after a fourth delay, the switches corresponding to the remaining sampling channel lines of the second chip may be randomly closed.

[0221] According to this embodiment, it is possible to further test the operating conditions that may occur in the simulated usage scenario, and by using random closed logic, the simulation results can be made more realistic and comprehensive. Specifically, for the fourth example scenario, other common plugging and unplugging conditions and various sampling channels can be covered, thereby enabling risk testing and assessment of each chip sampling channel and the corresponding circuit components, obtaining more reliable test results.

[0222] According to some embodiments, the operation end condition may include at least one of the following: the number of executions of the closing operation for the at least one chip reaches a first threshold, or the number of executions of the closing operation based on a specific configuration mode reaches a second threshold for the specific configuration mode.

[0223] According to such an embodiment, after the number of tests is met, it can be determined that the operation end condition is met, thereby testing the chip performance, such as a five-point test. It is understandable that the first threshold and the second threshold can also be 1, that is, it can also cover the scenario of only testing once.

[0224] According to some embodiments, the operation termination condition may also include that a closing operation has been achieved under one or more specific operating conditions for a specific configuration mode. As a specific non-limiting example, the operation termination condition may include that, for a first configuration mode (a first example scenario), a first predetermined number of closing operations have been achieved under a first operating condition, and a second predetermined number of closing operations have been achieved under a second operating condition, and so on. As a more specific non-limiting example, the number of hot plugs under each operating condition may be specified to be no less than 30 times, but it will be understood that the present application is not limited to this.

[0225] Therefore, by defining the end conditions, the chip test can be further standardized.

[0226] Specifically, when the first or second threshold in the operation termination condition is set to greater than 1, reliability can be further tested by adding multiple repeated tests under the same operating conditions. For example, if the same first or second threshold is specified for different chip manufacturers or testing locations, chip testing can be further standardized, reducing differences in test results and resulting in more stable and standardized chips.

[0227] According to some embodiments, the testing method may further include, in response to determining that the operation termination condition is not met: performing a power-off operation on the at least one chip; discharging the capacitor in the at least one chip; and repeatedly performing the closing operation for closing at least two switches in the switch matrix and testing the function of the at least one chip, wherein the operation termination condition includes at least one of the following items: the number of executions of the closing operation for the at least one chip reaches a first threshold, or the number of executions for each operating condition in the at least one operating condition reaches a second threshold for the operating condition.

[0228] According to such an embodiment, when the termination condition is not met (for example, the number of times is insufficient or the test is not performed for a specific configuration mode), the switch can be disconnected, the configuration mode can be determined, and the execution can be repeated, thereby further standardizing and automating the test plan, avoiding the manual plugging and unplugging process, and improving the efficiency of the test.

[0229] According to such an embodiment, after the number of tests is met, it can be determined that the operation end condition is met, thereby testing the chip function, such as but not limited to the various sample function tests described below. It is understandable that the first threshold and the second threshold can also be 1, that is, it can also cover the scenario of only testing once.

[0230] According to some embodiments, the operation termination condition may also include that a closing operation has been achieved under one or more specific operating conditions for a specific configuration mode. As a specific non-limiting example, the operation termination condition may include that, for a first configuration mode (a first example scenario), a first predetermined number of closing operations have been achieved under a first operating condition, and a second predetermined number of closing operations have been achieved under a second operating condition, and so on. As a more specific non-limiting example, the number of hot plugs under each operating condition may be specified to be no less than 30 times, but it will be understood that the present application is not limited to this.

[0231] Therefore, by defining the end conditions, the chip test can be further standardized.

[0232] Specifically, when the first or second threshold in the operation termination condition is set to greater than 1, reliability can be further tested by adding multiple repeated tests under the same operating conditions. For example, if the same first or second threshold is specified for different chip manufacturers or testing locations, chip testing can be further standardized, reducing differences in test results and resulting in more stable and standardized chips.

[0233] In addition, according to such an embodiment, a discharge operation is performed before each repeated closing operation to ensure that the repeated operations are performed under the condition that the capacitor is not charged, reducing the impact of the previous operation on the charged capacitor, thereby making the test conditions more severe, and the chip function obtained by the test is more guaranteed. Specifically, if the discharge unit is missing, the AFE chip may be partially charged after the first hot plug (closing operation), and the subsequent hot plug stress will become weaker and weaker. On the contrary, by adding a discharge unit by design, each hot plug is closer to the real situation, thereby obtaining a more realistic test effect, and is more conducive to repeated testing to improve reliability.

[0234] It is understood that the discharge operation can be achieved by grounding, or by other operations that can be understood by those skilled in the art. For example, the discharge process can be considered to be completed after the discharge circuit is connected for a certain period of time. Such a period of time can be determined by those skilled in the art based on experience, experiments or other factors, and can be fixed in the hot plug test, or modified according to other environmental conditions, circuit conditions or sample conditions. The discharge operation can also be a discharge operation for a test bench.

[0235] According to one or more embodiments of the present application, various possible hot-swap scenarios and working conditions in actual applications can be simulated, the application scenarios are wide, and there is considerable standardization and consistency.

[0236] According to some embodiments, the testing method may further include: in response to determining that the step of powering on the at least one chip is performed for the first time for the at least one chip, before testing the function of the at least one chip, adjusting the single cell voltage of the battery in the at least one battery module to a specified value.

[0237] According to such an embodiment, the stability of the test can be ensured. As a non-limiting example, the specified value of the single cell voltage can be 4.25V. For example, the specified value of the single cell voltage can be substantially equal to the cell voltage to be used in the corresponding scenario or operating condition, or it can be higher than the cell voltage to be used in the corresponding scenario or operating condition to obtain more reliable test results. Other examples will be described in detail below in conjunction with specific embodiments.

[0238] According to some embodiments, testing the performance of the at least one chip includes performing a supply voltage range test on the at least one chip.

[0239] The supply voltage range test can be a five-point test, that is, the chip is tested five times under five predetermined combinations of ambient temperature, voltage, etc. The supply voltage range test can also be other tests, inspections, checks, or verifications of the chip's voltage performance that are understood by those skilled in the art.

[0240] Additionally or alternatively, testing the functionality of the at least one chip may further include performing at least one of the following on the at least one chip: a power supply current range test, a cell voltage sampling accuracy test, a cell temperature sampling accuracy test, and a leakage current diagnostic threshold test. It is also understood that these tests may be tests, inspections, checks, or verifications of the corresponding performance of the chip, as understood by those skilled in the art.

[0241] Some non-limiting examples of chip testing are given below and will not be repeated here.

[0242] According to such an embodiment, the performance of the chip can be ensured, thereby making the test effect more reliable.

[0243] According to one or more aspects of the present application, a testing device for a chip is also disclosed, comprising: a switch matrix; and a control device, wherein the control device is capable of controlling the operation of at least one switch in the switch matrix to power on at least one chip according to a configuration mode, and wherein the control device is configured to: connect the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

[0244] According to some example embodiments, the testing device may further include at least one battery module, wherein performing a power-on operation on the at least one chip according to the configuration mode includes connecting the at least one chip to the at least one battery module.

[0245] According to some example embodiments, connecting the at least one chip to the at least one battery module includes performing a closing operation for closing at least two switches in the switch matrix.

[0246] According to some exemplary embodiments, performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy, wherein the first strategy is used to preferentially close two switches that form a power-on loop with a maximum potential difference; or a second strategy, wherein the second strategy is used to preferentially close switches that can form a path between the at least one battery module.

[0247] According to some exemplary embodiments, the testing device comprises an interface for connecting to the at least one chip, for example, an interface for connecting to a chip under test such as an AFE or a CSC.

[0248] According to some exemplary embodiments, the control device includes a host computer.

[0249] According to one or more aspects of the present application, a testing device for a chip is also disclosed, comprising: at least one battery module; a switch matrix; and a host computer, wherein the host computer is capable of controlling the operation of at least one switch in the switch matrix, wherein the switch matrix is ​​capable of connecting at least one chip to the at least one battery module, and the host computer is configured to execute the method described in one or more embodiments of the present application.

[0250] 9 , a test apparatus 900 may include at least one battery module 910, a switch matrix 920, and a host computer 940. At least one chip 930 may be configured to be connected to corresponding switches 920-1, 920-2, 920-3, ..., 920-N of the switch matrix 920, such that when the corresponding switches 920-1, 920-2, 920-3, ..., 920-N are turned on, the sampling channel lines 930-1, 930-2, 930-3, ..., 930-N of the at least one chip 930 can be respectively connected to the corresponding sampling leads 910-1, 910-2, 910-3, ..., 910-N of the at least one battery module 910.

[0251] As those skilled in the art will appreciate, the upper computer being able to control the operation of at least one switch in the switch matrix may mean that the upper computer is able to be electrically connected, signal-connected, or otherwise operably connected to the switch matrix to control the opening or closing of one or more switches in the switch matrix.

[0252] According to some embodiments, the testing device may further include at least one discharge unit, which is capable of discharging a corresponding capacitor in the at least one chip when turned on.

[0253] For example, referring to FIG9 , the test apparatus 900 may further include a discharge unit 950 . Specifically, the discharge unit 950 may include a grounding switch and a resistor. Alternatively, the discharge unit may employ other circuit configurations capable of discharging a capacitor, and the present application is not limited thereto.

[0254] According to such an embodiment, by providing a grounding switch, the chip can be discharged, thereby enabling a closing operation to be performed while the capacitor is discharged, reducing the impact of possible capacitor charge in the chip, thereby achieving more reliable testing.

[0255] According to one or more aspects of the present application, a host computer is also disclosed, which is capable of controlling the operation of at least one switch in a switch matrix, wherein the switch matrix is ​​configured to connect at least one chip to at least one battery module, wherein the host computer is configured to execute the method described in one or more embodiments of the present application.

[0256] According to one or more aspects of the present application, a chip for a battery is also disclosed. The chip is tested according to the method described in one or more embodiments of the present application.

[0257] According to one or more aspects of the present application, an electronic device is also disclosed, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method according to one or more embodiments of the present application.

[0258] According to one or more aspects of the present application, a non-transitory computer-readable storage medium storing computer instructions is further disclosed, wherein the computer instructions are used to enable the computer to execute the method according to one or more embodiments of the present application.

[0259] In the following, illustrative examples of a computer device, a non-transitory computer-readable storage medium, and a computer program product according to the present application are described in conjunction with FIG. 10 .

[0260] Figure 10 shows an example configuration of a computer device 1000 that can be used to implement the methods described herein. The computer device 1000 can be a variety of different types of devices, such as a server of a service provider, a device associated with a client (e.g., a client device), a system on a chip, and / or any other suitable computer device or computing system. Examples of computer devices 1000 include, but are not limited to, desktop computers, server computers, laptop or netbook computers, mobile devices (e.g., tablet computers, cellular or other wireless phones (e.g., smart phones), notepad computers, mobile stations), wearable devices (e.g., glasses, watches), or other display devices, car computers, etc. Therefore, the scope of computer devices 1000 can range from full-resource devices (e.g., personal computers) with large amounts of memory and processor resources to low-resource devices with limited memory and / or processing resources.

[0261] The computer device 1000 may include at least one processor 1002, memory 1004, communication interface(s) 1006, a display device 1008, other input / output (I / O) devices 1010, and one or more mass storage devices 1012, all capable of communicating with one another, such as via a system bus 1014 or other appropriate connections.

[0262] The processor 1002 may be a single processing unit or multiple processing units, all of which may include a single or multiple computing units or multiple cores. The processor 1002 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that manipulates signals based on operational instructions. Among other capabilities, the processor 1002 may be configured to retrieve and execute computer-readable instructions stored in the memory 1004, mass storage device 1012, or other computer-readable media, such as program code for an operating system 1016, program code for application programs 1018, program code for other programs 1020, and the like.

[0263] The memory 1004 and the mass storage device 1012 are examples of computer-readable storage media for storing instructions that are executed by the processor 1002 to implement the various functions described above. For example, the memory 1004 may generally include both volatile memory and non-volatile memory (e.g., RAM, ROM, etc.). In addition, the mass storage device 1012 may generally include a hard drive, a solid-state drive, removable media, including external and removable drives, memory cards, flash memory, floppy disks, optical disks (e.g., CDs, DVDs), storage arrays, network attached storage, storage area networks, etc. The memory 1004 and the mass storage device 1012 may all be collectively referred to herein as memory or computer-readable storage media, and may be non-transitory media capable of storing computer-readable, processor-executable program instructions as computer program code, which may be executed by the processor 1002 as a specific machine configured to implement the operations and functions described in the examples herein.

[0264] A plurality of program modules may be stored on the mass storage device 1012. These programs include an operating system 1016, one or more application programs 1018, other programs 1020, and program data 1022, and they may be loaded into the memory 1004 for execution. Examples of such application programs or program modules may include, for example, computer program logic (e.g., computer program code or instructions) for implementing methods according to one or more embodiments of the present application.

[0265] 10 as being stored in the memory 1004 of the computer device 1000, the modules 1016, 1018, 1020, and 1022, or portions thereof, may be implemented using any form of computer-readable media accessible by the computer device 1000. As used herein, "computer-readable media" includes at least two types of computer-readable media, namely, computer storage media and communication media.

[0266] Computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVDs), or other optical storage devices, magnetic cassettes, magnetic tape, magnetic disk storage devices or other magnetic storage devices, or any other non-transmission media that can be used to store information for access by a computer device.

[0267] In contrast, communication media may embody computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism. Computer storage media as defined herein does not include communication media.

[0268] The computer device 1000 may also include one or more communication interfaces 1006 for exchanging data with other devices, such as through a network, a direct connection, etc., as previously discussed. Such communication interfaces may be one or more of the following: any type of network interface (e.g., a network interface card (NIC)), a wired or wireless (such as an IEEE 802.10 wireless LAN (WLAN)) wireless interface, a Worldwide Interoperability for Microwave Access (Wi-MAX) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth TM The communication interface 1006 may include a wireless communication interface, a near field communication (NFC) interface, and the like. The communication interface 1006 may facilitate communication within a variety of network and protocol types, including wired networks (e.g., LAN, cable, etc.) and wireless networks (e.g., WLAN, cellular, satellite, etc.), the Internet, and the like. The communication interface 1006 may also provide for communication with external storage devices (not shown) such as storage arrays, network attached storage, storage area networks, and the like.

[0269] In some examples, a display device 1008 such as a monitor may be included for displaying information and images to the user. Other I / O devices 1010 may be devices that receive various inputs from the user and provide various outputs to the user, and may include a touch input device, a gesture input device, a camera, a keyboard, a remote control, a mouse, a printer, an audio input / output device, and the like.

[0270] Non-limiting specific examples according to the present application will be described below with reference to FIG. 11-14 .

[0271] As shown in FIG. 11 , an exemplary test circuit 1100 may include at least one battery module 1110 , a switch matrix 1120 , at least one chip 1130 , and a host computer 1140 .

[0272] According to the specific example of FIG11 , two analog front-end (AFE) chips 1131 and 1132 are shown. The two AFE chips can be designed using typical recommended circuits to form a cell monitoring circuit (CMC) or a cell monitoring unit (CMU). In some embodiments, a CMC needs to have at least two AFE chips.

[0273] At least one battery module 1110 may include battery modules 1111 and 1112. The number of cells in a battery module may vary in actual applications. Real cells or cell simulators may be used.

[0274] The switch matrix 1120 can include switches for connecting and disconnecting modules and a discharge circuit for discharging the CMC. Closing the on-off switch can equate to plugging in a connector, while opening the switch equates to unplugging the connector. By closing and opening switches (relays, semiconductor switches, etc.), the on-off and off-off of connectors in actual applications can be simulated, providing greater flexibility. Furthermore, the switch matrix, in conjunction with the host computer, can flexibly simulate any plugging and unplugging sequence.

[0275] The host computer 1140 can be used to control the opening and closing logic and closing timing of the switch matrix, simulating hot-swap conditions with different access sequences. In addition, the host computer 1140 can be used to receive and read information from the CMC to confirm whether the circuit function of the CMC is normal after hot-swapping. The host computer 1140 can be used to execute the method described in accordance with one or more embodiments of the present application. It is understood that the present application is not limited thereto, and the method described in accordance with one or more embodiments of the present application can be implemented using other devices, apparatuses, units, code logic, etc.

[0276] Continuing with Figure 11, an example test circuit configuration for the first example scenario is shown. As a specific, non-limiting example, the number of cells in the first battery 1111 matches the number of sampling channels in the first chip 1131. All sampling leads for the first battery 1111 are concentrated on the F1 connector, and all sampling channel lines for the first chip 1131 are concentrated on J1. As a more specific, non-limiting example, the number of cells in the first battery 1111 and the number of sampling channels in the first chip 1131 can both be 16.

[0277] For such a circuit configuration, as an example of a first operating condition for a first exemplary scenario as described herein, for the first chip 1131 , the worst operating condition may be that the two-terminal switches K1 and Km are closed first.

[0278] According to some embodiments, FIG11 also shows a second chip 1132, which may be configured the same as the first chip 1131. It will be understood that although the two chips 1131 and 1132 are shown to be configured to be connected to the corresponding two batteries 1111 and 1112, respectively, the present application is not limited to this. For example, the test circuit may include only one chip and one battery module. Alternatively, the test circuit may include more chips and more battery modules. In such an example, for the second chip 1132, the example of the first operating condition for the first example scenario, that is, the worst operating condition, is that the switches Km+1 and K2m at both ends are closed first.

[0279] For example, the host computer 1140 (or other possible units, devices, etc.) can be configured to independently or simultaneously perform a closing operation on the first chip and the second chip to close the switches on both sides. Alternatively, the host computer 1140 can be configured to perform a closing operation on the first chip and the second chip separately to test two or more chips in sequence, and so on, and the present application is not limited thereto.

[0280] For the first chip 1131, after the two-terminal switches K1 and Km are first closed, the other pins may be closed in a random order and / or with a random delay. Similarly, for the second chip 1132, according to some embodiments, after the two-terminal switches Km+1 and K2m are first closed, the other pins may be closed in a random order and / or with a random delay.

[0281] As another example, as a second working condition for the first example scenario, in order to simulate the most realistic situation, switches K1-Km and switches Km+1-K2m may be randomly closed, including, for example, random time delays and random closing sequences.

[0282] According to one or more embodiments of the present application, the discharge unit 1150 may be configured according to some embodiments. For example, after each hot-swap simulated power-off, all discharge switches in the discharge unit 1150 may be closed to discharge the circuit to restore the initial state, thereby ensuring consistency of the initial state for each hot-swap.

[0283] The following describes an example test circuit configuration for the second example scenario in conjunction with Figure 12. As shown in Figure 12, test circuit 1200 may include at least one battery module 1210, a switch matrix 1220, at least one chip 1230, and a host computer 1240. More specifically, at least one battery module 1210 includes battery modules 1211 and 1212, and at least one chip includes an AFE chip 1231. The sum of the number of cells in battery modules 1211 and 1212 matches the number of sampling channels of AFE chip 1231. Battery modules 1211 and 1212 have independent sampling leads F1 and F2, respectively. All sampling channel lines of AFE chip 1231 are concentrated on J1. More specifically, battery module 1211 may have 8 cells (M1), battery module 1212 may have 8 cells (M2), M1 + M2 = 16, and AFE chip 1231 may have 16 sampling channels. According to some embodiments, a second AFE chip may be further included, and its configuration may be the same as that of the first AFE chip (not shown).

[0284] As a first simulated operating condition for the second example scenario, switches K1 to Km of the AFE chip 1231 may be closed first, followed by switches Km+1 to K2m after a certain delay. During the closing process of switches Km+1 to K2m, K2m may be closed first, followed by random closing of switches Km+1 to K2m-1.

[0285] As a second simulation condition for the second example scenario, switches Km+1 to K2m of the AFE chip 1231 may be closed first, and then switches K1 to Km are closed after a certain delay. During the closing process of switches K1 to Km, K1 may be closed first, and then switches K2 to Km may be closed randomly.

[0286] According to one or more embodiments of the present application, the discharge unit 1250 may be configured according to some embodiments. For example, after each hot-swap simulated power-off, all discharge switches in the discharge unit 1250 may be closed to discharge the circuit to restore the initial state, thereby ensuring consistency of the initial state for each hot-swap.

[0287] The following describes an example test circuit configuration for the third example scenario in conjunction with Figure 13. As shown in Figure 13, test circuit 1300 may include at least one battery module 1310, a switch matrix 1320, at least one chip 1330, and a host computer 1340. More specifically, at least one battery module 1310 includes a battery module 1311, and the at least one chip includes an AFE chip 1331 and an AFE chip 1332. The number of cells in battery module 1311 is consistent with the sum of the number of sampling channels of AFE chip 1331 and AFE chip 1332.

[0288] Battery module 1311 can be connected to a single connector F1. Alternatively, battery module 1311 can be divided into two connectors F1 and F2 (not shown). All sampling channel lines of AFE chip 1331 and AFE chip 1332 are concentrated at J1. As a more specific example, the number of cells M1 in battery module 1311 is 32, and the number of sampling channels of AFE chip 1331 and AFE chip 1332 are both 16+16.

[0289] As a first simulation working condition for the third example scenario, switches Km and Km+1 may be closed first, K1 and K2m are closed after a delay, and the remaining switches are closed randomly.

[0290] As a second simulation working condition for the third example scenario, all switches K1 to K2m may be closed with a random delay.

[0291] According to one or more embodiments of the present application, the discharge unit 1350 can be configured in an exemplary manner. For example, after each hot plug simulates power-off, all discharge switches in the discharge unit 1350 can be closed to discharge the circuit to restore the initial state, ensuring consistency of the initial state of each hot plug.

[0292] An example of a test circuit configuration for a fourth example scenario is described below in conjunction with Figure 14. The fourth example scenario may be a scenario based on the third example scenario where a short node exists between two AFE chips.

[0293] As shown in Figure 14 , test circuit 1400 may include at least one battery module 1410, a switch matrix 1420, at least one chip 1430, and a host computer 1440. More specifically, at least one battery module 1410 includes a battery module 1411, and at least one chip includes an AFE chip 1431 and an AFE chip 1432. The number of cells in battery module 1411 is consistent with the sum of the number of sampling channels of AFE chips 1431 and 1432. AFE chips 1431 and 1432 can be short-circuited via a shorting wire 14301.

[0294] Battery module 1411 can be connected to a single connector F1. Alternatively, battery module 1411 can be divided into two connectors F1 and F2 (not shown). All sampling channel lines of AFE chip 1431 and AFE chip 1432 are concentrated at J1. As a more specific example, the number of cells M1 in battery module 1411 is 32, and the number of sampling channels of AFE chip 1431 and AFE chip 1432 are both 16+16.

[0295] It can be understood that in such an example, switches Km and Km+1 may correspond to the first sampling lead and the second sampling lead as described above, respectively, and switches K1 and K2m may correspond to the third sampling channel line and the fourth sampling channel line.

[0296] As a first simulation working condition for the fourth example scenario, switches Km+1 to K2m may be closed first, then switch K1 may be closed with a delay, and finally switches K2 to Km may be closed randomly.

[0297] As a second simulation working condition for the fourth example scenario, switches K1 to Km may be closed first, then switch K2m is closed with a delay, and finally switches Km+1 to K2m-1 are closed randomly.

[0298] According to one or more embodiments of the present application, a discharge unit 1450 may be configured. For example, after each hot-swap simulated power-off, all discharge switches in the discharge unit 1450 may be closed to discharge the circuit to restore the initial state, thereby ensuring consistency of the initial state for each hot-swap.

[0299] According to one or more embodiments of the present application, the following exemplary provisions may be made for the sample status:

[0300] ——Number of samples: 6, from 3 different batches;

[0301] ——Sample string number configuration: the chip sampling channel needs to be fully configured;

[0302] ——Number of hot plugs under each working condition: not less than 30 times;

[0303] ——Battery cell voltage: not less than 4.25V;

[0304] ——Sample status: No abnormalities after five-point functional verification;

[0305] As a specific non-limiting example, in an experiment, the following steps may be included:

[0306] a) Complete the construction of the simulation test bench according to the requirements of the hot-swap test bench for the test samples;

[0307] b) Power on the test sample, adjust the single cell voltage to the specified value, and check whether the function of the test sample meets the specified requirements;

[0308] c) Cut off the power supply to the test sample and discharge the residual charge of the sample;

[0309] d) Simulate the hot-swap scenario and corresponding working conditions, connect the corresponding battery cell channels in sequence, and after all channels are connected, check whether the sample functions normally;

[0310] e) Repeat steps c to d to complete the required number of hot-swap tests under this working condition;

[0311] f) Repeat steps c to e to complete the test requirements for the remaining hot-swap conditions;

[0312] g) For example, the process from b to f can be repeated to complete the test requirements of the hot-swap working conditions of the remaining samples.

[0313] It will be understood that the above-mentioned “scenarios” and “operating conditions” may correspond to various “example scenarios” and “simulated operating conditions” described in this application.

[0314] The following are exemplary test sample parameters:

[0315] - Sample size 6, or other sample size;

[0316] ——The number of sample configuration strings S can be selected according to the specific hot-swap test bench requirements, typical circuit configuration, battery modules, the number of cells in each battery module, CMU configuration requirements, etc.

[0317] ——Sample status: After testing, the functional status meets the required level requirements.

[0318] The single cell voltage value, for example, 4.25V, can be determined through negotiation between the manufacturer and the user. As an example, if there is a deviation in the single cell voltage value, the difference may be required to be explained in the test report.

[0319] ——Hot plug times: not less than 30 times.

[0320] It will be understood that throughout the text, unless otherwise specified or clearly indicated from the context, terms such as test sample, chip, device under test, test sample, test chip, etc. may be used interchangeably to indicate a chip that is to be tested, is undergoing testing, or has undergone hot-swap testing; and terms such as test, test, verification, functional check, etc. may be used interchangeably to indicate verification of the performance of a chip or test sample or checking of its function, and the present disclosure is not limited to this.

[0321] By way of example, the following examples of environmental conditions and supply voltages are given.

[0322] Exemplary environmental conditions may include:

[0323] ——Room temperature: 23℃±5℃;

[0324] ——Relative humidity: 20%RH~80%RH;

[0325] ——Atmospheric pressure: 86kPa~106kPa;

[0326] - Altitude: not exceeding 1000m. As an example, if the altitude exceeds 1000m, the result is corrected, and illustratively, the result is corrected according to the relevant provisions of GB / T 18488.1-2015.

[0327] Example supply voltage conditions may include:

[0328] ——Single cell voltage: 3.65V;

[0329] ——Total supply voltage: (3.65*L)V

[0330] Wherein, L is the number of cells in the battery module, which can be 8, 12, 16, 18, etc., and can be changed according to the specific hot-swap test bench requirements, typical circuit configuration, battery module, the number of cells in each battery module, CMU configuration requirements, etc.

[0331] The following are specific, non-limiting examples of some exemplary functional parameter testing methods.

[0332] Exemplarily, the power supply voltage range test may include verifying the power supply voltage range of the AFE chip according to the following test method.

[0333] a) Place the test sample in the incubator and adjust the incubator temperature to the specified value;

[0334] b) Power on the test sample, adjust the single cell voltage to the specified value, and check whether the function of the test sample meets the specified requirements;

[0335] c) After the temperature of the test sample reaches stability, maintain the specified operating time under this condition;

[0336] d) During operation, real-time monitoring shall be carried out to ensure that the working status of the test sample meets the specified requirements.

[0337] ——Number of samples: 6

[0338] ——Running time: 24h

[0339] ——The combination of ambient temperature and supply voltage can be shown in Table 1.

[0340] Table 1 Combinations of ambient temperature and supply voltage

[0341] Wherein, L is the number of battery cells, which can be 8, 12, 16, 18, etc., and can be changed according to the specific requirements of the hot-swap test bench, typical circuit configuration, battery module, the number of battery cells per battery module, CMU configuration requirements, etc. The number of battery cells L can be selected in conjunction with the number of samples and the sampling channels of each sample chip, or vice versa.

[0342] It is understood that the ambient temperature and supply voltage shown in Table 1 can be referred to as a five-point test. Furthermore, it is understood that the above temperature and voltage values ​​are merely examples and can be adjusted as needed. In other cases, more combinations of ambient temperature and supply voltage can be selected, for example, to perform more than five-point tests.

[0343] For example, a power supply current range test can be performed on the chip. The power supply current range of the AFE chip can be verified using the following test method.

[0344] a) Place the test sample in the incubator and adjust the incubator temperature to the specified value;

[0345] b) Power on the test sample, adjust the single cell voltage to the specified value, and check whether the function of the test sample meets the specified requirements;

[0346] c) When the temperature of the test sample reaches a stable state, set the test sample to enter the shutdown state;

[0347] d) Maintain the specified operating time under these conditions;

[0348] e) During operation, the working current of the test sample shall be monitored in real time and recorded;

[0349] f) Repeat steps a to e to complete the sleep state and running state current tests.

[0350] ——Number of samples: 6

[0351] ——Run time: 15 minutes

[0352] ——The combination of ambient temperature and supply voltage can be referred to Table 1, for example.

[0353] For example, the chip can be tested for cell voltage sampling accuracy. The AFE chip can be tested for cell voltage sampling accuracy using the following test method.

[0354] a) Place the test sample in the incubator and adjust the incubator temperature to the specified value;

[0355] b) Power on the test sample, adjust the single cell voltage to the specified value, and check whether the function of the test sample meets the specified requirements;

[0356] c) When the temperature of the test sample reaches a stable state, start reading the voltage value of the single cell collected from the test sample;

[0357] d) Compare the voltage value collected from the test sample with the value of the detection equipment and record them;

[0358] e) Repeat steps a to d to complete the voltage sampling accuracy test at all set temperatures.

[0359] ——Number of samples: 32

[0360] ——The number of sample configuration strings can be S. S can be the number selected according to actual scenarios and typical working conditions.

[0361] - Sample condition: Sample aged for 1000 hours at +125°C. The aging conditions may be those understood by those skilled in the art, such as those set forth in relevant standards.

[0362] ——Run time: 1 minute

[0363] ——For example, see Table 2 for combinations of ambient temperature and supply voltage.

[0364] Table 2 Combinations of ambient temperature and single cell voltage

[0365] For example, the chip can be tested for cell temperature sampling accuracy. The AFE chip can be tested for cell voltage sampling accuracy using the following test method.

[0366] a) Place the test sample in the incubator and adjust the incubator temperature to the specified value;

[0367] b) Power on the test sample, adjust the single cell voltage to the specified value, and check whether the function of the test sample meets the specified requirements;

[0368] c) When the temperature of the test sample reaches stability, start reading the temperature sampling line voltage value collected from the test sample;

[0369] d) Compare the voltage value collected from the test sample with the value of the detection equipment and record them;

[0370] e) Repeat steps a to d to complete the temperature sampling line voltage value accuracy test at all set temperatures.

[0371] ——Number of samples: 32;

[0372] ——The number of sample configuration strings can be S. S can be the number selected according to actual scenarios and typical working conditions.

[0373] - Sample condition: Sample aged for 1000 hours at +125°C. The aging conditions may be those understood by those skilled in the art, such as those set forth in relevant standards.

[0374] ——Running time: 1min;

[0375] ——For example, see Table 3 for combinations of ambient temperature and supply voltage.

[0376] Table 3 Combination of ambient temperature and temperature sampling line input voltage

[0377] For example, a leakage current diagnosis threshold test can be performed on the chip. The leakage current diagnosis threshold test can be performed on the AFE chip according to the following test method.

[0378] a) Complete the construction of the simulation test bench according to the leakage current diagnostic threshold test requirements for the test samples;

[0379] b) Power on the test sample, adjust the single cell voltage to the specified value, and check whether the function of the test sample meets the specified requirements;

[0380] c) Use a waveform generator to generate specific waveform interference and apply it to the corresponding diagnostic channel;

[0381] d) Observe and record the changes in the diagnostic channel thresholds through the host computer;

[0382] e) Repeat steps c to d to complete the test requirements for the remaining channels;

[0383] ——Number of samples: 6;

[0384] ——The number of sample configuration strings can be S. S can be the number selected according to actual scenarios and typical working conditions.

[0385] ——Sample status: After testing and verification within the power supply voltage range, the functional status meets the grade requirements;

[0386] ——Interference waveform parameters: frequency 1kHz~20kHz, amplitude ±300mV;

[0387] ——Interference duration: 5 minutes.

[0388] By way of example, a definition of the functional status level is given, wherein the classification of the device under test (DUT) is defined according to its functional status during and after being subjected to electromagnetic interference.

[0389] --State A: During and after the test, all functions and parameters of the DUT meet the design specifications.

[0390] State B: During the test, all DUT functions are normal, but one or more parameters exceed the specifications. After the test, all parameters automatically return to the specified requirements.

[0391] --State C: During the test, one or more functions of the DUT cannot be performed normally. After the test, all functions automatically return to the specified requirements.

[0392] --State D: During the test, one or more functions of the DUT cannot be performed normally, and cannot automatically recover to the specified requirements after the test. Simple operation or reactivation of the DUT is required.

[0393] --Status E: During the test, one or more functions of the DUT cannot be performed normally, and cannot automatically recover to the specified requirements after the test. The DUT needs to be repaired or replaced.

[0394] Illustratively, the functional state level A of the no-power / off state / sleep state test is determined by powering on after the test.

[0395] As an example, the terms "meeting the required grade requirements" and "meeting grade requirements" mentioned in the chip functional test section of this article may refer to the sample meeting the grade of status A, but it can be understood that the present disclosure is not limited to this.

[0396] According to this application, the following examples are also provided:

[0397] Example 1 is a testing method for a chip, including:

[0398] determining a configuration mode of a test circuit, the test circuit comprising at least one chip and at least one battery module, the at least one chip being connectable to the at least one battery module according to the configuration mode; and

[0399] Based on at least one operating condition corresponding to the configuration mode, the at least one chip is connected to the at least one battery module.

[0400] Example 2 is a method according to Example 1, further comprising testing the performance of the at least one chip.

[0401] Example 3 is a method according to Example 2, further comprising: before testing the performance of the at least one chip, determining whether an operation end condition is satisfied; and

[0402] In response to determining that the operation end condition is satisfied, the performance of the at least one chip is tested.

[0403] Example 4 is a method according to any one of Examples 1-3, wherein the test circuit further comprises a switch matrix, the switch matrix being interposed between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode, and

[0404] Wherein, connecting the at least one chip to the at least one battery module includes: performing a closing operation for closing at least two switches in the switch matrix.

[0405] Example 5 is a method according to Example 4, wherein performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy, wherein the first strategy is used to preferentially close two switches that form a power-on loop with a maximum potential difference; or a second strategy, wherein the second strategy is used to preferentially close switches that can form a path between the at least one battery module.

[0406] Example 6 is a method according to Example 4, wherein the at least one chip includes a first chip, the at least one battery module includes a first battery module, and determining the configuration mode of the test circuit includes determining that the test circuit is in a first configuration mode, the first configuration mode indicating that the first chip is configured to be connected to the corresponding switches of the switch matrix, so that when the corresponding switches are turned on, the sampling channel lines of the first chip can be respectively connected to the corresponding sampling leads of the first battery module.

[0407] Example 7 is the method of Example 6, wherein, in response to determining that the test circuit is in the first configuration mode, performing the closing operation includes:

[0408] When switches corresponding to the remaining sampling channel lines except the pair of sampling channel lines associated with the maximum battery potential difference in the first chip are not closed, a pair of switches corresponding to the pair of sampling channel lines is closed.

[0409] Example 8 is the method of Example 7, wherein, in response to determining that the test circuit is in the first configuration mode, performing the closing operation further comprises:

[0410] After the pair of switches corresponding to the pair of sampling channel lines are closed, the switches corresponding to the remaining sampling channel lines in the first chip are randomly closed.

[0411] Example 9 is a method according to any one of Examples 6-8, wherein, in response to determining that the test circuit is in the first configuration mode, performing the closing operation includes: causing switches corresponding to sampling channel lines of the first chip to be randomly closed.

[0412] Example 10 is a method according to Example 4, wherein the at least one chip includes a first chip, the at least one battery module includes at least two battery modules connected in series, and determining the configuration mode of the test circuit includes determining that the test circuit is in a second configuration mode, and the second configuration mode indicates that: the first chip is configured to be connected to the corresponding switches of the switch matrix, so that when the corresponding switches are turned on, the sampling channel lines of the first chip can be respectively connected to the corresponding sampling leads of the at least two battery modules.

[0413] Example 11 is the method of Example 10, wherein, in response to determining that the test circuit is in the second configuration mode, performing the closing operation includes:

[0414] When none of the switches corresponding to the sampling leads of the positive-side battery module of the at least two battery modules are closed, closing the switches corresponding to the sampling leads of the remaining battery modules of the at least two battery modules except the positive-side battery module; and

[0415] After the switches corresponding to the sampling leads of the remaining battery modules are closed for a first time delay, the switch corresponding to the sampling lead associated with the highest battery potential of the positive-side battery module is closed.

[0416] Example 12 is the method of Example 11, wherein performing the closing operation further comprises:

[0417] After the switch corresponding to the sampling lead associated with the highest battery potential is closed, the switches corresponding to the remaining sampling leads of the positive-side battery module except the sampling lead associated with the highest battery potential are randomly closed.

[0418] Example 13 is a method according to any of Examples 10-12, wherein, in response to determining that the test circuit is in the second configuration mode, performing the closing operation includes:

[0419] When none of the switches corresponding to the sampling leads of the negative-side battery module of the at least two battery modules are closed, closing the switches corresponding to the sampling leads of the remaining battery modules of the at least two battery modules except the negative-side battery module; and

[0420] After the switches corresponding to the sampling leads of the remaining battery modules are closed for a second time delay, the switch corresponding to the sampling lead associated with the lowest battery potential of the negative-side battery module is closed.

[0421] Example 14 is the method of Example 13, wherein performing the closing operation further comprises:

[0422] After the switch corresponding to the sampling lead associated with the lowest battery potential is closed, the switches corresponding to the remaining sampling leads of the negative-side battery module except the sampling lead associated with the lowest battery potential are randomly closed.

[0423] Example 15 is a method according to Example 4, wherein the at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and determining the configuration mode of the test circuit includes determining that the test circuit is in a third configuration mode, and the third configuration mode indicates that: the first chip and the second chip are configured to be connected to corresponding switches in the switch matrix, so that when the corresponding switches are turned on, the first chip and the second chip can be connected to the corresponding sampling leads of the first battery module.

[0424] Example 16 is the method according to Example 14, wherein the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first and second sampling leads of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to third and fourth sampling leads of the first battery module that are associated with a maximum battery potential difference, and in response to determining that the test circuit is in the third configuration mode, performing the closing operation includes:

[0425] When the switches corresponding to the remaining sampling channel lines of the first chip and the second chip except the first sampling channel line and the second sampling channel line are not closed, closing the switches corresponding to the first sampling channel line and the second sampling channel line; and

[0426] After the switches corresponding to the first sampling channel line and the second sampling channel line are closed for a third time delay, the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed.

[0427] Example 17 is the method of Example 16, wherein performing the closing operation further comprises:

[0428] After the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed, the switches corresponding to the remaining sampling channel lines of the first chip and the second chip except the first sampling channel line, the second sampling channel line, the third sampling channel line and the fourth sampling channel line are randomly closed.

[0429] Example 18 is a method according to any one of Examples 15-17, wherein, in response to determining that the test circuit is in a third configuration mode, performing the closing operation includes: causing switches corresponding to sampling channel lines of the first chip and the second chip to be randomly closed.

[0430] Example 19 is a method according to Example 15, wherein the first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to the adjacent first sampling lead and second sampling lead of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third sampling lead and fourth sampling lead of the first battery module associated with the maximum battery potential difference, and the third configuration mode also indicates that the first sampling channel line is electrically connected to the second sampling channel line.

[0431] Example 20 is the method of Example 19, wherein, in response to determining that the test circuit is in a third configuration mode, performing the closing operation includes:

[0432] When none of the switches corresponding to the sampling channel lines of the first chip are closed, closing the switches corresponding to the sampling channel lines of the second chip; and

[0433] After a third time delay has passed since the switch corresponding to the sampling channel line of the second chip was closed, the switch corresponding to the third sampling channel line is closed.

[0434] Example 21 is the method of Example 20, wherein performing the closing operation further comprises:

[0435] After the switch corresponding to the third sampling channel line is closed, the switches corresponding to the remaining sampling channel lines of the first chip except the third sampling channel line are randomly closed.

[0436] Example 22 is a test method according to any one of Examples 3-21, wherein the operation termination condition includes at least one of the following items: the number of executions of the closing operation for the at least one chip reaches a first threshold, or the number of executions of the closing operation based on a specific configuration mode reaches a second threshold for the specific configuration mode.

[0437] Example 23 is a test method according to any one of Examples 1-22, further comprising:

[0438] opening the at least two switches;

[0439] determining a current configuration mode between the first chip and the at least one battery module; and

[0440] The closing operation is performed again based on the current configuration mode.

[0441] Example 24 is a testing method according to Example 23, further comprising: performing a discharge operation before performing a closing operation again based on the current configuration mode.

[0442] Example 25 is a method according to any one of Examples 1-24, further comprising, in response to determining that the second operation end condition is not satisfied:

[0443] performing a power-off operation on the at least one chip;

[0444] discharging a capacitor in the at least one chip; and

[0445] Repeating the steps of closing at least two switches in the switch matrix and testing the function of the at least one chip,

[0446] The second operation termination condition includes at least one of the following: the number of executions of the closing operation for the at least one chip reaches a first threshold, or the number of executions for each of the at least one operating condition reaches a second threshold for the operating condition.

[0447] Example 26 is a method according to any one of Examples 1-25, further comprising: in response to determining that the step of connecting the at least one chip to the at least one battery module is performed for the first time, adjusting the single cell voltage of the battery in the at least one battery module to a specified value before testing the function of the at least one chip.

[0448] Example 27 is a method according to any one of Examples 1-26, wherein testing the performance of the at least one chip includes performing a supply voltage range test on the at least one chip.

[0449] Example 28 is a testing device for a chip, comprising:

[0450] switch matrix; and

[0451] a control device capable of controlling the operation of at least one switch in the switch matrix to power on at least one chip in a configuration mode, and

[0452] The control device is configured to connect the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

[0453] Example 29 is a testing device according to Example 28, further comprising at least one battery module, wherein powering on the at least one chip according to the configuration mode includes connecting the at least one chip to the at least one battery module.

[0454] Example 30 is a testing apparatus according to Example 29, wherein connecting the at least one chip to the at least one battery module includes: performing a closing operation for closing at least two switches in the switch matrix.

[0455] Example 31 is a testing device according to Example 30, wherein performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy, wherein the first strategy is used to preferentially close two switches that form a power-on loop with a maximum potential difference; or a second strategy, wherein the second strategy is used to preferentially close switches that can form a path between the at least one battery module.

[0456] Example 32 is a test device according to any of Examples 28-31, wherein the test device includes an interface for connecting to the at least one chip.

[0457] Example 33 is a testing apparatus according to any one of Examples 28-31, wherein the control device includes a host computer.

[0458] Example 34 is a testing device according to any one of Examples 28-31, further comprising at least one discharge unit, which is capable of discharging a corresponding capacitor in the at least one chip when turned on.

[0459] Example 35 is a host computer capable of controlling the operation of at least one switch in a switch matrix, wherein the switch matrix is ​​configured to connect at least one chip to at least one battery module, wherein the host computer is configured to perform a method according to any one of Examples 1-27.

[0460] Example 36 is a chip for a battery, the chip being tested according to the method of any one of Examples 1-27.

[0461] Example 37 is an electronic device comprising: at least one processor; and

[0462] a memory communicatively coupled to the at least one processor; wherein

[0463] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method of any one of Examples 1-27.

[0464] Example 38 is a non-transitory computer-readable storage medium storing computer instructions for causing the computer to perform the method according to any one of Examples 1-27.

[0465] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A chip testing method, comprising: determining a configuration mode of a test circuit, the test circuit comprising at least one chip and at least one battery module, the at least one chip being connectable to the at least one battery module according to the configuration mode; as well as Based on at least one operating condition corresponding to the configuration mode, the at least one chip is connected to the at least one battery module. 2 . The method according to claim 1 , further comprising testing the performance of the at least one chip.

3. The method according to claim 2, further comprising: Before testing the performance of the at least one chip, determining whether an operation end condition is satisfied; as well as In response to determining that the operation end condition is satisfied, the performance of the at least one chip is tested.

4. The method according to any one of claims 1 to 3, wherein: The test circuit further comprises a switch matrix, the switch matrix being interposed between the at least one chip and the at least one battery module, the switch matrix being capable of connecting the at least one chip to the at least one battery module according to the configuration mode, and Wherein, connecting the at least one chip to the at least one battery module comprises: performing a closing operation for closing at least two switches in the switch matrix.

5. The method according to claim 4, wherein: Performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy, wherein the first strategy is used to preferentially close two switches that form a power-on loop with a maximum potential difference; or a second strategy, wherein the second strategy is used to preferentially close switches that can form a path between the at least one battery module.

6. The method according to claim 4, wherein: The at least one chip includes a first chip, the at least one battery module includes a first battery module, and determining the configuration mode of the test circuit includes determining that the test circuit is in a first configuration mode, wherein the first configuration mode indicates that the first chip is configured to be connected to corresponding switches of the switch matrix, so that when the corresponding switches are turned on, the sampling channel lines of the first chip can be respectively connected to corresponding sampling leads of the first battery module.

7. The method according to claim 6, wherein: In response to determining that the test circuit is in the first configuration mode, performing the closing operation includes: When switches corresponding to the remaining sampling channel lines except a pair of sampling channel lines associated with the maximum battery potential difference in the first chip are not closed, a pair of switches corresponding to the pair of sampling channel lines is closed.

8. The method according to claim 7, wherein: In response to determining that the test circuit is in the first configuration mode, performing the closing operation further includes: After the pair of switches corresponding to the pair of sampling channel lines are closed, the switches corresponding to the remaining sampling channel lines in the first chip are randomly closed.

9. The method according to any one of claims 6 to 8, wherein: In response to determining that the test circuit is in the first configuration mode, performing the closing operation includes: causing switches corresponding to sampling channel lines of the first chip to be randomly closed.

10. The method according to claim 4, wherein: The at least one chip includes a first chip, the at least one battery module includes at least two battery modules connected in series, and determining the configuration mode of the test circuit includes determining that the test circuit is in a second configuration mode, and the second configuration mode indicates that: the first chip is configured to be connected to corresponding switches of the switch matrix, so that when the corresponding switches are turned on, the sampling channel lines of the first chip can be respectively connected to the corresponding sampling leads of the at least two battery modules.

11. The method according to claim 10, wherein: In response to determining that the test circuit is in the second configuration mode, performing the closing operation includes: When the switches corresponding to the sampling leads of the positive-side battery module of the at least two battery modules are not closed, closing the switches corresponding to the sampling leads of the remaining battery modules of the at least two battery modules except the positive-side battery module; and After the switches corresponding to the sampling leads of the remaining battery modules are closed for a first time delay, the switch corresponding to the sampling lead associated with the highest battery potential of the positive-side battery module is closed.

12. The method according to claim 11, wherein: Performing the closing operation further includes: After the switch corresponding to the sampling lead associated with the highest battery potential is closed, the switches corresponding to the remaining sampling leads of the positive-side battery module except the sampling lead associated with the highest battery potential are randomly closed.

13. The method according to any one of claims 10 to 12, wherein: In response to determining that the test circuit is in the second configuration mode, performing the closing operation includes: When the switches corresponding to the sampling leads of the negative-side battery module of the at least two battery modules are not closed, closing the switches corresponding to the sampling leads of the remaining battery modules of the at least two battery modules except the negative-side battery module; and After the switches corresponding to the sampling leads of the remaining battery modules are closed for a second time delay, the switch corresponding to the sampling lead associated with the lowest battery potential of the negative-side battery module is closed.

14. The method according to claim 13, wherein: Performing the closing operation further includes: After the switch corresponding to the sampling lead associated with the lowest battery potential is closed, the switches corresponding to the remaining sampling leads of the negative-side battery module except the sampling lead associated with the lowest battery potential are randomly closed.

15. The method according to claim 4, wherein: The at least one chip includes a first chip and a second chip, the at least one battery module includes a first battery module, and determining the configuration mode of the test circuit includes determining that the test circuit is in a third configuration mode, and the third configuration mode indicates that the first chip and the second chip are configured to be connected to corresponding switches in the switch matrix, so that when the corresponding switches are turned on, the first chip and the second chip can be connected to corresponding sampling leads of the first battery module.

16. The method according to claim 14, wherein: The first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to adjacent first sampling leads and second sampling leads of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to third sampling leads and fourth sampling leads of the first battery module associated with the maximum battery potential difference, and in response to determining that the test circuit is in the third configuration mode, performing the closing operation includes: When switches corresponding to the remaining sampling channel lines of the first chip and the second chip except the first sampling channel line and the second sampling channel line are not closed, closing the switches corresponding to the first sampling channel line and the second sampling channel line; and After the switches corresponding to the first sampling channel line and the second sampling channel line are closed for a third time delay, the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed.

17. The method according to claim 16, wherein: Performing the closing operation further includes: After the switch corresponding to the third sampling channel line and the switch corresponding to the fourth sampling channel line are closed, the switches corresponding to the remaining sampling channel lines of the first chip and the second chip except the first sampling channel line, the second sampling channel line, the third sampling channel line and the fourth sampling channel line are randomly closed.

18. The method according to any one of claims 15 to 17, wherein: In response to determining that the test circuit is in the third configuration mode, performing the closing operation includes: causing switches corresponding to sampling channel lines of the first chip and the second chip to be randomly closed.

19. The method according to claim 15, wherein: The first sampling channel line of the first chip and the second sampling channel line of the second chip can be connected to the adjacent first sampling lead and second sampling lead of the first battery module, the third sampling channel line of the first chip and the fourth sampling channel line of the second chip can be connected to the third sampling lead and fourth sampling lead of the first battery module associated with the maximum battery potential difference, and the third configuration mode also indicates that the first sampling channel line is electrically connected to the second sampling channel line.

20. The method according to claim 19, wherein: In response to determining that the test circuit is in a third configuration mode, performing the closing operation includes: When the switches corresponding to the sampling channel lines of the first chip are not closed, closing the switches corresponding to the sampling channel lines of the second chip; and After the switch corresponding to the sampling channel line of the second chip is closed for a third time delay, the switch corresponding to the third sampling channel line is closed.

21. The method according to claim 20, wherein: Performing the closing operation further includes: After the switch corresponding to the third sampling channel line is closed, the switches corresponding to the remaining sampling channel lines of the first chip except the third sampling channel line are randomly closed.

22. According to the testing method described in any one of claims 3-21, the operation end condition includes at least one of the following items: the number of executions of the closing operation for the at least one chip reaches a first threshold, or the number of executions of the closing operation based on a specific configuration mode reaches a second threshold for the specific configuration mode.

23. The testing method according to any one of claims 1 to 22, further comprising: Disconnecting the at least two switches; determining a current configuration mode between the first chip and the at least one battery module; as well as The closing operation is performed again based on the current configuration mode.

24. The testing method according to claim 23, further comprising: Before performing the closing operation again based on the current configuration mode, a discharging operation is performed.

25. The method according to any one of claims 1 to 24, further comprising, in response to determining that the second operation end condition is not satisfied: Performing a power-off operation on the at least one chip; discharging a capacitor in the at least one chip; as well as Repeating the steps of closing at least two switches in the switch matrix and testing the function of the at least one chip, The second operation termination condition includes at least one of the following items: the number of executions of the closing operation for the at least one chip reaches a first threshold, or the number of executions of each operating condition in the at least one operating condition reaches a second threshold for the operating condition.

26. The method according to any one of claims 1 to 25, further comprising: In response to determining that the step of connecting the at least one chip to the at least one battery module is performed for the first time, before testing the function of the at least one chip, a single cell voltage of a battery in the at least one battery module is adjusted to a specified value.

27. The method according to any one of claims 1 to 26, wherein: Testing the performance of the at least one chip includes performing a supply voltage range test on the at least one chip.

28. A testing device for a chip, comprising: Switch matrix; as well as a control device capable of controlling the operation of at least one switch in the switch matrix to power on at least one chip in a configuration mode, and The control device is configured to connect the at least one chip to the at least one battery module based on at least one operating condition corresponding to the configuration mode.

29. The testing device according to claim 28, further comprising at least one battery module, wherein: The powering-on operation of the at least one chip according to the configuration mode includes connecting the at least one chip to the at least one battery module.

30. The testing device according to claim 29, wherein: Connecting the at least one chip to the at least one battery module includes performing a closing operation for closing at least two switches in the switch matrix.

31. The testing device according to claim 30, wherein: Performing a closing operation for closing at least two switches in the switch matrix includes closing the switches in the switch matrix based on at least one of the following strategies: a first strategy, wherein the first strategy is used to preferentially close two switches that form a power-on loop with a maximum potential difference; or a second strategy, wherein the second strategy is used to preferentially close switches that can form a path between the at least one battery module.

32. The testing device according to any one of claims 28 to 31, wherein: The testing device comprises an interface for connecting to the at least one chip.

33. The testing device according to any one of claims 28 to 31, wherein: The control device includes a host computer.

34. The testing device according to any one of claims 28 to 31, further comprising at least one discharge unit, wherein the at least one discharge unit is capable of discharging a corresponding capacitor in the at least one chip when being turned on.

35. A host computer capable of controlling the operation of at least one switch in a switch matrix, wherein the switch matrix is ​​configured to connect at least one chip to at least one battery module, wherein: The host computer is configured to execute the method according to any one of claims 1-27.

36. A chip for a battery, the chip being tested by the method according to any one of claims 1-27.

37. An electronic device comprising: at least one processor; as well as a memory communicatively coupled to the at least one processor; in The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 27.

38. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1-27.

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