Floating point execution circuit for subset of binary logarithmic input ranges

Abstract

Techniques relating to polynomial approximation of logarithms based on 2 are disclosed. In some embodiments, the floating point circuit is configured to perform an approximation of a logarithmic operation based on 2 and provide a fixed minimum precision unit (ULP) error over an input range. In some embodiments, the floating point circuit includes a set of parallel pipelines for polynomial approximation, where an output is selected from a particular pipeline based on a determination of whether the input operand is in a first subset of input ranges. Compared to conventional techniques, the disclosed techniques may advantageously provide a fixed ULP error for the entire input operand range of the floating point logarithmic function with 2 as a base, with minimal area and energy footprint.

Description

Background Art Technical Field

[0001] The present disclosure relates generally to floating point execution circuits, and more particularly to execution circuits configured to approximate binary logarithm operations.

[0002] Related technical description

[0003] In general, the nature of certain functions and the format of floating point numbers can result in significant accuracy loss during polynomial approximation, for example, when the result of a nonlinear function is very close to 1.0. Uniform least precision unit (ULP) error over the entire input range of a function may be desirable in various contexts, but may be challenging to achieve in the context of typical area and power constraints. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a block diagram illustrating an overview of an example floating point circuit according to some embodiments.

[0005] Figure 2 is a block diagram illustrating a detailed example floating-point circuit with parallel pipelines for different ranges of input operands according to some embodiments.

[0006] Figure 3A is a diagram illustrating an example first subset of input ranges according to some embodiments.

[0007] Figure 3B is a diagram illustrating an example second subset of input ranges according to some embodiments.

[0008] Figure 4 is a diagram illustrating an example base-2 logarithmic function according to some embodiments.

[0009] Figure 5 is a flow chart illustrating an example method for performing a floating-point approximation of a base-2 logarithm according to some embodiments.

[0010] Figure 6 is a block diagram illustrating an example computing device according to some embodiments.

[0011] Figure 7 is a diagram illustrating an example application of the disclosed systems and devices according to some embodiments.

[0012] Figure 8 is a block diagram illustrating an example computer-readable medium storing circuit design information according to some embodiments. DETAILED DESCRIPTION

[0013] For certain nonlinear functions, when performing polynomial approximations, significant accuracy may be lost when the function crosses (or is very close to) 1.0. The base-2 logarithm (also known as the binary logarithm) is a function that exhibits this behavior for floating-point numbers represented in binary format. For example, for a range of input values ​​close to 1.0, the base-2 logarithm may exhibit large ULP errors relative to inputs outside of this range. In this context, adding circuitry (e.g., to perform a higher-order polynomial approximation or some other more complex approximation) can mitigate these problems, but may be infeasible and cost-prohibitive in real-world applications.

[0014] In some embodiments discussed in detail below, the floating point circuitry may include a set of parallel pipelines that operate on input operands to generate a polynomial approximation of a base 2 logarithm, select outputs from the set of parallel pipelines based on a range in which the input operands fall, and reassemble the outputs into a floating point approximation of the base 2 logarithm result. Note that one of the pipelines may be clock gated or power gated to reduce power consumption when the input is in a range handled by another pipeline.

[0015] The disclosed techniques can advantageously improve the accuracy of polynomial approximations of base-2 logarithms of a set of inputs that may exhibit low accuracy under conventional techniques. The disclosed techniques can also provide fixed ULP errors for the entire input operand range of floating-point base-2 logarithm functions without significant area and energy footprints.

[0016] Overview of Floating Point Circuits

[0017] Figure 1 is a block diagram illustrating an overview of an example floating point circuit according to some embodiments. In the illustrated embodiment, floating point circuit 100 includes floating point decomposition circuit 110, first pipeline circuit 120, second pipeline circuit 130, selection circuit 140, and floating point reassembly circuit 150.

[0018] In the illustrated embodiment, the floating point decomposition circuit 110 is configured to decompose the floating point input operand into its basic fixed point components, such as a sign, an exponent, and a mantissa. In some embodiments, in addition to separating the components from each other, the decomposition may include converting one of the components (e.g., a mantissa, an exponent, etc.) into another format (e.g., a two's complement format).

[0019] In some embodiments, the input operands can be classified as falling into a first subset of the input range or falling into a second subset of the input range. In some embodiments, the first subset includes the value 1.0. In some embodiments, the second subset of the input range includes both a value greater than one or more values ​​in the first subset and a value less than one or more values ​​in the first subset. In some embodiments, the first subset and the second subset of the input range do not overlap.

[0020] In the illustrated embodiment, the first pipeline circuit 120 is configured to perform a base-2 logarithm approximation on the input operand and output the result to the selection circuit 140. In some embodiments, the base-2 logarithm approximation may include performing natural logarithm operations, multiplication operations, and second-order or higher-order polynomial operations, as described below with reference to Figure 2 Discuss in detail.

[0021] In the illustrated embodiment, the second pipeline circuit 130 is configured to perform an approximation of a logarithm with a base of 2 on the input operand and output the result to the selection circuit 140. In various embodiments, the second pipeline circuit can use a different algorithm than the first pipeline circuit 120. For example, in some embodiments where the first pipeline circuit 120 implements natural logarithms and second-order polynomials, the second pipeline circuit 130 can implement third-order polynomial approximation. For example, the second pipeline circuit 130 can be configured to perform polynomial approximation using coefficients determined based on running multiple fit functions on binary logarithms. These coefficients can be stored in hardware during the processor design stage (e.g., using a lookup table) and accessed during operation of the processor based on the value of the input operand.

[0022] In the illustrated embodiment, selection circuit 140 is configured to select between the outputs of first pipeline circuit 120 and second pipeline circuit 130 based on determining whether the input operand falls within a first subset of the input range. In some embodiments, selection circuit 140 is configured to select the output of first pipeline circuit 120 based on determining that the input operand falls within the first subset of the input range that is close to 1.0.

[0023] In the illustrated embodiment, floating point reassembly circuit 150 is configured to generate a floating point approximation of a base 2 logarithm based on a fixed point input. In some embodiments, such as embodiments where pipelines 120 and 130 operate on the mantissa of an input operand, floating point reassembly circuit 150 receives as input an output of one of first pipeline circuit 120 or second pipeline circuit 130 from selection circuit 140.

[0024] Example Detailed Floating Point Circuit

[0025] Figure 2 is a block diagram illustrating detailed floating point circuitry according to some embodiments. In the illustrated example, the first pipeline 120 for a subset of inputs close to 1.0 includes 2 , a shift circuit 210, an input logic circuit 215, a sign circuit 220, an adder 222, a multiplier 224, and a sign circuit 228. In this example, the second pipeline 130 includes stages 230A-230N and the selection circuit 140 is implemented by a MUX 226. The sign circuits 220 and 228 are configured to properly correct the sign if necessary, as discussed in detail below.

[0026] In the illustrated example, the first pipeline is configured to implement the equation: This equation can advantageously provide a good approximation for functions close to 1.0 with limited circuit area and power consumption.

[0027] In this example, AisLT1.0 and AisGE1.0 refer to binary values ​​indicating whether the input operand A is less than 1.0 or greater than or equal to 1.0, respectively. For example, for an input operand A greater than or equal to 1.0, the first pipeline is configured to implement the equation where A=1+x and the result is always positive. Similarly, for an input operand A less than 1.0, the first pipeline is configured to implement the equation where A=1-x and the result is always negative. In some embodiments, the input operand A represents the mantissa.

[0028] In the illustrated embodiment, input logic circuit 215 receives input operand A as input and calculates a value x based on whether input operand A is less than 1.0 or greater than or equal to 1.0. In some embodiments, when input operand A is greater than or equal to 1.0, input logic circuit 215 calculates and outputs x=A-1. In some embodiments, when input operand A is less than 1.0, input logic circuit 215 calculates and outputs x=1-A. In some embodiments, input logic circuit 215 includes a comparator circuit configured to compare A to a value of 1.0.

[0029] In the example illustrated, The operands are generated by shift circuit 210 and the sign value is generated by sign circuit 220. In the illustrated example, The operands are Circuit 205 generates. In some embodiments, Circuit 205 includes a squaring unit to calculate x 2 In some embodiments, the division by three operation is performed by a multiplication circuit that multiplies x 2Multiply by the reciprocal of three (e.g., multiply by 1 / 3). In some embodiments, the reciprocal value is stored as a constant, such as in a register. Polynomial expansion Generated by adder 222. Operand is the input to multiplier 224. In some embodiments, The operand is calculated using a multiplier unit, where the reciprocal of ln2 is one multiplier input and x is another multiplier input. In some embodiments, the reciprocal of ln2 is stored in a register. In the illustrated example, the output of adder 222 is multiplied by the operand using multiplier 224. The output of the above equation is generated; where the sign value is determined by the sign circuit 228.

[0030] In the illustrated embodiment, Circuit 205 is configured to calculate the square of input x and divide it by three. Circuit 205 receives as input an input x.

[0031] In the illustrated embodiment, the shift circuit 210 is configured to perform a shift operation on the input x to generate The result of the shift operation performed by the shift circuit 210 is propagated to the sign circuit 220.

[0032] In the illustrated embodiment, the sign circuit 220 is configured to perform a sign operation on the input and generate an output. In some embodiments, when the input operand A is less than 1.0 (e.g., as determined by the input logic circuit 215), the sign circuit 220 can negate the input received from the shift circuit 210, which is equivalent to a multiplication operation by a factor of negative 1. In some embodiments, the sign circuit 220 includes an inverter circuit to perform a negation operation (e.g., by inverting the bits of the input and adding one for a two's complement representation). In some embodiments, when the input operand A is greater than or equal to 1.0, the sign circuit 220 can propagate the input received from the shift circuit 210 to the adder circuit 222 without performing any operation on the input.

[0033] In the illustrated embodiment, the adder circuit 222 is configured to receive the The outputs of circuit 205 and sign circuit 220 perform an addition operation. In some embodiments, the result of the addition operation is propagated to multiplier circuit 224.

[0034] In the illustrated embodiment, the multiplier circuit 224 is configured to add the output and input of the adder. The multiplication operation is performed, the result of which is propagated to sign circuit 228. In some embodiments, sign circuit 228 is configured to conditionally invert the sign of its input, as discussed above with reference to sign circuit 220.

[0035] In some embodiments, Circuit 205 , shift circuit 210 , sign circuit 220 , sign circuit 228 , adder circuit 222 , and multiplier circuit 224 are elements included in the first pipeline circuit 120 .

[0036] In the illustrated embodiment, the polynomial approximation pipeline circuits 230A- 230N are configured to perform a polynomial approximation of a base-2 logarithm based on the input operand A. In some embodiments, the polynomial approximation pipeline circuits 230A- 230N are included in the second pipeline circuit 130 .

[0037] In some embodiments, the polynomial approximation pipeline circuits 230A-230N perform a polynomial approximation of a base-2 logarithm in a cascade of multiplication and addition operations utilizing a polynomial coefficient table. For example, the polynomial approximation may be a second-order polynomial of the form: log2A≈((A*C0+C1)*A+C2). As another example, the polynomial approximation may be a third-order polynomial of the form: log2A≈((A*C0+C1)*A+C2)*A+C3. In these examples, coefficients C0-C3 are retrieved from the polynomial coefficient table and used in multiple addition / multiplication operations to generate a base-2 logarithm approximation. In other embodiments, a second-order or higher-order polynomial approximation may be performed.

[0038] In the illustrated embodiment, multiplexer circuit 226 provides an output selected from two inputs received from sign circuit 228 and polynomial approximation pipeline circuit 230N based on whether input operand A falls within a first subset of the input range.

[0039] In some embodiments, in response to input operand A being in the first subset of the input range, the multiplexer circuit may select the result of the polynomial approximation propagated by sign circuit 228. In some embodiments, in response to input operand A not being in the first subset of the input range, the multiplexer circuit may select the result of the polynomial approximation generated by polynomial approximation pipeline circuit 230N.

[0040] In the illustrated embodiment, floating point recombination circuitry 150 is configured to perform floating point recombination based on fixed point values ​​received from the multiplexer circuitry to generate a floating point result.

[0041] In the illustrated embodiment, the gating circuit 240 is configured to power down one or more elements based on whether the input operand A falls within the first subset of the input range. For example, the gating circuit 240 can power down the polynomial approximation pipeline circuits 230A-230N in response to the input operand A being within the first subset of the input range. This can advantageously provide a fixed ULP error for the entire input operand range without a significant energy footprint.

[0042] Example Input Range

[0043] Figure 3A is a diagram illustrating an example first subset of input ranges according to some embodiments. In the illustrated embodiment, the first subset of input ranges includes a value range that includes the value 1.0.

[0044] Figure 3B is a diagram illustrating an example second subset of input ranges according to some embodiments. In the illustrated embodiment, the second subset of input ranges includes values ​​greater than one or more values ​​in the first subset and less than one or more values ​​in the first subset.

[0045] In some embodiments, the first subset and the second subset of the input range do not overlap.

[0046] Example Logarithm to base 2

[0047] Figure 4 is a diagram illustrating an example base-2 logarithm function according to some embodiments. In the illustrated embodiment, the base-2 logarithm (also called the "binary logarithm") is a nonlinear function that finds the power to which 2 must be raised to obtain the value n, e.g., x=log2n.

[0048] In some embodiments, for inputs very close to or equal to 1.0, the base 2 logarithm exhibits an almost linear relationship. This region may be referred to as a near-linear region. The disclosed technique of using the first pipeline circuit 120 for inputs in this region and the second pipeline circuit 130 for other regions may achieve the various advantages discussed in detail above.

[0049] Example Method

[0050] Figure 5 is a flow chart illustrating an example method for performing a floating-point approximation of a base-2 logarithm according to some embodiments. Figure 5The method shown can be used in conjunction with any of the computer circuits, systems, devices, elements or components disclosed herein. In various embodiments, some of the method elements shown can be performed concurrently in a different order than shown, or can be omitted. Additional method elements can also be performed as needed.

[0051] At 510, in the illustrated embodiment, a first floating point pipeline circuit performs a first approximation of a base 2 logarithm in response to a first input operand falling within a first subset of an input range.

[0052] In some embodiments, the first approximation of the base 2 logarithm may include performing natural logarithm operations, multiplication operations, and second-order or higher-order polynomial operations.

[0053] In some embodiments, the second-order or higher-order polynomial operation is part of a Taylor series expansion. In some embodiments, the shift circuit implements one or more division operations for the polynomial operation. In some embodiments, the first subset of the input range includes a value range that includes the value 1.0. In some embodiments, the first floating-point pipeline circuit performs fixed-point operations on the mantissa of the input operand.

[0054] In some embodiments, the fixed-point to floating-point circuit performs reorganization of output data from the first floating-point pipeline circuit to generate a floating-point result.

[0055] At 520, in the illustrated embodiment, the second floating point pipeline circuit performs a first approximation of a base 2 logarithm in response to the second input operand falling within the second subset of the input range.

[0056] In some embodiments, the second approximation of the base 2 logarithm may include performing a polynomial approximation using coefficients determined based on running a multiple fit function on the binary logarithm.

[0057] In some embodiments, the second subset of the input range includes values ​​that are greater than one or more values ​​in the first subset and less than one or more values ​​in the first subset.

[0058] In some embodiments, the first subset and the second subset of the input range do not overlap.

[0059] Example Device

[0060] Reference now Figure 6, which shows a block diagram of an example embodiment of an illustrative device 600. In some embodiments, elements of the device 600 may be included in a system on a chip. In some embodiments, the device 600 may be included in a mobile device that may be battery powered. Therefore, the power consumption of the device 600 may be an important design consideration. In the illustrated embodiment, the device 600 includes a structure 610, a computing complex 620, an input / output (I / O) bridge 650, a cache / memory controller 645, a graphics unit 675, and a display unit 665. In some embodiments, in addition to or in place of the illustrated components, the device 600 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0061] The structure 610 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various elements of the device 600. In some embodiments, portions of the structure 610 may be configured to implement a variety of different communication protocols. In other embodiments, the structure 610 may implement a single communication protocol, and elements coupled to the structure 610 may internally convert from the single communication protocol to other communication protocols.

[0062] In the illustrated embodiment, computing complex 620 includes bus interface unit (BIU) 625, cache 630, and cores 635 and 640. In various embodiments, computing complex 620 may include various numbers of processors, processor cores, and caches. For example, computing complex 620 may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, cache 630 is a set of associative L2 caches. In some embodiments, cores 635 and 640 may include internal instruction and data caches. In some embodiments, a consistency unit (not shown) in structure 610, cache 630, or elsewhere in device 600 may be configured to maintain consistency between the various caches of device 600. BIU 625 may be configured to manage communications between computing complex 620 and other elements of device 600. Processor cores such as cores 635 and 640 may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions.

[0063] The cache / memory controller 645 may be configured to manage data transfers between the structure 610 and one or more caches and memories. For example, the cache / memory controller 645 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 645 may be coupled directly to the memory. In some embodiments, the cache / memory controller 645 may include one or more internal caches.

[0064] As used herein, the term "coupled to" may indicate one or more connections between elements, and a coupling may include intermediate elements. Figure 6 , graphics unit 675 may be described as being "coupled to" memory via structure 610 and cache / memory controller 645. In contrast, in Figure 6 In the illustrated embodiment, graphics unit 675 is "directly coupled" to structure 610 because there are no intervening elements.

[0065] Graphics unit 675 may include one or more processors, such as one or more graphics processing units (GPUs). For example, graphics unit 675 may receive graphics-oriented instructions, such as Metal or Instructions. Graphics unit 675 can execute dedicated GPU instructions or perform other operations based on the received graphics-oriented instructions. Graphics unit 675 can generally be configured to process large blocks of data in parallel and can build images in a frame buffer for output to a display, which can be included in the device or can be a separate device. Graphics unit 675 may include transformation, lighting, triangle and rendering engines in one or more graphics processing pipelines. Graphics unit 675 can output pixel information for displaying images. In various embodiments, graphics unit 675 may include programmable shader circuits, which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks and computational tasks (which may be graphics-related or may not be graphics-related).

[0066] The display unit 665 can be configured to read data from the frame buffer and provide a stream of pixel values ​​for display. In some embodiments, the display unit 665 can be configured as a display pipeline. In addition, the display unit 665 can be configured to blend multiple frames to produce an output frame. In addition, the display unit 665 can include one or more interfaces (e.g., a touch screen or an external display) for coupling to a user display (e.g., or embedded DisplayPort (eDP).

[0067] The I / O bridge 650 may include various elements configured to implement, for example, universal serial bus (USB) communications, security, audio, and low-power always-on functionality. The I / O bridge 650 may also include, for example, interfaces such as pulse width modulation (PWM), general purpose input / output (GPIO), serial peripheral interface (SPI), and inter-integrated circuit (I2C). Various types of peripherals and devices may be coupled to the device 600 via the I / O bridge 650.

[0068] In some embodiments, the device 600 includes a network interface circuit (not explicitly shown), which can be connected to the structure 610 or the I / O bridge 650. The network interface circuit can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuit can be configured to communicate via a wired local area network, a wireless local area network (e.g., via WiFi) or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuit is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuit is configured to communicate using device-to-device communication (e.g., Bluetooth or WiFi Direct) and the like. In various embodiments, the network interface circuit can provide the device 600 with connections to various types of other devices and networks.

[0069] Sample Application

[0070] Now go to Figure 7 , various types of systems that may include any of the circuits, devices, or systems described above are shown. Systems or devices 700 that may incorporate or otherwise utilize one or more of the techniques described herein may be used in a wide variety of fields. For example, system or device 700 may be used as part of the hardware of a system such as a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a television 750 (or a set-top box coupled to a television).

[0071] Similarly, the disclosed elements can be used in a wearable device 760, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. The wearable device can also be designed to perform only health monitoring functions, such as monitoring the user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices that can be implanted in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0072] The system or device 700 may also be used in various other contexts. For example, the system or device 700 may be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 770. Further, the system or device 700 may be implemented in a wide range of dedicated everyday devices, including devices 780 commonly found in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is generally referred to as the "Internet of Things" (IoT). Elements may also be implemented in various modes of transportation. For example, the system or device 700 may be used for control systems, guidance systems, entertainment systems, etc., of various types of vehicles 790.

[0073] Figure 7 The applications illustrated in the examples are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable game devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0074] Example Computer Readable Medium

[0075] The disclosure has described various example circuits in detail above. It is intended that the disclosure encompass not only embodiments including such circuits, but also computer-readable storage media including design information specifying such circuits. Thus, the disclosure is intended to support claims that encompass not only devices including the disclosed circuits, but also storage media that specify the circuits in a format recognized by a manufacturing system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed circuits. Claims to such storage media are intended to cover, for example, entities that generate a circuit design but do not manufacture the design itself.

[0076] Figure 8 810 is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, semiconductor manufacturing system 820 is configured to process design information 815 stored on non-transitory computer-readable medium 810 and manufacture integrated circuit 830 based on design information 815.

[0077] The non-transitory computer-readable storage medium 810 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 810 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar types of memory elements, etc. The non-transitory computer-readable storage medium 810 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 810 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0078] The design information 815 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. The design information 815 may be used by the semiconductor manufacturing system 820 to manufacture at least a portion of the integrated circuit 830. The format of the design information 815 may be identified by at least one semiconductor manufacturing system 820. In some embodiments, the design information 815 may also include one or more cell libraries that specify the synthesis, layout, or both of the integrated circuit 830. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies the cell library elements and their connectivity. The design information 815 obtained separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, the design information 815 may specify the circuit elements to be manufactured, but not their physical layout. In this case, the design information 815 may need to be combined with the layout information to actually manufacture the specified circuit.

[0079] In various embodiments, the integrated circuit 830 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, the design information 815 may include information related to the included macrocells. Such information may include, but is not limited to, a schematic capture database, mask design data, behavioral models, and device or transistor level netlists. As used herein, the mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0080] Semiconductor manufacturing system 820 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 820 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0081] In various embodiments, integrated circuit 830 is configured to operate according to the circuit design specified by design information 815, which may include performing any of the functionality described herein. For example, integrated circuit 830 may include Figure 1 and Figure 6 Any of the various elements shown in . In addition, the integrated circuit 830 can be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein can be performed by multiple connected integrated circuits.

[0082] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0083] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. are not necessarily to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0084] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0085] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The embodiments disclosed by the present invention are intended to be illustrative and non-restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0086] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0087] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0088] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0089] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0090] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a group of two or more items.

[0091] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0092] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0093] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0094] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0095] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0096] The phrase "based on" or is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0097] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0098] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0099] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0100] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform the particular function.

[0101] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0102] Different "circuits" may be described in the present disclosure. These circuits or "circuits" constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits.

[0103] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of the circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0104] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0105] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of identical structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0106] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. A device, comprising: A floating point circuit configured to perform an approximation of a base 2 logarithm operation and provide a fixed least unit precision (ULP) error over an input range, wherein the floating point circuit comprises: a first pipeline circuit configured to perform said approximation of said base-2 logarithm for input operands in a first subset of said input range; and a second pipeline circuit configured to perform said approximation of said base 2 logarithm for input operands in a second subset of said input range; and A selection circuit is configured to select a result of a first pipeline or a second pipeline based on whether a given input operand is in the first subset of the input range.

2. The device according to claim 1, wherein: To perform the approximation of the base-2 logarithm, the first pipeline circuit is configured to perform a natural logarithm operation.

3. The device according to claim 2, wherein: To perform the approximation of the base-2 logarithm, the first pipeline circuit is further configured to perform second-order or higher-order polynomial operations.

4. The apparatus of claim 3, wherein the polynomial operation is part of a Taylor series expansion.

5. The device according to claim 3, further comprising: A shift circuit is configured to implement one or more division operations for the polynomial operation. The apparatus of claim 1 , wherein the first subset of the input range comprises a range of values, the range of values ​​comprising a value of 1.

0.

7. The apparatus of claim 1, wherein the first subset and the second subset of the input range do not overlap, and the second subset of the input range includes values ​​greater than one or more values ​​in the first subset and less than one or more values ​​in the first subset.

8. The apparatus of claim 1, wherein the first pipeline circuit is configured to perform fixed-point operations on a mantissa of an input operand.

9. The device according to claim 8, further comprising: Fixed-point to floating-point circuitry is configured to reassemble output data from the first pipeline to generate a floating-point result.

10. The apparatus of claim 1, wherein the apparatus is a computing device, the computing device further comprising: monitor; Central processing unit; and Network interface circuit.

11. A method comprising: performing, by the first floating point pipeline circuit, a first approximation of a base 2 logarithm in response to the first input operand falling within the first subset of the input range; as well as A second approximation of the base 2 logarithm is performed by a second floating point pipeline circuit in response to a second input operand falling within a second subset of the input range.

12. The method according to claim 11, further comprising: A natural logarithm operation is performed by a first pipeline circuit for the first approximation of the base 2 logarithm.

13. The method according to claim 12, further comprising: A second-order or higher-order polynomial operation is performed by a first pipeline circuit for the first approximation of the base-2 logarithm.

14. The method according to claim 13, further comprising: A portion of a Taylor series expansion for the polynomial operation is performed by a first pipeline circuit.

15. The method of claim 11, wherein the first subset of the range of the input range includes a value range that includes the value 1.

0.

16. The method of claim 11, wherein the second subset of the input range includes values ​​greater than one or more values ​​in the first subset and less than one or more values ​​in the first subset, and the first and second subsets of the input range do not overlap.

17. A non-transitory computer-readable storage medium storing thereon design information, the design information specifying a design of at least a portion of a hardware integrated circuit in a format recognizable by a semiconductor manufacturing system, the semiconductor manufacturing system being configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit comprises: A floating point circuit configured to perform an approximation of a base 2 logarithm operation and provide a fixed least unit precision (ULP) error over an input range, wherein the floating point circuit comprises: a first pipeline circuit configured to perform said approximation of said base-2 logarithm for input operands in a first subset of said input range; and a second pipeline circuit configured to perform said approximation of said base 2 logarithm for input operands in a second subset of said input range; and A selection circuit is configured to select a result of a first pipeline or a second pipeline based on whether a given input operand is in the first subset of the input range.

18. The non-transitory computer-readable storage medium of claim 17, wherein to perform the approximation of the base-2 logarithm, the first pipeline circuit is configured to perform a natural logarithm operation.

19. The non-transitory computer-readable storage medium of claim 18, wherein to perform the approximation of the base-2 logarithm, the first pipeline is further configured to perform second-order or higher-order polynomial operations.

20. The non-transitory computer-readable storage medium of claim 17, wherein the first subset of the input range includes a range of values, the range of values ​​including the value 1.0.

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